From 50ac2848239cf5969b80c427a95b6098fd1e2f1c Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 3 Sep 2014 13:39:46 +0200 Subject: Fixes in $alu SAT- and eval-models --- kernel/consteval.h | 4 ++-- kernel/satgen.h | 7 +++---- 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/kernel/consteval.h b/kernel/consteval.h index fb54b72f6..c73a0b351 100644 --- a/kernel/consteval.h +++ b/kernel/consteval.h @@ -178,8 +178,8 @@ struct ConstEval RTLIL::SigSpec sig_co = cell->getPort("\\CO"); bool any_input_undef = !(sig_a.is_fully_def() && sig_b.is_fully_def() && sig_ci.is_fully_def() && sig_bi.is_fully_def()); - sig_a.extend(SIZE(sig_y), signed_a); - sig_b.extend(SIZE(sig_y), signed_b); + sig_a.extend_u0(SIZE(sig_y), signed_a); + sig_b.extend_u0(SIZE(sig_y), signed_b); bool carry = sig_ci[0] == RTLIL::S1; bool b_inv = sig_bi[0] == RTLIL::S1; diff --git a/kernel/satgen.h b/kernel/satgen.h index 3685cd6e6..c7f1680d4 100644 --- a/kernel/satgen.h +++ b/kernel/satgen.h @@ -934,9 +934,9 @@ struct SatGen std::vector undef_x = importUndefSigSpec(cell->getPort("\\X"), timestep); std::vector undef_co = importUndefSigSpec(cell->getPort("\\CO"), timestep); - extendSignalWidth(undef_a, undef_b, undef_y, cell, true); - extendSignalWidth(undef_a, undef_b, undef_x, cell, true); - extendSignalWidth(undef_a, undef_b, undef_co, cell, true); + extendSignalWidth(undef_a, undef_b, undef_y, cell); + extendSignalWidth(undef_a, undef_b, undef_x, cell); + extendSignalWidth(undef_a, undef_b, undef_co, cell); std::vector all_inputs_undef; all_inputs_undef.insert(all_inputs_undef.end(), undef_a.begin(), undef_a.end()); @@ -955,7 +955,6 @@ struct SatGen undefGating(x, def_x, undef_x); undefGating(co, def_co, undef_co); } - log_ping(); return true; } -- cgit v1.2.3