From 453904dd0020ed8aacf8319cb90d1f0e05c9daa9 Mon Sep 17 00:00:00 2001 From: "William D. Jones" <thor0505@comcast.net> Date: Thu, 26 Nov 2020 21:58:20 -0500 Subject: machxo2: Add add_sub test. Fix tests to include FACADE_IO primitives. --- tests/arch/machxo2/add_sub.ys | 8 ++++++++ tests/arch/machxo2/dffs.ys | 4 ++-- tests/arch/machxo2/logic.ys | 2 +- 3 files changed, 11 insertions(+), 3 deletions(-) create mode 100644 tests/arch/machxo2/add_sub.ys diff --git a/tests/arch/machxo2/add_sub.ys b/tests/arch/machxo2/add_sub.ys new file mode 100644 index 000000000..d9497b818 --- /dev/null +++ b/tests/arch/machxo2/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/dffs.ys b/tests/arch/machxo2/dffs.ys index 83a07cfee..83a79a9d6 100644 --- a/tests/arch/machxo2/dffs.ys +++ b/tests/arch/machxo2/dffs.ys @@ -7,7 +7,7 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:FACADE_FF -select -assert-none t:FACADE_FF %% t:* %D +select -assert-none t:FACADE_FF t:FACADE_IO %% t:* %D design -load read hierarchy -top dffe @@ -16,4 +16,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module select -assert-count 2 t:FACADE_FF t:LUT4 -select -assert-none t:FACADE_FF t:LUT4 %% t:* %D +select -assert-none t:FACADE_FF t:LUT4 t:FACADE_IO %% t:* %D diff --git a/tests/arch/machxo2/logic.ys b/tests/arch/machxo2/logic.ys index c5d2fb08e..bf93ab128 100644 --- a/tests/arch/machxo2/logic.ys +++ b/tests/arch/machxo2/logic.ys @@ -5,4 +5,4 @@ equiv_opt -assert -map +/machxo2/cells_sim.v synth_machxo2 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 9 t:LUT4 -select -assert-none t:LUT4 %% t:* %D +select -assert-none t:LUT4 t:FACADE_IO %% t:* %D -- cgit v1.2.3