From d90c1e952256dc00d070863835e061d73e4bc6b3 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 20 Apr 2016 20:48:19 -0700 Subject: Added GP_VREF cell --- techlibs/greenpak4/cells_sim.v | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 554e2e13f..40d79aeae 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -263,6 +263,12 @@ module GP_VDD(output OUT); assign OUT = 1; endmodule +module GP_VREF(input VIN, output reg VOUT); + parameter VIN_DIV = 1; + parameter VREF = 0; + //cannot simulate mixed signal IP +endmodule + module GP_VSS(output OUT); assign OUT = 0; endmodule -- cgit v1.2.3 From 0cbe70eaa40056a9d41070652282694cd7285b1a Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Fri, 22 Apr 2016 19:08:19 -0700 Subject: Fixed typo --- techlibs/greenpak4/cells_sim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 40d79aeae..706e955b6 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -235,7 +235,7 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); reg[15:0] shreg = 0; - always @(posedge clk, negedge RSTN) begin + always @(posedge clk, negedge nRST) begin if(!nRST) shreg = 0; -- cgit v1.2.3