From 5aa8d7ceeb663be24c7b815822d0de2ee25431a6 Mon Sep 17 00:00:00 2001 From: Diego H Date: Mon, 2 Sep 2019 17:43:27 -0500 Subject: Updating gowin --- techlibs/gowin/arith_map.v | 2 +- techlibs/gowin/synth_gowin.cc | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index e15de6423..af805b254 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -45,7 +45,7 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - ALU #(.ALU_MODE(32'b0)) + ALU #(.ALU_MODE(0)) alu(.I0(AA[i]), .I1(BB[i]), .I3(1'b0), diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index ac3dbfb29..1fc029e3c 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -226,7 +226,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("vout")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -nodec -attr2comment -defparam -renameprefix gen %s", + run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s", help_mode ? "" : vout_file.c_str())); } } -- cgit v1.2.3 From 11f330ed223f524cbbdbe2433599990a69b8f380 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 11:53:37 +0300 Subject: Add tests for ECP5 architecture --- Makefile | 1 + tests/ecp5/.gitignore | 2 + tests/ecp5/add_sub.v | 13 + tests/ecp5/add_sub.ys | 8 + tests/ecp5/adffs.v | 91 ++ tests/ecp5/adffs.ys | 10 + tests/ecp5/alu.v | 19 + tests/ecp5/alu.ys | 11 + tests/ecp5/counter.v | 17 + tests/ecp5/counter.ys | 11 + tests/ecp5/dffs.v | 37 + tests/ecp5/dffs.ys | 9 + tests/ecp5/div_mod.v | 13 + tests/ecp5/div_mod.ys | 12 + tests/ecp5/dpram.v | 23 + tests/ecp5/dpram.ys | 18 + tests/ecp5/dpram_synth.v | 165 ++++ tests/ecp5/fsm.v | 73 ++ tests/ecp5/fsm.ys | 13 + tests/ecp5/latches.v | 58 ++ tests/ecp5/latches.ys | 17 + tests/ecp5/latches_synth.v | 109 +++ tests/ecp5/logic.v | 18 + tests/ecp5/logic.ys | 7 + tests/ecp5/macc.v | 25 + tests/ecp5/macc.ys | 15 + tests/ecp5/memory.v | 21 + tests/ecp5/memory.ys | 21 + tests/ecp5/memory_synth.v | 2121 ++++++++++++++++++++++++++++++++++++++++++++ tests/ecp5/mul.v | 11 + tests/ecp5/mul.ys | 11 + tests/ecp5/mux.v | 100 +++ tests/ecp5/mux.ys | 11 + tests/ecp5/rom.v | 18 + tests/ecp5/rom.ys | 9 + tests/ecp5/run-test.sh | 20 + tests/ecp5/shifter.v | 22 + tests/ecp5/shifter.ys | 9 + tests/ecp5/tribuf.v | 23 + tests/ecp5/tribuf.ys | 9 + 40 files changed, 3201 insertions(+) create mode 100644 tests/ecp5/.gitignore create mode 100644 tests/ecp5/add_sub.v create mode 100644 tests/ecp5/add_sub.ys create mode 100644 tests/ecp5/adffs.v create mode 100644 tests/ecp5/adffs.ys create mode 100644 tests/ecp5/alu.v create mode 100644 tests/ecp5/alu.ys create mode 100644 tests/ecp5/counter.v create mode 100644 tests/ecp5/counter.ys create mode 100644 tests/ecp5/dffs.v create mode 100644 tests/ecp5/dffs.ys create mode 100644 tests/ecp5/div_mod.v create mode 100644 tests/ecp5/div_mod.ys create mode 100644 tests/ecp5/dpram.v create mode 100644 tests/ecp5/dpram.ys create mode 100644 tests/ecp5/dpram_synth.v create mode 100644 tests/ecp5/fsm.v create mode 100644 tests/ecp5/fsm.ys create mode 100644 tests/ecp5/latches.v create mode 100644 tests/ecp5/latches.ys create mode 100644 tests/ecp5/latches_synth.v create mode 100644 tests/ecp5/logic.v create mode 100644 tests/ecp5/logic.ys create mode 100644 tests/ecp5/macc.v create mode 100644 tests/ecp5/macc.ys create mode 100644 tests/ecp5/memory.v create mode 100644 tests/ecp5/memory.ys create mode 100644 tests/ecp5/memory_synth.v create mode 100644 tests/ecp5/mul.v create mode 100644 tests/ecp5/mul.ys create mode 100644 tests/ecp5/mux.v create mode 100644 tests/ecp5/mux.ys create mode 100644 tests/ecp5/rom.v create mode 100644 tests/ecp5/rom.ys create mode 100755 tests/ecp5/run-test.sh create mode 100644 tests/ecp5/shifter.v create mode 100644 tests/ecp5/shifter.ys create mode 100644 tests/ecp5/tribuf.v create mode 100644 tests/ecp5/tribuf.ys diff --git a/Makefile b/Makefile index 2cac80f0f..d4f1d3d68 100644 --- a/Makefile +++ b/Makefile @@ -710,6 +710,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys new file mode 100644 index 000000000..03aec6694 --- /dev/null +++ b/tests/ecp5/add_sub.ys @@ -0,0 +1,8 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/ecp5/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys new file mode 100644 index 000000000..7ec2b0114 --- /dev/null +++ b/tests/ecp5/adffs.ys @@ -0,0 +1,10 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:TRELLIS_FF +select -assert-count 7 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/alu.v b/tests/ecp5/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/ecp5/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/ecp5/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/ecp5/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys new file mode 100644 index 000000000..c65c21622 --- /dev/null +++ b/tests/ecp5/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/ecp5/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys new file mode 100644 index 000000000..5510bb440 --- /dev/null +++ b/tests/ecp5/dffs.ys @@ -0,0 +1,9 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 2 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ecp5/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys new file mode 100644 index 000000000..fb13be5d5 --- /dev/null +++ b/tests/ecp5/div_mod.ys @@ -0,0 +1,12 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 28 t:CCU2C +select -assert-count 48 t:L6MUX21 +select -assert-count 194 t:LUT4 +select -assert-count 84 t:PFUMX +select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/ecp5/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/ecp5/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/ecp5/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/ecp5/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys new file mode 100644 index 000000000..f454a0c02 --- /dev/null +++ b/tests/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 55fbc1a355a6139872a176318356ecdb71a35f5d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 3 Sep 2019 12:11:12 +0300 Subject: Uncomment sat command in memory.ys test. --- tests/ecp5/memory.ys | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys index c90f1991e..9cc6bb5be 100644 --- a/tests/ecp5/memory.ys +++ b/tests/ecp5/memory.ys @@ -7,8 +7,7 @@ memory opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top -- cgit v1.2.3 From ec56438cf29c6cfdad5cc28987298ec6bd363d47 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 4 Sep 2019 10:33:47 +0200 Subject: gowin: add splitnets to appease the PnR --- techlibs/gowin/synth_gowin.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index ac3dbfb29..9c2a5c837 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -186,6 +186,7 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/techmap.v"); if (retime || help_mode) run("abc -dff", "(only if -retime)"); + run("splitnets"); } if (check_label("map_ffs")) -- cgit v1.2.3 From 6cf5157fe7a8f4299a002f1be6c95ba5507a2cd4 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 4 Sep 2019 10:52:28 +0200 Subject: Update example for GW1NR-9 This uses the Trenz TEC0117 on Gowin IDE 1.8.4 --- examples/gowin/demo.cst | 51 ++++++++++------------------------------------- examples/gowin/demo.v | 5 +---- examples/gowin/device.cfg | 16 +++++++++++++++ examples/gowin/run.sh | 3 +-- 4 files changed, 28 insertions(+), 47 deletions(-) create mode 100644 examples/gowin/device.cfg diff --git a/examples/gowin/demo.cst b/examples/gowin/demo.cst index 22d7eb668..c8f89dcf8 100644 --- a/examples/gowin/demo.cst +++ b/examples/gowin/demo.cst @@ -1,41 +1,10 @@ -// 50 MHz Clock -IO_LOC "clk" D11; - -// LEDs -IO_LOC "leds[0]" D22; -IO_LOC "leds[1]" E22; -IO_LOC "leds[2]" G22; -IO_LOC "leds[3]" J22; -IO_LOC "leds[4]" L22; -IO_LOC "leds[5]" L19; -IO_LOC "leds[6]" L20; -IO_LOC "leds[7]" M21; -IO_LOC "leds[8]" N19; -IO_LOC "leds[9]" R19; -IO_LOC "leds[10]" T18; -IO_LOC "leds[11]" AA22; -IO_LOC "leds[12]" U18; -IO_LOC "leds[13]" V20; -IO_LOC "leds[14]" AA21; -IO_LOC "leds[15]" AB21; - - -// 7-Segment Display -IO_LOC "seg7dig[0]" E20; -IO_LOC "seg7dig[1]" G18; -IO_LOC "seg7dig[2]" G20; -IO_LOC "seg7dig[3]" F21; -IO_LOC "seg7dig[4]" J20; -IO_LOC "seg7dig[5]" H21; -IO_LOC "seg7dig[6]" H18; -IO_LOC "seg7dig[7]" D20; -IO_LOC "seg7sel[0]" C19; -IO_LOC "seg7sel[1]" B22; -IO_LOC "seg7sel[2]" C20; -IO_LOC "seg7sel[3]" C21; - -// Switches -IO_LOC "sw[0]" AB20; -IO_LOC "sw[1]" AB19; -IO_LOC "sw[2]" AB18; -IO_LOC "sw[3]" AB17; +IO_LOC "clk" 35; +//IO_LOC "rst_n" 77; +IO_LOC "leds[0]" 79; +IO_LOC "leds[1]" 80; +IO_LOC "leds[2]" 81; +IO_LOC "leds[3]" 82; +IO_LOC "leds[4]" 83; +IO_LOC "leds[5]" 84; +IO_LOC "leds[6]" 85; +IO_LOC "leds[7]" 86; \ No newline at end of file diff --git a/examples/gowin/demo.v b/examples/gowin/demo.v index 6ea108384..3cb782fa7 100644 --- a/examples/gowin/demo.v +++ b/examples/gowin/demo.v @@ -1,9 +1,6 @@ module demo ( input clk, - input [3:0] sw, - output [15:0] leds, - output [7:0] seg7dig, - output [3:0] seg7sel + output [15:0] leds ); localparam PRESCALE = 20; reg [PRESCALE+3:0] counter = 0; diff --git a/examples/gowin/device.cfg b/examples/gowin/device.cfg new file mode 100644 index 000000000..f6ab82159 --- /dev/null +++ b/examples/gowin/device.cfg @@ -0,0 +1,16 @@ +set JTAG regular_io = false +set SSPI regular_io = false +set MSPI regular_io = false +set READY regular_io = false +set DONE regular_io = false +set RECONFIG_N regular_io = false +set MODE regular_io = false +set CRC_check = true +set compress = false +set encryption = false +set security_bit_enable = true +set bsram_init_fuse_print = true +set download_speed = 250/100 +set spi_flash_address = 0x00FFF000 +set format = txt +set background_programming = false diff --git a/examples/gowin/run.sh b/examples/gowin/run.sh index 33a7b5c37..cd260101e 100644 --- a/examples/gowin/run.sh +++ b/examples/gowin/run.sh @@ -1,8 +1,7 @@ #!/bin/bash set -ex yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v -$GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW2A55-PBGA484-6 \ - -warning_all -out demo_out.v -rpt demo.rpt -tr demo_tr.html -bit demo.bit +$GOWIN_HOME/bin/gowin -d demo_syn.v -cst demo.cst -sdc demo.sdc -p GW1NR-9-QFN88-6 -pn GW1NR-LV9QN88C6/I5 -cfg device.cfg -bit -tr -ph -timing -gpa -rpt -warning_all # post place&route simulation (icarus verilog) if false; then -- cgit v1.2.3 From 072367245184528de0907f48ed45af79901d93eb Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 4 Sep 2019 10:58:48 +0200 Subject: Add demonstration of breakage Unused outputs lead to undriven buffers, which lead to syntax errors. --- examples/gowin/demo.v | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/gowin/demo.v b/examples/gowin/demo.v index 3cb782fa7..f5c001893 100644 --- a/examples/gowin/demo.v +++ b/examples/gowin/demo.v @@ -1,6 +1,7 @@ module demo ( input clk, output [15:0] leds + //,output unused ); localparam PRESCALE = 20; reg [PRESCALE+3:0] counter = 0; -- cgit v1.2.3 From a203c8569cb6fc7093a5d09e4c64d8e545f81e39 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 4 Sep 2019 12:15:52 +0300 Subject: Fix ecp5 tests - remove *_synth.v files and generation in scripts; - change synth_ice40 to synth_ecp5; --- tests/ecp5/alu.ys | 12 +- tests/ecp5/counter.ys | 9 +- tests/ecp5/dpram.ys | 1 - tests/ecp5/dpram_synth.v | 165 ---- tests/ecp5/fsm.ys | 15 +- tests/ecp5/latches.ys | 1 - tests/ecp5/latches_synth.v | 109 --- tests/ecp5/logic.ys | 6 +- tests/ecp5/memory.ys | 1 - tests/ecp5/memory_synth.v | 2121 -------------------------------------------- tests/ecp5/shifter.ys | 7 +- 11 files changed, 26 insertions(+), 2421 deletions(-) delete mode 100644 tests/ecp5/dpram_synth.v delete mode 100644 tests/ecp5/latches_synth.v delete mode 100644 tests/ecp5/memory_synth.v diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys index bd859efc4..d10cd63b2 100644 --- a/tests/ecp5/alu.ys +++ b/tests/ecp5/alu.ys @@ -2,10 +2,12 @@ read_verilog alu.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D +select -assert-count 32 t:CCU2C +select -assert-count 253 t:L6MUX21 +select -assert-count 1150 t:LUT4 +select -assert-count 423 t:PFUMX +select -assert-count 32 t:TRELLIS_FF +select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys index c65c21622..8ef70778f 100644 --- a/tests/ecp5/counter.ys +++ b/tests/ecp5/counter.ys @@ -2,10 +2,9 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:SB_CARRY -select -assert-count 8 t:SB_DFFR -select -assert-count 8 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D +select -assert-count 4 t:CCU2C +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys index b88eb80dd..786dee134 100644 --- a/tests/ecp5/dpram.ys +++ b/tests/ecp5/dpram.ys @@ -15,4 +15,3 @@ design -load postopt cd top select -assert-count 1 t:DP16KD select -assert-none t:DP16KD %% t:* %D -write_verilog dpram_synth.v diff --git a/tests/ecp5/dpram_synth.v b/tests/ecp5/dpram_synth.v deleted file mode 100644 index 7ae20bbba..000000000 --- a/tests/ecp5/dpram_synth.v +++ /dev/null @@ -1,165 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* dynports = 1 *) -(* top = 1 *) -(* src = "dpram.v:4" *) -module top(din, write_en, waddr, wclk, raddr, rclk, dout); - (* unused_bits = "8" *) - wire [8:0] _0_; - (* src = "dpram.v:8" *) - input [7:0] din; - (* src = "dpram.v:10" *) - output [7:0] dout; - (* src = "dpram.v:7" *) - input [7:0] raddr; - (* src = "dpram.v:9" *) - input rclk; - (* src = "dpram.v:7" *) - input [7:0] waddr; - (* src = "dpram.v:9" *) - input wclk; - (* src = "dpram.v:9" *) - input write_en; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/brams_map.v:79" *) - DP16KD #( - .CLKAMUX("CLKA"), - .CLKBMUX("CLKB"), - .DATA_WIDTH_A(32'sd9), - .DATA_WIDTH_B(32'sd9), - .GSR("DISABLED"), - .INITVAL_00(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_01(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_02(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_03(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_04(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_05(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_06(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_07(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_08(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_09(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_0F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_10(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_11(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_12(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_13(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_14(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_15(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_16(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_17(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_18(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_19(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_1F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_20(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_21(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_22(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_23(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_24(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_25(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_26(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_27(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_28(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_29(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_2F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_30(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_31(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_32(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_33(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_34(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_35(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_36(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_37(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_38(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_39(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3A(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3B(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3C(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3D(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3E(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .INITVAL_3F(320'b00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx00xxxxxxxxxxxxxxxxxx), - .WRITEMODE_A("READBEFOREWRITE"), - .WRITEMODE_B("READBEFOREWRITE") - ) \mem.0.0.0 ( - .ADA0(1'h0), - .ADA1(1'h0), - .ADA10(waddr[7]), - .ADA11(1'h0), - .ADA12(1'h0), - .ADA13(1'h0), - .ADA2(1'h0), - .ADA3(waddr[0]), - .ADA4(waddr[1]), - .ADA5(waddr[2]), - .ADA6(waddr[3]), - .ADA7(waddr[4]), - .ADA8(waddr[5]), - .ADA9(waddr[6]), - .ADB0(1'h0), - .ADB1(1'h0), - .ADB10(raddr[7]), - .ADB11(1'h0), - .ADB12(1'h0), - .ADB13(1'h0), - .ADB2(1'h0), - .ADB3(raddr[0]), - .ADB4(raddr[1]), - .ADB5(raddr[2]), - .ADB6(raddr[3]), - .ADB7(raddr[4]), - .ADB8(raddr[5]), - .ADB9(raddr[6]), - .CEA(1'h1), - .CEB(1'h1), - .CLKA(wclk), - .CLKB(rclk), - .DIA0(din[0]), - .DIA1(din[1]), - .DIA10(1'h0), - .DIA11(1'h0), - .DIA12(1'h0), - .DIA13(1'h0), - .DIA14(1'h0), - .DIA15(1'h0), - .DIA16(1'h0), - .DIA17(1'h0), - .DIA2(din[2]), - .DIA3(din[3]), - .DIA4(din[4]), - .DIA5(din[5]), - .DIA6(din[6]), - .DIA7(din[7]), - .DIA8(1'h0), - .DIA9(1'h0), - .DOB0(dout[0]), - .DOB1(dout[1]), - .DOB2(dout[2]), - .DOB3(dout[3]), - .DOB4(dout[4]), - .DOB5(dout[5]), - .DOB6(dout[6]), - .DOB7(dout[7]), - .DOB8(_0_[8]), - .OCEA(1'h1), - .OCEB(1'h1), - .RSTA(1'h0), - .RSTB(1'h0), - .WEA(write_en), - .WEB(1'h0) - ); - assign _0_[7:0] = dout; -endmodule diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 4cc8629d6..bdd910163 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -2,12 +2,13 @@ read_verilog fsm.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module - -select -assert-count 2 t:SB_DFFESR -select -assert-count 2 t:SB_DFFSR -select -assert-count 1 t:SB_DFFSS -select -assert-count 13 t:SB_LUT4 -select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D +select -assert-count 1 t:L6MUX21 +select -assert-count 15 t:LUT4 +select -assert-count 6 t:PFUMX +select -assert-count 6 t:TRELLIS_FF +select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index 6eaf77cfd..b9d8faf87 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -14,4 +14,3 @@ cd top select -assert-count 4 t:LUT4 select -assert-count 1 t:PFUMX select -assert-none t:LUT4 t:PFUMX %% t:* %D -write_verilog latches_synth.v diff --git a/tests/ecp5/latches_synth.v b/tests/ecp5/latches_synth.v deleted file mode 100644 index 816e10d4d..000000000 --- a/tests/ecp5/latches_synth.v +++ /dev/null @@ -1,109 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* top = 1 *) -(* src = "latches.v:27" *) -module top(clk, clr, pre, a, b, b1, b2); - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *) - wire _0_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:105" *) - wire _1_; - (* src = "latches.v:31" *) - input a; - (* src = "latches.v:32" *) - output b; - (* src = "latches.v:32" *) - output b1; - (* src = "latches.v:32" *) - output b2; - (* src = "latches.v:28" *) - input clk; - (* src = "latches.v:29" *) - input clr; - (* src = "latches.v:30" *) - input pre; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.d ; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.en ; - (* src = "latches.v:43|latches.v:9" *) - wire \u_latchn.q ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.d ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.en ; - (* src = "latches.v:36|latches.v:2" *) - wire \u_latchp.q ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.clr ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.d ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.en ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.pre ; - (* src = "latches.v:50|latches.v:16" *) - wire \u_latchsr.q ; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:106" *) - LUT4 #( - .INIT(16'h5150) - ) _2_ ( - .A(clr), - .B(clk), - .C(pre), - .D(b2), - .Z(_0_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:108" *) - LUT4 #( - .INIT(16'h5554) - ) _3_ ( - .A(clr), - .B(clk), - .C(pre), - .D(b2), - .Z(_1_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:110" *) - PFUMX _4_ ( - .ALUT(_1_), - .BLUT(_0_), - .C0(a), - .Z(b2) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x1x1x0x0x1x0x0) - ) _5_ ( - .A(1'h0), - .B(clk), - .C(b), - .D(a), - .Z(b) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x1x0x1x1x0x0x0) - ) _6_ ( - .A(1'h0), - .B(clk), - .C(b1), - .D(a), - .Z(b1) - ); - assign \u_latchn.d = a; - assign \u_latchn.en = clk; - assign \u_latchn.q = b1; - assign \u_latchp.d = a; - assign \u_latchp.en = clk; - assign \u_latchp.q = b; - assign \u_latchsr.clr = clr; - assign \u_latchsr.d = a; - assign \u_latchsr.en = clk; - assign \u_latchsr.pre = pre; - assign \u_latchsr.q = b2; -endmodule diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys index fc5e5b1d8..34125fea9 100644 --- a/tests/ecp5/logic.ys +++ b/tests/ecp5/logic.ys @@ -1,7 +1,7 @@ read_verilog logic.v hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 9 t:SB_LUT4 -select -assert-none t:SB_LUT4 %% t:* %D +select -assert-count 9 t:LUT4 +select -assert-none t:LUT4 %% t:* %D diff --git a/tests/ecp5/memory.ys b/tests/ecp5/memory.ys index 9cc6bb5be..9b475f122 100644 --- a/tests/ecp5/memory.ys +++ b/tests/ecp5/memory.ys @@ -17,4 +17,3 @@ select -assert-count 32 t:PFUMX select -assert-count 8 t:TRELLIS_DPR16X4 select -assert-count 35 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D -write_verilog memory_synth.v diff --git a/tests/ecp5/memory_synth.v b/tests/ecp5/memory_synth.v deleted file mode 100644 index a6172de61..000000000 --- a/tests/ecp5/memory_synth.v +++ /dev/null @@ -1,2121 +0,0 @@ -/* Generated by Yosys 0.9+36 (git sha1 7e8f7f4c, gcc 8.3.0-6ubuntu1 -Og -fPIC) */ - -(* top = 1 *) -(* src = "memory.v:1" *) -module top(data_a, addr_a, we_a, clk, q_a); - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _000_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _001_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _002_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _003_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _004_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _005_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _006_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _007_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _008_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _009_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _010_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _011_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _012_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _013_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _014_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _015_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _016_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _017_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _018_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _019_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _020_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _021_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _022_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _023_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _024_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _025_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _026_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _027_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _028_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _029_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _030_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _031_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _032_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _033_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _034_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _035_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _036_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _037_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _038_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _039_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _040_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _041_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _042_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _043_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _044_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _045_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _046_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _047_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _048_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _049_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _050_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _051_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _052_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _053_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _054_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _055_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _056_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _057_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _058_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _059_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _060_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _061_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _062_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _063_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _064_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _065_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _066_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _067_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _068_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _069_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _070_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _071_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _072_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _073_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _074_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _075_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _076_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _077_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _078_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _079_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _080_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _081_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _082_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _083_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _084_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _085_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _086_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _087_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _088_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _089_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _090_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _091_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _092_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _093_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _094_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _095_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _096_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _097_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _098_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _099_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _100_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _101_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _102_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _103_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _104_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _105_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _106_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _107_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _108_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _109_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _110_; - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:129" *) - wire _111_; - wire _112_; - wire _113_; - wire _114_; - wire _115_; - wire _116_; - wire _117_; - wire _118_; - wire _119_; - wire _120_; - wire _121_; - wire _122_; - wire _123_; - wire _124_; - wire _125_; - wire _126_; - wire _127_; - wire _128_; - wire _129_; - wire _130_; - wire _131_; - wire _132_; - wire _133_; - wire _134_; - wire _135_; - wire _136_; - wire _137_; - wire _138_; - wire _139_; - wire _140_; - wire _141_; - wire _142_; - wire _143_; - wire _144_; - wire _145_; - wire _146_; - wire _147_; - wire _148_; - wire _149_; - wire _150_; - wire _151_; - wire _152_; - wire _153_; - wire [3:0] _154_; - wire [3:0] _155_; - wire [3:0] _156_; - wire [3:0] _157_; - wire [3:0] _158_; - wire [3:0] _159_; - wire [3:0] _160_; - wire [3:0] _161_; - (* src = "memory.v:4" *) - input [6:1] addr_a; - (* src = "memory.v:5" *) - input clk; - (* src = "memory.v:3" *) - input [7:0] data_a; - (* src = "memory.v:6" *) - output [7:0] q_a; - (* src = "memory.v:5" *) - input we_a; - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx0xxx1) - ) _162_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_147_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx1xxx0) - ) _163_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_148_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:92" *) - LUT4 #( - .INIT(16'bxxx0xxx0xxx1xxx0) - ) _164_ ( - .A(1'h0), - .B(1'h0), - .C(addr_a[6]), - .D(addr_a[5]), - .Z(_149_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx1x0x0x0x0x0x0x0) - ) _165_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_153_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x0x0x1x0) - ) _166_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x1x0x0x0) - ) _167_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[5]), - .D(addr_a[6]), - .Z(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:96" *) - LUT4 #( - .INIT(16'bx0x0x0x0x1x0x0x0) - ) _168_ ( - .A(1'h0), - .B(we_a), - .C(addr_a[6]), - .D(addr_a[5]), - .Z(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _169_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_000_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _170_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_001_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _171_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_002_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _172_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_003_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _173_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_004_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _174_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_005_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _175_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_006_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _176_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_136_), - .Z(_007_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _177_ ( - .ALUT(_001_), - .BLUT(_000_), - .C0(_132_), - .Z(_008_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _178_ ( - .ALUT(_003_), - .BLUT(_002_), - .C0(_132_), - .Z(_009_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _179_ ( - .ALUT(_005_), - .BLUT(_004_), - .C0(_132_), - .Z(_010_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _180_ ( - .ALUT(_007_), - .BLUT(_006_), - .C0(_132_), - .Z(_011_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _181_ ( - .D0(_008_), - .D1(_009_), - .SD(_128_), - .Z(_012_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _182_ ( - .D0(_010_), - .D1(_011_), - .SD(_128_), - .Z(_013_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _183_ ( - .D0(_012_), - .D1(_013_), - .SD(_140_), - .Z(q_a[4]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _184_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_014_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _185_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_015_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _186_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_016_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _187_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_017_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _188_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_018_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _189_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_019_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _190_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_020_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _191_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_137_), - .Z(_021_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _192_ ( - .ALUT(_015_), - .BLUT(_014_), - .C0(_133_), - .Z(_022_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _193_ ( - .ALUT(_017_), - .BLUT(_016_), - .C0(_133_), - .Z(_023_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _194_ ( - .ALUT(_019_), - .BLUT(_018_), - .C0(_133_), - .Z(_024_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _195_ ( - .ALUT(_021_), - .BLUT(_020_), - .C0(_133_), - .Z(_025_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _196_ ( - .D0(_022_), - .D1(_023_), - .SD(_129_), - .Z(_026_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _197_ ( - .D0(_024_), - .D1(_025_), - .SD(_129_), - .Z(_027_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _198_ ( - .D0(_026_), - .D1(_027_), - .SD(_141_), - .Z(q_a[5]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _199_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_028_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _200_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_029_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _201_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_030_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _202_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_031_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _203_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_032_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _204_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_033_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _205_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_034_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _206_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_138_), - .Z(_035_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _207_ ( - .ALUT(_029_), - .BLUT(_028_), - .C0(_134_), - .Z(_036_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _208_ ( - .ALUT(_031_), - .BLUT(_030_), - .C0(_134_), - .Z(_037_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _209_ ( - .ALUT(_033_), - .BLUT(_032_), - .C0(_134_), - .Z(_038_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _210_ ( - .ALUT(_035_), - .BLUT(_034_), - .C0(_134_), - .Z(_039_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _211_ ( - .D0(_036_), - .D1(_037_), - .SD(_130_), - .Z(_040_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _212_ ( - .D0(_038_), - .D1(_039_), - .SD(_130_), - .Z(_041_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _213_ ( - .D0(_040_), - .D1(_041_), - .SD(_142_), - .Z(q_a[6]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _214_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_042_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _215_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_043_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _216_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_044_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _217_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_045_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _218_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_046_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _219_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_047_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _220_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_048_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _221_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_139_), - .Z(_049_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _222_ ( - .ALUT(_043_), - .BLUT(_042_), - .C0(_135_), - .Z(_050_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _223_ ( - .ALUT(_045_), - .BLUT(_044_), - .C0(_135_), - .Z(_051_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _224_ ( - .ALUT(_047_), - .BLUT(_046_), - .C0(_135_), - .Z(_052_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _225_ ( - .ALUT(_049_), - .BLUT(_048_), - .C0(_135_), - .Z(_053_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _226_ ( - .D0(_050_), - .D1(_051_), - .SD(_131_), - .Z(_054_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _227_ ( - .D0(_052_), - .D1(_053_), - .SD(_131_), - .Z(_055_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _228_ ( - .D0(_054_), - .D1(_055_), - .SD(_143_), - .Z(q_a[7]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _229_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_056_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _230_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_057_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _231_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_058_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _232_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_059_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _233_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_060_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _234_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_061_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _235_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_062_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _236_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_120_), - .Z(_063_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _237_ ( - .ALUT(_057_), - .BLUT(_056_), - .C0(_116_), - .Z(_064_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _238_ ( - .ALUT(_059_), - .BLUT(_058_), - .C0(_116_), - .Z(_065_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _239_ ( - .ALUT(_061_), - .BLUT(_060_), - .C0(_116_), - .Z(_066_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _240_ ( - .ALUT(_063_), - .BLUT(_062_), - .C0(_116_), - .Z(_067_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _241_ ( - .D0(_064_), - .D1(_065_), - .SD(_112_), - .Z(_068_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _242_ ( - .D0(_066_), - .D1(_067_), - .SD(_112_), - .Z(_069_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _243_ ( - .D0(_068_), - .D1(_069_), - .SD(_124_), - .Z(q_a[0]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _244_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_070_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _245_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_071_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _246_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_072_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _247_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_073_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _248_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_074_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _249_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_075_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _250_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_076_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _251_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_121_), - .Z(_077_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _252_ ( - .ALUT(_071_), - .BLUT(_070_), - .C0(_117_), - .Z(_078_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _253_ ( - .ALUT(_073_), - .BLUT(_072_), - .C0(_117_), - .Z(_079_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _254_ ( - .ALUT(_075_), - .BLUT(_074_), - .C0(_117_), - .Z(_080_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _255_ ( - .ALUT(_077_), - .BLUT(_076_), - .C0(_117_), - .Z(_081_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _256_ ( - .D0(_078_), - .D1(_079_), - .SD(_113_), - .Z(_082_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _257_ ( - .D0(_080_), - .D1(_081_), - .SD(_113_), - .Z(_083_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _258_ ( - .D0(_082_), - .D1(_083_), - .SD(_125_), - .Z(q_a[1]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _259_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_084_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _260_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_085_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _261_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_086_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _262_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_087_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _263_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_088_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _264_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_089_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _265_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_090_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _266_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_122_), - .Z(_091_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _267_ ( - .ALUT(_085_), - .BLUT(_084_), - .C0(_118_), - .Z(_092_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _268_ ( - .ALUT(_087_), - .BLUT(_086_), - .C0(_118_), - .Z(_093_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _269_ ( - .ALUT(_089_), - .BLUT(_088_), - .C0(_118_), - .Z(_094_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _270_ ( - .ALUT(_091_), - .BLUT(_090_), - .C0(_118_), - .Z(_095_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _271_ ( - .D0(_092_), - .D1(_093_), - .SD(_114_), - .Z(_096_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _272_ ( - .D0(_094_), - .D1(_095_), - .SD(_114_), - .Z(_097_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _273_ ( - .D0(_096_), - .D1(_097_), - .SD(_126_), - .Z(q_a[2]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:130" *) - LUT4 #( - .INIT(16'hf000) - ) _274_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_098_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:132" *) - LUT4 #( - .INIT(16'hfccc) - ) _275_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_099_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:135" *) - LUT4 #( - .INIT(16'hfaaa) - ) _276_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_100_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:137" *) - LUT4 #( - .INIT(16'hfeee) - ) _277_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_101_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:140" *) - LUT4 #( - .INIT(16'hf101) - ) _278_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_102_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:142" *) - LUT4 #( - .INIT(16'hfdcd) - ) _279_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_103_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:145" *) - LUT4 #( - .INIT(16'hfbab) - ) _280_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_104_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:147" *) - LUT4 #( - .INIT(16'hffef) - ) _281_ ( - .A(_144_), - .B(_145_), - .C(_146_), - .D(_123_), - .Z(_105_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:150" *) - PFUMX _282_ ( - .ALUT(_099_), - .BLUT(_098_), - .C0(_119_), - .Z(_106_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:151" *) - PFUMX _283_ ( - .ALUT(_101_), - .BLUT(_100_), - .C0(_119_), - .Z(_107_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:152" *) - PFUMX _284_ ( - .ALUT(_103_), - .BLUT(_102_), - .C0(_119_), - .Z(_108_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:153" *) - PFUMX _285_ ( - .ALUT(_105_), - .BLUT(_104_), - .C0(_119_), - .Z(_109_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:154" *) - L6MUX21 _286_ ( - .D0(_106_), - .D1(_107_), - .SD(_115_), - .Z(_110_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:155" *) - L6MUX21 _287_ ( - .D0(_108_), - .D1(_109_), - .SD(_115_), - .Z(_111_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:156" *) - L6MUX21 _288_ ( - .D0(_110_), - .D1(_111_), - .SD(_127_), - .Z(q_a[3]) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _289_ ( - .CLK(clk), - .DI(_147_), - .LSR(1'h0), - .Q(_144_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _290_ ( - .CLK(clk), - .DI(_154_[0]), - .LSR(1'h0), - .Q(_112_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _291_ ( - .CLK(clk), - .DI(_154_[1]), - .LSR(1'h0), - .Q(_113_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _292_ ( - .CLK(clk), - .DI(_154_[2]), - .LSR(1'h0), - .Q(_114_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _293_ ( - .CLK(clk), - .DI(_154_[3]), - .LSR(1'h0), - .Q(_115_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _294_ ( - .CLK(clk), - .DI(_155_[0]), - .LSR(1'h0), - .Q(_116_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _295_ ( - .CLK(clk), - .DI(_155_[1]), - .LSR(1'h0), - .Q(_117_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _296_ ( - .CLK(clk), - .DI(_155_[2]), - .LSR(1'h0), - .Q(_118_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _297_ ( - .CLK(clk), - .DI(_155_[3]), - .LSR(1'h0), - .Q(_119_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _298_ ( - .CLK(clk), - .DI(_156_[0]), - .LSR(1'h0), - .Q(_120_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _299_ ( - .CLK(clk), - .DI(_156_[1]), - .LSR(1'h0), - .Q(_121_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _300_ ( - .CLK(clk), - .DI(_156_[2]), - .LSR(1'h0), - .Q(_122_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _301_ ( - .CLK(clk), - .DI(_156_[3]), - .LSR(1'h0), - .Q(_123_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _302_ ( - .CLK(clk), - .DI(_149_), - .LSR(1'h0), - .Q(_146_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _303_ ( - .CLK(clk), - .DI(_157_[0]), - .LSR(1'h0), - .Q(_124_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _304_ ( - .CLK(clk), - .DI(_157_[1]), - .LSR(1'h0), - .Q(_125_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _305_ ( - .CLK(clk), - .DI(_157_[2]), - .LSR(1'h0), - .Q(_126_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _306_ ( - .CLK(clk), - .DI(_157_[3]), - .LSR(1'h0), - .Q(_127_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _307_ ( - .CLK(clk), - .DI(_158_[0]), - .LSR(1'h0), - .Q(_128_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _308_ ( - .CLK(clk), - .DI(_158_[1]), - .LSR(1'h0), - .Q(_129_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _309_ ( - .CLK(clk), - .DI(_158_[2]), - .LSR(1'h0), - .Q(_130_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _310_ ( - .CLK(clk), - .DI(_158_[3]), - .LSR(1'h0), - .Q(_131_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _311_ ( - .CLK(clk), - .DI(_159_[0]), - .LSR(1'h0), - .Q(_132_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _312_ ( - .CLK(clk), - .DI(_159_[1]), - .LSR(1'h0), - .Q(_133_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _313_ ( - .CLK(clk), - .DI(_159_[2]), - .LSR(1'h0), - .Q(_134_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _314_ ( - .CLK(clk), - .DI(_159_[3]), - .LSR(1'h0), - .Q(_135_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _315_ ( - .CLK(clk), - .DI(_148_), - .LSR(1'h0), - .Q(_145_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _316_ ( - .CLK(clk), - .DI(_160_[0]), - .LSR(1'h0), - .Q(_136_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _317_ ( - .CLK(clk), - .DI(_160_[1]), - .LSR(1'h0), - .Q(_137_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _318_ ( - .CLK(clk), - .DI(_160_[2]), - .LSR(1'h0), - .Q(_138_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _319_ ( - .CLK(clk), - .DI(_160_[3]), - .LSR(1'h0), - .Q(_139_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _320_ ( - .CLK(clk), - .DI(_161_[0]), - .LSR(1'h0), - .Q(_140_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _321_ ( - .CLK(clk), - .DI(_161_[1]), - .LSR(1'h0), - .Q(_141_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _322_ ( - .CLK(clk), - .DI(_161_[2]), - .LSR(1'h0), - .Q(_142_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/cells_map.v:2" *) - TRELLIS_FF #( - .CEMUX("1"), - .CLKMUX("CLK"), - .GSR("DISABLED"), - .LSRMUX("LSR"), - .REGSET("RESET") - ) _323_ ( - .CLK(clk), - .DI(_161_[3]), - .LSR(1'h0), - .Q(_143_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.0.0 ( - .DI(data_a[3:0]), - .DO(_154_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.1.0 ( - .DI(data_a[3:0]), - .DO(_155_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.2.0 ( - .DI(data_a[3:0]), - .DO(_156_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.0.3.0 ( - .DI(data_a[3:0]), - .DO(_157_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_153_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.0.0 ( - .DI(data_a[7:4]), - .DO(_158_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_150_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.1.0 ( - .DI(data_a[7:4]), - .DO(_159_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_151_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.2.0 ( - .DI(data_a[7:4]), - .DO(_160_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_152_) - ); - (* module_not_derived = 32'd1 *) - (* src = "/home/sergeid/WORK/SymbioticEDA/yosys-cover/share/ecp5/lutrams_map.v:15" *) - TRELLIS_DPR16X4 #( - .INITVAL(64'hxxxxxxxxxxxxxxxx), - .WCKMUX("WCK"), - .WREMUX("WRE") - ) \ram.1.3.0 ( - .DI(data_a[7:4]), - .DO(_161_), - .RAD(addr_a[4:1]), - .WAD(addr_a[4:1]), - .WCK(clk), - .WRE(_153_) - ); -endmodule diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys index 47d95d298..70fe6c45c 100644 --- a/tests/ecp5/shifter.ys +++ b/tests/ecp5/shifter.ys @@ -2,8 +2,9 @@ read_verilog shifter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:SB_DFF -select -assert-none t:SB_DFF %% t:* %D +stat +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D -- cgit v1.2.3 From 93f305b1c53ce49338bf276a7fb9c3aa4d578c9e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 4 Sep 2019 14:57:45 +0300 Subject: Remove stat command form shifter.ys test --- tests/ecp5/shifter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys index 70fe6c45c..e1901e1a8 100644 --- a/tests/ecp5/shifter.ys +++ b/tests/ecp5/shifter.ys @@ -5,6 +5,6 @@ flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -stat + select -assert-count 8 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D -- cgit v1.2.3 From 06062090dacf868b2a4eda32152c188a1b8be089 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 4 Sep 2019 14:47:59 +0200 Subject: add broken TCL run script --- examples/gowin/pnr.cfg | 8 ++++++++ examples/gowin/run.tcl | 10 ++++++++++ 2 files changed, 18 insertions(+) create mode 100644 examples/gowin/pnr.cfg create mode 100644 examples/gowin/run.tcl diff --git a/examples/gowin/pnr.cfg b/examples/gowin/pnr.cfg new file mode 100644 index 000000000..a1b43cc3b --- /dev/null +++ b/examples/gowin/pnr.cfg @@ -0,0 +1,8 @@ +-sdf +-oc +-ibs +-posp +-o +-warning_all +-tt +-timing diff --git a/examples/gowin/run.tcl b/examples/gowin/run.tcl new file mode 100644 index 000000000..7bb5648e5 --- /dev/null +++ b/examples/gowin/run.tcl @@ -0,0 +1,10 @@ +# gw_sh run.tcl +exec yosys -p "synth_gowin -top demo -vout demo_syn.v" demo.v +add_file -cst demo.cst +add_file -sdc demo.sdc +add_file -vm demo_syn.v +add_file -cfg device.cfg +add_setting -pnr pnr.cfg +set_option -device GW1NR-9-QFN88-6 +set_option -pn GW1NR-LV9QN88C6/I5 +run_pnr -- cgit v1.2.3 From d65a47c86d4ccc89db419638896fefd3b2324588 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 4 Sep 2019 15:35:33 +0200 Subject: fix tcl script --- examples/gowin/run.tcl | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/examples/gowin/run.tcl b/examples/gowin/run.tcl index 7bb5648e5..39da11cee 100644 --- a/examples/gowin/run.tcl +++ b/examples/gowin/run.tcl @@ -4,7 +4,6 @@ add_file -cst demo.cst add_file -sdc demo.sdc add_file -vm demo_syn.v add_file -cfg device.cfg -add_setting -pnr pnr.cfg set_option -device GW1NR-9-QFN88-6 set_option -pn GW1NR-LV9QN88C6/I5 -run_pnr +run_pnr -opt pnr.cfg -- cgit v1.2.3 From ae93c034adc8a7d14a9f39175dacdddda75ea7a2 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 4 Sep 2019 16:29:40 +0200 Subject: set undriven pads to zero --- examples/gowin/demo.v | 4 ++-- techlibs/gowin/synth_gowin.cc | 1 + 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/examples/gowin/demo.v b/examples/gowin/demo.v index f5c001893..485fec97f 100644 --- a/examples/gowin/demo.v +++ b/examples/gowin/demo.v @@ -1,7 +1,7 @@ module demo ( input clk, - output [15:0] leds - //,output unused + output [15:0] leds, + output unused ); localparam PRESCALE = 20; reg [PRESCALE+3:0] counter = 0; diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 0bfa9da1a..f7a5006bc 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -210,6 +210,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_cells")) { run("techmap -map +/gowin/cells_map.v"); + run("setundef -undriven -zero"); run("hilomap -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); -- cgit v1.2.3 From 3eff2271d0fe25632f7e6b22cf0be078d2cd9990 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 5 Sep 2019 13:36:41 +0200 Subject: add MUX support --- techlibs/gowin/cells_map.v | 3 +++ techlibs/gowin/cells_sim.v | 13 +++++++++++++ techlibs/gowin/synth_gowin.cc | 1 + 3 files changed, 17 insertions(+) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index ebdc88a0a..c38805b91 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -5,6 +5,9 @@ module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule module \$__DFFS_PP1_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule +module \$_MUX_ (input A, B, S, output Y); MUX2 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule +module \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule + module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index ebb238bad..98dfef9bf 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -24,6 +24,19 @@ module LUT4(output F, input I0, I1, I2, I3); assign F = I0 ? s1[1] : s1[0]; endmodule +module MUX2 (I0, I1, S0, O); +input I0, I1, S0; +output O; +assign O = S0 ? I1 : I0; +endmodule + +module MUX4 (I0, I1, I2, I3, S0, S1, O); +input I0, I1, I2, I3, S0, S1; +output O; +assign O = S1 ? (S0 ? I3 : I2) : + (S0 ? I1 : I0); +endmodule + module DFF (output reg Q, input CLK, D); parameter [0:0] INIT = 1'b0; initial Q = INIT; diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index f7a5006bc..4d32f62d4 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -196,6 +196,7 @@ struct SynthGowinPass : public ScriptPass run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); + run("muxcover -mux4"); run("techmap -map +/gowin/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); -- cgit v1.2.3 From 7a43be5e431f7518203b37bad2eb9ffb3b74add4 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 5 Sep 2019 16:38:47 +0200 Subject: use singleton ground and vcc nets, apparently this makes pnr happier --- techlibs/gowin/synth_gowin.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 4d32f62d4..3581d050e 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -212,7 +212,7 @@ struct SynthGowinPass : public ScriptPass { run("techmap -map +/gowin/cells_map.v"); run("setundef -undriven -zero"); - run("hilomap -hicell VCC V -locell GND G"); + run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); run("clean"); -- cgit v1.2.3 From 47374a495d3cbfa424cbe312aa4762e7c4e855ff Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 5 Sep 2019 17:25:51 +0200 Subject: support bram initialisation --- techlibs/gowin/Makefile.inc | 10 ++++++++++ techlibs/gowin/bram.txt | 3 +-- techlibs/gowin/brams_init.py | 8 ++++++++ techlibs/gowin/brams_map.v | 5 +++++ techlibs/gowin/synth_gowin.cc | 2 +- 5 files changed, 25 insertions(+), 3 deletions(-) create mode 100755 techlibs/gowin/brams_init.py diff --git a/techlibs/gowin/Makefile.inc b/techlibs/gowin/Makefile.inc index 6f2159349..d2853704b 100644 --- a/techlibs/gowin/Makefile.inc +++ b/techlibs/gowin/Makefile.inc @@ -15,3 +15,13 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/dram.txt)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh)) +EXTRA_OBJS += techlibs/gowin/brams_init.mk +.SECONDARY: techlibs/gowin/brams_init.mk + +techlibs/gowin/brams_init.mk: techlibs/gowin/brams_init.py + $(Q) mkdir -p techlibs/gowin + $(P) python3 $< + $(Q) touch $@ + +techlibs/gowin/bram_init_16.vh: techlibs/gowin/brams_init.mk +$(eval $(call add_gen_share_file,share/gowin,techlibs/gowin/bram_init_16.vh)) diff --git a/techlibs/gowin/bram.txt b/techlibs/gowin/bram.txt index b5f9a981c..366a7106e 100644 --- a/techlibs/gowin/bram.txt +++ b/techlibs/gowin/bram.txt @@ -1,6 +1,5 @@ bram $__GW1NR_SDP -# uncomment when done -# init 1 + init 1 abits 10 @a10d18 dbits 16 @a10d18 abits 11 @a11d9 diff --git a/techlibs/gowin/brams_init.py b/techlibs/gowin/brams_init.py new file mode 100755 index 000000000..b78eb8da5 --- /dev/null +++ b/techlibs/gowin/brams_init.py @@ -0,0 +1,8 @@ +#!/usr/bin/env python3 + +with open("techlibs/gowin/bram_init_16.vh", "w") as f: + for i in range(0, 0x40): + low = i << 8 + hi = ((i+1) << 8)-1 + snippet = "INIT[%d:%d]" % (hi, low) + print(".INIT_RAM_%02X({%s})," % (i, snippet), file=f) diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v index e963cfa88..c60330b4f 100644 --- a/techlibs/gowin/brams_map.v +++ b/techlibs/gowin/brams_map.v @@ -28,6 +28,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); generate if (CFG_DBITS == 1) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(1), .BIT_WIDTH_1(1), @@ -42,6 +43,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); ); end else if (CFG_DBITS == 2) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(2), .BIT_WIDTH_1(2), @@ -56,6 +58,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); ); end else if (CFG_DBITS <= 4) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(4), .BIT_WIDTH_1(4), @@ -70,6 +73,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); ); end else if (CFG_DBITS <= 8) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(8), .BIT_WIDTH_1(8), @@ -84,6 +88,7 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); ); end else if (CFG_DBITS <= 16) begin SDP #( + `include "bram_init_16.vh" .READ_MODE(0), .BIT_WIDTH_0(16), .BIT_WIDTH_1(16), diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 3581d050e..cfddcec12 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -229,7 +229,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("vout")) { if (!vout_file.empty() || help_mode) - run(stringf("write_verilog -nohex -decimal -attr2comment -defparam -renameprefix gen %s", + run(stringf("write_verilog -decimal -attr2comment -defparam -renameprefix gen %s", help_mode ? "" : vout_file.c_str())); } } -- cgit v1.2.3 From 5168b6ffa4047340b3412aa17be7e2d7ac587ee1 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 5 Sep 2019 19:12:47 +0200 Subject: WIP aditional DFF primitives --- techlibs/gowin/cells_map.v | 47 +++++++++++++++++++++++++++++++++++++++++++++- techlibs/gowin/cells_sim.v | 2 ++ 2 files changed, 48 insertions(+), 1 deletion(-) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index c38805b91..aea11d97e 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -1,9 +1,54 @@ +// TODO add these DFF types +// Primitive Description +// DFFSE D Flip-Flop with Clock Enable and Synchronous Set +// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset + +// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set +// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set +// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset +// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset +// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset +// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset +// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear +// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear + +//TODO all DFF* have INIT + +// DFFN D Flip-Flop with Negative-Edge Clock module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule +// DFF D Flip-Flop module \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule +// DFFE D Flip-Flop with Clock Enable +module \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule +module \$_DFFE_PN_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule + +// DFFNE D Flip-Flop with Negative-Edge Clock and Clock Enable +module \$_DFFE_NP_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule +module \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(!E)); endmodule + +// DFFR D Flip-Flop with Synchronous Reset module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule -module \$__DFFS_PP1_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule + +// DFFS D Flip-Flop with Synchronous Set +module \$__DFFS_PN1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!S)); endmodule +module \$__DFFS_PP1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(S)); endmodule + +// DFFP D Flip-Flop with Asynchronous Preset +module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule +module \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule +// DFFC D Flip-Flop with Asynchronous Clear +module \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule +module \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule + +// DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset +module \$__DFFE_PP1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule +module \$__DFFE_PN1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule +// DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear +module \$__DFFE_PP0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule +module \$__DFFE_PN0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule + module \$_MUX_ (input A, B, S, output Y); MUX2 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule module \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 98dfef9bf..c8475b28f 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -62,6 +62,8 @@ module DFFR (output reg Q, input D, CLK, RESET); end endmodule // DFFR (positive clock edge; synchronous reset) +// TODO add more DFF sim cells + module VCC(output V); assign V = 1; endmodule -- cgit v1.2.3 From 1b9f7f49b5e90f51f8c3c2d2e8afbaa074137413 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Fri, 6 Sep 2019 09:01:07 +0200 Subject: add more DFF to sim lib --- techlibs/gowin/cells_map.v | 12 +++--- techlibs/gowin/cells_sim.v | 105 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 111 insertions(+), 6 deletions(-) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index aea11d97e..08eb0a9c3 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -32,8 +32,8 @@ module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule // DFFS D Flip-Flop with Synchronous Set -module \$__DFFS_PN1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!S)); endmodule -module \$__DFFS_PP1_ (input D, C, S, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(S)); endmodule +module \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule +module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule // DFFP D Flip-Flop with Asynchronous Preset module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule @@ -43,11 +43,11 @@ module \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q module \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule // DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset -module \$__DFFE_PP1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule -module \$__DFFE_PN1_ (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule +module \$__DFFE_PP1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule +module \$__DFFE_PN1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule // DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear -module \$__DFFE_PP0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule -module \$__DFFE_PN0_ (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule +module \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule +module \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule module \$_MUX_ (input A, B, S, output Y); MUX2 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index c8475b28f..a2f60b99e 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -62,6 +62,111 @@ module DFFR (output reg Q, input D, CLK, RESET); end endmodule // DFFR (positive clock edge; synchronous reset) +module DFFE (output reg Q, input D, CLK, CE); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (CE) + Q <= D; + end +endmodule // DFFE (positive clock edge; clock enable) + + +module DFFS (output reg Q, input D, CLK, SET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (SET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFS (positive clock edge; synchronous set) + + +module DFFSE (output reg Q, input D, CLK, CE, SET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (SET) + Q <= 1'b1; + else if (CE) + Q <= D; +end +endmodule // DFFSE (positive clock edge; synchronous set takes precedence over clock enable) + + +module DFFR (output reg Q, input D, CLK, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (RESET) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFR (positive clock edge; synchronous reset) + + +module DFFRE (output reg Q, input D, CLK, CE, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK) begin + if (RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFRE (positive clock edge; synchronous reset takes precedence over clock enable) + + +module DFFP (output reg Q, input D, CLK, PRESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFP (positive clock edge; asynchronous preset) + + +module DFFPE (output reg Q, input D, CLK, CE, PRESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else if (CE) + Q <= D; + end +endmodule // DFFPE (positive clock edge; asynchronous preset; clock enable) + + +module DFFC (output reg Q, input D, CLK, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFC (positive clock edge; asynchronous clear) + + +module DFFCE (output reg Q, input D, CLK, CE, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(posedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable) + // TODO add more DFF sim cells module VCC(output V); -- cgit v1.2.3 From 96efa63f16ae30927759b374c86a68753199d0d2 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Fri, 6 Sep 2019 10:55:04 +0200 Subject: fix BRAM width and init --- techlibs/gowin/brams_map.v | 38 +++++++++++++++++++++++++++----------- techlibs/gowin/synth_gowin.cc | 2 +- 2 files changed, 28 insertions(+), 12 deletions(-) diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v index c60330b4f..6c5e4733a 100644 --- a/techlibs/gowin/brams_map.v +++ b/techlibs/gowin/brams_map.v @@ -8,23 +8,24 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); parameter CFG_ABITS = 10; parameter CFG_DBITS = 16; - parameter CFG_ENABLE_A = 3; - - parameter [16383:0] INIT = 16384'hx; - parameter CLKPOL2 = 1; - parameter CLKPOL3 = 1; + parameter CFG_ENABLE_A = 1; + parameter [16383:0] INIT = 16384'hx; + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; input CLK2; input CLK3; input [CFG_ABITS-1:0] A1ADDR; input [CFG_DBITS-1:0] A1DATA; - input [CFG_ENABLE_A-1:0] A1EN; + input [CFG_ENABLE_A-1:0] A1EN; input [CFG_ABITS-1:0] B1ADDR; output [CFG_DBITS-1:0] B1DATA; input B1EN; + wire [31-CFG_DBITS:0] open; + generate if (CFG_DBITS == 1) begin SDP #( @@ -39,7 +40,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .CEA(1'b1), .WREB(1'b0), .CEB(B1EN), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else if (CFG_DBITS == 2) begin SDP #( @@ -54,7 +58,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .CEA(1'b1), .WREB(1'b0), .CEB(B1EN), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else if (CFG_DBITS <= 4) begin SDP #( @@ -69,7 +76,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .WREB(1'b0), .CEB(B1EN), .CEA(1'b1), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else if (CFG_DBITS <= 8) begin SDP #( @@ -84,7 +94,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .CEA(1'b1), .WREB(1'b0), .CEB(B1EN), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else if (CFG_DBITS <= 16) begin SDP #( @@ -99,7 +112,10 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .WREA(A1EN), .OCE(1'b0), .WREB(1'b0), .CEB(B1EN), .CEA(1'b1), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), - .DI(A1DATA), .DO(B1DATA), .ADA(A1ADDR), .ADB(B1ADDR) + .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), + .DO({open, B1DATA}), + .ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, 2'b11}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else begin wire TECHMAP_FAIL = 1'b1; diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index cfddcec12..f67627e8a 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -211,7 +211,7 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_cells")) { run("techmap -map +/gowin/cells_map.v"); - run("setundef -undriven -zero"); + run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); -- cgit v1.2.3 From 2fb20f184aad4e0286afb6b44712cf5bffb531f4 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Fri, 6 Sep 2019 11:28:17 +0200 Subject: Revert "add MUX support" It turns out that they make everything worse and they don't PnR. This reverts commit 3eff2271d0fe25632f7e6b22cf0be078d2cd9990. --- techlibs/gowin/cells_map.v | 3 --- techlibs/gowin/cells_sim.v | 13 ------------- techlibs/gowin/synth_gowin.cc | 1 - 3 files changed, 17 deletions(-) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index 08eb0a9c3..dc0e16db8 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -50,9 +50,6 @@ module \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D module \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule -module \$_MUX_ (input A, B, S, output Y); MUX2 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .S0(S), .O(Y)); endmodule -module \$_MUX4_ (input A, B, C, D, S, T, output Y); MUX4 _TECHMAP_REPLACE_ (.I0(A), .I1(B), .I2(C), .I3(D), .S0(S), .S1(T), .O(Y)); endmodule - module \$lut (A, Y); parameter WIDTH = 0; parameter LUT = 0; diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index a2f60b99e..b70d1299c 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -24,19 +24,6 @@ module LUT4(output F, input I0, I1, I2, I3); assign F = I0 ? s1[1] : s1[0]; endmodule -module MUX2 (I0, I1, S0, O); -input I0, I1, S0; -output O; -assign O = S0 ? I1 : I0; -endmodule - -module MUX4 (I0, I1, I2, I3, S0, S1, O); -input I0, I1, I2, I3, S0, S1; -output O; -assign O = S1 ? (S0 ? I3 : I2) : - (S0 ? I1 : I0); -endmodule - module DFF (output reg Q, input CLK, D); parameter [0:0] INIT = 1'b0; initial Q = INIT; diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index f67627e8a..e93225fab 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -196,7 +196,6 @@ struct SynthGowinPass : public ScriptPass run("opt_clean"); if (!nodffe) run("dff2dffe -direct-match $_DFF_* -direct-match $__DFFS_*"); - run("muxcover -mux4"); run("techmap -map +/gowin/cells_map.v"); run("opt_expr -mux_undef"); run("simplemap"); -- cgit v1.2.3 From c597c2f2ae10111b2dc28e9738ea336d8ad22b31 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 17 Sep 2019 12:19:31 +0300 Subject: adffs test update (equiv_opt -multiclock). div_mod test fix --- tests/ecp5/adffs.v | 18 +++++++----------- tests/ecp5/adffs.ys | 5 ++--- tests/ecp5/div_mod.ys | 6 +++--- 3 files changed, 12 insertions(+), 17 deletions(-) diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/ecp5/adffs.v +++ b/tests/ecp5/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index 7ec2b0114..fc1363a32 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,10 +1,9 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 4 t:TRELLIS_FF -select -assert-count 7 t:LUT4 +select -assert-count 3 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys index fb13be5d5..9efb00701 100644 --- a/tests/ecp5/div_mod.ys +++ b/tests/ecp5/div_mod.ys @@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 28 t:CCU2C -select -assert-count 48 t:L6MUX21 -select -assert-count 194 t:LUT4 -select -assert-count 84 t:PFUMX +select -assert-count 26 t:L6MUX21 +select -assert-count 138 t:LUT4 +select -assert-count 60 t:PFUMX select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D -- cgit v1.2.3 From 5eb91fa69fc62482d09c1927b3a6f8164dee9408 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 18 Sep 2019 12:16:04 +0300 Subject: Add comment to dpram test about related issue. --- tests/ecp5/dpram.ys | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys index 786dee134..3bc6bc1d0 100644 --- a/tests/ecp5/dpram.ys +++ b/tests/ecp5/dpram.ys @@ -8,6 +8,7 @@ opt -full miter -equiv -flatten -make_assert -make_outputs gold gate miter +#Blocked by issue #1358 (Missing ECP5 simulation models) #ERROR: Failed to import cell gate.mem.0.0.0 (type DP16KD) to SAT database. #sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter -- cgit v1.2.3 From 4f426c2ac48bbb5ae9e92ca046aa20af35d75a52 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sun, 22 Sep 2019 16:52:06 +0000 Subject: write_verilog: do not print (*init*) attributes on regs. If an init value is emitted for a reg, an (*init*) attribute is never necessary, since it is exactly equivalent. On the other hand, some tools that consume Verilog (ISE, Vivado, Quartus) complain about (*init*) attributes because their interpretation differs from Yosys. All (*init*) attributes that would not become reg init values anyway are emitted as before. --- backends/verilog/verilog_backend.cc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 7b1db4776..24e397bda 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -371,13 +371,14 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig) } } -void dump_attributes(std::ostream &f, std::string indent, dict &attributes, char term = '\n', bool modattr = false, bool as_comment = false) +void dump_attributes(std::ostream &f, std::string indent, dict &attributes, char term = '\n', bool modattr = false, bool regattr = false, bool as_comment = false) { if (noattr) return; if (attr2comment) as_comment = true; for (auto it = attributes.begin(); it != attributes.end(); ++it) { + if (it->first == "\\init" && regattr) continue; f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str()); f << stringf(" = "); if (modattr && (it->second == State::S0 || it->second == Const(0))) @@ -392,7 +393,7 @@ void dump_attributes(std::ostream &f, std::string indent, dictattributes); + dump_attributes(f, indent, wire->attributes, '\n', /*modattr=*/false, /*regattr=*/reg_wires.count(wire->name)); #if 0 if (wire->port_input && !wire->port_output) f << stringf("%s" "input %s", indent.c_str(), reg_wires.count(wire->name) ? "reg " : ""); @@ -1521,7 +1522,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw bool got_default = false; for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) { - dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*as_comment=*/true); + dump_attributes(f, indent + " ", (*it)->attributes, '\n', /*modattr=*/false, /*regattr=*/false, /*as_comment=*/true); if ((*it)->compare.size() == 0) { if (got_default) continue; @@ -1686,7 +1687,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module) } } - dump_attributes(f, indent, module->attributes, '\n', /*attr2comment=*/true); + dump_attributes(f, indent, module->attributes, '\n', /*modattr=*/true); f << stringf("%s" "module %s(", indent.c_str(), id(module->name, false).c_str()); bool keep_running = true; for (int port_id = 1; keep_running; port_id++) { -- cgit v1.2.3 From 27377c46634263beb5f8c28cb34b0c87ed6e9525 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 23 Sep 2019 12:12:02 +0300 Subject: Add new tests for Anlogic architecture Problems/questions: - memory.ys: ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. Why EG_LOGIC_DRAM16X4, not AL_LOGIC_BRAM? - Internal cell type $_TBUF_ is present. --- Makefile | 1 + tests/anlogic/.gitignore | 4 ++ tests/anlogic/add_sub.v | 13 ++++++ tests/anlogic/add_sub.ys | 9 +++++ tests/anlogic/alu.v | 19 +++++++++ tests/anlogic/alu.ys | 17 ++++++++ tests/anlogic/counter.v | 17 ++++++++ tests/anlogic/counter.ys | 11 +++++ tests/anlogic/dffs.v | 37 +++++++++++++++++ tests/anlogic/dffs.ys | 10 +++++ tests/anlogic/fsm.v | 73 +++++++++++++++++++++++++++++++++ tests/anlogic/fsm.ys | 14 +++++++ tests/anlogic/latches.v | 58 +++++++++++++++++++++++++++ tests/anlogic/latches.ys | 16 ++++++++ tests/anlogic/memory.v | 21 ++++++++++ tests/anlogic/memory.ys | 21 ++++++++++ tests/anlogic/mux.v | 100 ++++++++++++++++++++++++++++++++++++++++++++++ tests/anlogic/mux.ys | 12 ++++++ tests/anlogic/run-test.sh | 20 ++++++++++ tests/anlogic/shifter.v | 22 ++++++++++ tests/anlogic/shifter.ys | 9 +++++ tests/anlogic/tribuf.v | 23 +++++++++++ tests/anlogic/tribuf.ys | 9 +++++ 23 files changed, 536 insertions(+) create mode 100644 tests/anlogic/.gitignore create mode 100644 tests/anlogic/add_sub.v create mode 100644 tests/anlogic/add_sub.ys create mode 100644 tests/anlogic/alu.v create mode 100644 tests/anlogic/alu.ys create mode 100644 tests/anlogic/counter.v create mode 100644 tests/anlogic/counter.ys create mode 100644 tests/anlogic/dffs.v create mode 100644 tests/anlogic/dffs.ys create mode 100644 tests/anlogic/fsm.v create mode 100644 tests/anlogic/fsm.ys create mode 100644 tests/anlogic/latches.v create mode 100644 tests/anlogic/latches.ys create mode 100644 tests/anlogic/memory.v create mode 100644 tests/anlogic/memory.ys create mode 100644 tests/anlogic/mux.v create mode 100644 tests/anlogic/mux.ys create mode 100755 tests/anlogic/run-test.sh create mode 100644 tests/anlogic/shifter.v create mode 100644 tests/anlogic/shifter.ys create mode 100644 tests/anlogic/tribuf.v create mode 100644 tests/anlogic/tribuf.ys diff --git a/Makefile b/Makefile index 2cac80f0f..742692f0d 100644 --- a/Makefile +++ b/Makefile @@ -710,6 +710,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/anlogic && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/anlogic/.gitignore b/tests/anlogic/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/anlogic/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/anlogic/add_sub.v b/tests/anlogic/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/anlogic/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys new file mode 100644 index 000000000..55c090506 --- /dev/null +++ b/tests/anlogic/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:AL_MAP_ADDER +select -assert-count 4 t:AL_MAP_LUT1 +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D + diff --git a/tests/anlogic/alu.v b/tests/anlogic/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/anlogic/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/anlogic/alu.ys b/tests/anlogic/alu.ys new file mode 100644 index 000000000..532ce82d5 --- /dev/null +++ b/tests/anlogic/alu.ys @@ -0,0 +1,17 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 66 t:AL_MAP_ADDER +select -assert-count 32 t:AL_MAP_LUT1 +select -assert-count 23 t:AL_MAP_LUT2 +select -assert-count 61 t:AL_MAP_LUT3 +select -assert-count 209 t:AL_MAP_LUT4 +select -assert-count 100 t:AL_MAP_LUT5 +select -assert-count 79 t:AL_MAP_LUT6 +select -assert-count 32 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/counter.v b/tests/anlogic/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/anlogic/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys new file mode 100644 index 000000000..5210221e3 --- /dev/null +++ b/tests/anlogic/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:AL_MAP_ADDER +select -assert-count 8 t:AL_MAP_SEQ +select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/anlogic/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys new file mode 100644 index 000000000..a15c6f24e --- /dev/null +++ b/tests/anlogic/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 2 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/anlogic/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys new file mode 100644 index 000000000..6eb7b9a71 --- /dev/null +++ b/tests/anlogic/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT2 +select -assert-count 5 t:AL_MAP_LUT5 +select -assert-count 1 t:AL_MAP_LUT6 +select -assert-count 6 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/anlogic/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys new file mode 100644 index 000000000..b5e52cf16 --- /dev/null +++ b/tests/anlogic/latches.ys @@ -0,0 +1,16 @@ +read_verilog latches.v +design -save read + +proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock +flatten +synth_anlogic +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read +synth_anlogic +cd top +select -assert-count 2 t:AL_MAP_LUT3 +select -assert-count 1 t:AL_MAP_LUT5 +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D diff --git a/tests/anlogic/memory.v b/tests/anlogic/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/anlogic/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/anlogic/memory.ys b/tests/anlogic/memory.ys new file mode 100644 index 000000000..8c0ce844e --- /dev/null +++ b/tests/anlogic/memory.ys @@ -0,0 +1,21 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top + +select -assert-count 8 t:AL_MAP_LUT2 +select -assert-count 8 t:AL_MAP_LUT4 +select -assert-count 8 t:AL_MAP_LUT5 +select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/anlogic/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys new file mode 100644 index 000000000..84a8bcccf --- /dev/null +++ b/tests/anlogic/mux.ys @@ -0,0 +1,12 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 4 t:AL_MAP_LUT4 +select -assert-count 4 t:AL_MAP_LUT5 +select -assert-count 1 t:AL_MAP_LUT6 +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D diff --git a/tests/anlogic/run-test.sh b/tests/anlogic/run-test.sh new file mode 100755 index 000000000..2c72ca3a9 --- /dev/null +++ b/tests/anlogic/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/anlogic/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys new file mode 100644 index 000000000..edd89b344 --- /dev/null +++ b/tests/anlogic/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/anlogic/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys new file mode 100644 index 000000000..663e93fb2 --- /dev/null +++ b/tests/anlogic/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 1070f2e90b9ba37856932189ef09a0f2316d9a21 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 23 Sep 2019 15:51:41 +0300 Subject: Add new tests for Efinix architecture. Problems/questions: - fsm.ys. equiv_opt -assert failed because of unproven cells; - latches.ys,tribuf.ys - internal cells present; - memory.ys - sat called with -verify and proof did fail. --- Makefile | 1 + tests/efinix/.gitignore | 3 ++ tests/efinix/add_sub.v | 13 ++++++ tests/efinix/add_sub.ys | 9 +++++ tests/efinix/adffs.v | 87 +++++++++++++++++++++++++++++++++++++++++ tests/efinix/adffs.ys | 12 ++++++ tests/efinix/alu.v | 19 +++++++++ tests/efinix/alu.ys | 13 ++++++ tests/efinix/counter.v | 17 ++++++++ tests/efinix/counter.ys | 12 ++++++ tests/efinix/dffs.v | 37 ++++++++++++++++++ tests/efinix/dffs.ys | 12 ++++++ tests/efinix/div_mod.v | 13 ++++++ tests/efinix/div_mod.ys | 10 +++++ tests/efinix/fsm.v | 73 ++++++++++++++++++++++++++++++++++ tests/efinix/fsm.ys | 14 +++++++ tests/efinix/latches.v | 58 +++++++++++++++++++++++++++ tests/efinix/latches.ys | 20 ++++++++++ tests/efinix/logic.v | 18 +++++++++ tests/efinix/logic.ys | 8 ++++ tests/efinix/memory.v | 21 ++++++++++ tests/efinix/memory.ys | 18 +++++++++ tests/efinix/mul.v | 11 ++++++ tests/efinix/mul.ys | 9 +++++ tests/efinix/mux.v | 100 +++++++++++++++++++++++++++++++++++++++++++++++ tests/efinix/mux.ys | 8 ++++ tests/efinix/run-test.sh | 20 ++++++++++ tests/efinix/shifter.v | 22 +++++++++++ tests/efinix/shifter.ys | 11 ++++++ tests/efinix/tribuf.v | 29 ++++++++++++++ tests/efinix/tribuf.ys | 12 ++++++ 31 files changed, 710 insertions(+) create mode 100644 tests/efinix/.gitignore create mode 100644 tests/efinix/add_sub.v create mode 100644 tests/efinix/add_sub.ys create mode 100644 tests/efinix/adffs.v create mode 100644 tests/efinix/adffs.ys create mode 100644 tests/efinix/alu.v create mode 100644 tests/efinix/alu.ys create mode 100644 tests/efinix/counter.v create mode 100644 tests/efinix/counter.ys create mode 100644 tests/efinix/dffs.v create mode 100644 tests/efinix/dffs.ys create mode 100644 tests/efinix/div_mod.v create mode 100644 tests/efinix/div_mod.ys create mode 100644 tests/efinix/fsm.v create mode 100644 tests/efinix/fsm.ys create mode 100644 tests/efinix/latches.v create mode 100644 tests/efinix/latches.ys create mode 100644 tests/efinix/logic.v create mode 100644 tests/efinix/logic.ys create mode 100644 tests/efinix/memory.v create mode 100644 tests/efinix/memory.ys create mode 100644 tests/efinix/mul.v create mode 100644 tests/efinix/mul.ys create mode 100644 tests/efinix/mux.v create mode 100644 tests/efinix/mux.ys create mode 100755 tests/efinix/run-test.sh create mode 100644 tests/efinix/shifter.v create mode 100644 tests/efinix/shifter.ys create mode 100644 tests/efinix/tribuf.v create mode 100644 tests/efinix/tribuf.ys diff --git a/Makefile b/Makefile index 2cac80f0f..1be01a86c 100644 --- a/Makefile +++ b/Makefile @@ -710,6 +710,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/efinix && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/efinix/.gitignore b/tests/efinix/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/efinix/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/efinix/add_sub.v b/tests/efinix/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/efinix/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/efinix/add_sub.ys b/tests/efinix/add_sub.ys new file mode 100644 index 000000000..67fa9f2e7 --- /dev/null +++ b/tests/efinix/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:EFX_ADD +select -assert-count 4 t:EFX_LUT4 +select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D + diff --git a/tests/efinix/adffs.v b/tests/efinix/adffs.v new file mode 100644 index 000000000..05e68caf7 --- /dev/null +++ b/tests/efinix/adffs.v @@ -0,0 +1,87 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffs u_dffs ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnr u_ndffnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys new file mode 100644 index 000000000..642faa76b --- /dev/null +++ b/tests/efinix/adffs.ys @@ -0,0 +1,12 @@ +read_verilog adffs.v +proc +#async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -multiclock -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 4 t:EFX_FF +select -assert-count 2 t:EFX_LUT4 +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/alu.v b/tests/efinix/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/efinix/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/efinix/alu.ys b/tests/efinix/alu.ys new file mode 100644 index 000000000..0d58a7c8a --- /dev/null +++ b/tests/efinix/alu.ys @@ -0,0 +1,13 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 66 t:EFX_ADD +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 32 t:EFX_FF +select -assert-count 605 t:EFX_LUT4 +select -assert-none t:EFX_ADD t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/counter.v b/tests/efinix/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/efinix/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/efinix/counter.ys b/tests/efinix/counter.ys new file mode 100644 index 000000000..82e61d39b --- /dev/null +++ b/tests/efinix/counter.ys @@ -0,0 +1,12 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 8 t:EFX_FF +select -assert-count 9 t:EFX_ADD +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D diff --git a/tests/efinix/dffs.v b/tests/efinix/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/efinix/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys new file mode 100644 index 000000000..557dfd3d0 --- /dev/null +++ b/tests/efinix/dffs.ys @@ -0,0 +1,12 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 2 t:EFX_FF +select -assert-count 1 t:EFX_LUT4 +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/div_mod.v b/tests/efinix/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/efinix/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/efinix/div_mod.ys b/tests/efinix/div_mod.ys new file mode 100644 index 000000000..3b6f2f0f4 --- /dev/null +++ b/tests/efinix/div_mod.ys @@ -0,0 +1,10 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 95 t:EFX_ADD +select -assert-count 114 t:EFX_LUT4 +select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/fsm.v b/tests/efinix/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/efinix/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/efinix/fsm.ys b/tests/efinix/fsm.ys new file mode 100644 index 000000000..9de6aa280 --- /dev/null +++ b/tests/efinix/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 6 t:EFX_FF +select -assert-count 15 t:EFX_LUT4 +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/latches.v b/tests/efinix/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/efinix/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule diff --git a/tests/efinix/latches.ys b/tests/efinix/latches.ys new file mode 100644 index 000000000..2867ec93e --- /dev/null +++ b/tests/efinix/latches.ys @@ -0,0 +1,20 @@ +read_verilog latches.v +design -save read + +proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock +flatten +synth_efinix +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read + +synth_efinix +flatten +cd top +#Internall cell type $_DLATCH_P_. Should be realized by using LUTs. +#The same result by using just synth_efinix. +select -assert-count 3 t:$_DLATCH_P_ +select -assert-count 3 t:EFX_LUT4 +select -assert-none t:$_DLATCH_P_ t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/logic.v b/tests/efinix/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/efinix/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys new file mode 100644 index 000000000..c2a7f5169 --- /dev/null +++ b/tests/efinix/logic.ys @@ -0,0 +1,8 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:EFX_LUT4 +select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/memory.v b/tests/efinix/memory.v new file mode 100644 index 000000000..5634d6507 --- /dev/null +++ b/tests/efinix/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [8:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/efinix/memory.ys b/tests/efinix/memory.ys new file mode 100644 index 000000000..fe24b0a9b --- /dev/null +++ b/tests/efinix/memory.ys @@ -0,0 +1,18 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_RAM_5K +select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/efinix/mul.v b/tests/efinix/mul.v new file mode 100644 index 000000000..0f1618698 --- /dev/null +++ b/tests/efinix/mul.v @@ -0,0 +1,11 @@ +module top +( + input [7:0] x, + input [7:0] y, + + output [15:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/efinix/mul.ys b/tests/efinix/mul.ys new file mode 100644 index 000000000..7d349f3f8 --- /dev/null +++ b/tests/efinix/mul.ys @@ -0,0 +1,9 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 17 t:EFX_ADD +select -assert-count 149 t:EFX_LUT4 +select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/mux.v b/tests/efinix/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/efinix/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/efinix/mux.ys b/tests/efinix/mux.ys new file mode 100644 index 000000000..a2d653568 --- /dev/null +++ b/tests/efinix/mux.ys @@ -0,0 +1,8 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 13 t:EFX_LUT4 +select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/run-test.sh b/tests/efinix/run-test.sh new file mode 100755 index 000000000..ea56b70f0 --- /dev/null +++ b/tests/efinix/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/efinix/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/efinix/shifter.ys b/tests/efinix/shifter.ys new file mode 100644 index 000000000..1a6b5565c --- /dev/null +++ b/tests/efinix/shifter.ys @@ -0,0 +1,11 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 8 t:EFX_FF +select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D diff --git a/tests/efinix/tribuf.v b/tests/efinix/tribuf.v new file mode 100644 index 000000000..3fa6eb6c6 --- /dev/null +++ b/tests/efinix/tribuf.v @@ -0,0 +1,29 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; +`ifndef BUG + + always @(en or i) + o <= (en)? i : 1'bZ; +`else + + always @(en or i) + o <= (en)? ~i : 1'bZ; +`endif +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/efinix/tribuf.ys b/tests/efinix/tribuf.ys new file mode 100644 index 000000000..20d4f215d --- /dev/null +++ b/tests/efinix/tribuf.ys @@ -0,0 +1,12 @@ +read_verilog tribuf.v +hierarchy -top top +proc +tribuf +flatten +synth +equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From eeb86247c59f7ea7f98c05eaa456d0ebe041d149 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 15:14:41 -0700 Subject: Update fsm.ys resource count --- tests/ecp5/fsm.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index bdd910163..36b10c0ce 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -8,7 +8,7 @@ equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 -select -assert-count 15 t:LUT4 -select -assert-count 6 t:PFUMX -select -assert-count 6 t:TRELLIS_FF +select -assert-count 13 t:LUT4 +select -assert-count 5 t:PFUMX +select -assert-count 5 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D -- cgit v1.2.3 From d992858318c9fae869a7d0d4ed046ed8c5ea5811 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 15:15:14 -0700 Subject: Move $x to end as per 7f0eec8 --- tests/ecp5/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/ecp5/run-test.sh b/tests/ecp5/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/ecp5/run-test.sh +++ b/tests/ecp5/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From f8d5e11aa7285fc92832b87063d530afe27eca28 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:54:04 -0700 Subject: Update resource count for alu.ys --- tests/ecp5/alu.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys index d10cd63b2..c2950b164 100644 --- a/tests/ecp5/alu.ys +++ b/tests/ecp5/alu.ys @@ -6,8 +6,8 @@ equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 32 t:CCU2C -select -assert-count 253 t:L6MUX21 -select -assert-count 1150 t:LUT4 -select -assert-count 423 t:PFUMX +select -assert-count 242 t:L6MUX21 +select -assert-count 1127 t:LUT4 +select -assert-count 417 t:PFUMX select -assert-count 32 t:TRELLIS_FF select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D -- cgit v1.2.3 From 1caaf5149258ff84ac2a6532c26e9ffb076183a9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:54:59 -0700 Subject: equiv_opt with -assert --- tests/ecp5/fsm.ys | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 36b10c0ce..6368edc57 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -2,9 +2,7 @@ read_verilog fsm.v hierarchy -top top proc flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 -- cgit v1.2.3 From fc56459746fec7751735749e3328378e1089b914 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Tue, 1 Oct 2019 10:55:34 +0300 Subject: run-test.sh Move $x at end of line. --- tests/anlogic/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/anlogic/run-test.sh b/tests/anlogic/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/anlogic/run-test.sh +++ b/tests/anlogic/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From eb750670e3835a1bad36cb604e04bf4836cc7f91 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Tue, 1 Oct 2019 11:14:12 +0300 Subject: run-test.sh Move $x at end of line. --- tests/efinix/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/efinix/run-test.sh b/tests/efinix/run-test.sh index ea56b70f0..46716f9a0 100755 --- a/tests/efinix/run-test.sh +++ b/tests/efinix/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From f6b5e47e40b4a2bda6e5d928480ea218a6a911c2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 20:43:13 +0100 Subject: sv: Switch parser to glr, prep for typedef Signed-off-by: David Shah --- frontends/ast/ast.cc | 3 +++ frontends/ast/ast.h | 7 ++++-- frontends/ast/genrtlil.cc | 1 + frontends/ast/simplify.cc | 51 ++++++++++++++++++++++++++++++++++---- frontends/verilog/verilog_parser.y | 38 +++++++++++++++++++++++++--- tests/svtypes/typedef1.sv | 22 ++++++++++++++++ 6 files changed, 111 insertions(+), 11 deletions(-) create mode 100644 tests/svtypes/typedef1.sv diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 21279cbfa..937dad9be 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -164,6 +164,8 @@ std::string AST::type2str(AstNodeType type) X(AST_MODPORT) X(AST_MODPORTMEMBER) X(AST_PACKAGE) + X(AST_WIRETYPE) + X(AST_TYPEDEF) #undef X default: log_abort(); @@ -206,6 +208,7 @@ AstNode::AstNode(AstNodeType type, AstNode *child1, AstNode *child2, AstNode *ch was_checked = false; range_valid = false; range_swapped = false; + is_custom_type = false; port_id = 0; range_left = -1; range_right = 0; diff --git a/frontends/ast/ast.h b/frontends/ast/ast.h index 93fee913e..fcc661b4c 100644 --- a/frontends/ast/ast.h +++ b/frontends/ast/ast.h @@ -148,7 +148,10 @@ namespace AST AST_INTERFACEPORTTYPE, AST_MODPORT, AST_MODPORTMEMBER, - AST_PACKAGE + AST_PACKAGE, + + AST_WIRETYPE, + AST_TYPEDEF }; // convert an node type to a string (e.g. for debug output) @@ -174,7 +177,7 @@ namespace AST // node content - most of it is unused in most node types std::string str; std::vector bits; - bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized; + bool is_input, is_output, is_reg, is_logic, is_signed, is_string, is_wand, is_wor, range_valid, range_swapped, was_checked, is_unsized, is_custom_type; int port_id, range_left, range_right; uint32_t integer; double realvalue; diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 407a34472..94f5c0a04 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -863,6 +863,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint) case AST_PACKAGE: case AST_MODPORT: case AST_MODPORTMEMBER: + case AST_TYPEDEF: break; case AST_INTERFACEPORT: { // If a port in a module with unknown type is found, mark it with the attribute 'is_interface' diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index b1ee22f42..b94662bcd 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -318,7 +318,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } // activate const folding if this is anything that must be evaluated statically (ranges, parameters, attributes, etc.) - if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX) + if (type == AST_WIRE || type == AST_PARAMETER || type == AST_LOCALPARAM || type == AST_DEFPARAM || type == AST_PARASET || type == AST_RANGE || type == AST_PREFIX || type == AST_TYPEDEF) const_fold = true; if (type == AST_IDENTIFIER && current_scope.count(str) > 0 && (current_scope[str]->type == AST_PARAMETER || current_scope[str]->type == AST_LOCALPARAM)) const_fold = true; @@ -336,6 +336,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, std::map this_wire_scope; for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; + if (node->type == AST_WIRE) { if (node->children.size() == 1 && node->children[0]->type == AST_RANGE) { for (auto c : node->children[0]->children) { @@ -405,14 +406,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, this_wire_scope[node->str] = node; } if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_GENVAR || - node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_DPI_FUNCTION || node->type == AST_CELL) { + node->type == AST_MEMORY || node->type == AST_FUNCTION || node->type == AST_TASK || node->type == AST_DPI_FUNCTION || node->type == AST_CELL || + node->type == AST_TYPEDEF) { backup_scope[node->str] = current_scope[node->str]; current_scope[node->str] = node; } } for (size_t i = 0; i < children.size(); i++) { AstNode *node = children[i]; - if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY) + if (node->type == AST_PARAMETER || node->type == AST_LOCALPARAM || node->type == AST_WIRE || node->type == AST_AUTOWIRE || node->type == AST_MEMORY || node->type == AST_TYPEDEF) while (node->simplify(true, false, false, 1, -1, false, node->type == AST_PARAMETER || node->type == AST_LOCALPARAM)) did_something = true; } @@ -780,6 +782,44 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, delete_children(); } + // resolve typedefs + if (type == AST_TYPEDEF) { + log_assert(children.size() == 1); + log_assert(children[0]->type == AST_WIRE); + while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + log_assert(!children[0]->is_custom_type); + } + + // resolve types of wires and parameters + if (type == AST_WIRE || type == AST_LOCALPARAM || type == AST_PARAMETER) { + if (is_custom_type) { + log_assert(children.size() == 1); + log_assert(children[0]->type == AST_WIRETYPE); + if (!current_scope.count(children[0]->str)) + log_file_error(filename, linenum, "Unknown identifier `%s' used as type name", children[0]->str.c_str()); + AstNode *resolved_type = current_scope.at(children[0]->str); + if (resolved_type->type != AST_TYPEDEF) + log_file_error(filename, linenum, "`%s' does not name a type", children[0]->str.c_str()); + log_assert(resolved_type->children.size() == 1); + AstNode *templ = resolved_type->children[0]; + delete_children(); // type reference no longer needed + + is_reg = templ->is_reg; + is_logic = templ->is_logic; + is_signed = templ->is_signed; + is_string = templ->is_string; + is_custom_type = templ->is_custom_type; + + range_valid = templ->range_valid; + range_swapped = templ->range_swapped; + range_left = templ->range_left; + range_right = templ->range_right; + for (auto template_child : templ->children) + children.push_back(template_child->clone()); + } + log_assert(!is_custom_type); + } + // resolve constant prefixes if (type == AST_PREFIX) { if (children[0]->type != AST_CONSTANT) { @@ -1194,7 +1234,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_BLOCK && str.empty()) { for (size_t i = 0; i < children.size(); i++) - if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM) + if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) log_file_error(children[i]->filename, children[i]->linenum, "Local declaration in unnamed block is an unsupported SystemVerilog feature!\n"); } @@ -1206,7 +1246,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, std::vector new_children; for (size_t i = 0; i < children.size(); i++) - if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM) { + if (children[i]->type == AST_WIRE || children[i]->type == AST_MEMORY || children[i]->type == AST_PARAMETER || children[i]->type == AST_LOCALPARAM || children[i]->type == AST_TYPEDEF) { children[i]->simplify(false, false, false, stage, -1, false, false); current_ast_mod->children.push_back(children[i]); current_scope[children[i]->str] = children[i]; @@ -2945,6 +2985,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma child->expand_genblock(index_var, prefix, name_map); } + if (backup_name_map.size() > 0) name_map.swap(backup_name_map); } diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 4afd72b73..eb091bea6 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -112,6 +112,8 @@ struct specify_rise_fall { %define api.prefix {frontend_verilog_yy} +%glr-parser + /* The union is defined in the header, so we need to provide all the * includes it requires */ @@ -180,7 +182,7 @@ struct specify_rise_fall { %right UNARY_OPS %define parse.error verbose -%define parse.lac full +// %define parse.lac full %nonassoc FAKE_THEN %nonassoc TOK_ELSE @@ -206,6 +208,7 @@ design: task_func_decl design | param_decl design | localparam_decl design | + typedef_decl design | package design | interface design | /* empty */; @@ -426,6 +429,7 @@ package_body: package_body package_body_stmt |; package_body_stmt: + typedef_decl | localparam_decl; interface: @@ -452,7 +456,7 @@ interface_body: interface_body interface_body_stmt |; interface_body_stmt: - param_decl | localparam_decl | defparam_decl | wire_decl | always_stmt | assign_stmt | + param_decl | localparam_decl | typedef_decl | defparam_decl | wire_decl | always_stmt | assign_stmt | modport_stmt; non_opt_delay: @@ -529,6 +533,11 @@ wire_type_token: } | TOK_CONST { current_wire_const = true; + } | + hierarchical_id { + astbuf3->is_custom_type = true; + astbuf3->children.push_back(new AstNode(AST_WIRETYPE)); + astbuf3->children.back()->str = *$1; }; non_opt_range: @@ -591,7 +600,7 @@ module_body: /* empty */; module_body_stmt: - task_func_decl | specify_block |param_decl | localparam_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | + task_func_decl | specify_block |param_decl | localparam_decl | typedef_decl | defparam_decl | specparam_declaration | wire_decl | assign_stmt | cell_stmt | always_stmt | TOK_GENERATE module_gen_body TOK_ENDGENERATE | defattr | assert_property | checker_decl | ignored_specify_block; checker_decl: @@ -1377,6 +1386,27 @@ assign_expr: ast_stack.back()->children.push_back(new AstNode(AST_ASSIGN, $1, $3)); }; +typedef_decl: + TOK_TYPEDEF wire_type range TOK_ID ';' { + astbuf1 = $2; + astbuf2 = $3; + if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { + if (astbuf2) { + frontend_verilog_yyerror("integer/genvar types cannot have packed dimensions."); + } else { + astbuf2 = new AstNode(AST_RANGE); + astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_left, true)); + astbuf2->children.push_back(AstNode::mkconst_int(astbuf1->range_right, true)); + } + } + if (astbuf2 && astbuf2->children.size() != 2) + frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [:], [+:], or [-:]"); + if (astbuf2) + astbuf1->children.push_back(astbuf2); + ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1)); + ast_stack.back()->children.back()->str = *$4; + }; + cell_stmt: attr TOK_ID { astbuf1 = new AstNode(AST_CELL); @@ -1823,7 +1853,7 @@ simple_behavioral_stmt: // this production creates the obligatory if-else shift/reduce conflict behavioral_stmt: - defattr | assert | wire_decl | param_decl | localparam_decl | + defattr | assert | wire_decl | param_decl | localparam_decl | typedef_decl | non_opt_delay behavioral_stmt | simple_behavioral_stmt ';' | ';' | hierarchical_id attr { diff --git a/tests/svtypes/typedef1.sv b/tests/svtypes/typedef1.sv new file mode 100644 index 000000000..9e5d02364 --- /dev/null +++ b/tests/svtypes/typedef1.sv @@ -0,0 +1,22 @@ +`define STRINGIFY(x) `"x`" +`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) + +module top; + + typedef logic [1:0] uint2_t; + typedef logic signed [3:0] int4_t; + typedef logic signed [7:0] int8_t; + typedef int8_t char_t; + + (* keep *) uint2_t int2 = 2'b10; + (* keep *) int4_t int4 = -1; + (* keep *) int8_t int8 = int4; + (* keep *) char_t ch = int8; + + + always @* assert(int2 == 2'b10); + always @* assert(int4 == 4'b1111); + always @* assert(int8 == 8'b11111111); + always @* assert(ch == 8'b11111111); + +endmodule \ No newline at end of file -- cgit v1.2.3 From c9629516120930aedaf52d72fec5d7fabe51d496 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 21:07:20 +0100 Subject: sv: Fix typedef parameters Signed-off-by: David Shah --- frontends/ast/simplify.cc | 33 +++++++++++++++++++++++++++++++-- frontends/verilog/verilog_parser.y | 21 +++++++++++++++++---- tests/svtypes/typedef1.sv | 22 ---------------------- tests/svtypes/typedef_param.sv | 22 ++++++++++++++++++++++ tests/svtypes/typedef_simple.sv | 19 +++++++++++++++++++ 5 files changed, 89 insertions(+), 28 deletions(-) delete mode 100644 tests/svtypes/typedef1.sv create mode 100644 tests/svtypes/typedef_param.sv create mode 100644 tests/svtypes/typedef_simple.sv diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index b94662bcd..9abd2916d 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -790,8 +790,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(!children[0]->is_custom_type); } - // resolve types of wires and parameters - if (type == AST_WIRE || type == AST_LOCALPARAM || type == AST_PARAMETER) { + // resolve types of wires + if (type == AST_WIRE) { if (is_custom_type) { log_assert(children.size() == 1); log_assert(children[0]->type == AST_WIRETYPE); @@ -820,6 +820,35 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(!is_custom_type); } + // resolve types of parameters + if (type == AST_LOCALPARAM || type == AST_PARAMETER) { + if (is_custom_type) { + log_assert(children.size() == 2); + log_assert(children[1]->type == AST_WIRETYPE); + if (!current_scope.count(children[1]->str)) + log_file_error(filename, linenum, "Unknown identifier `%s' used as type name", children[1]->str.c_str()); + AstNode *resolved_type = current_scope.at(children[1]->str); + if (resolved_type->type != AST_TYPEDEF) + log_file_error(filename, linenum, "`%s' does not name a type", children[1]->str.c_str()); + log_assert(resolved_type->children.size() == 1); + AstNode *templ = resolved_type->children[0]; + delete children[1]; + children.pop_back(); + + is_signed = templ->is_signed; + is_string = templ->is_string; + is_custom_type = templ->is_custom_type; + + range_valid = templ->range_valid; + range_swapped = templ->range_swapped; + range_left = templ->range_left; + range_right = templ->range_right; + for (auto template_child : templ->children) + children.push_back(template_child->clone()); + } + log_assert(!is_custom_type); + } + // resolve constant prefixes if (type == AST_PREFIX) { if (children[0]->type != AST_CONSTANT) { diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index eb091bea6..8cc084fe0 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -327,13 +327,13 @@ single_module_para: astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); append_attr(astbuf1, $1); - } param_signed param_integer param_range single_param_decl | + } int_param_type single_param_decl | attr TOK_LOCALPARAM { if (astbuf1) delete astbuf1; astbuf1 = new AstNode(AST_LOCALPARAM); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); append_attr(astbuf1, $1); - } param_signed param_integer param_range single_param_decl | + } int_param_type single_param_decl | single_param_decl; module_args_opt: @@ -1158,12 +1158,25 @@ param_range: } }; +custom_param_type: + hierarchical_id { + astbuf1->is_custom_type = true; + astbuf1->children.push_back(new AstNode(AST_WIRETYPE)); + astbuf1->children.back()->str = *$1; + }; + +param_type: + param_signed param_integer param_real param_range | custom_param_type; + +int_param_type: + param_signed param_integer param_range | custom_param_type; + param_decl: attr TOK_PARAMETER { astbuf1 = new AstNode(AST_PARAMETER); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); append_attr(astbuf1, $1); - } param_signed param_integer param_real param_range param_decl_list ';' { + } param_type param_decl_list ';' { delete astbuf1; }; @@ -1172,7 +1185,7 @@ localparam_decl: astbuf1 = new AstNode(AST_LOCALPARAM); astbuf1->children.push_back(AstNode::mkconst_int(0, true)); append_attr(astbuf1, $1); - } param_signed param_integer param_real param_range param_decl_list ';' { + } param_type param_decl_list ';' { delete astbuf1; }; diff --git a/tests/svtypes/typedef1.sv b/tests/svtypes/typedef1.sv deleted file mode 100644 index 9e5d02364..000000000 --- a/tests/svtypes/typedef1.sv +++ /dev/null @@ -1,22 +0,0 @@ -`define STRINGIFY(x) `"x`" -`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) - -module top; - - typedef logic [1:0] uint2_t; - typedef logic signed [3:0] int4_t; - typedef logic signed [7:0] int8_t; - typedef int8_t char_t; - - (* keep *) uint2_t int2 = 2'b10; - (* keep *) int4_t int4 = -1; - (* keep *) int8_t int8 = int4; - (* keep *) char_t ch = int8; - - - always @* assert(int2 == 2'b10); - always @* assert(int4 == 4'b1111); - always @* assert(int8 == 8'b11111111); - always @* assert(ch == 8'b11111111); - -endmodule \ No newline at end of file diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv new file mode 100644 index 000000000..13a522f19 --- /dev/null +++ b/tests/svtypes/typedef_param.sv @@ -0,0 +1,22 @@ +`define STRINGIFY(x) `"x`" +`define STATIC_ASSERT(x) if(!(x)) $error({"assert failed: ", `STRINGIFY(x)}) + +module top; + + typedef logic [1:0] uint2_t; + typedef logic signed [3:0] int4_t; + typedef logic signed [7:0] int8_t; + typedef int8_t char_t; + + parameter uint2_t int2 = 2'b10; + localparam int4_t int4 = -1; + localparam int8_t int8 = int4; + localparam char_t ch = int8; + + + `STATIC_ASSERT(int2 == 2'b10); + `STATIC_ASSERT(int4 == 4'b1111); + `STATIC_ASSERT(int8 == 8'b11111111); + `STATIC_ASSERT(ch == 8'b11111111); + +endmodule \ No newline at end of file diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv new file mode 100644 index 000000000..0cf2c072c --- /dev/null +++ b/tests/svtypes/typedef_simple.sv @@ -0,0 +1,19 @@ +module top; + + typedef logic [1:0] uint2_t; + typedef logic signed [3:0] int4_t; + typedef logic signed [7:0] int8_t; + typedef int8_t char_t; + + (* keep *) uint2_t int2 = 2'b10; + (* keep *) int4_t int4 = -1; + (* keep *) int8_t int8 = int4; + (* keep *) char_t ch = int8; + + + always @* assert(int2 == 2'b10); + always @* assert(int4 == 4'b1111); + always @* assert(int8 == 8'b11111111); + always @* assert(ch == 8'b11111111); + +endmodule \ No newline at end of file -- cgit v1.2.3 From e70e4afb60a41da6d9f6200b20f36f61c6b993b2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 19 Sep 2019 21:21:21 +0100 Subject: sv: Fix typedefs in packages Signed-off-by: David Shah --- frontends/ast/simplify.cc | 14 ++++++++++---- tests/svtypes/typedef_package.sv | 11 +++++++++++ 2 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 tests/svtypes/typedef_package.sv diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 9abd2916d..44e32b29c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -796,14 +796,17 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children.size() == 1); log_assert(children[0]->type == AST_WIRETYPE); if (!current_scope.count(children[0]->str)) - log_file_error(filename, linenum, "Unknown identifier `%s' used as type name", children[0]->str.c_str()); + log_file_error(filename, linenum, "Unknown identifier `%s' used as type name\n", children[0]->str.c_str()); AstNode *resolved_type = current_scope.at(children[0]->str); if (resolved_type->type != AST_TYPEDEF) - log_file_error(filename, linenum, "`%s' does not name a type", children[0]->str.c_str()); + log_file_error(filename, linenum, "`%s' does not name a type\n", children[0]->str.c_str()); log_assert(resolved_type->children.size() == 1); AstNode *templ = resolved_type->children[0]; delete_children(); // type reference no longer needed + // Ensure typedef itself is fully simplified + while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + is_reg = templ->is_reg; is_logic = templ->is_logic; is_signed = templ->is_signed; @@ -826,15 +829,18 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_assert(children.size() == 2); log_assert(children[1]->type == AST_WIRETYPE); if (!current_scope.count(children[1]->str)) - log_file_error(filename, linenum, "Unknown identifier `%s' used as type name", children[1]->str.c_str()); + log_file_error(filename, linenum, "Unknown identifier `%s' used as type name\n", children[1]->str.c_str()); AstNode *resolved_type = current_scope.at(children[1]->str); if (resolved_type->type != AST_TYPEDEF) - log_file_error(filename, linenum, "`%s' does not name a type", children[1]->str.c_str()); + log_file_error(filename, linenum, "`%s' does not name a type\n", children[1]->str.c_str()); log_assert(resolved_type->children.size() == 1); AstNode *templ = resolved_type->children[0]; delete children[1]; children.pop_back(); + // Ensure typedef itself is fully simplified + while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + is_signed = templ->is_signed; is_string = templ->is_string; is_custom_type = templ->is_custom_type; diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv new file mode 100644 index 000000000..4aa22b6af --- /dev/null +++ b/tests/svtypes/typedef_package.sv @@ -0,0 +1,11 @@ +package pkg; + typedef logic [7:0] uint8_t; +endpackage + +module top; + + (* keep *) pkg::uint8_t a = 8'hAA; + + always @* assert(a == 8'hAA); + +endmodule \ No newline at end of file -- cgit v1.2.3 From 30d23260309ef392a0e69fe5294c38b71ad0692e Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 11:39:15 +0100 Subject: sv: Add support for memory typedefs Signed-off-by: David Shah --- frontends/ast/simplify.cc | 17 +++++++++++++++-- frontends/verilog/verilog_parser.y | 20 +++++++++++++++++++- tests/svtypes/typedef_memory.sv | 10 ++++++++++ 3 files changed, 44 insertions(+), 3 deletions(-) create mode 100644 tests/svtypes/typedef_memory.sv diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 44e32b29c..a6ac04037 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -785,8 +785,10 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // resolve typedefs if (type == AST_TYPEDEF) { log_assert(children.size() == 1); - log_assert(children[0]->type == AST_WIRE); - while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + log_assert(children[0]->type == AST_WIRE || children[0]->type == AST_MEMORY); + while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { + did_something = true; + }; log_assert(!children[0]->is_custom_type); } @@ -807,6 +809,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // Ensure typedef itself is fully simplified while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + type = templ->type; is_reg = templ->is_reg; is_logic = templ->is_logic; is_signed = templ->is_signed; @@ -819,6 +822,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_right = templ->range_right; for (auto template_child : templ->children) children.push_back(template_child->clone()); + did_something = true; } log_assert(!is_custom_type); } @@ -841,6 +845,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, // Ensure typedef itself is fully simplified while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; + if (templ->type == AST_MEMORY) + log_file_error(filename, linenum, "unpacked array type `%s' cannot be used for a parameter\n", children[1]->str.c_str()); is_signed = templ->is_signed; is_string = templ->is_string; is_custom_type = templ->is_custom_type; @@ -851,6 +857,7 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_right = templ->range_right; for (auto template_child : templ->children) children.push_back(template_child->clone()); + did_something = true; } log_assert(!is_custom_type); } @@ -3074,6 +3081,9 @@ void AstNode::mem2reg_as_needed_pass1(dict> &mem2reg uint32_t children_flags = 0; int lhs_children_counter = 0; + if (type == AST_TYPEDEF) + return; // don't touch content of typedefs + if (type == AST_ASSIGN || type == AST_ASSIGN_LE || type == AST_ASSIGN_EQ) { // mark all memories that are used in a complex expression on the left side of an assignment @@ -3231,6 +3241,9 @@ bool AstNode::mem2reg_as_needed_pass2(pool &mem2reg_set, AstNode *mod, if (type == AST_FUNCTION || type == AST_TASK) return false; + if (type == AST_TYPEDEF) + return false; + if (type == AST_MEMINIT && id2ast && mem2reg_set.count(id2ast)) { log_assert(children[0]->type == AST_CONSTANT); diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 8cc084fe0..ba44d7f3d 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1400,7 +1400,7 @@ assign_expr: }; typedef_decl: - TOK_TYPEDEF wire_type range TOK_ID ';' { + TOK_TYPEDEF wire_type range TOK_ID range_or_multirange ';' { astbuf1 = $2; astbuf2 = $3; if (astbuf1->range_left >= 0 && astbuf1->range_right >= 0) { @@ -1416,6 +1416,24 @@ typedef_decl: frontend_verilog_yyerror("wire/reg/logic packed dimension must be of the form: [:], [+:], or [-:]"); if (astbuf2) astbuf1->children.push_back(astbuf2); + + if ($5 != NULL) { + if (!astbuf2) { + AstNode *rng = new AstNode(AST_RANGE); + rng->children.push_back(AstNode::mkconst_int(0, true)); + rng->children.push_back(AstNode::mkconst_int(0, true)); + astbuf1->children.push_back(rng); + } + astbuf1->type = AST_MEMORY; + auto *rangeNode = $5; + if (rangeNode->type == AST_RANGE && rangeNode->children.size() == 1) { + // SV array size [n], rewrite as [n-1:0] + rangeNode->children[0] = new AstNode(AST_SUB, rangeNode->children[0], AstNode::mkconst_int(1, true)); + rangeNode->children.push_back(AstNode::mkconst_int(0, false)); + } + astbuf1->children.push_back(rangeNode); + } + ast_stack.back()->children.push_back(new AstNode(AST_TYPEDEF, astbuf1)); ast_stack.back()->children.back()->str = *$4; }; diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv new file mode 100644 index 000000000..c848c3287 --- /dev/null +++ b/tests/svtypes/typedef_memory.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] ram16x4_t[0:15]; + + ram16x4_t mem; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule \ No newline at end of file -- cgit v1.2.3 From af25585170f87506bcc7dbe5afe0fec868290d5b Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 11:46:37 +0100 Subject: sv: Add support for memories of a typedef Signed-off-by: David Shah --- frontends/ast/simplify.cc | 26 ++++++++++++++++++++------ tests/svtypes/typedef_memory_2.sv | 10 ++++++++++ 2 files changed, 30 insertions(+), 6 deletions(-) create mode 100644 tests/svtypes/typedef_memory_2.sv diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index a6ac04037..aaf1188b4 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -793,9 +793,9 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, } // resolve types of wires - if (type == AST_WIRE) { + if (type == AST_WIRE || type == AST_MEMORY) { if (is_custom_type) { - log_assert(children.size() == 1); + log_assert(children.size() >= 1); log_assert(children[0]->type == AST_WIRETYPE); if (!current_scope.count(children[0]->str)) log_file_error(filename, linenum, "Unknown identifier `%s' used as type name\n", children[0]->str.c_str()); @@ -804,12 +804,15 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, log_file_error(filename, linenum, "`%s' does not name a type\n", children[0]->str.c_str()); log_assert(resolved_type->children.size() == 1); AstNode *templ = resolved_type->children[0]; - delete_children(); // type reference no longer needed + // Remove type reference + delete children[0]; + children.erase(children.begin()); // Ensure typedef itself is fully simplified while(templ->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) {}; - type = templ->type; + if (type == AST_WIRE) + type = templ->type; is_reg = templ->is_reg; is_logic = templ->is_logic; is_signed = templ->is_signed; @@ -820,8 +823,19 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, range_swapped = templ->range_swapped; range_left = templ->range_left; range_right = templ->range_right; - for (auto template_child : templ->children) - children.push_back(template_child->clone()); + + // Insert clones children from template at beginning + for (int i = 0; i < GetSize(templ->children); i++) + children.insert(children.begin() + i, templ->children[i]->clone()); + + if (type == AST_MEMORY && GetSize(children) == 1) { + // Single-bit memories must have [0:0] range + AstNode *rng = new AstNode(AST_RANGE); + rng->children.push_back(AstNode::mkconst_int(0, true)); + rng->children.push_back(AstNode::mkconst_int(0, true)); + children.insert(children.begin(), rng); + } + did_something = true; } log_assert(!is_custom_type); diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv new file mode 100644 index 000000000..1e8abb155 --- /dev/null +++ b/tests/svtypes/typedef_memory_2.sv @@ -0,0 +1,10 @@ +module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); + typedef logic [3:0] nibble; + + nibble mem[0:15]; + + always @(posedge clk) begin + if (wen) mem[addr] <= wdata; + rdata <= mem[addr]; + end +endmodule \ No newline at end of file -- cgit v1.2.3 From 497faf4ec0c078093ecef547965ae9d0fd153edb Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 11:59:33 +0100 Subject: sv: Add %expect Signed-off-by: David Shah --- frontends/verilog/verilog_parser.y | 1 + 1 file changed, 1 insertion(+) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index ba44d7f3d..e0a654b76 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -113,6 +113,7 @@ struct specify_rise_fall { %define api.prefix {frontend_verilog_yy} %glr-parser +%expect 22 /* The union is defined in the header, so we need to provide all the * includes it requires -- cgit v1.2.3 From c0bb47beca2fb78670ab14515047a88a677cc608 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 12:11:17 +0100 Subject: sv: Fix memories of typedefs Signed-off-by: David Shah --- frontends/verilog/verilog_parser.y | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index e0a654b76..516fa4138 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -1350,7 +1350,7 @@ wire_name: if ($2 != NULL) { if (node->is_input || node->is_output) frontend_verilog_yyerror("input/output/inout ports cannot have unpacked dimensions."); - if (!astbuf2) { + if (!astbuf2 && !node->is_custom_type) { AstNode *rng = new AstNode(AST_RANGE); rng->children.push_back(AstNode::mkconst_int(0, true)); rng->children.push_back(AstNode::mkconst_int(0, true)); -- cgit v1.2.3 From abc155715dbe8db5ee95707f7c243f23954ca139 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 13:00:26 +0100 Subject: sv: Add test scripts for typedefs Signed-off-by: David Shah --- Makefile | 1 + tests/svtypes/.gitignore | 3 +++ tests/svtypes/run-test.sh | 20 ++++++++++++++++++++ tests/svtypes/typedef_memory.ys | 3 +++ tests/svtypes/typedef_memory_2.ys | 4 ++++ 5 files changed, 31 insertions(+) create mode 100644 tests/svtypes/.gitignore create mode 100755 tests/svtypes/run-test.sh create mode 100644 tests/svtypes/typedef_memory.ys create mode 100644 tests/svtypes/typedef_memory_2.ys diff --git a/Makefile b/Makefile index 2644721be..4dfed54eb 100644 --- a/Makefile +++ b/Makefile @@ -708,6 +708,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/various && bash run-test.sh +cd tests/sat && bash run-test.sh +cd tests/svinterfaces && bash run-test.sh $(SEEDOPT) + +cd tests/svtypes && bash run-test.sh $(SEEDOPT) +cd tests/proc && bash run-test.sh +cd tests/opt && bash run-test.sh +cd tests/aiger && bash run-test.sh $(ABCOPT) diff --git a/tests/svtypes/.gitignore b/tests/svtypes/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/svtypes/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/svtypes/run-test.sh b/tests/svtypes/run-test.sh new file mode 100755 index 000000000..09a30eed1 --- /dev/null +++ b/tests/svtypes/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log $x" +done +for x in *.sv; do + if [ ! -f "${x%.sv}.ys" ]; then + echo "all:: check-$x" + echo "check-$x:" + echo " @echo 'Checking $x..'" + echo " @../../yosys -ql ${x%.sv}.log -p \"prep -top top; sat -verify -prove-asserts\" $x" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys new file mode 100644 index 000000000..bc1127dc5 --- /dev/null +++ b/tests/svtypes/typedef_memory.ys @@ -0,0 +1,3 @@ +read -sv typedef_memory.sv +prep -top top +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys new file mode 100644 index 000000000..571e28914 --- /dev/null +++ b/tests/svtypes/typedef_memory_2.ys @@ -0,0 +1,4 @@ +read -sv typedef_memory_2.sv +prep -top top +dump +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file -- cgit v1.2.3 From 1746b6373b55490314bc2e12c6584c4a1cb38a6a Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 13:01:47 +0100 Subject: Update CHANGELOG and README Signed-off-by: David Shah --- CHANGELOG | 1 + README.md | 2 ++ 2 files changed, 3 insertions(+) diff --git a/CHANGELOG b/CHANGELOG index c1ffaa44a..51d5e1dc9 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -50,6 +50,7 @@ Yosys 0.9 .. Yosys 0.9-dev - "synth_ecp5" to now infer DSP blocks (-nodsp to disable, experimental) - "synth_ice40 -dsp" to infer DSP blocks - Added latch support to synth_xilinx + - Added support for SystemVerilog typedefs Yosys 0.8 .. Yosys 0.9 ---------------------- diff --git a/README.md b/README.md index fdd4bb410..db7810cb4 100644 --- a/README.md +++ b/README.md @@ -510,6 +510,8 @@ from SystemVerilog: into a design with ``read_verilog``, all its packages are available to SystemVerilog files being read into the same design afterwards. +- typedefs are supported (including inside packages) + - SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether ports are inputs or outputs are supported. -- cgit v1.2.3 From 8cc1bee33c04690d729d1a8b8622be05d65f7911 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 16:12:09 +0100 Subject: sv: Disambiguate interface ports Signed-off-by: David Shah --- frontends/verilog/verilog_parser.y | 22 +++++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y index 516fa4138..0024d4778 100644 --- a/frontends/verilog/verilog_parser.y +++ b/frontends/verilog/verilog_parser.y @@ -113,7 +113,8 @@ struct specify_rise_fall { %define api.prefix {frontend_verilog_yy} %glr-parser -%expect 22 +%expect 21 +%expect-rr 2 /* The union is defined in the header, so we need to provide all the * includes it requires @@ -157,7 +158,7 @@ struct specify_rise_fall { %token TOK_INCREMENT TOK_DECREMENT TOK_UNIQUE TOK_PRIORITY %type range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int -%type wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list +%type wire_type wire_type_io expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type opt_label opt_sva_label tok_prim_wrapper hierarchical_id %type opt_signed opt_property unique_case_attr %type attr case_attr @@ -395,7 +396,7 @@ module_arg: ast_stack.back()->children.push_back(astbuf2); delete astbuf1; // really only needed if multiple instances of same type. } module_arg_opt_assignment | - attr wire_type range TOK_ID { + attr wire_type_io range TOK_ID { AstNode *node = $2; node->str = *$4; node->port_id = ++port_counter; @@ -479,6 +480,15 @@ wire_type: $$ = astbuf3; }; +wire_type_io: + { + astbuf3 = new AstNode(AST_WIRE); + current_wire_rand = false; + current_wire_const = false; + } io_wire_type_token_list delay { + $$ = astbuf3; + }; + wire_type_token_list: wire_type_token | wire_type_token_list wire_type_token | wire_type_token_io ; @@ -541,6 +551,12 @@ wire_type_token: astbuf3->children.back()->str = *$1; }; +wire_type_token_list_without_io: + wire_type_token | wire_type_token_list wire_type_token; + +io_wire_type_token_list: + wire_type_token_io | wire_type_token_io wire_type_token_list_without_io; + non_opt_range: '[' expr ':' expr ']' { $$ = new AstNode(AST_RANGE); -- cgit v1.2.3 From 5501d9090aaf2d508b2f082f8453effe7fce08df Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 18:40:23 +0100 Subject: sv: Fix typedefs in blocks Signed-off-by: David Shah --- frontends/ast/simplify.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index aaf1188b4..0ebc183b2 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -3002,7 +3002,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma } } - if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL) && name_map.count(str) > 0) + if ((type == AST_IDENTIFIER || type == AST_FCALL || type == AST_TCALL || type == AST_WIRETYPE) && name_map.count(str) > 0) str = name_map[str]; std::map backup_name_map; @@ -3010,7 +3010,7 @@ void AstNode::expand_genblock(std::string index_var, std::string prefix, std::ma for (size_t i = 0; i < children.size(); i++) { AstNode *child = children[i]; if (child->type == AST_WIRE || child->type == AST_MEMORY || child->type == AST_PARAMETER || child->type == AST_LOCALPARAM || - child->type == AST_FUNCTION || child->type == AST_TASK || child->type == AST_CELL) { + child->type == AST_FUNCTION || child->type == AST_TASK || child->type == AST_CELL || child->type == AST_TYPEDEF) { if (backup_name_map.size() == 0) backup_name_map = name_map; std::string new_name = prefix[0] == '\\' ? prefix.substr(1) : prefix; -- cgit v1.2.3 From 9b9d24f15b1b91b64b97e12bd05693f4539762d9 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 20 Sep 2019 18:40:35 +0100 Subject: sv: Improve tests Signed-off-by: David Shah --- tests/svtypes/typedef_memory.sv | 2 +- tests/svtypes/typedef_memory.ys | 2 +- tests/svtypes/typedef_memory_2.sv | 2 +- tests/svtypes/typedef_memory_2.ys | 2 +- tests/svtypes/typedef_package.sv | 2 +- tests/svtypes/typedef_param.sv | 2 +- tests/svtypes/typedef_scopes.sv | 23 +++++++++++++++++++++++ tests/svtypes/typedef_simple.sv | 2 +- 8 files changed, 30 insertions(+), 7 deletions(-) create mode 100644 tests/svtypes/typedef_scopes.sv diff --git a/tests/svtypes/typedef_memory.sv b/tests/svtypes/typedef_memory.sv index c848c3287..37e63c1d0 100644 --- a/tests/svtypes/typedef_memory.sv +++ b/tests/svtypes/typedef_memory.sv @@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); if (wen) mem[addr] <= wdata; rdata <= mem[addr]; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_memory.ys b/tests/svtypes/typedef_memory.ys index bc1127dc5..d0b8cf5bf 100644 --- a/tests/svtypes/typedef_memory.ys +++ b/tests/svtypes/typedef_memory.ys @@ -1,3 +1,3 @@ read -sv typedef_memory.sv prep -top top -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_memory_2.sv b/tests/svtypes/typedef_memory_2.sv index 1e8abb155..6d65131db 100644 --- a/tests/svtypes/typedef_memory_2.sv +++ b/tests/svtypes/typedef_memory_2.sv @@ -7,4 +7,4 @@ module top(input [3:0] addr, wdata, input clk, wen, output reg [3:0] rdata); if (wen) mem[addr] <= wdata; rdata <= mem[addr]; end -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_memory_2.ys b/tests/svtypes/typedef_memory_2.ys index 571e28914..0997beeea 100644 --- a/tests/svtypes/typedef_memory_2.ys +++ b/tests/svtypes/typedef_memory_2.ys @@ -1,4 +1,4 @@ read -sv typedef_memory_2.sv prep -top top dump -select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i \ No newline at end of file +select -assert-count 1 t:$mem r:SIZE=16 %i r:WIDTH=4 %i diff --git a/tests/svtypes/typedef_package.sv b/tests/svtypes/typedef_package.sv index 4aa22b6af..bee88b7ae 100644 --- a/tests/svtypes/typedef_package.sv +++ b/tests/svtypes/typedef_package.sv @@ -8,4 +8,4 @@ module top; always @* assert(a == 8'hAA); -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_param.sv b/tests/svtypes/typedef_param.sv index 13a522f19..d838dd828 100644 --- a/tests/svtypes/typedef_param.sv +++ b/tests/svtypes/typedef_param.sv @@ -19,4 +19,4 @@ module top; `STATIC_ASSERT(int8 == 8'b11111111); `STATIC_ASSERT(ch == 8'b11111111); -endmodule \ No newline at end of file +endmodule diff --git a/tests/svtypes/typedef_scopes.sv b/tests/svtypes/typedef_scopes.sv new file mode 100644 index 000000000..340defbbb --- /dev/null +++ b/tests/svtypes/typedef_scopes.sv @@ -0,0 +1,23 @@ + +typedef logic [3:0] outer_uint4_t; + +module top; + + outer_uint4_t u4_i = 8'hA5; + always @(*) assert(u4_i == 4'h5); + + typedef logic [3:0] inner_type; + inner_type inner_i1 = 8'h5A; + always @(*) assert(inner_i1 == 4'hA); + + if (1) begin: genblock + typedef logic [7:0] inner_type; + inner_type inner_gb_i = 8'hA5; + always @(*) assert(inner_gb_i == 8'hA5); + end + + inner_type inner_i2 = 8'h42; + always @(*) assert(inner_i2 == 4'h2); + + +endmodule diff --git a/tests/svtypes/typedef_simple.sv b/tests/svtypes/typedef_simple.sv index 0cf2c072c..8f89910e5 100644 --- a/tests/svtypes/typedef_simple.sv +++ b/tests/svtypes/typedef_simple.sv @@ -16,4 +16,4 @@ module top; always @* assert(int8 == 8'b11111111); always @* assert(ch == 8'b11111111); -endmodule \ No newline at end of file +endmodule -- cgit v1.2.3 From e46e8753c84ee83f871d5ce116ce4c08dd49a031 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 3 Oct 2019 09:55:43 +0100 Subject: frontends/ast: code style Signed-off-by: David Shah --- frontends/ast/simplify.cc | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 0ebc183b2..44fd32cdc 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -786,9 +786,8 @@ bool AstNode::simplify(bool const_fold, bool at_zero, bool in_lvalue, int stage, if (type == AST_TYPEDEF) { log_assert(children.size() == 1); log_assert(children[0]->type == AST_WIRE || children[0]->type == AST_MEMORY); - while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) { + while(children[0]->simplify(const_fold, at_zero, in_lvalue, stage, width_hint, sign_hint, in_param)) did_something = true; - }; log_assert(!children[0]->is_custom_type); } -- cgit v1.2.3 From d19f765a581ac465a7f7cea22f1d96c9da9cbe01 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:41:53 +0200 Subject: Removed alu and div_mod tests as agreed --- tests/ecp5/alu.v | 19 ------------------- tests/ecp5/alu.ys | 13 ------------- tests/ecp5/div_mod.v | 13 ------------- tests/ecp5/div_mod.ys | 12 ------------ 4 files changed, 57 deletions(-) delete mode 100644 tests/ecp5/alu.v delete mode 100644 tests/ecp5/alu.ys delete mode 100644 tests/ecp5/div_mod.v delete mode 100644 tests/ecp5/div_mod.ys diff --git a/tests/ecp5/alu.v b/tests/ecp5/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/ecp5/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/ecp5/alu.ys b/tests/ecp5/alu.ys deleted file mode 100644 index c2950b164..000000000 --- a/tests/ecp5/alu.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 32 t:CCU2C -select -assert-count 242 t:L6MUX21 -select -assert-count 1127 t:LUT4 -select -assert-count 417 t:PFUMX -select -assert-count 32 t:TRELLIS_FF -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/div_mod.v b/tests/ecp5/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ecp5/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ecp5/div_mod.ys b/tests/ecp5/div_mod.ys deleted file mode 100644 index 9efb00701..000000000 --- a/tests/ecp5/div_mod.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 28 t:CCU2C -select -assert-count 26 t:L6MUX21 -select -assert-count 138 t:LUT4 -select -assert-count 60 t:PFUMX -select -assert-none t:LUT4 t:CCU2C t:L6MUX21 t:PFUMX %% t:* %D -- cgit v1.2.3 From 9e8175fc759478a7a496ac0d492cb4b6d0f13799 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:42:29 +0200 Subject: Check flops one by one --- tests/ecp5/adffs.v | 40 ---------------------------------------- tests/ecp5/adffs.ys | 41 ++++++++++++++++++++++++++++++++++++----- tests/ecp5/dffs.v | 22 ---------------------- tests/ecp5/dffs.ys | 18 ++++++++++++++---- 4 files changed, 50 insertions(+), 71 deletions(-) diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v index 05e68caf7..223b52d21 100644 --- a/tests/ecp5/adffs.v +++ b/tests/ecp5/adffs.v @@ -45,43 +45,3 @@ module ndffnr else q <= d; endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index fc1363a32..658f302d0 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,9 +1,40 @@ read_verilog adffs.v +design -save read + proc -flatten -equiv_opt -multiclock -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +hierarchy -top adff +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 4 t:TRELLIS_FF -select -assert-count 3 t:LUT4 +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +proc +hierarchy -top adffn +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top dffs +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top ndffnr +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v index d97840c43..3418787c9 100644 --- a/tests/ecp5/dffs.v +++ b/tests/ecp5/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 5510bb440..93b8595ad 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,9 +1,19 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 2 t:TRELLIS_FF +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D \ No newline at end of file -- cgit v1.2.3 From abb5a3a44df18a6ca18b6998f4c35aafc4284df8 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:44:10 +0200 Subject: Check for MULT18X18D, since that is working now --- tests/ecp5/macc.ys | 12 +++++------- tests/ecp5/mul.ys | 13 ++++++------- 2 files changed, 11 insertions(+), 14 deletions(-) diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index bc6340509..f60281a54 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,15 +1,13 @@ read_verilog macc.v proc hierarchy -top top -#Failed because of 14 unproven cells. -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -#equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +# Blocked by issue #1358 (Missing ECP5 simulation models) +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18D select -assert-count 4 t:CCU2C -select -assert-count 6 t:L6MUX21 -select -assert-count 49 t:LUT4 -select -assert-count 19 t:PFUMX select -assert-count 7 t:TRELLIS_FF -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D +select -assert-none t:CCU2C t:MULT18X18D t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys index 0e8d6908f..132340664 100644 --- a/tests/ecp5/mul.ys +++ b/tests/ecp5/mul.ys @@ -1,11 +1,10 @@ read_verilog mul.v hierarchy -top top -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +# Blocked by issue #1358 (Missing ECP5 simulation models) +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:CCU2C -select -assert-count 46 t:L6MUX21 -select -assert-count 169 t:LUT4 -select -assert-count 72 t:PFUMX - -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX %% t:* %D +select -assert-count 1 t:MULT18X18D +select -assert-none t:MULT18X18D %% t:* %D -- cgit v1.2.3 From d6ef9b1a6b47e740dba948e5f2fcf456d7ee79cf Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:45:58 +0200 Subject: Cleaned verilog code from not used defines --- tests/ecp5/shifter.v | 6 ------ 1 file changed, 6 deletions(-) diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v index c55632552..04ae49d83 100644 --- a/tests/ecp5/shifter.v +++ b/tests/ecp5/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule -- cgit v1.2.3 From 3c40c810307c2bed62527f4f067790edc4ac8823 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:52:54 +0200 Subject: Test muxes synth one by one --- tests/ecp5/mux.v | 34 ---------------------------------- tests/ecp5/mux.ys | 43 +++++++++++++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 38 deletions(-) diff --git a/tests/ecp5/mux.v b/tests/ecp5/mux.v index 0814b733e..782424a9b 100644 --- a/tests/ecp5/mux.v +++ b/tests/ecp5/mux.v @@ -64,37 +64,3 @@ assign Y = D[S]; endmodule - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys index 7d40c9cf1..eada276ba 100644 --- a/tests/ecp5/mux.ys +++ b/tests/ecp5/mux.ys @@ -1,11 +1,46 @@ read_verilog mux.v +design -save read + +proc +hierarchy -top mux2 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + +design -load read +proc +hierarchy -top mux4 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:L6MUX21 +select -assert-count 4 t:LUT4 +select -assert-count 2 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:L6MUX21 +select -assert-count 7 t:LUT4 +select -assert-count 2 t:PFUMX + +select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D + +design -load read proc -flatten +hierarchy -top mux16 equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 32 t:LUT4 +cd mux16 # Constrain all select calls below inside the top module select -assert-count 8 t:L6MUX21 -select -assert-count 14 t:PFUMX +select -assert-count 26 t:LUT4 +select -assert-count 12 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D -- cgit v1.2.3 From 3358b2f18597c59ee3cac5f123f954ca79e0baad Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:53:54 +0200 Subject: Removed top module where not needed --- tests/ecp5/fsm.v | 18 ------------------ tests/ecp5/fsm.ys | 4 ++-- tests/ecp5/tribuf.v | 15 --------------- tests/ecp5/tribuf.ys | 4 ++-- 4 files changed, 4 insertions(+), 37 deletions(-) diff --git a/tests/ecp5/fsm.v b/tests/ecp5/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/ecp5/fsm.v +++ b/tests/ecp5/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/ecp5/fsm.ys b/tests/ecp5/fsm.ys index 6368edc57..ded91e5f7 100644 --- a/tests/ecp5/fsm.ys +++ b/tests/ecp5/fsm.ys @@ -1,10 +1,10 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:L6MUX21 select -assert-count 13 t:LUT4 select -assert-count 5 t:PFUMX diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v index 870a02584..90dd314e4 100644 --- a/tests/ecp5/tribuf.v +++ b/tests/ecp5/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); assign o = en ? i : 1'bz; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys index f454a0c02..a6e9c9598 100644 --- a/tests/ecp5/tribuf.ys +++ b/tests/ecp5/tribuf.ys @@ -1,9 +1,9 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 7785f23719cdbcae6816415cf2dc124aba312c66 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:31:51 +0200 Subject: Check latches type one by one --- tests/ecp5/latches.v | 34 ---------------------------------- tests/ecp5/latches.ys | 31 +++++++++++++++++++++++++------ 2 files changed, 25 insertions(+), 40 deletions(-) diff --git a/tests/ecp5/latches.v b/tests/ecp5/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/ecp5/latches.v +++ b/tests/ecp5/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index b9d8faf87..f32998232 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -1,16 +1,35 @@ + read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 + +select -assert-none t:LUT4 %% t:* %D + design -load read +proc +hierarchy -top latchn +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 -cd top -select -assert-count 4 t:LUT4 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT4 + +select -assert-none t:LUT4 %% t:* %D + + +design -load read +proc +hierarchy -top latchsr +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ecp5 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:LUT4 select -assert-count 1 t:PFUMX + select -assert-none t:LUT4 t:PFUMX %% t:* %D -- cgit v1.2.3 From 1435b9bf97bc5c4e625bd3ef5db19065a0af2632 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:55:13 +0200 Subject: remove alu test --- tests/anlogic/alu.v | 19 ------------------- tests/anlogic/alu.ys | 17 ----------------- 2 files changed, 36 deletions(-) delete mode 100644 tests/anlogic/alu.v delete mode 100644 tests/anlogic/alu.ys diff --git a/tests/anlogic/alu.v b/tests/anlogic/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/anlogic/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/anlogic/alu.ys b/tests/anlogic/alu.ys deleted file mode 100644 index 532ce82d5..000000000 --- a/tests/anlogic/alu.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 66 t:AL_MAP_ADDER -select -assert-count 32 t:AL_MAP_LUT1 -select -assert-count 23 t:AL_MAP_LUT2 -select -assert-count 61 t:AL_MAP_LUT3 -select -assert-count 209 t:AL_MAP_LUT4 -select -assert-count 100 t:AL_MAP_LUT5 -select -assert-count 79 t:AL_MAP_LUT6 -select -assert-count 32 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D -- cgit v1.2.3 From 3d3479b0af0d2d59708a0828cfa785257c52d6fd Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 10:57:47 +0200 Subject: Cleanup top modules and not used defines --- tests/anlogic/fsm.v | 18 ------------------ tests/anlogic/fsm.ys | 6 +++--- tests/anlogic/shifter.v | 6 ------ tests/anlogic/tribuf.v | 15 --------------- tests/anlogic/tribuf.ys | 4 ++-- 5 files changed, 5 insertions(+), 44 deletions(-) diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/anlogic/fsm.v +++ b/tests/anlogic/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys index 6eb7b9a71..76a5d3e43 100644 --- a/tests/anlogic/fsm.ys +++ b/tests/anlogic/fsm.ys @@ -1,12 +1,12 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc -flatten +#flatten #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v index c55632552..04ae49d83 100644 --- a/tests/anlogic/shifter.v +++ b/tests/anlogic/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v index 870a02584..90dd314e4 100644 --- a/tests/anlogic/tribuf.v +++ b/tests/anlogic/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); assign o = en ? i : 1'bz; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys index 663e93fb2..0eb1338ac 100644 --- a/tests/anlogic/tribuf.ys +++ b/tests/anlogic/tribuf.ys @@ -1,9 +1,9 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc flatten equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 91ad3ab717159da311b72531f4b9c77a7522702a Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:00:49 +0200 Subject: check ff's separately --- tests/anlogic/dffs.v | 22 ---------------------- tests/anlogic/dffs.ys | 18 ++++++++++++++---- 2 files changed, 14 insertions(+), 26 deletions(-) diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v index d97840c43..3418787c9 100644 --- a/tests/anlogic/dffs.v +++ b/tests/anlogic/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys index a15c6f24e..38dffa326 100644 --- a/tests/anlogic/dffs.ys +++ b/tests/anlogic/dffs.ys @@ -1,10 +1,20 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 2 t:AL_MAP_SEQ +select -assert-count 1 t:AL_MAP_SEQ select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D -- cgit v1.2.3 From 3238ee7d354aed51eb61ce5a8c2799f56f2cb4b2 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:04:18 +0200 Subject: check muxes per type --- tests/anlogic/mux.v | 35 ----------------------------------- tests/anlogic/mux.ys | 44 +++++++++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 42 deletions(-) diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v index 0814b733e..27bc0bf0b 100644 --- a/tests/anlogic/mux.v +++ b/tests/anlogic/mux.v @@ -63,38 +63,3 @@ module mux16 (D, S, Y); assign Y = D[S]; endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys index 84a8bcccf..354fc836c 100644 --- a/tests/anlogic/mux.ys +++ b/tests/anlogic/mux.ys @@ -1,12 +1,42 @@ read_verilog mux.v +design -save read + +proc +hierarchy -top mux2 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + +design -load read +proc +hierarchy -top mux4 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT6 %% t:* %D + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 3 t:AL_MAP_LUT4 +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D + +design -load read proc -flatten +hierarchy -top mux16 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:AL_MAP_LUT6 -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 4 t:AL_MAP_LUT4 -select -assert-count 4 t:AL_MAP_LUT5 -select -assert-count 1 t:AL_MAP_LUT6 -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D +select -assert-none t:AL_MAP_LUT6 %% t:* %D -- cgit v1.2.3 From a5844e3ceb76152d1e87ad8fdf1c71553238ef64 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:08:42 +0200 Subject: split latches into separate checks --- tests/anlogic/latches.v | 34 ---------------------------------- tests/anlogic/latches.ys | 31 ++++++++++++++++++++++++------- 2 files changed, 24 insertions(+), 41 deletions(-) diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/anlogic/latches.v +++ b/tests/anlogic/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys index b5e52cf16..ae9e15ff8 100644 --- a/tests/anlogic/latches.ys +++ b/tests/anlogic/latches.ys @@ -2,15 +2,32 @@ read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp +# Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + + +design -load read +proc +hierarchy -top latchn +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + design -load read +proc +hierarchy -top latchsr +# Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic -cd top -select -assert-count 2 t:AL_MAP_LUT3 +cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:AL_MAP_LUT5 -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D + +select -assert-none t:AL_MAP_LUT5 %% t:* %D -- cgit v1.2.3 From 03a3deec43ef4e92b251ea4bceaadc77c8044df0 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 11:09:59 +0200 Subject: Cleanup and formating --- tests/anlogic/add_sub.ys | 2 +- tests/anlogic/counter.ys | 2 +- tests/anlogic/fsm.ys | 1 + tests/anlogic/shifter.ys | 1 + 4 files changed, 4 insertions(+), 2 deletions(-) diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys index 55c090506..994cd0d03 100644 --- a/tests/anlogic/add_sub.ys +++ b/tests/anlogic/add_sub.ys @@ -5,5 +5,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 10 t:AL_MAP_ADDER select -assert-count 4 t:AL_MAP_LUT1 -select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys index 5210221e3..036fdba46 100644 --- a/tests/anlogic/counter.ys +++ b/tests/anlogic/counter.ys @@ -8,4 +8,4 @@ cd top # Constrain all select calls below inside the top module select -assert-count 9 t:AL_MAP_ADDER select -assert-count 8 t:AL_MAP_SEQ -select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D +select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys index 76a5d3e43..452ef9251 100644 --- a/tests/anlogic/fsm.ys +++ b/tests/anlogic/fsm.ys @@ -11,4 +11,5 @@ select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 select -assert-count 6 t:AL_MAP_SEQ + select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys index edd89b344..5eaed30a3 100644 --- a/tests/anlogic/shifter.ys +++ b/tests/anlogic/shifter.ys @@ -6,4 +6,5 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 8 t:AL_MAP_SEQ + select -assert-none t:AL_MAP_SEQ %% t:* %D -- cgit v1.2.3 From f94dc2c072572f5b4316cb26415e7a3a4183c362 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 12:41:41 +0200 Subject: Remove not needed tests --- tests/efinix/alu.v | 19 ------------------- tests/efinix/alu.ys | 13 ------------- tests/efinix/div_mod.v | 13 ------------- tests/efinix/div_mod.ys | 10 ---------- tests/efinix/mul.v | 11 ----------- tests/efinix/mul.ys | 9 --------- 6 files changed, 75 deletions(-) delete mode 100644 tests/efinix/alu.v delete mode 100644 tests/efinix/alu.ys delete mode 100644 tests/efinix/div_mod.v delete mode 100644 tests/efinix/div_mod.ys delete mode 100644 tests/efinix/mul.v delete mode 100644 tests/efinix/mul.ys diff --git a/tests/efinix/alu.v b/tests/efinix/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/efinix/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/efinix/alu.ys b/tests/efinix/alu.ys deleted file mode 100644 index 0d58a7c8a..000000000 --- a/tests/efinix/alu.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 66 t:EFX_ADD -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 32 t:EFX_FF -select -assert-count 605 t:EFX_LUT4 -select -assert-none t:EFX_ADD t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/div_mod.v b/tests/efinix/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/efinix/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/efinix/div_mod.ys b/tests/efinix/div_mod.ys deleted file mode 100644 index 3b6f2f0f4..000000000 --- a/tests/efinix/div_mod.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 95 t:EFX_ADD -select -assert-count 114 t:EFX_LUT4 -select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/mul.v b/tests/efinix/mul.v deleted file mode 100644 index 0f1618698..000000000 --- a/tests/efinix/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [7:0] x, - input [7:0] y, - - output [15:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/efinix/mul.ys b/tests/efinix/mul.ys deleted file mode 100644 index 7d349f3f8..000000000 --- a/tests/efinix/mul.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog mul.v -hierarchy -top top -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 17 t:EFX_ADD -select -assert-count 149 t:EFX_LUT4 -select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D -- cgit v1.2.3 From 286a2728729a6cf4b65afec6dbe65d269f1a5ca6 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 12:42:06 +0200 Subject: Cleaned tests --- tests/efinix/fsm.v | 18 ------------------ tests/efinix/fsm.ys | 4 ++-- tests/efinix/shifter.v | 6 ------ tests/efinix/tribuf.v | 21 --------------------- tests/efinix/tribuf.ys | 4 ++-- 5 files changed, 4 insertions(+), 49 deletions(-) diff --git a/tests/efinix/fsm.v b/tests/efinix/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/efinix/fsm.v +++ b/tests/efinix/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/efinix/fsm.ys b/tests/efinix/fsm.ys index 9de6aa280..2ec75215d 100644 --- a/tests/efinix/fsm.ys +++ b/tests/efinix/fsm.ys @@ -1,12 +1,12 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc flatten #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_GBUFCE select -assert-count 6 t:EFX_FF diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v index c55632552..ce2c81dd2 100644 --- a/tests/efinix/shifter.v +++ b/tests/efinix/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG - out <= out >> 1; - out[7] <= in; -`else - out <= out << 1; out[7] <= in; -`endif end endmodule diff --git a/tests/efinix/tribuf.v b/tests/efinix/tribuf.v index 3fa6eb6c6..c64468253 100644 --- a/tests/efinix/tribuf.v +++ b/tests/efinix/tribuf.v @@ -2,28 +2,7 @@ module tristate (en, i, o); input en; input i; output reg o; -`ifndef BUG always @(en or i) o <= (en)? i : 1'bZ; -`else - - always @(en or i) - o <= (en)? ~i : 1'bZ; -`endif -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - endmodule diff --git a/tests/efinix/tribuf.ys b/tests/efinix/tribuf.ys index 20d4f215d..2e2ab9e65 100644 --- a/tests/efinix/tribuf.ys +++ b/tests/efinix/tribuf.ys @@ -1,12 +1,12 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc tribuf flatten synth equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module #Internal cell type used. Need support it. select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 3de7889d08d0b02f1af6b9027b6e753eb0f6f490 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 12:48:27 +0200 Subject: Separate check for ff's types --- tests/efinix/adffs.v | 40 ------------------------------------- tests/efinix/adffs.ys | 55 ++++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 48 insertions(+), 47 deletions(-) diff --git a/tests/efinix/adffs.v b/tests/efinix/adffs.v index 05e68caf7..223b52d21 100644 --- a/tests/efinix/adffs.v +++ b/tests/efinix/adffs.v @@ -45,43 +45,3 @@ module ndffnr else q <= d; endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys index 642faa76b..d0be205d5 100644 --- a/tests/efinix/adffs.ys +++ b/tests/efinix/adffs.ys @@ -1,12 +1,53 @@ read_verilog adffs.v +design -save read + proc -#async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock -flatten -equiv_opt -multiclock -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +hierarchy -top adff +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE + +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + +design -load read +proc +hierarchy -top adffn +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF select -assert-count 1 t:EFX_GBUFCE -select -assert-count 4 t:EFX_FF -select -assert-count 2 t:EFX_LUT4 -select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D + +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + + +design -load read +proc +hierarchy -top dffs +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D + + +design -load read +proc +hierarchy -top ndffnr +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE + +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D -- cgit v1.2.3 From 2c3e14024637bed14d8e8142f4d05c471630dbf7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 12:51:45 +0200 Subject: split rest od ff's --- tests/efinix/adffs.ys | 3 --- tests/efinix/dffs.v | 22 ---------------------- tests/efinix/dffs.ys | 22 +++++++++++++++++----- 3 files changed, 17 insertions(+), 30 deletions(-) diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys index d0be205d5..3471a0a80 100644 --- a/tests/efinix/adffs.ys +++ b/tests/efinix/adffs.ys @@ -43,9 +43,6 @@ hierarchy -top ndffnr equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE - select -assert-count 1 t:EFX_FF select -assert-count 1 t:EFX_GBUFCE select -assert-count 1 t:EFX_LUT4 diff --git a/tests/efinix/dffs.v b/tests/efinix/dffs.v index d97840c43..3418787c9 100644 --- a/tests/efinix/dffs.v +++ b/tests/efinix/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys index 557dfd3d0..fe8d93123 100644 --- a/tests/efinix/dffs.ys +++ b/tests/efinix/dffs.ys @@ -1,12 +1,24 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF select -assert-count 1 t:EFX_GBUFCE -select -assert-count 2 t:EFX_FF select -assert-count 1 t:EFX_LUT4 -select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D -- cgit v1.2.3 From 77d557d00b5672eb4c20fe0179c5d706abb43807 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 12:58:11 +0200 Subject: Add missing latch mapping --- techlibs/efinix/cells_map.v | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/techlibs/efinix/cells_map.v b/techlibs/efinix/cells_map.v index 0aeab1902..3ecec3bac 100644 --- a/techlibs/efinix/cells_map.v +++ b/techlibs/efinix/cells_map.v @@ -17,6 +17,18 @@ module \$_DFF_NP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b0), .CE module \$_DFF_PP0_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b0), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule module \$_DFF_PP1_ (input D, C, R, output Q); EFX_FF #(.CLK_POLARITY(1'b1), .CE_POLARITY(1'b1), .SR_POLARITY(1'b1), .D_POLARITY(1'b1), .SR_SYNC(1'b0), .SR_VALUE(1'b1), .SR_SYNC_PRIORITY(1'b1)) _TECHMAP_REPLACE_ (.D(D), .CE(1'b1), .CLK(C), .SR(R), .Q(Q)); endmodule +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule + `ifndef NO_LUT module \$lut (A, Y); parameter WIDTH = 0; -- cgit v1.2.3 From 1b80489486434a427b8043579426b575e09edc0b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 13:00:09 +0200 Subject: Split latch check --- tests/efinix/latches.v | 34 ---------------------------------- tests/efinix/latches.ys | 35 ++++++++++++++++++++++++----------- 2 files changed, 24 insertions(+), 45 deletions(-) diff --git a/tests/efinix/latches.v b/tests/efinix/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/efinix/latches.v +++ b/tests/efinix/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/efinix/latches.ys b/tests/efinix/latches.ys index 2867ec93e..f729c3bd9 100644 --- a/tests/efinix/latches.ys +++ b/tests/efinix/latches.ys @@ -2,19 +2,32 @@ read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp +# Can't run any sort of equivalence check because latches are blown to LUTs synth_efinix -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + design -load read +proc +hierarchy -top latchn +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +proc +hierarchy -top latchsr +# Can't run any sort of equivalence check because latches are blown to LUTs synth_efinix -flatten -cd top -#Internall cell type $_DLATCH_P_. Should be realized by using LUTs. -#The same result by using just synth_efinix. -select -assert-count 3 t:$_DLATCH_P_ -select -assert-count 3 t:EFX_LUT4 -select -assert-none t:$_DLATCH_P_ t:EFX_LUT4 %% t:* %D +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D -- cgit v1.2.3 From c0fa6f3e1a001c3cd68c4be3eac877e08fd19971 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 13:05:16 +0200 Subject: Split mux tests per type --- tests/efinix/mux.v | 35 ----------------------------------- tests/efinix/mux.ys | 39 ++++++++++++++++++++++++++++++++++++--- 2 files changed, 36 insertions(+), 38 deletions(-) diff --git a/tests/efinix/mux.v b/tests/efinix/mux.v index 0814b733e..27bc0bf0b 100644 --- a/tests/efinix/mux.v +++ b/tests/efinix/mux.v @@ -63,38 +63,3 @@ module mux16 (D, S, Y); assign Y = D[S]; endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/efinix/mux.ys b/tests/efinix/mux.ys index a2d653568..efe27583d 100644 --- a/tests/efinix/mux.ys +++ b/tests/efinix/mux.ys @@ -1,8 +1,41 @@ read_verilog mux.v +design -save read + proc -flatten +hierarchy -top mux2 equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 13 t:EFX_LUT4 +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +proc +hierarchy -top mux4 +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +proc +hierarchy -top mux16 +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 12 t:EFX_LUT4 + select -assert-none t:EFX_LUT4 %% t:* %D -- cgit v1.2.3 From 44c3472b9f92e2db855056bff9c0e9549e4cbf3c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 13:27:10 +0200 Subject: FF should be initialized to 0 --- techlibs/efinix/cells_sim.v | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/techlibs/efinix/cells_sim.v b/techlibs/efinix/cells_sim.v index 2fc2034a6..a74d1c571 100644 --- a/techlibs/efinix/cells_sim.v +++ b/techlibs/efinix/cells_sim.v @@ -59,7 +59,9 @@ module EFX_FF( assign ce = CE_POLARITY ? CE : ~CE; assign sr = SR_POLARITY ? SR : ~SR; assign d = D_POLARITY ? D : ~D; - + + initial Q = 1'b0; + generate if (SR_SYNC == 1) begin -- cgit v1.2.3 From 9c59a56aa495a9d73979c76b92440ad256ca0f13 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 9 Oct 2019 13:59:35 +0200 Subject: Expose global variables and allow logging to python streams Global variables are now accessible via the Yosys class. To capture Yosys output, once can now register an output stream in Pyosys. --- misc/py_wrap_generator.py | 292 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 286 insertions(+), 6 deletions(-) diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py index 4ce8e947e..d8649e9ce 100644 --- a/misc/py_wrap_generator.py +++ b/misc/py_wrap_generator.py @@ -253,6 +253,8 @@ class WContainer: candidate = WType.from_string(arg.strip(), containing_file, line_number) if candidate == None: return None + if candidate.name == "void": + return None cont.args.append(candidate) return cont @@ -880,11 +882,8 @@ class WClass: text += fun.gen_def_virtual() return text - def gen_boost_py(self): - text = "\n\t\tclass_<" + self.name - if self.link_type == link_types.derive: - text += "Wrap, boost::noncopyable" - text += ">(\"" + self.name + "\"" + def gen_boost_py_body(self): + text = "" if self.printable_constrs() == 0 or not self.contains_default_constr(): text += ", no_init" text += ")" @@ -907,6 +906,21 @@ class WClass: text += "\n\t\t\t;\n" return text + def gen_boost_py(self): + body = self.gen_boost_py_body() + if self.link_type == link_types.derive: + text = "\n\t\tclass_<" + self.name + ">(\"" + self.name + "\"" + text += body + text += "\n\t\tclass_<" + self.name + text += "Wrap, boost::noncopyable" + text += ">(\"" + self.name + "\"" + text += body + else: + text = "\n\t\tclass_<" + self.name + ">(\"Cpp" + self.name + "\"" + text += body + return text + + def contains_default_constr(self): for c in self.found_constrs: if len(c.args) == 0: @@ -974,6 +988,7 @@ blacklist_methods = ["YOSYS_NAMESPACE::Pass::run_register", "YOSYS_NAMESPACE::Mo enum_names = ["State","SyncType","ConstFlags"] enums = [] #Do not edit +glbls = [] unowned_functions = [] @@ -1723,6 +1738,159 @@ class WMember: text += ")" return text +class WGlobal: + orig_text = None + wtype = attr_types.default + name = None + containing_file = None + namespace = "" + is_const = False + + def from_string(str_def, containing_file, line_number, namespace): + glbl = WGlobal() + glbl.orig_text = str_def + glbl.wtype = None + glbl.name = "" + glbl.containing_file = containing_file + glbl.namespace = namespace + glbl.is_const = False + + if not str.startswith(str_def, "extern"): + return None + str_def = str_def[7:] + + if str.startswith(str_def, "const "): + glbl.is_const = True + str_def = str_def[6:] + + if str_def.count(" ") == 0: + return None + + parts = split_list(str_def.strip(), " ") + + prefix = "" + i = 0 + for part in parts: + if part in ["unsigned", "long", "short"]: + prefix += part + " " + i += 1 + else: + break + parts = parts[i:] + + if len(parts) <= 1: + return None + + glbl.wtype = WType.from_string(prefix + parts[0], containing_file, line_number) + + if glbl.wtype == None: + return None + + str_def = parts[1] + for part in parts[2:]: + str_def = str_def + " " + part + + if str_def.find("(") != -1 or str_def.find(")") != -1 or str_def.find("{") != -1 or str_def.find("}") != -1: + return None + + found = str_def.find(";") + if found == -1: + return None + + found_eq = str_def.find("=") + if found_eq != -1: + found = found_eq + + glbl.name = str_def[:found] + str_def = str_def[found+1:] + if glbl.name.find("*") == 0: + glbl.name = glbl.name.replace("*", "") + glbl.wtype.attr_type = attr_types.star + if glbl.name.find("&&") == 0: + glbl.name = glbl.name.replace("&&", "") + glbl.wtype.attr_type = attr_types.ampamp + if glbl.name.find("&") == 0: + glbl.name = glbl.name.replace("&", "") + glbl.wtype.attr_type = attr_types.amp + + if(len(str_def.strip()) != 0): + return None + + if len(glbl.name.split(",")) > 1: + glbl_list = [] + for name in glbl.name.split(","): + name = name.strip(); + glbl_list.append(WGlobal()) + glbl_list[-1].orig_text = glbl.orig_text + glbl_list[-1].wtype = glbl.wtype + glbl_list[-1].name = name + glbl_list[-1].containing_file = glbl.containing_file + glbl_list[-1].namespace = glbl.namespace + glbl_list[-1].is_const = glbl.is_const + return glbl_list + + return glbl + + def gen_def(self): + text = "\n\t" + if self.is_const: + text += "const " + text += self.wtype.gen_text() + " get_var_py_" + self.name + "()" + text += "\n\t{\n\t\t" + if self.wtype.attr_type == attr_types.star: + text += "if(" + self.namespace + "::" + self.name + " == NULL)\n\t\t\t" + text += "throw std::runtime_error(\"" + self.namespace + "::" + self.name + " is NULL\");\n\t\t" + if self.wtype.name in known_containers: + text += self.wtype.gen_text_cpp() + else: + if self.is_const: + text += "const " + text += self.wtype.gen_text() + + if self.wtype.name in classnames or (self.wtype.name in known_containers and self.wtype.attr_type == attr_types.star): + text += "*" + text += " ret_ = " + if self.wtype.name in classnames: + text += self.wtype.name + "::get_py_obj(" + if self.wtype.attr_type != attr_types.star: + text += "&" + text += self.namespace + "::" + self.name + if self.wtype.name in classnames: + text += ")" + text += ";" + + if self.wtype.name in classnames: + text += "\n\t\treturn *ret_;" + elif self.wtype.name in known_containers: + text += known_containers[self.wtype.name].translate_cpp("ret_", self.wtype.cont.args, "\n\t\t", self.wtype.attr_type == attr_types.star) + text += "\n\t\treturn ret____tmp;" + else: + text += "\n\t\treturn ret_;" + text += "\n\t}\n" + + if self.is_const: + return text + + ret = Attribute(self.wtype, "rhs"); + + if self.wtype.name in classnames: + text += "\n\tvoid set_var_py_" + self.name + "(" + self.wtype.gen_text() + " *rhs)" + else: + text += "\n\tvoid set_var_py_" + self.name + "(" + self.wtype.gen_text() + " rhs)" + text += "\n\t{" + text += ret.gen_translation() + text += "\n\t\t" + self.namespace + "::" + self.name + " = " + ret.gen_call() + ";" + text += "\n\t}\n" + + return text; + + def gen_boost_py(self): + text = "\n\t\t\t.add_static_property(\"" + self.name + "\", &" + "YOSYS_PYTHON::get_var_py_" + self.name + if not self.is_const: + text += ", &YOSYS_PYTHON::set_var_py_" + self.name + text += ")" + return text + def concat_namespace(tuple_list): if len(tuple_list) == 0: return "" @@ -1859,6 +2027,16 @@ def parse_header(source): else: debug("\t\tFound member \"" + candidate.name + "\" of class \"" + class_[0].name + "\" of type \"" + candidate.wtype.name + "\"", 2) class_[0].found_vars.append(candidate) + if candidate == None and class_ == None: + candidate = WGlobal.from_string(ugly_line, source.name, i, concat_namespace(namespaces)) + if candidate != None: + if type(candidate) == list: + for c in candidate: + glbls.append(c) + debug("\tFound global \"" + c.name + "\" in namespace " + concat_namespace(namespaces), 2) + else: + glbls.append(candidate) + debug("\tFound global \"" + candidate.name + "\" in namespace " + concat_namespace(namespaces), 2) j = i line = unpretty_string(line) @@ -1888,6 +2066,17 @@ def parse_header(source): debug("\t\tFound constructor of class \"" + class_[0].name + "\" in namespace " + concat_namespace(namespaces),2) class_[0].found_constrs.append(candidate) continue + if class_ == None: + candidate = WGlobal.from_string(line, source.name, i, concat_namespace(namespaces)) + if candidate != None: + if type(candidate) == list: + for c in candidate: + glbls.append(c) + debug("\tFound global \"" + c.name + "\" in namespace " + concat_namespace(namespaces), 2) + else: + glbls.append(candidate) + debug("\tFound global \"" + candidate.name + "\" in namespace " + concat_namespace(namespaces), 2) + continue if candidate != None: while i < j: i += 1 @@ -1990,6 +2179,7 @@ def gen_wrappers(filename, debug_level_ = 0): if len(class_.found_constrs) == 0: class_.found_constrs.append(WConstructor(source.name, class_)) debug(str(len(unowned_functions)) + " functions are unowned", 1) + debug(str(len(unowned_functions)) + " global variables", 1) for enum in enums: debug("Enum " + assure_length(enum.name, len(max(enum_names, key=len)), True) + " contains " + assure_length(str(len(enum.values)), 2, False) + " values", 1) debug("-"*col, 1) @@ -2025,10 +2215,15 @@ def gen_wrappers(filename, debug_level_ = 0): #include #include #include - +#include // std::streamsize +#include +#include // boost::iostreams::sink +#include USING_YOSYS_NAMESPACE namespace YOSYS_PYTHON { + + struct YosysStatics{}; """) for source in sources: @@ -2050,6 +2245,9 @@ namespace YOSYS_PYTHON { for fun in unowned_functions: wrapper_file.write(fun.gen_def()) + for glbl in glbls: + wrapper_file.write(glbl.gen_def()) + wrapper_file.write(""" struct Initializer { Initializer() { @@ -2068,12 +2266,89 @@ namespace YOSYS_PYTHON { } }; + + /// source: https://stackoverflow.com/questions/26033781/converting-python-io-object-to-stdostream-when-using-boostpython?noredirect=1&lq=1 + /// @brief Type that implements the Boost.IOStream's Sink and Flushable + /// concept for writing data to Python object that support: + /// n = object.write(str) # n = None or bytes written + /// object.flush() # if flush exists, then it is callable + class PythonOutputDevice + { + public: + + // This class models both the Sink and Flushable concepts. + struct category + : boost::iostreams::sink_tag, + boost::iostreams::flushable_tag + {}; + + explicit + PythonOutputDevice(boost::python::object object) + : object_(object) + {} + + // Sink concept. + public: + + typedef char char_type; + + std::streamsize write(const char* buffer, std::streamsize buffer_size) + { + namespace python = boost::python; + // Copy the buffer to a python string. + python::str data(buffer, buffer_size); + + // Invoke write on the python object, passing in the data. The following + // is equivalent to: + // n = object_.write(data) + python::extract bytes_written( + object_.attr("write")(data)); + + // Per the Sink concept, return the number of bytes written. If the + // Python return value provides a numeric result, then use it. Otherwise, + // such as the case of a File object, use the buffer_size. + return bytes_written.check() + ? bytes_written + : buffer_size; + } + + // Flushable concept. + public: + + bool flush() + { + // If flush exists, then call it. + boost::python::object flush = object_.attr("flush"); + if (!flush.is_none()) + { + flush(); + } + + // Always return true. If an error occurs, an exception should be thrown. + return true; + } + + private: + boost::python::object object_; + }; + + /// @brief Use an auxiliary function to adapt the legacy function. + void log_to_stream(boost::python::object object) + { + // Create an ostream that delegates to the python object. + boost::iostreams::stream* output = new boost::iostreams::stream(object); + Yosys::log_streams.insert(Yosys::log_streams.begin(), output); + }; + + BOOST_PYTHON_MODULE(libyosys) { using namespace boost::python; class_("Initializer"); scope().attr("_hidden") = new Initializer(); + + def("log_to_stream", &log_to_stream); """) for enum in enums: @@ -2086,6 +2361,11 @@ namespace YOSYS_PYTHON { for fun in unowned_functions: wrapper_file.write(fun.gen_boost_py()) + wrapper_file.write("\n\n\t\tclass_(\"Yosys\")\n") + for glbl in glbls: + wrapper_file.write(glbl.gen_boost_py()) + wrapper_file.write("\t\t;\n") + wrapper_file.write("\n\t}\n}\n#endif") def print_includes(): -- cgit v1.2.3 From 79be986e2248540854c3e8e1e21f5bf971079690 Mon Sep 17 00:00:00 2001 From: Benedikt Tutzer Date: Wed, 9 Oct 2019 14:21:52 +0200 Subject: Fix renaming all classes to Cpp* (This is only relevant for classes that are exposed twice, one time as a base class and one time as a derived class that can in turn be overridden in python, but actually all others were renamed) --- misc/py_wrap_generator.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/misc/py_wrap_generator.py b/misc/py_wrap_generator.py index d8649e9ce..c58c3f66a 100644 --- a/misc/py_wrap_generator.py +++ b/misc/py_wrap_generator.py @@ -909,14 +909,14 @@ class WClass: def gen_boost_py(self): body = self.gen_boost_py_body() if self.link_type == link_types.derive: - text = "\n\t\tclass_<" + self.name + ">(\"" + self.name + "\"" + text = "\n\t\tclass_<" + self.name + ">(\"Cpp" + self.name + "\"" text += body text += "\n\t\tclass_<" + self.name text += "Wrap, boost::noncopyable" text += ">(\"" + self.name + "\"" text += body else: - text = "\n\t\tclass_<" + self.name + ">(\"Cpp" + self.name + "\"" + text = "\n\t\tclass_<" + self.name + ">(\"" + self.name + "\"" text += body return text -- cgit v1.2.3 From 526fe4cb89c912dee152e28a05f4ba3b5de6c3a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Thu, 10 Oct 2019 11:31:33 +0200 Subject: xilinx: Add simulation model for IBUFG. --- techlibs/xilinx/cells_sim.v | 11 +++++++++++ techlibs/xilinx/cells_xtra.py | 6 +++--- techlibs/xilinx/xc6s_cells_xtra.v | 10 ---------- techlibs/xilinx/xc6v_cells_xtra.v | 10 ---------- techlibs/xilinx/xc7_cells_xtra.v | 10 ---------- 5 files changed, 14 insertions(+), 33 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 28cd208cd..03985b1be 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -38,6 +38,17 @@ module IBUF( assign O = I; endmodule +module IBUFG( + output O, + (* iopad_external_pin *) + input I); + parameter CAPACITANCE = "DONT_CARE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + assign O = I; +endmodule + module OBUF( (* iopad_external_pin *) output O, diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index ee20ae992..9a4747ff3 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -53,7 +53,7 @@ XC6S_CELLS = [ # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), @@ -174,7 +174,7 @@ XC6V_CELLS = [ Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), @@ -307,7 +307,7 @@ XC7_CELLS = [ Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), diff --git a/techlibs/xilinx/xc6s_cells_xtra.v b/techlibs/xilinx/xc6s_cells_xtra.v index f8dcce81d..7c0462b52 100644 --- a/techlibs/xilinx/xc6s_cells_xtra.v +++ b/techlibs/xilinx/xc6s_cells_xtra.v @@ -1282,16 +1282,6 @@ module IBUFDS_DIFF_OUT (...); input IB; endmodule -module IBUFG (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; -endmodule - module IBUFGDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v index d9e06eae2..87656fa49 100644 --- a/techlibs/xilinx/xc6v_cells_xtra.v +++ b/techlibs/xilinx/xc6v_cells_xtra.v @@ -1821,16 +1821,6 @@ module IBUFDS_GTHE1 (...); input IB; endmodule -module IBUFG (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; -endmodule - module IBUFGDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v index f36e4baa2..10eea4a5f 100644 --- a/techlibs/xilinx/xc7_cells_xtra.v +++ b/techlibs/xilinx/xc7_cells_xtra.v @@ -3932,16 +3932,6 @@ module IBUFDS_INTERMDISABLE (...); input INTERMDISABLE; endmodule -module IBUFG (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; -endmodule - module IBUFGDS (...); parameter CAPACITANCE = "DONT_CARE"; parameter DIFF_TERM = "FALSE"; -- cgit v1.2.3 From 3b44e80d4babb57f4b7c5325f666f0731a4d878b Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 10 Oct 2019 15:55:16 +0100 Subject: ecp5: Set syn_useioff on IO FFs to enable packing Signed-off-by: David Shah --- techlibs/ecp5/cells_ff.vh | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/techlibs/ecp5/cells_ff.vh b/techlibs/ecp5/cells_ff.vh index 0c9689ebd..501c1b3b2 100644 --- a/techlibs/ecp5/cells_ff.vh +++ b/techlibs/ecp5/cells_ff.vh @@ -23,15 +23,15 @@ module FD1S3JX(input PD, D, CK, output Q); parameter GSR = "ENABLED"; TRELLI // module FL1S3AY(); endmodule // Diamond I/O registers -module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module IFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="input" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule -module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3BX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3DX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("ASYNC")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3IX(input CD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("RESET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(CD), .CE(SP), .DI(D), .Q(Q)); endmodule +module OFS1P3JX(input PD, D, SP, SCLK, output Q); parameter GSR = "ENABLED"; (* syn_useioff, ioff_dir="output" *) TRELLIS_FF #(.GSR(GSR), .CEMUX("CE"), .CLKMUX("CLK"), .LSRMUX("LSR"), .REGSET("SET"), .SRMODE("LSR_OVER_CE")) _TECHMAP_REPLACE_ (.CLK(SCLK), .LSR(PD), .CE(SP), .DI(D), .Q(Q)); endmodule // TODO: Diamond I/O latches // module IFS1S1B(input PD, D, SCLK, output Q); endmodule -- cgit v1.2.3 From 7b1a6706d801773ec44d00bda0fd292c50fe39b7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 10 Oct 2019 15:58:31 +0100 Subject: ecp5: Add attrmvcp to copy syn_useioff to driving FF Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 80aa1dbc5..a79dee31f 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -297,6 +297,7 @@ struct SynthEcp5Pass : public ScriptPass run("simplemap"); run("ecp5_ffinit"); run("ecp5_gsr"); + run("attrmvcp -copy -attr syn_useioff"); run("opt_clean"); } -- cgit v1.2.3 From e1d4e683b42bb1b75acb4054a94610cdc9fec0e7 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 11 Oct 2019 14:50:33 +0100 Subject: ecp5: Add ECLKBRIDGECS blackbox Signed-off-by: David Shah --- techlibs/ecp5/cells_bb.v | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/techlibs/ecp5/cells_bb.v b/techlibs/ecp5/cells_bb.v index 0a5046db2..ae124e7a3 100644 --- a/techlibs/ecp5/cells_bb.v +++ b/techlibs/ecp5/cells_bb.v @@ -333,6 +333,13 @@ module ECLKSYNCB( ); endmodule +(* blackbox *) +module ECLKBRIDGECS( + input CLK0, CLK1, SEL, + output ECSOUT +); +endmodule + (* blackbox *) module DCCA( input CLKI, CE, -- cgit v1.2.3 From 935d3e19e2ddc315d06b4a7fe649f06578eeeb81 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 00:00:27 +0200 Subject: Add .blackbox support to blif front-end Signed-off-by: Clifford Wolf --- frontends/blif/blifparse.cc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index d17cacf29..bfcfad78a 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -174,6 +174,12 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool if (module == nullptr) goto error; + if (!strcmp(cmd, ".blackbox")) + { + module->attributes["\\blackbox"] = RTLIL::Const(1); + continue; + } + if (!strcmp(cmd, ".end")) { for (auto &wp : wideports_cache) -- cgit v1.2.3 From 71936209cf194c06dc59d5e17bf3c153a000892f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 09:06:57 +0200 Subject: Fix parsing of .cname BLIF statements Signed-off-by: Clifford Wolf --- frontends/blif/blifparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/blif/blifparse.cc b/frontends/blif/blifparse.cc index bfcfad78a..cab210605 100644 --- a/frontends/blif/blifparse.cc +++ b/frontends/blif/blifparse.cc @@ -286,7 +286,7 @@ void parse_blif(RTLIL::Design *design, std::istream &f, IdString dff_name, bool goto error_with_reason; } - module->rename(lastcell, p); + module->rename(lastcell, RTLIL::escape_id(p)); continue; } -- cgit v1.2.3 From af61d924419844b90bf6d54453489b3e41b7e353 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 10:43:47 +0200 Subject: Disable left-over log_debug in peepopt_dffmux.pmg Signed-off-by: Clifford Wolf --- passes/pmgen/peepopt_dffmux.pmg | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index bfd155c58..15c8dc22f 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -76,7 +76,7 @@ code int i = width-1; while (i > 1) { - log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]); + // log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]); if (D[i] != D[i-1]) break; if (!cmpx(rst[i], rst[i-1])) -- cgit v1.2.3 From 72323e11a4ee222c0ce928669d33333c46fb25aa Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 16 Oct 2019 11:24:56 +0200 Subject: remove duplicate DFFR --- techlibs/gowin/cells_sim.v | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index b70d1299c..de0cfa9f3 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -38,16 +38,6 @@ module DFFN (output reg Q, input CLK, D); Q <= D; endmodule -module DFFR (output reg Q, input D, CLK, RESET); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(posedge CLK) begin - if (RESET) - Q <= 1'b0; - else - Q <= D; - end -endmodule // DFFR (positive clock edge; synchronous reset) module DFFE (output reg Q, input D, CLK, CE); parameter [0:0] INIT = 1'b0; -- cgit v1.2.3 From bb0851bfc52455f2d93ee878f1876a691564b4ed Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 11:40:01 +0200 Subject: Move GENERATE_PATTERN macro to separate utility header Signed-off-by: Clifford Wolf --- passes/pmgen/generate.h | 140 +++++++++++++++++++++++++++++++++++++++++++++ passes/pmgen/pmgen.py | 16 +++++- passes/pmgen/test_pmgen.cc | 129 +---------------------------------------- 3 files changed, 157 insertions(+), 128 deletions(-) create mode 100644 passes/pmgen/generate.h diff --git a/passes/pmgen/generate.h b/passes/pmgen/generate.h new file mode 100644 index 000000000..354583de5 --- /dev/null +++ b/passes/pmgen/generate.h @@ -0,0 +1,140 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#ifndef PMGEN_GENERATE +#define PMGEN_GENERATE + +#define GENERATE_PATTERN(pmclass, pattern) \ + generate_pattern([](pmclass &pm, std::function f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design) + +void pmtest_addports(Module *module) +{ + pool driven_bits, used_bits; + SigMap sigmap(module); + int icnt = 0, ocnt = 0; + + for (auto cell : module->cells()) + for (auto conn : cell->connections()) + { + if (cell->input(conn.first)) + for (auto bit : sigmap(conn.second)) + used_bits.insert(bit); + if (cell->output(conn.first)) + for (auto bit : sigmap(conn.second)) + driven_bits.insert(bit); + } + + for (auto wire : vector(module->wires())) + { + SigSpec ibits, obits; + for (auto bit : sigmap(wire)) { + if (!used_bits.count(bit)) + obits.append(bit); + if (!driven_bits.count(bit)) + ibits.append(bit); + } + if (!ibits.empty()) { + Wire *w = module->addWire(stringf("\\i%d", icnt++), GetSize(ibits)); + w->port_input = true; + module->connect(ibits, w); + } + if (!obits.empty()) { + Wire *w = module->addWire(stringf("\\o%d", ocnt++), GetSize(obits)); + w->port_output = true; + module->connect(w, obits); + } + } + + module->fixup_ports(); +} + +template +void generate_pattern(std::function)> run, const char *pmclass, const char *pattern, Design *design) +{ + log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass); + + int modcnt = 0; + int maxmodcnt = 100; + int maxsubcnt = 4; + int timeout = 0; + vector mods; + + while (modcnt < maxmodcnt) + { + int submodcnt = 0, itercnt = 0, cellcnt = 0; + Module *mod = design->addModule(NEW_ID); + + while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000) + { + if (timeout++ > 10000) + log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n"); + + pm matcher(mod, mod->cells()); + + matcher.rng(1); + matcher.rngseed += modcnt; + matcher.rng(1); + matcher.rngseed += submodcnt; + matcher.rng(1); + matcher.rngseed += itercnt; + matcher.rng(1); + matcher.rngseed += cellcnt; + matcher.rng(1); + + if (GetSize(mod->cells()) != cellcnt) + { + bool found_match = false; + run(matcher, [&](){ found_match = true; }); + cellcnt = GetSize(mod->cells()); + + if (found_match) { + Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d", + pmclass, pattern, modcnt++)); + log("Creating module %s with %d cells.\n", log_id(m), cellcnt); + mod->cloneInto(m); + pmtest_addports(m); + mods.push_back(m); + submodcnt++; + timeout = 0; + } + } + + matcher.generate_mode = true; + run(matcher, [](){}); + } + + if (submodcnt && maxsubcnt < (1 << 16)) + maxsubcnt *= 2; + + design->remove(mod); + } + + Module *m = design->addModule(stringf("\\pmtest_%s_%s", pmclass, pattern)); + log("Creating module %s with %d cells.\n", log_id(m), GetSize(mods)); + for (auto mod : mods) { + Cell *c = m->addCell(mod->name, mod->name); + for (auto port : mod->ports) { + Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port))); + c->setPort(port, w); + } + } + pmtest_addports(m); +} + +#endif diff --git a/passes/pmgen/pmgen.py b/passes/pmgen/pmgen.py index 39a09991d..df0ffaff2 100644 --- a/passes/pmgen/pmgen.py +++ b/passes/pmgen/pmgen.py @@ -362,6 +362,7 @@ with open(outfile, "w") as f: print(" Module *module;", file=f) print(" SigMap sigmap;", file=f) print(" std::function on_accept;", file=f) + print(" bool setup_done;", file=f) print(" bool generate_mode;", file=f) print(" int accept_cnt;", file=f) print("", file=f) @@ -477,7 +478,17 @@ with open(outfile, "w") as f: print("", file=f) print(" {}_pm(Module *module, const vector &cells) :".format(prefix), file=f) - print(" module(module), sigmap(module), generate_mode(false), rngseed(12345678) {", file=f) + print(" module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f) + print(" setup(cells);", file=f) + print(" }", file=f) + print("", file=f) + + print(" {}_pm(Module *module) :".format(prefix), file=f) + print(" module(module), sigmap(module), setup_done(false), generate_mode(false), rngseed(12345678) {", file=f) + print(" }", file=f) + print("", file=f) + + print(" void setup(const vector &cells) {", file=f) for current_pattern in sorted(patterns.keys()): for s, t in sorted(udata_types[current_pattern].items()): if t.endswith("*"): @@ -485,6 +496,8 @@ with open(outfile, "w") as f: else: print(" ud_{}.{} = {}();".format(current_pattern, s, t), file=f) current_pattern = None + print(" log_assert(!setup_done);", file=f) + print(" setup_done = true;", file=f) print(" for (auto port : module->ports)", file=f) print(" add_siguser(module->wire(port), nullptr);", file=f) print(" for (auto cell : module->cells())", file=f) @@ -539,6 +552,7 @@ with open(outfile, "w") as f: for current_pattern in sorted(patterns.keys()): print(" int run_{}(std::function on_accept_f) {{".format(current_pattern), file=f) + print(" log_assert(setup_done);", file=f) print(" accept_cnt = 0;", file=f) print(" on_accept = on_accept_f;", file=f) print(" rollback = 0;", file=f) diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 4f3eec935..72dc18dcc 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -23,13 +23,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -// for peepopt_pm -bool did_something; - #include "passes/pmgen/test_pmgen_pm.h" #include "passes/pmgen/ice40_dsp_pm.h" #include "passes/pmgen/xilinx_srl_pm.h" -#include "passes/pmgen/peepopt_pm.h" + +#include "generate.h" void reduce_chain(test_pmgen_pm &pm) { @@ -118,123 +116,6 @@ void opt_eqpmux(test_pmgen_pm &pm) log(" -> %s (%s)\n", log_id(c), log_id(c->type)); } -#define GENERATE_PATTERN(pmclass, pattern) \ - generate_pattern([](pmclass &pm, std::function f){ return pm.run_ ## pattern(f); }, #pmclass, #pattern, design) - -void pmtest_addports(Module *module) -{ - pool driven_bits, used_bits; - SigMap sigmap(module); - int icnt = 0, ocnt = 0; - - for (auto cell : module->cells()) - for (auto conn : cell->connections()) - { - if (cell->input(conn.first)) - for (auto bit : sigmap(conn.second)) - used_bits.insert(bit); - if (cell->output(conn.first)) - for (auto bit : sigmap(conn.second)) - driven_bits.insert(bit); - } - - for (auto wire : vector(module->wires())) - { - SigSpec ibits, obits; - for (auto bit : sigmap(wire)) { - if (!used_bits.count(bit)) - obits.append(bit); - if (!driven_bits.count(bit)) - ibits.append(bit); - } - if (!ibits.empty()) { - Wire *w = module->addWire(stringf("\\i%d", icnt++), GetSize(ibits)); - w->port_input = true; - module->connect(ibits, w); - } - if (!obits.empty()) { - Wire *w = module->addWire(stringf("\\o%d", ocnt++), GetSize(obits)); - w->port_output = true; - module->connect(w, obits); - } - } - - module->fixup_ports(); -} - -template -void generate_pattern(std::function)> run, const char *pmclass, const char *pattern, Design *design) -{ - log("Generating \"%s\" patterns for pattern matcher \"%s\".\n", pattern, pmclass); - - int modcnt = 0; - int maxmodcnt = 100; - int maxsubcnt = 4; - int timeout = 0; - vector mods; - - while (modcnt < maxmodcnt) - { - int submodcnt = 0, itercnt = 0, cellcnt = 0; - Module *mod = design->addModule(NEW_ID); - - while (modcnt < maxmodcnt && submodcnt < maxsubcnt && itercnt++ < 1000) - { - if (timeout++ > 10000) - log_error("pmgen generator is stuck: 10000 iterations with no matching module generated.\n"); - - pm matcher(mod, mod->cells()); - - matcher.rng(1); - matcher.rngseed += modcnt; - matcher.rng(1); - matcher.rngseed += submodcnt; - matcher.rng(1); - matcher.rngseed += itercnt; - matcher.rng(1); - matcher.rngseed += cellcnt; - matcher.rng(1); - - if (GetSize(mod->cells()) != cellcnt) - { - bool found_match = false; - run(matcher, [&](){ found_match = true; }); - cellcnt = GetSize(mod->cells()); - - if (found_match) { - Module *m = design->addModule(stringf("\\pmtest_%s_%s_%05d", - pmclass, pattern, modcnt++)); - log("Creating module %s with %d cells.\n", log_id(m), cellcnt); - mod->cloneInto(m); - pmtest_addports(m); - mods.push_back(m); - submodcnt++; - timeout = 0; - } - } - - matcher.generate_mode = true; - run(matcher, [](){}); - } - - if (submodcnt && maxsubcnt < (1 << 16)) - maxsubcnt *= 2; - - design->remove(mod); - } - - Module *m = design->addModule(stringf("\\pmtest_%s_%s", pmclass, pattern)); - log("Creating module %s with %d cells.\n", log_id(m), GetSize(mods)); - for (auto mod : mods) { - Cell *c = m->addCell(mod->name, mod->name); - for (auto port : mod->ports) { - Wire *w = m->addWire(NEW_ID, GetSize(mod->wire(port))); - c->setPort(port, w); - } - } - pmtest_addports(m); -} - struct TestPmgenPass : public Pass { TestPmgenPass() : Pass("test_pmgen", "test pass for pmgen") { } void help() YS_OVERRIDE @@ -355,12 +236,6 @@ struct TestPmgenPass : public Pass { if (pattern == "xilinx_srl.variable") return GENERATE_PATTERN(xilinx_srl_pm, variable); - if (pattern == "peepopt-muldiv") - return GENERATE_PATTERN(peepopt_pm, muldiv); - - if (pattern == "peepopt-shiftmul") - return GENERATE_PATTERN(peepopt_pm, shiftmul); - log_cmd_error("Unknown pattern: %s\n", pattern.c_str()); } -- cgit v1.2.3 From b8774ae849cb6aa54a852a245f8634afaac1eb76 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 16 Oct 2019 11:40:32 +0200 Subject: Fix dffmux peepopt init handling Signed-off-by: Clifford Wolf --- passes/pmgen/peepopt.cc | 76 +++++++++++++++++++++++++++++++++++++---- passes/pmgen/peepopt_dffmux.pmg | 64 +++++++++++++++++++++++----------- 2 files changed, 113 insertions(+), 27 deletions(-) diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc index 72b02127a..2230145df 100644 --- a/passes/pmgen/peepopt.cc +++ b/passes/pmgen/peepopt.cc @@ -24,8 +24,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN bool did_something; +dict initbits; +pool rminitbits; #include "passes/pmgen/peepopt_pm.h" +#include "generate.h" struct PeepoptPass : public Pass { PeepoptPass() : Pass("peepopt", "collection of peephole optimizers") { } @@ -40,27 +43,86 @@ struct PeepoptPass : public Pass { } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { + std::string genmode; + log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n"); size_t argidx; for (argidx = 1; argidx < args.size(); argidx++) { - // if (args[argidx] == "-singleton") { - // singleton_mode = true; - // continue; - // } + if (args[argidx] == "-generate" && argidx+1 < args.size()) { + genmode = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); - for (auto module : design->selected_modules()) { + if (!genmode.empty()) + { + initbits.clear(); + rminitbits.clear(); + + if (genmode == "shiftmul") + GENERATE_PATTERN(peepopt_pm, shiftmul); + else if (genmode == "muldiv") + GENERATE_PATTERN(peepopt_pm, muldiv); + else if (genmode == "dffmux") + GENERATE_PATTERN(peepopt_pm, dffmux); + else + log_abort(); + return; + } + + for (auto module : design->selected_modules()) + { did_something = true; - while (did_something) { + + while (did_something) + { did_something = false; - peepopt_pm pm(module, module->selected_cells()); + initbits.clear(); + rminitbits.clear(); + + peepopt_pm pm(module); + + for (auto w : module->wires()) { + auto it = w->attributes.find(ID(init)); + if (it != w->attributes.end()) { + SigSpec sig = pm.sigmap(w); + Const val = it->second; + int len = std::min(GetSize(sig), GetSize(val)); + for (int i = 0; i < len; i++) { + if (sig[i].wire == nullptr) + continue; + if (val[i] != State::S0 && val[i] != State::S1) + continue; + initbits[sig[i]] = val[i]; + } + } + } + + pm.setup(module->selected_cells()); + pm.run_shiftmul(); pm.run_muldiv(); pm.run_dffmux(); + + for (auto w : module->wires()) { + auto it = w->attributes.find(ID(init)); + if (it != w->attributes.end()) { + SigSpec sig = pm.sigmap(w); + Const &val = it->second; + int len = std::min(GetSize(sig), GetSize(val)); + for (int i = 0; i < len; i++) { + if (rminitbits.count(sig[i])) + val[i] = State::Sx; + } + } + } + + initbits.clear(); + rminitbits.clear(); } } } diff --git a/passes/pmgen/peepopt_dffmux.pmg b/passes/pmgen/peepopt_dffmux.pmg index 15c8dc22f..0069b0570 100644 --- a/passes/pmgen/peepopt_dffmux.pmg +++ b/passes/pmgen/peepopt_dffmux.pmg @@ -60,12 +60,13 @@ code SigSpec Q = port(dff, \Q); int width = GetSize(D); - SigSpec &dffD = dff->connections_.at(\D); - SigSpec &dffQ = dff->connections_.at(\Q); - Const init; - for (const auto &b : Q) { - auto it = b.wire->attributes.find(\init); - init.bits.push_back(it == b.wire->attributes.end() ? State::Sx : it->second[b.offset]); + SigSpec dffD = dff->getPort(\D); + SigSpec dffQ = dff->getPort(\Q); + + Const initval; + for (auto b : Q) { + auto it = initbits.find(b); + initval.bits.push_back(it == initbits.end() ? State::Sx : it->second); } auto cmpx = [=](State lhs, State rhs) { @@ -76,56 +77,68 @@ code int i = width-1; while (i > 1) { - // log_dump(i, D[i], D[i-1], rst[i], rst[i-1], init[i], init[i-1]); if (D[i] != D[i-1]) break; if (!cmpx(rst[i], rst[i-1])) break; - if (!cmpx(init[i], init[i-1])) + if (!cmpx(initval[i], initval[i-1])) break; - if (!cmpx(rst[i], init[i])) + if (!cmpx(rst[i], initval[i])) break; + rminitbits.insert(Q[i]); module->connect(Q[i], Q[i-1]); i--; } if (i < width-1) { did_something = true; if (cemux) { - SigSpec &ceA = cemux->connections_.at(\A); - SigSpec &ceB = cemux->connections_.at(\B); - SigSpec &ceY = cemux->connections_.at(\Y); + SigSpec ceA = cemux->getPort(\A); + SigSpec ceB = cemux->getPort(\B); + SigSpec ceY = cemux->getPort(\Y); ceA.remove(i, width-1-i); ceB.remove(i, width-1-i); ceY.remove(i, width-1-i); + cemux->setPort(\A, ceA); + cemux->setPort(\B, ceB); + cemux->setPort(\Y, ceY); cemux->fixup_parameters(); + blacklist(cemux); } if (rstmux) { - SigSpec &rstA = rstmux->connections_.at(\A); - SigSpec &rstB = rstmux->connections_.at(\B); - SigSpec &rstY = rstmux->connections_.at(\Y); + SigSpec rstA = rstmux->getPort(\A); + SigSpec rstB = rstmux->getPort(\B); + SigSpec rstY = rstmux->getPort(\Y); rstA.remove(i, width-1-i); rstB.remove(i, width-1-i); rstY.remove(i, width-1-i); + rstmux->setPort(\A, rstA); + rstmux->setPort(\B, rstB); + rstmux->setPort(\Y, rstY); rstmux->fixup_parameters(); + blacklist(rstmux); } dffD.remove(i, width-1-i); dffQ.remove(i, width-1-i); + dff->setPort(\D, dffD); + dff->setPort(\Q, dffQ); dff->fixup_parameters(); + blacklist(dff); log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed top %d bits.\n", log_id(module), log_id(dff), log_id(cemux, "n/a"), log_id(rstmux, "n/a"), width-1-i); width = i+1; } if (cemux) { - SigSpec &ceA = cemux->connections_.at(\A); - SigSpec &ceB = cemux->connections_.at(\B); - SigSpec &ceY = cemux->connections_.at(\Y); + SigSpec ceA = cemux->getPort(\A); + SigSpec ceB = cemux->getPort(\B); + SigSpec ceY = cemux->getPort(\Y); int count = 0; for (int i = width-1; i >= 0; i--) { if (D[i].wire) continue; - if (cmpx(rst[i], D[i].data) && cmpx(init[i], D[i].data)) { + if (cmpx(rst[i], D[i].data) && cmpx(initval[i], D[i].data)) { count++; + rminitbits.insert(Q[i]); module->connect(Q[i], D[i]); ceA.remove(i); ceB.remove(i); @@ -134,10 +147,21 @@ code dffQ.remove(i); } } - if (count > 0) { + if (count > 0) + { did_something = true; + + cemux->setPort(\A, ceA); + cemux->setPort(\B, ceB); + cemux->setPort(\Y, ceY); cemux->fixup_parameters(); + blacklist(cemux); + + dff->setPort(\D, dffD); + dff->setPort(\Q, dffQ); dff->fixup_parameters(); + blacklist(dff); + log("dffcemux pattern in %s: dff=%s, cemux=%s, rstmux=%s; removed %d constant bits.\n", log_id(module), log_id(dff), log_id(cemux), log_id(rstmux, "n/a"), count); } } -- cgit v1.2.3 From 2ae7dec5300bb61a90842fefb1e846cd9f667a9e Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Mon, 9 Sep 2019 08:33:26 +0300 Subject: Add tests for Xilinx UG901 examples --- Makefile | 1 + tests/xilinx_ug901/asym_ram_sdp_read_wider.v | 74 +++++++++++++ tests/xilinx_ug901/asym_ram_sdp_read_wider.ys | 22 ++++ tests/xilinx_ug901/asym_ram_sdp_write_wider.v | 75 +++++++++++++ tests/xilinx_ug901/asym_ram_sdp_write_wider.ys | 31 ++++++ tests/xilinx_ug901/asym_ram_tdp_read_first.v | 85 ++++++++++++++ tests/xilinx_ug901/asym_ram_tdp_read_first.ys | 21 ++++ tests/xilinx_ug901/asym_ram_tdp_write_first.v | 92 ++++++++++++++++ tests/xilinx_ug901/asym_ram_tdp_write_first.ys | 29 +++++ tests/xilinx_ug901/black_box_1.v | 19 ++++ tests/xilinx_ug901/black_box_1.ys | 15 +++ tests/xilinx_ug901/bytewrite_ram_1b.v | 42 +++++++ tests/xilinx_ug901/bytewrite_ram_1b.ys | 22 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_nc.v | 78 +++++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys | 22 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v | 71 ++++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys | 21 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_rf.v | 61 +++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys | 21 ++++ tests/xilinx_ug901/bytewrite_tdp_ram_wf.v | 68 ++++++++++++ tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys | 23 ++++ tests/xilinx_ug901/cmacc.v | 122 +++++++++++++++++++++ tests/xilinx_ug901/cmacc.ys | 25 +++++ tests/xilinx_ug901/cmult.v | 71 ++++++++++++ tests/xilinx_ug901/cmult.ys | 31 ++++++ tests/xilinx_ug901/dynamic_shift_registers_1.v | 21 ++++ tests/xilinx_ug901/dynamic_shift_registers_1.ys | 15 +++ tests/xilinx_ug901/dynpreaddmultadd.v | 47 ++++++++ tests/xilinx_ug901/dynpreaddmultadd.ys | 31 ++++++ tests/xilinx_ug901/fsm_1.v | 42 +++++++ tests/xilinx_ug901/fsm_1.ys | 16 +++ tests/xilinx_ug901/latches.v | 17 +++ tests/xilinx_ug901/latches.ys | 10 ++ tests/xilinx_ug901/macc.v | 47 ++++++++ tests/xilinx_ug901/macc.ys | 23 ++++ tests/xilinx_ug901/mult_unsigned.v | 33 ++++++ tests/xilinx_ug901/mult_unsigned.ys | 29 +++++ tests/xilinx_ug901/presubmult.v | 43 ++++++++ tests/xilinx_ug901/presubmult.ys | 23 ++++ tests/xilinx_ug901/ram_simple_dual_one_clock.v | 25 +++++ tests/xilinx_ug901/ram_simple_dual_one_clock.ys | 20 ++++ tests/xilinx_ug901/ram_simple_dual_two_clocks.v | 30 +++++ tests/xilinx_ug901/ram_simple_dual_two_clocks.ys | 20 ++++ tests/xilinx_ug901/rams_dist.v | 24 ++++ tests/xilinx_ug901/rams_dist.ys | 21 ++++ tests/xilinx_ug901/rams_init_file.data | 64 +++++++++++ tests/xilinx_ug901/rams_init_file.v | 24 ++++ tests/xilinx_ug901/rams_init_file.ys | 22 ++++ tests/xilinx_ug901/rams_pipeline.v | 42 +++++++ tests/xilinx_ug901/rams_pipeline.ys | 22 ++++ tests/xilinx_ug901/rams_sp_nc.v | 26 +++++ tests/xilinx_ug901/rams_sp_nc.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rf.v | 26 +++++ tests/xilinx_ug901/rams_sp_rf.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rf_rst.v | 29 +++++ tests/xilinx_ug901/rams_sp_rf_rst.ys | 28 +++++ tests/xilinx_ug901/rams_sp_rom.v | 46 ++++++++ tests/xilinx_ug901/rams_sp_rom.ys | 22 ++++ tests/xilinx_ug901/rams_sp_rom_1.v | 53 +++++++++ tests/xilinx_ug901/rams_sp_rom_1.ys | 22 ++++ tests/xilinx_ug901/rams_sp_wf.v | 26 +++++ tests/xilinx_ug901/rams_sp_wf.ys | 26 +++++ tests/xilinx_ug901/rams_tdp_rf_rf.v | 33 ++++++ tests/xilinx_ug901/rams_tdp_rf_rf.ys | 21 ++++ tests/xilinx_ug901/registers_1.v | 25 +++++ tests/xilinx_ug901/registers_1.ys | 12 ++ tests/xilinx_ug901/run-test.sh | 20 ++++ tests/xilinx_ug901/sfir_shifter.v | 19 ++++ tests/xilinx_ug901/sfir_shifter.ys | 16 +++ tests/xilinx_ug901/shift_registers_0.v | 22 ++++ tests/xilinx_ug901/shift_registers_0.ys | 13 +++ tests/xilinx_ug901/shift_registers_1.v | 24 ++++ tests/xilinx_ug901/shift_registers_1.ys | 14 +++ tests/xilinx_ug901/squarediffmacc.v | 52 +++++++++ tests/xilinx_ug901/squarediffmacc.ys | 23 ++++ tests/xilinx_ug901/squarediffmult.v | 42 +++++++ tests/xilinx_ug901/squarediffmult.ys | 30 +++++ tests/xilinx_ug901/top_mux.v | 18 +++ tests/xilinx_ug901/top_mux.ys | 13 +++ tests/xilinx_ug901/tristates_1.v | 17 +++ tests/xilinx_ug901/tristates_1.ys | 13 +++ tests/xilinx_ug901/tristates_2.v | 10 ++ tests/xilinx_ug901/tristates_2.ys | 13 +++ .../xilinx_ultraram_single_port_no_change.v | 78 +++++++++++++ .../xilinx_ultraram_single_port_no_change.ys | 25 +++++ .../xilinx_ultraram_single_port_read_first.v | 78 +++++++++++++ .../xilinx_ultraram_single_port_read_first.ys | 24 ++++ .../xilinx_ultraram_single_port_write_first.v | 82 ++++++++++++++ .../xilinx_ultraram_single_port_write_first.ys | 24 ++++ 89 files changed, 2962 insertions(+) create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.v create mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.v create mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.ys create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.v create mode 100644 tests/xilinx_ug901/asym_ram_tdp_read_first.ys create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.v create mode 100644 tests/xilinx_ug901/asym_ram_tdp_write_first.ys create mode 100644 tests/xilinx_ug901/black_box_1.v create mode 100644 tests/xilinx_ug901/black_box_1.ys create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.v create mode 100644 tests/xilinx_ug901/bytewrite_ram_1b.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_rf.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_wf.v create mode 100644 tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys create mode 100644 tests/xilinx_ug901/cmacc.v create mode 100644 tests/xilinx_ug901/cmacc.ys create mode 100644 tests/xilinx_ug901/cmult.v create mode 100644 tests/xilinx_ug901/cmult.ys create mode 100644 tests/xilinx_ug901/dynamic_shift_registers_1.v create mode 100644 tests/xilinx_ug901/dynamic_shift_registers_1.ys create mode 100644 tests/xilinx_ug901/dynpreaddmultadd.v create mode 100644 tests/xilinx_ug901/dynpreaddmultadd.ys create mode 100644 tests/xilinx_ug901/fsm_1.v create mode 100644 tests/xilinx_ug901/fsm_1.ys create mode 100644 tests/xilinx_ug901/latches.v create mode 100644 tests/xilinx_ug901/latches.ys create mode 100644 tests/xilinx_ug901/macc.v create mode 100644 tests/xilinx_ug901/macc.ys create mode 100644 tests/xilinx_ug901/mult_unsigned.v create mode 100644 tests/xilinx_ug901/mult_unsigned.ys create mode 100644 tests/xilinx_ug901/presubmult.v create mode 100644 tests/xilinx_ug901/presubmult.ys create mode 100644 tests/xilinx_ug901/ram_simple_dual_one_clock.v create mode 100644 tests/xilinx_ug901/ram_simple_dual_one_clock.ys create mode 100644 tests/xilinx_ug901/ram_simple_dual_two_clocks.v create mode 100644 tests/xilinx_ug901/ram_simple_dual_two_clocks.ys create mode 100644 tests/xilinx_ug901/rams_dist.v create mode 100644 tests/xilinx_ug901/rams_dist.ys create mode 100644 tests/xilinx_ug901/rams_init_file.data create mode 100644 tests/xilinx_ug901/rams_init_file.v create mode 100644 tests/xilinx_ug901/rams_init_file.ys create mode 100644 tests/xilinx_ug901/rams_pipeline.v create mode 100644 tests/xilinx_ug901/rams_pipeline.ys create mode 100644 tests/xilinx_ug901/rams_sp_nc.v create mode 100644 tests/xilinx_ug901/rams_sp_nc.ys create mode 100644 tests/xilinx_ug901/rams_sp_rf.v create mode 100644 tests/xilinx_ug901/rams_sp_rf.ys create mode 100644 tests/xilinx_ug901/rams_sp_rf_rst.v create mode 100644 tests/xilinx_ug901/rams_sp_rf_rst.ys create mode 100644 tests/xilinx_ug901/rams_sp_rom.v create mode 100644 tests/xilinx_ug901/rams_sp_rom.ys create mode 100644 tests/xilinx_ug901/rams_sp_rom_1.v create mode 100644 tests/xilinx_ug901/rams_sp_rom_1.ys create mode 100644 tests/xilinx_ug901/rams_sp_wf.v create mode 100644 tests/xilinx_ug901/rams_sp_wf.ys create mode 100644 tests/xilinx_ug901/rams_tdp_rf_rf.v create mode 100644 tests/xilinx_ug901/rams_tdp_rf_rf.ys create mode 100644 tests/xilinx_ug901/registers_1.v create mode 100644 tests/xilinx_ug901/registers_1.ys create mode 100755 tests/xilinx_ug901/run-test.sh create mode 100644 tests/xilinx_ug901/sfir_shifter.v create mode 100644 tests/xilinx_ug901/sfir_shifter.ys create mode 100644 tests/xilinx_ug901/shift_registers_0.v create mode 100644 tests/xilinx_ug901/shift_registers_0.ys create mode 100644 tests/xilinx_ug901/shift_registers_1.v create mode 100644 tests/xilinx_ug901/shift_registers_1.ys create mode 100644 tests/xilinx_ug901/squarediffmacc.v create mode 100644 tests/xilinx_ug901/squarediffmacc.ys create mode 100644 tests/xilinx_ug901/squarediffmult.v create mode 100644 tests/xilinx_ug901/squarediffmult.ys create mode 100644 tests/xilinx_ug901/top_mux.v create mode 100644 tests/xilinx_ug901/top_mux.ys create mode 100644 tests/xilinx_ug901/tristates_1.v create mode 100644 tests/xilinx_ug901/tristates_1.ys create mode 100644 tests/xilinx_ug901/tristates_2.v create mode 100644 tests/xilinx_ug901/tristates_2.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_read_first.ys create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.v create mode 100644 tests/xilinx_ug901/xilinx_ultraram_single_port_write_first.ys diff --git a/Makefile b/Makefile index 895cfbf89..ef02bc947 100644 --- a/Makefile +++ b/Makefile @@ -715,6 +715,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh + +cd tests/xilinx_ug901 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v new file mode 100644 index 000000000..0716dffdc --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v @@ -0,0 +1,74 @@ +// Asymmetric port RAM +// Read Wider than Write. Read Statement in loop +//asym_ram_sdp_read_wider.v + +module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); +parameter WIDTHA = 4; +parameter SIZEA = 1024; +parameter ADDRWIDTHA = 10; + +parameter WIDTHB = 16; +parameter SIZEB = 256; +parameter ADDRWIDTHB = 8; +input clkA; +input clkB; +input weA; +input enaA, enaB; +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +output [WIDTHB-1:0] doB; +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHB-1:0] readB; + +always @(posedge clkA) +begin + if (enaA) begin + if (weA) + RAM[addrA] <= diA; + end +end + + +always @(posedge clkB) +begin : ramread + integer i; + reg [log2RATIO-1:0] lsbaddr; + if (enaB) begin + for (i = 0; i < RATIO; i = i+1) begin + lsbaddr = i; + readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; + end + end +end +assign doB = readB; + +endmodule + diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys new file mode 100644 index 000000000..c63157cdf --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys @@ -0,0 +1,22 @@ +read_verilog asym_ram_sdp_read_wider.v +hierarchy -top asym_ram_sdp_read_wider +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_sdp_read_wider +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 1 t:LUT2 +select -assert-count 4 t:RAMB18E1 + +select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v new file mode 100644 index 000000000..22d12d2ce --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v @@ -0,0 +1,75 @@ +// Asymmetric port RAM +// Write wider than Read. Write Statement in a loop. +// asym_ram_sdp_write_wider.v + +module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); +parameter WIDTHB = 4; +//Default parameters were changed because of slow test +//parameter SIZEB = 1024; +//parameter ADDRWIDTHB = 10; +parameter SIZEB = 256; +parameter ADDRWIDTHB = 8; + +//parameter WIDTHA = 16; +parameter WIDTHA = 8; +parameter SIZEA = 256; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA; +input enaA, enaB; +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +output [WIDTHB-1:0] doB; +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) begin + if (enaB) begin + readB <= RAM[addrB]; + end +end +assign doB = readB; + +always @(posedge clkA) +begin : ramwrite + integer i; + reg [log2RATIO-1:0] lsbaddr; + for (i=0; i< RATIO; i= i+ 1) begin : write1 + lsbaddr = i; + if (enaA) begin + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end +end + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys new file mode 100644 index 000000000..229d98df6 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys @@ -0,0 +1,31 @@ +read_verilog asym_ram_sdp_write_wider.v +hierarchy -top asym_ram_sdp_write_wider +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_sdp_write_wider +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 1028 t:FDRE +select -assert-count 170 t:LUT2 +select -assert-count 6 t:LUT3 +select -assert-count 518 t:LUT4 +select -assert-count 10 t:LUT5 +select -assert-count 484 t:LUT6 +select -assert-count 157 t:MUXF7 +select -assert-count 3 t:MUXF8 + +#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4 +#select -assert-count 8 t:RAM128X1D + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v new file mode 100644 index 000000000..2b807a382 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.v @@ -0,0 +1,85 @@ +// Asymetric RAM - TDP +// READ_FIRST MODE. +// asym_ram_tdp_read_first.v + + +module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); +parameter WIDTHB = 4; +parameter SIZEB = 1024; +parameter ADDRWIDTHB = 10; +parameter WIDTHA = 16; +parameter SIZEA = 256; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA, weB; +input enaA, enaB; + +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +input [WIDTHB-1:0] diB; + +output [WIDTHA-1:0] doA; +output [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHA-1:0] readA; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) +begin + if (enaB) begin + readB <= RAM[addrB] ; + if (weB) + RAM[addrB] <= diB; + end +end + + +always @(posedge clkA) +begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i=0; i< RATIO; i= i+ 1) begin + lsbaddr = i; + if (enaA) begin + readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}]; + + if (weA) + RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; + end + end +end + +assign doA = readA; +assign doB = readB; + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys new file mode 100644 index 000000000..5f96b800c --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys @@ -0,0 +1,21 @@ +read_verilog asym_ram_tdp_read_first.v +hierarchy -top asym_ram_tdp_read_first +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_tdp_read_first +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 1 t:$mem +select -assert-count 2 t:LUT2 + +select -assert-none t:$mem t:LUT2 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v new file mode 100644 index 000000000..90187ea26 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.v @@ -0,0 +1,92 @@ +// Asymmetric port RAM - TDP +// WRITE_FIRST MODE. +// asym_ram_tdp_write_first.v + + +module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); +parameter WIDTHB = 4; +//Default parameters were changed because of slow test +//parameter SIZEB = 1024; +//parameter ADDRWIDTHB = 10; +parameter SIZEB = 32; +parameter ADDRWIDTHB = 8; + +//parameter WIDTHA = 16; +parameter WIDTHA = 4; +//parameter SIZEA = 256; +parameter SIZEA = 32; +parameter ADDRWIDTHA = 8; +input clkA; +input clkB; +input weA, weB; +input enaA, enaB; + +input [ADDRWIDTHA-1:0] addrA; +input [ADDRWIDTHB-1:0] addrB; +input [WIDTHA-1:0] diA; +input [WIDTHB-1:0] diB; + +output [WIDTHA-1:0] doA; +output [WIDTHB-1:0] doB; + +`define max(a,b) {(a) > (b) ? (a) : (b)} +`define min(a,b) {(a) < (b) ? (a) : (b)} + +function integer log2; +input integer value; +reg [31:0] shifted; +integer res; +begin + if (value < 2) + log2 = value; + else + begin + shifted = value-1; + for (res=0; shifted>0; res=res+1) + shifted = shifted>>1; + log2 = res; + end +end +endfunction + +localparam maxSIZE = `max(SIZEA, SIZEB); +localparam maxWIDTH = `max(WIDTHA, WIDTHB); +localparam minWIDTH = `min(WIDTHA, WIDTHB); + +localparam RATIO = maxWIDTH / minWIDTH; +localparam log2RATIO = log2(RATIO); + +reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; +reg [WIDTHA-1:0] readA; +reg [WIDTHB-1:0] readB; + +always @(posedge clkB) +begin + if (enaB) begin + if (weB) + RAM[addrB] = diB; + readB = RAM[addrB] ; + end +end + + +always @(posedge clkA) +begin : portA + integer i; + reg [log2RATIO-1:0] lsbaddr ; + for (i=0; i< RATIO; i= i+ 1) begin + lsbaddr = i; + if (enaA) begin + + if (weA) + RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH]; + + readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}]; + end + end +end + +assign doA = readA; +assign doB = readB; + +endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys new file mode 100644 index 000000000..bbe3cc849 --- /dev/null +++ b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys @@ -0,0 +1,29 @@ +read_verilog asym_ram_tdp_write_first.v +hierarchy -top asym_ram_tdp_write_first +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd asym_ram_tdp_write_first +stat +#Vivado synthesizes 1 RAMB18E1. +select -assert-count 2 t:BUFG +select -assert-count 200 t:FDRE +select -assert-count 10 t:LUT2 +select -assert-count 44 t:LUT3 +select -assert-count 81 t:LUT4 +select -assert-count 104 t:LUT5 +select -assert-count 560 t:LUT6 +select -assert-count 261 t:MUXF7 +select -assert-count 127 t:MUXF8 + + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v new file mode 100644 index 000000000..40caa1b10 --- /dev/null +++ b/tests/xilinx_ug901/black_box_1.v @@ -0,0 +1,19 @@ +// Black Box +// black_box_1.v +// +(* black_box *) module black_box1 (in1, in2, dout); +input in1, in2; +output dout; +endmodule + +module black_box_1 (DI_1, DI_2, DOUT); +input DI_1, DI_2; +output DOUT; + +black_box1 U1 ( + .in1(DI_1), + .in2(DI_2), + .dout(DOUT) + ); + +endmodule diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys new file mode 100644 index 000000000..acf0b5761 --- /dev/null +++ b/tests/xilinx_ug901/black_box_1.ys @@ -0,0 +1,15 @@ +read_verilog black_box_1.v +hierarchy -top black_box_1 +proc +tribuf +flatten +synth +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd black_box_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 black box. +#stat +#select -assert-count 0 t:LUT1 +#select -assert-count 1 t:$_TBUF_ +#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v new file mode 100644 index 000000000..46d86c297 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_ram_1b.v @@ -0,0 +1,42 @@ +// Single-Port BRAM with Byte-wide Write Enable +// Read-First mode +// Single-process description +// Compact description of the write with a generate-for +// statement +// Column width and number of columns easily configurable +// +// bytewrite_ram_1b.v +// + +module bytewrite_ram_1b (clk, we, addr, di, do); + +parameter SIZE = 1024; +parameter ADDR_WIDTH = 10; +parameter COL_WIDTH = 8; +parameter NB_COL = 4; + +input clk; +input [NB_COL-1:0] we; +input [ADDR_WIDTH-1:0] addr; +input [NB_COL*COL_WIDTH-1:0] di; +output reg [NB_COL*COL_WIDTH-1:0] do; + +reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; + +always @(posedge clk) +begin + do <= RAM[addr]; +end + +generate genvar i; +for (i = 0; i < NB_COL; i = i+1) +begin +always @(posedge clk) +begin + if (we[i]) + RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; + end +end +endgenerate + +endmodule diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys new file mode 100644 index 000000000..4f0967801 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_ram_1b.ys @@ -0,0 +1,22 @@ +read_verilog bytewrite_ram_1b.v +hierarchy -top bytewrite_ram_1b +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd bytewrite_ram_1b +stat +#Vivado synthesizes 1 RAMB36E1. +select -assert-count 1 t:BUFG +select -assert-count 32 t:LUT2 +select -assert-count 8 t:RAMB36E1 + +select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v new file mode 100644 index 000000000..1093b0838 --- /dev/null +++ b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v @@ -0,0 +1,78 @@ +// +// True-Dual-Port BRAM with Byte-wide Write Enable +// No-Change mode +// +// bytewrite_tdp_ram_nc.v +// +// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended +module bytewrite_tdp_ram_nc + #( + //--------------------------------------------------------------- + parameter NUM_COL = 4, + parameter COL_WIDTH = 8, + parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth + parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits + //--------------------------------------------------------------- + ) ( + input clkA, + input enaA, + input [NUM_COL-1:0] weA, + input [ADDR_WIDTH-1:0] addrA, + input [DATA_WIDTH-1:0] dinA, + output reg [DATA_WIDTH-1:0] doutA, + + input clkB, + input enaB, + input [NUM_COL-1:0] weB, + input [ADDR_WIDTH-1:0] addrB, + input [DATA_WIDTH-1:0] dinB, + output reg [DATA_WIDTH-1:0] doutB + ); + + + // Core Memory + reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; + + // Port-A Operation + generate + genvar i; + for(i=0;i run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v new file mode 100644 index 000000000..a8b144bcd --- /dev/null +++ b/tests/xilinx_ug901/sfir_shifter.v @@ -0,0 +1,19 @@ +//sfir_shifter.v +(* dont_touch = "yes" *) +module sfir_shifter #(parameter dsize = 16, nbtap = 4) + (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout); + + (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1]; + integer i; + + always @(posedge clk) + begin + tmp[0] <= datain; + for (i=0; i<=2*nbtap-2; i=i+1) + tmp[i+1] <= tmp[i]; + end + + assign dataout = tmp[2*nbtap-1]; + +endmodule +// sfir_shifter diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys new file mode 100644 index 000000000..b9fbeb8cb --- /dev/null +++ b/tests/xilinx_ug901/sfir_shifter.ys @@ -0,0 +1,16 @@ +read_verilog sfir_shifter.v +hierarchy -top sfir_shifter +proc +flatten +#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd sfir_shifter +#Vivado synthesizes 32 FDRE, 16 SRL16E. +stat +select -assert-count 1 t:BUFG +select -assert-count 16 t:SRL16E + +select -assert-none t:BUFG t:SRL16E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v new file mode 100644 index 000000000..77a3ec893 --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_0.v @@ -0,0 +1,22 @@ +// 8-bit Shift Register +// Rising edge clock +// Active high clock enable +// Concatenation-based template +// File: shift_registers_0.v + +module shift_registers_0 (clk, clken, SI, SO); +parameter WIDTH = 32; +input clk, clken, SI; +output SO; + +reg [WIDTH-1:0] shreg; + +always @(posedge clk) + begin + if (clken) + shreg = {shreg[WIDTH-2:0], SI}; + end + +assign SO = shreg[WIDTH-1]; + +endmodule diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys new file mode 100644 index 000000000..ae7d23a7f --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_0.ys @@ -0,0 +1,13 @@ +read_verilog shift_registers_0.v +hierarchy -top shift_registers_0 +proc +flatten +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd shift_registers_0 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. +select -assert-count 1 t:BUFG +select -assert-count 1 t:SRLC32E +select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v new file mode 100644 index 000000000..d50820e7b --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_1.v @@ -0,0 +1,24 @@ +// 32-bit Shift Register +// Rising edge clock +// Active high clock enable +// For-loop based template +// File: shift_registers_1.v + +module shift_registers_1 (clk, clken, SI, SO); +parameter WIDTH = 32; +input clk, clken, SI; +output SO; +reg [WIDTH-1:0] shreg; + +integer i; +always @(posedge clk) +begin + if (clken) + begin + for (i = 0; i < WIDTH-1; i = i+1) + shreg[i+1] <= shreg[i]; + shreg[0] <= SI; + end +end +assign SO = shreg[WIDTH-1]; +endmodule diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys new file mode 100644 index 000000000..fb935c446 --- /dev/null +++ b/tests/xilinx_ug901/shift_registers_1.ys @@ -0,0 +1,14 @@ +read_verilog shift_registers_1.v +hierarchy -top shift_registers_1 +proc +flatten + +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd shift_registers_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. +select -assert-count 1 t:BUFG +select -assert-count 1 t:SRLC32E +select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v new file mode 100644 index 000000000..6535b24c4 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmacc.v @@ -0,0 +1,52 @@ +// This module performs subtraction of two inputs, squaring on the diff +// and then accumulation +// This can be implemented in 1 DSP Block (Ultrascale architecture) +// File : squarediffmacc.v +module squarediffmacc # ( + //Default parameters were changed because of slow test + //parameter SIZEIN = 16, + //SIZEOUT = 40 + parameter SIZEIN = 8, + SIZEOUT = 20 + ) + ( + input clk, + input ce, + input sload, + input signed [SIZEIN-1:0] a, + input signed [SIZEIN-1:0] b, + output signed [SIZEOUT+1:0] accum_out + ); + +// Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN:0] diff_reg; +reg sload_reg; +reg signed [2*SIZEIN+1:0] m_reg; +reg signed [SIZEOUT-1:0] adder_out, old_result; + + always @(sload_reg or adder_out) + if (sload_reg) + old_result <= 0; + else + // 'sload' is now and opens the accumulation loop. + // The accumulator takes the next multiplier output + // in the same cycle. + old_result <= adder_out; + + always @(posedge clk) + if (ce) + begin + a_reg <= a; + b_reg <= b; + diff_reg <= a_reg - b_reg; + m_reg <= diff_reg * diff_reg; + sload_reg <= sload; + // Store accumulation result into a register + adder_out <= old_result + m_reg; + end + + // Output accumulation result + assign accum_out = adder_out; + +endmodule // squarediffmacc diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys new file mode 100644 index 000000000..92474bea3 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmacc.ys @@ -0,0 +1,23 @@ +read_verilog squarediffmacc.v +hierarchy -top squarediffmacc +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd squarediffmacc +#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT. +stat +select -assert-count 1 t:BUFG +select -assert-count 64 t:FDRE +select -assert-count 78 t:LUT2 +select -assert-count 7 t:LUT3 +select -assert-count 11 t:LUT4 +select -assert-count 8 t:LUT5 +select -assert-count 125 t:LUT6 +select -assert-count 44 t:MUXCY +select -assert-count 50 t:MUXF7 +select -assert-count 17 t:MUXF8 +select -assert-count 47 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v new file mode 100644 index 000000000..0f41b67bc --- /dev/null +++ b/tests/xilinx_ug901/squarediffmult.v @@ -0,0 +1,42 @@ +// Squarer support for DSP block (DSP48E2) with +// pre-adder configured +// as subtractor +// File: squarediffmult.v + +module squarediffmult # (parameter SIZEIN = 16) + ( + input clk, ce, rst, + input signed [SIZEIN-1:0] a, b, + output signed [2*SIZEIN+1:0] square_out + ); + + // Declare registers for intermediate values +reg signed [SIZEIN-1:0] a_reg, b_reg; +reg signed [SIZEIN:0] diff_reg; +reg signed [2*SIZEIN+1:0] m_reg, p_reg; + +always @(posedge clk) +begin + if (rst) + begin + a_reg <= 0; + b_reg <= 0; + diff_reg <= 0; + m_reg <= 0; + p_reg <= 0; + end + else + if (ce) + begin + a_reg <= a; + b_reg <= b; + diff_reg <= a_reg - b_reg; + m_reg <= diff_reg * diff_reg; + p_reg <= m_reg; + end +end + +// Output result +assign square_out = p_reg; + +endmodule // squarediffmult diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys new file mode 100644 index 000000000..3468e5bb4 --- /dev/null +++ b/tests/xilinx_ug901/squarediffmult.ys @@ -0,0 +1,30 @@ +read_verilog squarediffmult.v +hierarchy -top squarediffmult +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd squarediffmult +stat +#Vivado synthesizes 16 FDRE, 1 DSP48E1. +select -assert-count 1 t:BUFG +select -assert-count 117 t:FDRE +select -assert-count 223 t:LUT2 +select -assert-count 50 t:LUT3 +select -assert-count 38 t:LUT4 +select -assert-count 56 t:LUT5 +select -assert-count 372 t:LUT6 +select -assert-count 49 t:MUXCY +select -assert-count 99 t:MUXF7 +select -assert-count 26 t:MUXF8 +select -assert-count 51 t:XORCY + +select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v new file mode 100644 index 000000000..c23c7491c --- /dev/null +++ b/tests/xilinx_ug901/top_mux.v @@ -0,0 +1,18 @@ +// Multiplexer using case statement +module mux4 (sel, a, b, c, d, outmux); +input [1:0] sel; +input [1:0] a, b, c, d; +output [1:0] outmux; +reg [1:0] outmux; + +always @ * + begin + case(sel) + 2'b00 : outmux = a; + 2'b01 : outmux = b; + 2'b10 : outmux = c; + 2'b11 : outmux = d; + endcase + end +endmodule + diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys new file mode 100644 index 000000000..0245f3bbc --- /dev/null +++ b/tests/xilinx_ug901/top_mux.ys @@ -0,0 +1,13 @@ +read_verilog top_mux.v +hierarchy -top mux4 +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +cd mux4 +#Vivado synthesizes 2 LUT. +stat +select -assert-count 2 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v new file mode 100644 index 000000000..0038a9989 --- /dev/null +++ b/tests/xilinx_ug901/tristates_1.v @@ -0,0 +1,17 @@ +// Tristate Description Using Combinatorial Always Block +// File: tristates_1.v +// +module tristates_1 (T, I, O); +input T, I; +output O; +reg O; + +always @(T or I) +begin + if (~T) + O = I; + else + O = 1'bZ; +end + +endmodule diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys new file mode 100644 index 000000000..7c13dc227 --- /dev/null +++ b/tests/xilinx_ug901/tristates_1.ys @@ -0,0 +1,13 @@ +read_verilog tristates_1.v +hierarchy -top tristates_1 +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristates_1 # Constrain all select calls below inside the top module +#Vivado synthesizes 3 IBUF, 1 OBUFT. +select -assert-count 1 t:LUT1 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v new file mode 100644 index 000000000..0c70a1257 --- /dev/null +++ b/tests/xilinx_ug901/tristates_2.v @@ -0,0 +1,10 @@ +// Tristate Description Using Concurrent Assignment +// File: tristates_2.v +// +module tristates_2 (T, I, O); +input T, I; +output O; + +assign O = (~T) ? I: 1'bZ; + +endmodule diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys new file mode 100644 index 000000000..ba2e1d855 --- /dev/null +++ b/tests/xilinx_ug901/tristates_2.ys @@ -0,0 +1,13 @@ +read_verilog tristates_2.v +hierarchy -top tristates_2 +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristates_2 # Constrain all select calls below inside the top module +#Vivado synthesizes 3 IBUF, 1 OBUFT. +select -assert-count 1 t:LUT1 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v new file mode 100644 index 000000000..f5e843dc9 --- /dev/null +++ b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v @@ -0,0 +1,78 @@ +// Xilinx UltraRAM Single Port No Change Mode. This code implements +// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is +// when data is written, the output of RAM is unchanged. Only when write is +// inactive data corresponding to the address is presented on the output port. +// +module xilinx_ultraram_single_port_no_change #( +//Default parameters were changed because of slow test + //parameter AWIDTH = 12, // Address Width + //parameter DWIDTH = 72, // Data Width + //parameter NBPIPE = 3 // Number of pipeline Registers + parameter AWIDTH = 8, // Address Width + parameter DWIDTH = 8, // Data Width + parameter NBPIPE = 3 // Number of pipeline Registers + ) ( + input clk, // Clock + input rst, // Reset + input we, // Write Enable + input regce, // Output Register Enable + input mem_en, // Memory Enable + input [DWIDTH-1:0] din, // Data Input + input [AWIDTH-1:0] addr, // Address Input + output reg [DWIDTH-1:0] dout // Data Output + ); + +(* ram_style = "ultra" *) +reg [DWIDTH-1:0] mem[(1< Date: Mon, 9 Sep 2019 08:49:29 +0300 Subject: Add comments for unproven cells. --- tests/xilinx_ug901/dynamic_shift_registers_1.ys | 2 +- tests/xilinx_ug901/shift_registers_0.ys | 1 + tests/xilinx_ug901/shift_registers_1.ys | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/tests/xilinx_ug901/dynamic_shift_registers_1.ys b/tests/xilinx_ug901/dynamic_shift_registers_1.ys index 994e12a3e..f70c84f2f 100644 --- a/tests/xilinx_ug901/dynamic_shift_registers_1.ys +++ b/tests/xilinx_ug901/dynamic_shift_registers_1.ys @@ -2,7 +2,7 @@ read_verilog dynamic_shift_registers_1.v hierarchy -top dynamic_shift_register_1 proc flatten - +#ERROR: Found 1 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys index ae7d23a7f..89da1d7cc 100644 --- a/tests/xilinx_ug901/shift_registers_0.ys +++ b/tests/xilinx_ug901/shift_registers_0.ys @@ -2,6 +2,7 @@ read_verilog shift_registers_0.v hierarchy -top shift_registers_0 proc flatten +#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys index fb935c446..b53b6cb25 100644 --- a/tests/xilinx_ug901/shift_registers_1.ys +++ b/tests/xilinx_ug901/shift_registers_1.ys @@ -2,7 +2,7 @@ read_verilog shift_registers_1.v hierarchy -top shift_registers_1 proc flatten - +#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -- cgit v1.2.3 From 757c476f625bef871f9a4388d4d19bf8c3bc400b Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 10 Sep 2019 08:08:03 +0300 Subject: Add smoke tests to tests/xilinx --- Makefile | 1 + tests/xilinx/add_sub.v | 13 ++++++ tests/xilinx/add_sub.ys | 10 +++++ tests/xilinx/adffs.v | 91 ++++++++++++++++++++++++++++++++++++++++++ tests/xilinx/adffs.ys | 14 +++++++ tests/xilinx/alu.v | 19 +++++++++ tests/xilinx/alu.ys | 21 ++++++++++ tests/xilinx/counter.v | 17 ++++++++ tests/xilinx/counter.ys | 14 +++++++ tests/xilinx/dffs.v | 37 ++++++++++++++++++ tests/xilinx/dffs.ys | 10 +++++ tests/xilinx/div_mod.v | 13 ++++++ tests/xilinx/div_mod.ys | 17 ++++++++ tests/xilinx/fsm.v | 73 ++++++++++++++++++++++++++++++++++ tests/xilinx/fsm.ys | 14 +++++++ tests/xilinx/latches.v | 6 +-- tests/xilinx/latches.ys | 17 +++++--- tests/xilinx/logic.v | 18 +++++++++ tests/xilinx/logic.ys | 10 +++++ tests/xilinx/memory.v | 21 ++++++++++ tests/xilinx/memory.ys | 17 ++++++++ tests/xilinx/mul.v | 11 ++++++ tests/xilinx/mul.ys | 15 +++++++ tests/xilinx/mux.v | 100 +++++++++++++++++++++++++++++++++++++++++++++++ tests/xilinx/mux.ys | 10 +++++ tests/xilinx/run-test.sh | 2 +- tests/xilinx/shifter.v | 22 +++++++++++ tests/xilinx/shifter.ys | 11 ++++++ tests/xilinx/tribuf.v | 29 ++++++++++++++ tests/xilinx/tribuf.ys | 11 ++++++ 30 files changed, 655 insertions(+), 9 deletions(-) create mode 100644 tests/xilinx/add_sub.v create mode 100644 tests/xilinx/add_sub.ys create mode 100644 tests/xilinx/adffs.v create mode 100644 tests/xilinx/adffs.ys create mode 100644 tests/xilinx/alu.v create mode 100644 tests/xilinx/alu.ys create mode 100644 tests/xilinx/counter.v create mode 100644 tests/xilinx/counter.ys create mode 100644 tests/xilinx/dffs.v create mode 100644 tests/xilinx/dffs.ys create mode 100644 tests/xilinx/div_mod.v create mode 100644 tests/xilinx/div_mod.ys create mode 100644 tests/xilinx/fsm.v create mode 100644 tests/xilinx/fsm.ys create mode 100644 tests/xilinx/logic.v create mode 100644 tests/xilinx/logic.ys create mode 100644 tests/xilinx/memory.v create mode 100644 tests/xilinx/memory.ys create mode 100644 tests/xilinx/mul.v create mode 100644 tests/xilinx/mul.ys create mode 100644 tests/xilinx/mux.v create mode 100644 tests/xilinx/mux.ys create mode 100644 tests/xilinx/shifter.v create mode 100644 tests/xilinx/shifter.ys create mode 100644 tests/xilinx/tribuf.v create mode 100644 tests/xilinx/tribuf.ys diff --git a/Makefile b/Makefile index ef02bc947..82af448da 100644 --- a/Makefile +++ b/Makefile @@ -715,6 +715,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/arch && bash run-test.sh +cd tests/ice40 && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh + +cd tests/xilinx && bash run-test.sh $(SEEDOPT) +cd tests/xilinx_ug901 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." diff --git a/tests/xilinx/add_sub.v b/tests/xilinx/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/xilinx/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys new file mode 100644 index 000000000..821341f20 --- /dev/null +++ b/tests/xilinx/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 14 t:LUT2 +select -assert-count 6 t:MUXCY +select -assert-count 8 t:XORCY +select -assert-none t:LUT2 t:MUXCY t:XORCY %% t:* %D + diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v new file mode 100644 index 000000000..93c8bf52c --- /dev/null +++ b/tests/xilinx/adffs.v @@ -0,0 +1,91 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffsr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre, posedge clr ) + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnsnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre, negedge clr ) + if ( !clr ) + q <= 1'b0; + else if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffsr u_dffsr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnsnr u_ndffnsnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys new file mode 100644 index 000000000..96d8e176f --- /dev/null +++ b/tests/xilinx/adffs.ys @@ -0,0 +1,14 @@ +read_verilog adffs.v +proc +async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 3 t:FDRE +select -assert-count 1 t:FDRE_1 +select -assert-count 4 t:LUT2 +select -assert-count 4 t:LUT3 +select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/xilinx/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys new file mode 100644 index 000000000..f85f03928 --- /dev/null +++ b/tests/xilinx/alu.ys @@ -0,0 +1,21 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + + +select -assert-count 1 t:BUFG +select -assert-count 32 t:LUT1 +select -assert-count 142 t:LUT2 +select -assert-count 55 t:LUT3 +select -assert-count 70 t:LUT4 +select -assert-count 46 t:LUT5 +select -assert-count 625 t:LUT6 +select -assert-count 62 t:MUXCY +select -assert-count 265 t:MUXF7 +select -assert-count 79 t:MUXF8 +select -assert-count 64 t:XORCY +select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/counter.v b/tests/xilinx/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/xilinx/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys new file mode 100644 index 000000000..b602b74d7 --- /dev/null +++ b/tests/xilinx/counter.ys @@ -0,0 +1,14 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDCE +select -assert-count 1 t:LUT1 +select -assert-count 7 t:MUXCY +select -assert-count 8 t:XORCY +select -assert-none t:BUFG t:FDCE t:LUT1 t:MUXCY t:XORCY %% t:* %D diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/xilinx/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys new file mode 100644 index 000000000..6a98994c0 --- /dev/null +++ b/tests/xilinx/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 2 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/xilinx/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys new file mode 100644 index 000000000..cc00b1a27 --- /dev/null +++ b/tests/xilinx/div_mod.ys @@ -0,0 +1,17 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 12 t:LUT1 +select -assert-count 21 t:LUT2 +select -assert-count 13 t:LUT4 +select -assert-count 6 t:LUT5 +select -assert-count 80 t:LUT6 +select -assert-count 65 t:MUXCY +select -assert-count 36 t:MUXF7 +select -assert-count 9 t:MUXF8 +select -assert-count 28 t:XORCY +select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v new file mode 100644 index 000000000..0605bd102 --- /dev/null +++ b/tests/xilinx/fsm.v @@ -0,0 +1,73 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + + endmodule + + module top ( +input clk, +input rst, +input a, +input b, +output g0, +output g1 +); + +fsm u_fsm ( .clock(clk), + .reset(rst), + .req_0(a), + .req_1(b), + .gnt_0(g0), + .gnt_1(g1)); + +endmodule diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys new file mode 100644 index 000000000..3b73891c2 --- /dev/null +++ b/tests/xilinx/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 5 t:FDRE +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT4 +select -assert-count 4 t:LUT6 +select -assert-none t:BUFG t:FDRE t:LUT3 t:LUT4 t:LUT6 %% t:* %D diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v index 83bad7f35..9dc43e4c2 100644 --- a/tests/xilinx/latches.v +++ b/tests/xilinx/latches.v @@ -1,19 +1,19 @@ module latchp - ( input d, en, output reg q ); + ( input d, clk, en, output reg q ); always @* if ( en ) q <= d; endmodule module latchn - ( input d, en, output reg q ); + ( input d, clk, en, output reg q ); always @* if ( !en ) q <= d; endmodule module latchsr - ( input d, en, clr, pre, output reg q ); + ( input d, clk, en, clr, pre, output reg q ); always @* if ( clr ) q <= 1'b0; diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index bd1dffd21..9ab562bcf 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -1,13 +1,20 @@ read_verilog latches.v +design -save read proc +async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +synth_xilinx +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) + +design -load read -design -load preopt synth_xilinx -cd top +#cd top + select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 -select -assert-count 3 t:LDCE -select -assert-none t:LUT1 t:LUT3 t:LDCE %% t:* %D +select -assert-count 3 t:$_DLATCH_P_ +#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D +#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D diff --git a/tests/xilinx/logic.v b/tests/xilinx/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/xilinx/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys new file mode 100644 index 000000000..e138ae6a3 --- /dev/null +++ b/tests/xilinx/logic.ys @@ -0,0 +1,10 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT1 +select -assert-count 6 t:LUT2 +select -assert-count 2 t:LUT4 +select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D diff --git a/tests/xilinx/memory.v b/tests/xilinx/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/xilinx/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/xilinx/memory.ys b/tests/xilinx/memory.ys new file mode 100644 index 000000000..5402513a2 --- /dev/null +++ b/tests/xilinx/memory.ys @@ -0,0 +1,17 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM64X1D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D diff --git a/tests/xilinx/mul.v b/tests/xilinx/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/xilinx/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys new file mode 100644 index 000000000..ec30c9c2c --- /dev/null +++ b/tests/xilinx/mul.ys @@ -0,0 +1,15 @@ +read_verilog mul.v +hierarchy -top top +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 12 t:LUT2 +select -assert-count 1 t:LUT3 +select -assert-count 6 t:LUT4 +select -assert-count 1 t:LUT5 +select -assert-count 33 t:LUT6 +select -assert-count 11 t:MUXCY +select -assert-count 1 t:MUXF7 +select -assert-count 12 t:XORCY +select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v new file mode 100644 index 000000000..0814b733e --- /dev/null +++ b/tests/xilinx/mux.v @@ -0,0 +1,100 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule + + +module top ( +input [3:0] S, +input [15:0] D, +output M2,M4,M8,M16 +); + +mux2 u_mux2 ( + .S (S[0]), + .A (D[0]), + .B (D[1]), + .Y (M2) + ); + + +mux4 u_mux4 ( + .S (S[1:0]), + .D (D[3:0]), + .Y (M4) + ); + +mux8 u_mux8 ( + .S (S[2:0]), + .D (D[7:0]), + .Y (M8) + ); + +mux16 u_mux16 ( + .S (S[3:0]), + .D (D[15:0]), + .Y (M16) + ); + +endmodule diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys new file mode 100644 index 000000000..6ecee58f5 --- /dev/null +++ b/tests/xilinx/mux.ys @@ -0,0 +1,10 @@ +read_verilog mux.v +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 2 t:LUT3 +select -assert-count 5 t:LUT6 +select -assert-none t:LUT3 t:LUT6 %% t:* %D diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh index ea56b70f0..2c72ca3a9 100755 --- a/tests/xilinx/run-test.sh +++ b/tests/xilinx/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x" + echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/xilinx/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/xilinx/shifter.ys b/tests/xilinx/shifter.ys new file mode 100644 index 000000000..84e16f41e --- /dev/null +++ b/tests/xilinx/shifter.ys @@ -0,0 +1,11 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v new file mode 100644 index 000000000..3fa6eb6c6 --- /dev/null +++ b/tests/xilinx/tribuf.v @@ -0,0 +1,29 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; +`ifndef BUG + + always @(en or i) + o <= (en)? i : 1'bZ; +`else + + always @(en or i) + o <= (en)? ~i : 1'bZ; +`endif +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys new file mode 100644 index 000000000..fc7ed37ef --- /dev/null +++ b/tests/xilinx/tribuf.ys @@ -0,0 +1,11 @@ +read_verilog tribuf.v +hierarchy -top top +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 6331fa5b022b9e16f9392d9604a545f86dc13385 Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 10 Sep 2019 08:11:56 +0300 Subject: Remove xilinx_ug901 tests (will be moved to yosys-tests) --- Makefile | 1 - tests/xilinx_ug901/asym_ram_sdp_read_wider.v | 74 ------------- tests/xilinx_ug901/asym_ram_sdp_read_wider.ys | 22 ---- tests/xilinx_ug901/asym_ram_sdp_write_wider.v | 75 ------------- tests/xilinx_ug901/asym_ram_sdp_write_wider.ys | 31 ------ tests/xilinx_ug901/asym_ram_tdp_read_first.v | 85 -------------- tests/xilinx_ug901/asym_ram_tdp_read_first.ys | 21 ---- tests/xilinx_ug901/asym_ram_tdp_write_first.v | 92 ---------------- tests/xilinx_ug901/asym_ram_tdp_write_first.ys | 29 ----- tests/xilinx_ug901/black_box_1.v | 19 ---- tests/xilinx_ug901/black_box_1.ys | 15 --- tests/xilinx_ug901/bytewrite_ram_1b.v | 42 ------- tests/xilinx_ug901/bytewrite_ram_1b.ys | 22 ---- tests/xilinx_ug901/bytewrite_tdp_ram_nc.v | 78 ------------- tests/xilinx_ug901/bytewrite_tdp_ram_nc.ys | 22 ---- tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.v | 71 ------------ tests/xilinx_ug901/bytewrite_tdp_ram_readfirst2.ys | 21 ---- tests/xilinx_ug901/bytewrite_tdp_ram_rf.v | 61 ----------- tests/xilinx_ug901/bytewrite_tdp_ram_rf.ys | 21 ---- tests/xilinx_ug901/bytewrite_tdp_ram_wf.v | 68 ------------ tests/xilinx_ug901/bytewrite_tdp_ram_wf.ys | 23 ---- tests/xilinx_ug901/cmacc.v | 122 --------------------- tests/xilinx_ug901/cmacc.ys | 25 ----- tests/xilinx_ug901/cmult.v | 71 ------------ tests/xilinx_ug901/cmult.ys | 31 ------ tests/xilinx_ug901/dynamic_shift_registers_1.v | 21 ---- tests/xilinx_ug901/dynamic_shift_registers_1.ys | 15 --- tests/xilinx_ug901/dynpreaddmultadd.v | 47 -------- tests/xilinx_ug901/dynpreaddmultadd.ys | 31 ------ tests/xilinx_ug901/fsm_1.v | 42 ------- tests/xilinx_ug901/fsm_1.ys | 16 --- tests/xilinx_ug901/latches.v | 17 --- tests/xilinx_ug901/latches.ys | 10 -- tests/xilinx_ug901/macc.v | 47 -------- tests/xilinx_ug901/macc.ys | 23 ---- tests/xilinx_ug901/mult_unsigned.v | 33 ------ tests/xilinx_ug901/mult_unsigned.ys | 29 ----- tests/xilinx_ug901/presubmult.v | 43 -------- tests/xilinx_ug901/presubmult.ys | 23 ---- tests/xilinx_ug901/ram_simple_dual_one_clock.v | 25 ----- tests/xilinx_ug901/ram_simple_dual_one_clock.ys | 20 ---- tests/xilinx_ug901/ram_simple_dual_two_clocks.v | 30 ----- tests/xilinx_ug901/ram_simple_dual_two_clocks.ys | 20 ---- tests/xilinx_ug901/rams_dist.v | 24 ---- tests/xilinx_ug901/rams_dist.ys | 21 ---- tests/xilinx_ug901/rams_init_file.data | 64 ----------- tests/xilinx_ug901/rams_init_file.v | 24 ---- tests/xilinx_ug901/rams_init_file.ys | 22 ---- tests/xilinx_ug901/rams_pipeline.v | 42 ------- tests/xilinx_ug901/rams_pipeline.ys | 22 ---- tests/xilinx_ug901/rams_sp_nc.v | 26 ----- tests/xilinx_ug901/rams_sp_nc.ys | 22 ---- tests/xilinx_ug901/rams_sp_rf.v | 26 ----- tests/xilinx_ug901/rams_sp_rf.ys | 22 ---- tests/xilinx_ug901/rams_sp_rf_rst.v | 29 ----- tests/xilinx_ug901/rams_sp_rf_rst.ys | 28 ----- tests/xilinx_ug901/rams_sp_rom.v | 46 -------- tests/xilinx_ug901/rams_sp_rom.ys | 22 ---- tests/xilinx_ug901/rams_sp_rom_1.v | 53 --------- tests/xilinx_ug901/rams_sp_rom_1.ys | 22 ---- tests/xilinx_ug901/rams_sp_wf.v | 26 ----- tests/xilinx_ug901/rams_sp_wf.ys | 26 ----- tests/xilinx_ug901/rams_tdp_rf_rf.v | 33 ------ tests/xilinx_ug901/rams_tdp_rf_rf.ys | 21 ---- tests/xilinx_ug901/registers_1.v | 25 ----- tests/xilinx_ug901/registers_1.ys | 12 -- tests/xilinx_ug901/run-test.sh | 20 ---- tests/xilinx_ug901/sfir_shifter.v | 19 ---- tests/xilinx_ug901/sfir_shifter.ys | 16 --- tests/xilinx_ug901/shift_registers_0.v | 22 ---- tests/xilinx_ug901/shift_registers_0.ys | 14 --- tests/xilinx_ug901/shift_registers_1.v | 24 ---- tests/xilinx_ug901/shift_registers_1.ys | 14 --- tests/xilinx_ug901/squarediffmacc.v | 52 --------- tests/xilinx_ug901/squarediffmacc.ys | 23 ---- tests/xilinx_ug901/squarediffmult.v | 42 ------- tests/xilinx_ug901/squarediffmult.ys | 30 ----- tests/xilinx_ug901/top_mux.v | 18 --- tests/xilinx_ug901/top_mux.ys | 13 --- tests/xilinx_ug901/tristates_1.v | 17 --- tests/xilinx_ug901/tristates_1.ys | 13 --- tests/xilinx_ug901/tristates_2.v | 10 -- tests/xilinx_ug901/tristates_2.ys | 13 --- .../xilinx_ultraram_single_port_no_change.v | 78 ------------- .../xilinx_ultraram_single_port_no_change.ys | 25 ----- .../xilinx_ultraram_single_port_read_first.v | 78 ------------- .../xilinx_ultraram_single_port_read_first.ys | 24 ---- .../xilinx_ultraram_single_port_write_first.v | 82 -------------- .../xilinx_ultraram_single_port_write_first.ys | 24 ---- 89 files changed, 2963 deletions(-) delete mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.v delete mode 100644 tests/xilinx_ug901/asym_ram_sdp_read_wider.ys delete mode 100644 tests/xilinx_ug901/asym_ram_sdp_write_wider.v delete mode 100644 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test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/ice40 && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh +cd tests/xilinx && bash run-test.sh $(SEEDOPT) - +cd tests/xilinx_ug901 && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v b/tests/xilinx_ug901/asym_ram_sdp_read_wider.v deleted file mode 100644 index 0716dffdc..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_read_wider.v +++ /dev/null @@ -1,74 +0,0 @@ -// Asymmetric port RAM -// Read Wider than Write. Read Statement in loop -//asym_ram_sdp_read_wider.v - -module asym_ram_sdp_read_wider (clkA, clkB, enaA, weA, enaB, addrA, addrB, diA, doB); -parameter WIDTHA = 4; -parameter SIZEA = 1024; -parameter ADDRWIDTHA = 10; - -parameter WIDTHB = 16; -parameter SIZEB = 256; -parameter ADDRWIDTHB = 8; -input clkA; -input clkB; -input weA; -input enaA, enaB; -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -output [WIDTHB-1:0] doB; -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHB-1:0] readB; - -always @(posedge clkA) -begin - if (enaA) begin - if (weA) - RAM[addrA] <= diA; - end -end - - -always @(posedge clkB) -begin : ramread - integer i; - reg [log2RATIO-1:0] lsbaddr; - if (enaB) begin - for (i = 0; i < RATIO; i = i+1) begin - lsbaddr = i; - readB[(i+1)*minWIDTH-1 -: minWIDTH] <= RAM[{addrB, lsbaddr}]; - end - end -end -assign doB = readB; - -endmodule - diff --git a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys deleted file mode 100644 index c63157cdf..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_read_wider.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog asym_ram_sdp_read_wider.v -hierarchy -top asym_ram_sdp_read_wider -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_sdp_read_wider -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 1 t:LUT2 -select -assert-count 4 t:RAMB18E1 - -select -assert-none t:BUFG t:LUT2 t:RAMB18E1 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v b/tests/xilinx_ug901/asym_ram_sdp_write_wider.v deleted file mode 100644 index 22d12d2ce..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_write_wider.v +++ /dev/null @@ -1,75 +0,0 @@ -// Asymmetric port RAM -// Write wider than Read. Write Statement in a loop. -// asym_ram_sdp_write_wider.v - -module asym_ram_sdp_write_wider (clkA, clkB, weA, enaA, enaB, addrA, addrB, diA, doB); -parameter WIDTHB = 4; -//Default parameters were changed because of slow test -//parameter SIZEB = 1024; -//parameter ADDRWIDTHB = 10; -parameter SIZEB = 256; -parameter ADDRWIDTHB = 8; - -//parameter WIDTHA = 16; -parameter WIDTHA = 8; -parameter SIZEA = 256; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA; -input enaA, enaB; -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -output [WIDTHB-1:0] doB; -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) begin - if (enaB) begin - readB <= RAM[addrB]; - end -end -assign doB = readB; - -always @(posedge clkA) -begin : ramwrite - integer i; - reg [log2RATIO-1:0] lsbaddr; - for (i=0; i< RATIO; i= i+ 1) begin : write1 - lsbaddr = i; - if (enaA) begin - if (weA) - RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; - end - end -end - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys b/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys deleted file mode 100644 index 229d98df6..000000000 --- a/tests/xilinx_ug901/asym_ram_sdp_write_wider.ys +++ /dev/null @@ -1,31 +0,0 @@ -read_verilog asym_ram_sdp_write_wider.v -hierarchy -top asym_ram_sdp_write_wider -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_sdp_write_wider -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 1028 t:FDRE -select -assert-count 170 t:LUT2 -select -assert-count 6 t:LUT3 -select -assert-count 518 t:LUT4 -select -assert-count 10 t:LUT5 -select -assert-count 484 t:LUT6 -select -assert-count 157 t:MUXF7 -select -assert-count 3 t:MUXF8 - -#RRAM128X1D will be synthesized in case when the parameter WIDTHA=4 -#select -assert-count 8 t:RAM128X1D - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.v b/tests/xilinx_ug901/asym_ram_tdp_read_first.v deleted file mode 100644 index 2b807a382..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_read_first.v +++ /dev/null @@ -1,85 +0,0 @@ -// Asymetric RAM - TDP -// READ_FIRST MODE. -// asym_ram_tdp_read_first.v - - -module asym_ram_tdp_read_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); -parameter WIDTHB = 4; -parameter SIZEB = 1024; -parameter ADDRWIDTHB = 10; -parameter WIDTHA = 16; -parameter SIZEA = 256; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA, weB; -input enaA, enaB; - -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -input [WIDTHB-1:0] diB; - -output [WIDTHA-1:0] doA; -output [WIDTHB-1:0] doB; - -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHA-1:0] readA; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) -begin - if (enaB) begin - readB <= RAM[addrB] ; - if (weB) - RAM[addrB] <= diB; - end -end - - -always @(posedge clkA) -begin : portA - integer i; - reg [log2RATIO-1:0] lsbaddr ; - for (i=0; i< RATIO; i= i+ 1) begin - lsbaddr = i; - if (enaA) begin - readA[(i+1)*minWIDTH -1 -: minWIDTH] <= RAM[{addrA, lsbaddr}]; - - if (weA) - RAM[{addrA, lsbaddr}] <= diA[(i+1)*minWIDTH-1 -: minWIDTH]; - end - end -end - -assign doA = readA; -assign doB = readB; - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys b/tests/xilinx_ug901/asym_ram_tdp_read_first.ys deleted file mode 100644 index 5f96b800c..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_read_first.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog asym_ram_tdp_read_first.v -hierarchy -top asym_ram_tdp_read_first -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_tdp_read_first -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 1 t:$mem -select -assert-count 2 t:LUT2 - -select -assert-none t:$mem t:LUT2 %% t:* %D diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.v b/tests/xilinx_ug901/asym_ram_tdp_write_first.v deleted file mode 100644 index 90187ea26..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_write_first.v +++ /dev/null @@ -1,92 +0,0 @@ -// Asymmetric port RAM - TDP -// WRITE_FIRST MODE. -// asym_ram_tdp_write_first.v - - -module asym_ram_tdp_write_first (clkA, clkB, enaA, weA, enaB, weB, addrA, addrB, diA, doA, diB, doB); -parameter WIDTHB = 4; -//Default parameters were changed because of slow test -//parameter SIZEB = 1024; -//parameter ADDRWIDTHB = 10; -parameter SIZEB = 32; -parameter ADDRWIDTHB = 8; - -//parameter WIDTHA = 16; -parameter WIDTHA = 4; -//parameter SIZEA = 256; -parameter SIZEA = 32; -parameter ADDRWIDTHA = 8; -input clkA; -input clkB; -input weA, weB; -input enaA, enaB; - -input [ADDRWIDTHA-1:0] addrA; -input [ADDRWIDTHB-1:0] addrB; -input [WIDTHA-1:0] diA; -input [WIDTHB-1:0] diB; - -output [WIDTHA-1:0] doA; -output [WIDTHB-1:0] doB; - -`define max(a,b) {(a) > (b) ? (a) : (b)} -`define min(a,b) {(a) < (b) ? (a) : (b)} - -function integer log2; -input integer value; -reg [31:0] shifted; -integer res; -begin - if (value < 2) - log2 = value; - else - begin - shifted = value-1; - for (res=0; shifted>0; res=res+1) - shifted = shifted>>1; - log2 = res; - end -end -endfunction - -localparam maxSIZE = `max(SIZEA, SIZEB); -localparam maxWIDTH = `max(WIDTHA, WIDTHB); -localparam minWIDTH = `min(WIDTHA, WIDTHB); - -localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = log2(RATIO); - -reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; -reg [WIDTHA-1:0] readA; -reg [WIDTHB-1:0] readB; - -always @(posedge clkB) -begin - if (enaB) begin - if (weB) - RAM[addrB] = diB; - readB = RAM[addrB] ; - end -end - - -always @(posedge clkA) -begin : portA - integer i; - reg [log2RATIO-1:0] lsbaddr ; - for (i=0; i< RATIO; i= i+ 1) begin - lsbaddr = i; - if (enaA) begin - - if (weA) - RAM[{addrA, lsbaddr}] = diA[(i+1)*minWIDTH-1 -: minWIDTH]; - - readA[(i+1)*minWIDTH -1 -: minWIDTH] = RAM[{addrA, lsbaddr}]; - end - end -end - -assign doA = readA; -assign doB = readB; - -endmodule diff --git a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys b/tests/xilinx_ug901/asym_ram_tdp_write_first.ys deleted file mode 100644 index bbe3cc849..000000000 --- a/tests/xilinx_ug901/asym_ram_tdp_write_first.ys +++ /dev/null @@ -1,29 +0,0 @@ -read_verilog asym_ram_tdp_write_first.v -hierarchy -top asym_ram_tdp_write_first -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd asym_ram_tdp_write_first -stat -#Vivado synthesizes 1 RAMB18E1. -select -assert-count 2 t:BUFG -select -assert-count 200 t:FDRE -select -assert-count 10 t:LUT2 -select -assert-count 44 t:LUT3 -select -assert-count 81 t:LUT4 -select -assert-count 104 t:LUT5 -select -assert-count 560 t:LUT6 -select -assert-count 261 t:MUXF7 -select -assert-count 127 t:MUXF8 - - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXF7 t:MUXF8 %% t:* %D diff --git a/tests/xilinx_ug901/black_box_1.v b/tests/xilinx_ug901/black_box_1.v deleted file mode 100644 index 40caa1b10..000000000 --- a/tests/xilinx_ug901/black_box_1.v +++ /dev/null @@ -1,19 +0,0 @@ -// Black Box -// black_box_1.v -// -(* black_box *) module black_box1 (in1, in2, dout); -input in1, in2; -output dout; -endmodule - -module black_box_1 (DI_1, DI_2, DOUT); -input DI_1, DI_2; -output DOUT; - -black_box1 U1 ( - .in1(DI_1), - .in2(DI_2), - .dout(DOUT) - ); - -endmodule diff --git a/tests/xilinx_ug901/black_box_1.ys b/tests/xilinx_ug901/black_box_1.ys deleted file mode 100644 index acf0b5761..000000000 --- a/tests/xilinx_ug901/black_box_1.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog black_box_1.v -hierarchy -top black_box_1 -proc -tribuf -flatten -synth -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd black_box_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 black box. -#stat -#select -assert-count 0 t:LUT1 -#select -assert-count 1 t:$_TBUF_ -#select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.v b/tests/xilinx_ug901/bytewrite_ram_1b.v deleted file mode 100644 index 46d86c297..000000000 --- a/tests/xilinx_ug901/bytewrite_ram_1b.v +++ /dev/null @@ -1,42 +0,0 @@ -// Single-Port BRAM with Byte-wide Write Enable -// Read-First mode -// Single-process description -// Compact description of the write with a generate-for -// statement -// Column width and number of columns easily configurable -// -// bytewrite_ram_1b.v -// - -module bytewrite_ram_1b (clk, we, addr, di, do); - -parameter SIZE = 1024; -parameter ADDR_WIDTH = 10; -parameter COL_WIDTH = 8; -parameter NB_COL = 4; - -input clk; -input [NB_COL-1:0] we; -input [ADDR_WIDTH-1:0] addr; -input [NB_COL*COL_WIDTH-1:0] di; -output reg [NB_COL*COL_WIDTH-1:0] do; - -reg [NB_COL*COL_WIDTH-1:0] RAM [SIZE-1:0]; - -always @(posedge clk) -begin - do <= RAM[addr]; -end - -generate genvar i; -for (i = 0; i < NB_COL; i = i+1) -begin -always @(posedge clk) -begin - if (we[i]) - RAM[addr][(i+1)*COL_WIDTH-1:i*COL_WIDTH] <= di[(i+1)*COL_WIDTH-1:i*COL_WIDTH]; - end -end -endgenerate - -endmodule diff --git a/tests/xilinx_ug901/bytewrite_ram_1b.ys b/tests/xilinx_ug901/bytewrite_ram_1b.ys deleted file mode 100644 index 4f0967801..000000000 --- a/tests/xilinx_ug901/bytewrite_ram_1b.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog bytewrite_ram_1b.v -hierarchy -top bytewrite_ram_1b -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd bytewrite_ram_1b -stat -#Vivado synthesizes 1 RAMB36E1. -select -assert-count 1 t:BUFG -select -assert-count 32 t:LUT2 -select -assert-count 8 t:RAMB36E1 - -select -assert-none t:BUFG t:LUT2 t:RAMB36E1 %% t:* %D diff --git a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v b/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v deleted file mode 100644 index 1093b0838..000000000 --- a/tests/xilinx_ug901/bytewrite_tdp_ram_nc.v +++ /dev/null @@ -1,78 +0,0 @@ -// -// True-Dual-Port BRAM with Byte-wide Write Enable -// No-Change mode -// -// bytewrite_tdp_ram_nc.v -// -// ByteWide Write Enable, - NO_CHANGE mode template - Vivado recomended -module bytewrite_tdp_ram_nc - #( - //--------------------------------------------------------------- - parameter NUM_COL = 4, - parameter COL_WIDTH = 8, - parameter ADDR_WIDTH = 10, // Addr Width in bits : 2**ADDR_WIDTH = RAM Depth - parameter DATA_WIDTH = NUM_COL*COL_WIDTH // Data Width in bits - //--------------------------------------------------------------- - ) ( - input clkA, - input enaA, - input [NUM_COL-1:0] weA, - input [ADDR_WIDTH-1:0] addrA, - input [DATA_WIDTH-1:0] dinA, - output reg [DATA_WIDTH-1:0] doutA, - - input clkB, - input enaB, - input [NUM_COL-1:0] weB, - input [ADDR_WIDTH-1:0] addrB, - input [DATA_WIDTH-1:0] dinB, - output reg [DATA_WIDTH-1:0] doutB - ); - - - // Core Memory - reg [DATA_WIDTH-1:0] ram_block [(2**ADDR_WIDTH)-1:0]; - - // Port-A Operation - generate - genvar i; - for(i=0;i run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx_ug901/sfir_shifter.v b/tests/xilinx_ug901/sfir_shifter.v deleted file mode 100644 index a8b144bcd..000000000 --- a/tests/xilinx_ug901/sfir_shifter.v +++ /dev/null @@ -1,19 +0,0 @@ -//sfir_shifter.v -(* dont_touch = "yes" *) -module sfir_shifter #(parameter dsize = 16, nbtap = 4) - (input clk,input [dsize-1:0] datain, output [dsize-1:0] dataout); - - (* srl_style = "srl_register" *) reg [dsize-1:0] tmp [0:2*nbtap-1]; - integer i; - - always @(posedge clk) - begin - tmp[0] <= datain; - for (i=0; i<=2*nbtap-2; i=i+1) - tmp[i+1] <= tmp[i]; - end - - assign dataout = tmp[2*nbtap-1]; - -endmodule -// sfir_shifter diff --git a/tests/xilinx_ug901/sfir_shifter.ys b/tests/xilinx_ug901/sfir_shifter.ys deleted file mode 100644 index b9fbeb8cb..000000000 --- a/tests/xilinx_ug901/sfir_shifter.ys +++ /dev/null @@ -1,16 +0,0 @@ -read_verilog sfir_shifter.v -hierarchy -top sfir_shifter -proc -flatten -#ERROR: Found 32 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd sfir_shifter -#Vivado synthesizes 32 FDRE, 16 SRL16E. -stat -select -assert-count 1 t:BUFG -select -assert-count 16 t:SRL16E - -select -assert-none t:BUFG t:SRL16E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_0.v b/tests/xilinx_ug901/shift_registers_0.v deleted file mode 100644 index 77a3ec893..000000000 --- a/tests/xilinx_ug901/shift_registers_0.v +++ /dev/null @@ -1,22 +0,0 @@ -// 8-bit Shift Register -// Rising edge clock -// Active high clock enable -// Concatenation-based template -// File: shift_registers_0.v - -module shift_registers_0 (clk, clken, SI, SO); -parameter WIDTH = 32; -input clk, clken, SI; -output SO; - -reg [WIDTH-1:0] shreg; - -always @(posedge clk) - begin - if (clken) - shreg = {shreg[WIDTH-2:0], SI}; - end - -assign SO = shreg[WIDTH-1]; - -endmodule diff --git a/tests/xilinx_ug901/shift_registers_0.ys b/tests/xilinx_ug901/shift_registers_0.ys deleted file mode 100644 index 89da1d7cc..000000000 --- a/tests/xilinx_ug901/shift_registers_0.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog shift_registers_0.v -hierarchy -top shift_registers_0 -proc -flatten -#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check - -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd shift_registers_0 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. -select -assert-count 1 t:BUFG -select -assert-count 1 t:SRLC32E -select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/shift_registers_1.v b/tests/xilinx_ug901/shift_registers_1.v deleted file mode 100644 index d50820e7b..000000000 --- a/tests/xilinx_ug901/shift_registers_1.v +++ /dev/null @@ -1,24 +0,0 @@ -// 32-bit Shift Register -// Rising edge clock -// Active high clock enable -// For-loop based template -// File: shift_registers_1.v - -module shift_registers_1 (clk, clken, SI, SO); -parameter WIDTH = 32; -input clk, clken, SI; -output SO; -reg [WIDTH-1:0] shreg; - -integer i; -always @(posedge clk) -begin - if (clken) - begin - for (i = 0; i < WIDTH-1; i = i+1) - shreg[i+1] <= shreg[i]; - shreg[0] <= SI; - end -end -assign SO = shreg[WIDTH-1]; -endmodule diff --git a/tests/xilinx_ug901/shift_registers_1.ys b/tests/xilinx_ug901/shift_registers_1.ys deleted file mode 100644 index b53b6cb25..000000000 --- a/tests/xilinx_ug901/shift_registers_1.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog shift_registers_1.v -hierarchy -top shift_registers_1 -proc -flatten -#ERROR: Found 2 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check - -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd shift_registers_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 1 BUFG, 2 FDRE, 3 SRLC32E. -select -assert-count 1 t:BUFG -select -assert-count 1 t:SRLC32E -select -assert-none t:BUFG t:SRLC32E %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmacc.v b/tests/xilinx_ug901/squarediffmacc.v deleted file mode 100644 index 6535b24c4..000000000 --- a/tests/xilinx_ug901/squarediffmacc.v +++ /dev/null @@ -1,52 +0,0 @@ -// This module performs subtraction of two inputs, squaring on the diff -// and then accumulation -// This can be implemented in 1 DSP Block (Ultrascale architecture) -// File : squarediffmacc.v -module squarediffmacc # ( - //Default parameters were changed because of slow test - //parameter SIZEIN = 16, - //SIZEOUT = 40 - parameter SIZEIN = 8, - SIZEOUT = 20 - ) - ( - input clk, - input ce, - input sload, - input signed [SIZEIN-1:0] a, - input signed [SIZEIN-1:0] b, - output signed [SIZEOUT+1:0] accum_out - ); - -// Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; -reg signed [SIZEIN:0] diff_reg; -reg sload_reg; -reg signed [2*SIZEIN+1:0] m_reg; -reg signed [SIZEOUT-1:0] adder_out, old_result; - - always @(sload_reg or adder_out) - if (sload_reg) - old_result <= 0; - else - // 'sload' is now and opens the accumulation loop. - // The accumulator takes the next multiplier output - // in the same cycle. - old_result <= adder_out; - - always @(posedge clk) - if (ce) - begin - a_reg <= a; - b_reg <= b; - diff_reg <= a_reg - b_reg; - m_reg <= diff_reg * diff_reg; - sload_reg <= sload; - // Store accumulation result into a register - adder_out <= old_result + m_reg; - end - - // Output accumulation result - assign accum_out = adder_out; - -endmodule // squarediffmacc diff --git a/tests/xilinx_ug901/squarediffmacc.ys b/tests/xilinx_ug901/squarediffmacc.ys deleted file mode 100644 index 92474bea3..000000000 --- a/tests/xilinx_ug901/squarediffmacc.ys +++ /dev/null @@ -1,23 +0,0 @@ -read_verilog squarediffmacc.v -hierarchy -top squarediffmacc -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd squarediffmacc -#Vivado synthesizes 1 DSP48E1, 33 FDRE, 16 LUT. -stat -select -assert-count 1 t:BUFG -select -assert-count 64 t:FDRE -select -assert-count 78 t:LUT2 -select -assert-count 7 t:LUT3 -select -assert-count 11 t:LUT4 -select -assert-count 8 t:LUT5 -select -assert-count 125 t:LUT6 -select -assert-count 44 t:MUXCY -select -assert-count 50 t:MUXF7 -select -assert-count 17 t:MUXF8 -select -assert-count 47 t:XORCY - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/squarediffmult.v b/tests/xilinx_ug901/squarediffmult.v deleted file mode 100644 index 0f41b67bc..000000000 --- a/tests/xilinx_ug901/squarediffmult.v +++ /dev/null @@ -1,42 +0,0 @@ -// Squarer support for DSP block (DSP48E2) with -// pre-adder configured -// as subtractor -// File: squarediffmult.v - -module squarediffmult # (parameter SIZEIN = 16) - ( - input clk, ce, rst, - input signed [SIZEIN-1:0] a, b, - output signed [2*SIZEIN+1:0] square_out - ); - - // Declare registers for intermediate values -reg signed [SIZEIN-1:0] a_reg, b_reg; -reg signed [SIZEIN:0] diff_reg; -reg signed [2*SIZEIN+1:0] m_reg, p_reg; - -always @(posedge clk) -begin - if (rst) - begin - a_reg <= 0; - b_reg <= 0; - diff_reg <= 0; - m_reg <= 0; - p_reg <= 0; - end - else - if (ce) - begin - a_reg <= a; - b_reg <= b; - diff_reg <= a_reg - b_reg; - m_reg <= diff_reg * diff_reg; - p_reg <= m_reg; - end -end - -// Output result -assign square_out = p_reg; - -endmodule // squarediffmult diff --git a/tests/xilinx_ug901/squarediffmult.ys b/tests/xilinx_ug901/squarediffmult.ys deleted file mode 100644 index 3468e5bb4..000000000 --- a/tests/xilinx_ug901/squarediffmult.ys +++ /dev/null @@ -1,30 +0,0 @@ -read_verilog squarediffmult.v -hierarchy -top squarediffmult -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -# TODO -#equiv_opt -run prove: -assert null -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter - -design -load postopt -cd squarediffmult -stat -#Vivado synthesizes 16 FDRE, 1 DSP48E1. -select -assert-count 1 t:BUFG -select -assert-count 117 t:FDRE -select -assert-count 223 t:LUT2 -select -assert-count 50 t:LUT3 -select -assert-count 38 t:LUT4 -select -assert-count 56 t:LUT5 -select -assert-count 372 t:LUT6 -select -assert-count 49 t:MUXCY -select -assert-count 99 t:MUXF7 -select -assert-count 26 t:MUXF8 -select -assert-count 51 t:XORCY - -select -assert-none t:BUFG t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx_ug901/top_mux.v b/tests/xilinx_ug901/top_mux.v deleted file mode 100644 index c23c7491c..000000000 --- a/tests/xilinx_ug901/top_mux.v +++ /dev/null @@ -1,18 +0,0 @@ -// Multiplexer using case statement -module mux4 (sel, a, b, c, d, outmux); -input [1:0] sel; -input [1:0] a, b, c, d; -output [1:0] outmux; -reg [1:0] outmux; - -always @ * - begin - case(sel) - 2'b00 : outmux = a; - 2'b01 : outmux = b; - 2'b10 : outmux = c; - 2'b11 : outmux = d; - endcase - end -endmodule - diff --git a/tests/xilinx_ug901/top_mux.ys b/tests/xilinx_ug901/top_mux.ys deleted file mode 100644 index 0245f3bbc..000000000 --- a/tests/xilinx_ug901/top_mux.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog top_mux.v -hierarchy -top mux4 -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -cd mux4 -#Vivado synthesizes 2 LUT. -stat -select -assert-count 2 t:LUT6 - -select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx_ug901/tristates_1.v b/tests/xilinx_ug901/tristates_1.v deleted file mode 100644 index 0038a9989..000000000 --- a/tests/xilinx_ug901/tristates_1.v +++ /dev/null @@ -1,17 +0,0 @@ -// Tristate Description Using Combinatorial Always Block -// File: tristates_1.v -// -module tristates_1 (T, I, O); -input T, I; -output O; -reg O; - -always @(T or I) -begin - if (~T) - O = I; - else - O = 1'bZ; -end - -endmodule diff --git a/tests/xilinx_ug901/tristates_1.ys b/tests/xilinx_ug901/tristates_1.ys deleted file mode 100644 index 7c13dc227..000000000 --- a/tests/xilinx_ug901/tristates_1.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog tristates_1.v -hierarchy -top tristates_1 -proc -tribuf -flatten -synth -equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristates_1 # Constrain all select calls below inside the top module -#Vivado synthesizes 3 IBUF, 1 OBUFT. -select -assert-count 1 t:LUT1 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/tristates_2.v b/tests/xilinx_ug901/tristates_2.v deleted file mode 100644 index 0c70a1257..000000000 --- a/tests/xilinx_ug901/tristates_2.v +++ /dev/null @@ -1,10 +0,0 @@ -// Tristate Description Using Concurrent Assignment -// File: tristates_2.v -// -module tristates_2 (T, I, O); -input T, I; -output O; - -assign O = (~T) ? I: 1'bZ; - -endmodule diff --git a/tests/xilinx_ug901/tristates_2.ys b/tests/xilinx_ug901/tristates_2.ys deleted file mode 100644 index ba2e1d855..000000000 --- a/tests/xilinx_ug901/tristates_2.ys +++ /dev/null @@ -1,13 +0,0 @@ -read_verilog tristates_2.v -hierarchy -top tristates_2 -proc -tribuf -flatten -synth -equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristates_2 # Constrain all select calls below inside the top module -#Vivado synthesizes 3 IBUF, 1 OBUFT. -select -assert-count 1 t:LUT1 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:LUT1 t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v b/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v deleted file mode 100644 index f5e843dc9..000000000 --- a/tests/xilinx_ug901/xilinx_ultraram_single_port_no_change.v +++ /dev/null @@ -1,78 +0,0 @@ -// Xilinx UltraRAM Single Port No Change Mode. This code implements -// a parameterizable UltraRAM block in No Change mode. The behavior of this RAM is -// when data is written, the output of RAM is unchanged. Only when write is -// inactive data corresponding to the address is presented on the output port. -// -module xilinx_ultraram_single_port_no_change #( -//Default parameters were changed because of slow test - //parameter AWIDTH = 12, // Address Width - //parameter DWIDTH = 72, // Data Width - //parameter NBPIPE = 3 // Number of pipeline Registers - parameter AWIDTH = 8, // Address Width - parameter DWIDTH = 8, // Data Width - parameter NBPIPE = 3 // Number of pipeline Registers - ) ( - input clk, // Clock - input rst, // Reset - input we, // Write Enable - input regce, // Output Register Enable - input mem_en, // Memory Enable - input [DWIDTH-1:0] din, // Data Input - input [AWIDTH-1:0] addr, // Address Input - output reg [DWIDTH-1:0] dout // Data Output - ); - -(* ram_style = "ultra" *) -reg [DWIDTH-1:0] mem[(1< Date: Tue, 10 Sep 2019 08:36:59 +0300 Subject: Fix latches.ys test --- tests/xilinx/latches.ys | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 9ab562bcf..042ee2d4f 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -11,10 +11,9 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p design -load read synth_xilinx -#cd top - +flatten +cd top select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 select -assert-count 3 t:$_DLATCH_P_ -#ERROR: Assertion failed: selection is not empty: t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D -#select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D +select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D -- cgit v1.2.3 From 7bc8f0c2e234641b8af7f8dd991ea65bd9a6ef1a Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Wed, 11 Sep 2019 17:01:19 +0300 Subject: Add comment with expected behavior for latches,tribuf tests;Update adffs test --- tests/xilinx/adffs.v | 18 +++++++----------- tests/xilinx/adffs.ys | 5 ++--- tests/xilinx/latches.ys | 1 + tests/xilinx/tribuf.ys | 1 + 4 files changed, 11 insertions(+), 14 deletions(-) diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v index 93c8bf52c..05e68caf7 100644 --- a/tests/xilinx/adffs.v +++ b/tests/xilinx/adffs.v @@ -22,30 +22,26 @@ module adffn q <= d; endmodule -module dffsr +module dffs ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, posedge pre, posedge clr ) - if ( clr ) - q <= 1'b0; - else if ( pre ) + always @( posedge clk ) + if ( pre ) q <= 1'b1; else q <= d; endmodule -module ndffnsnr +module ndffnr ( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk, negedge pre, negedge clr ) + always @( negedge clk ) if ( !clr ) q <= 1'b0; - else if ( !pre ) - q <= 1'b1; else q <= d; endmodule @@ -58,7 +54,7 @@ input a, output b,b1,b2,b3 ); -dffsr u_dffsr ( +dffs u_dffs ( .clk (clk ), .clr (clr), .pre (pre), @@ -66,7 +62,7 @@ dffsr u_dffsr ( .q (b ) ); -ndffnsnr u_ndffnsnr ( +ndffnr u_ndffnr ( .clk (clk ), .clr (clr), .pre (pre), diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 96d8e176f..38c82a36f 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -9,6 +9,5 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 3 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 4 t:LUT2 -select -assert-count 4 t:LUT3 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 t:LUT3 %% t:* %D +select -assert-count 5 t:LUT2 +select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 042ee2d4f..1f643cb4e 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -15,5 +15,6 @@ flatten cd top select -assert-count 1 t:LUT1 select -assert-count 2 t:LUT3 +#Xilinx Vivado synthesizes LDCE cell for this case. Need support it. select -assert-count 3 t:$_DLATCH_P_ select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index fc7ed37ef..76b00647d 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,5 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From df7fe40529f7e0a26626ac1b0ed12acf66bb40d3 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Wed, 11 Sep 2019 20:34:22 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index cc00b1a27..52e536a7f 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -6,7 +6,7 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 -select -assert-count 21 t:LUT2 +select -assert-count 23 t:LUT2 select -assert-count 13 t:LUT4 select -assert-count 6 t:LUT5 select -assert-count 80 t:LUT6 -- cgit v1.2.3 From 205f52ffe53778daf9fc1bcdd9bee4b53a6e2a60 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Wed, 11 Sep 2019 21:28:40 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 52e536a7f..e1c4d6912 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -7,7 +7,7 @@ cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 -select -assert-count 13 t:LUT4 +select -assert-count 12 t:LUT4 select -assert-count 6 t:LUT5 select -assert-count 80 t:LUT6 select -assert-count 65 t:MUXCY -- cgit v1.2.3 From c340d54657688542c5f3a8dabe3f68563dcc8d1c Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 06:24:18 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index e1c4d6912..7db336d00 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -8,7 +8,7 @@ cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 select -assert-count 12 t:LUT4 -select -assert-count 6 t:LUT5 +select -assert-count 9 t:LUT5 select -assert-count 80 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 36 t:MUXF7 -- cgit v1.2.3 From df6d0b95da89a4a7bd558dab0c112f5c7a989561 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 07:13:49 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 7db336d00..c5855f1dd 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -9,7 +9,7 @@ select -assert-count 12 t:LUT1 select -assert-count 23 t:LUT2 select -assert-count 12 t:LUT4 select -assert-count 9 t:LUT5 -select -assert-count 80 t:LUT6 +select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 36 t:MUXF7 select -assert-count 9 t:MUXF8 -- cgit v1.2.3 From 68f9239c5758e4f48dc290871cf108f85d5f5387 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 13:58:49 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index c5855f1dd..6a4c1e971 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -11,7 +11,7 @@ select -assert-count 12 t:LUT4 select -assert-count 9 t:LUT5 select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY -select -assert-count 36 t:MUXF7 +select -assert-count 39 t:MUXF7 select -assert-count 9 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D -- cgit v1.2.3 From bb70eb977dc29dbfe8cfb9af847046f387bd54b2 Mon Sep 17 00:00:00 2001 From: Sergey <37293587+SergeyDegtyar@users.noreply.github.com> Date: Thu, 12 Sep 2019 14:54:01 +0300 Subject: Fix div_mod test --- tests/xilinx/div_mod.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 6a4c1e971..4518db8bf 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -12,6 +12,6 @@ select -assert-count 9 t:LUT5 select -assert-count 84 t:LUT6 select -assert-count 65 t:MUXCY select -assert-count 39 t:MUXF7 -select -assert-count 9 t:MUXF8 +select -assert-count 15 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D -- cgit v1.2.3 From 305672170bcd6346bebbb01c843225fe0392a37d Mon Sep 17 00:00:00 2001 From: SergeyDegtyar Date: Tue, 17 Sep 2019 11:53:49 +0300 Subject: adffs test update (equiv_opt -multiclock) --- tests/xilinx/adffs.ys | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 38c82a36f..961e08ae9 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,13 +1,14 @@ read_verilog adffs.v proc -async2sync # converts async flops to a 'sync' variant clocked by a 'super'-clock flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 3 t:FDRE +select -assert-count 2 t:FDCE +select -assert-count 1 t:FDRE select -assert-count 1 t:FDRE_1 -select -assert-count 5 t:LUT2 -select -assert-none t:BUFG t:FDRE t:FDRE_1 t:LUT2 %% t:* %D +select -assert-count 1 t:LUT1 +select -assert-count 2 t:LUT2 +select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D -- cgit v1.2.3 From eded90b6b42117ba427469a6100c74e708c4f142 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:16:45 -0700 Subject: Move $x to end as 7f0eec8 --- tests/xilinx/run-test.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/run-test.sh b/tests/xilinx/run-test.sh index 2c72ca3a9..46716f9a0 100755 --- a/tests/xilinx/run-test.sh +++ b/tests/xilinx/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From a12801843bb400bba8f2f8ce99a3f524ac05b7e8 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:17:59 -0700 Subject: Add comment for lack of tristate logic pointing to #1225 --- tests/xilinx/tribuf.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 76b00647d..696be2620 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -7,6 +7,6 @@ synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -#Xilinx Vivado synthesizes OBUFT cell for this case. Need support it. +# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From 08bd1816e39d2abfbe36ce0b58c0d4506db303e4 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:20:47 -0700 Subject: Update area for div_mod --- tests/xilinx/div_mod.ys | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys index 4518db8bf..da7e60a9a 100644 --- a/tests/xilinx/div_mod.ys +++ b/tests/xilinx/div_mod.ys @@ -6,12 +6,12 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 12 t:LUT1 -select -assert-count 23 t:LUT2 -select -assert-count 12 t:LUT4 -select -assert-count 9 t:LUT5 -select -assert-count 84 t:LUT6 +select -assert-count 19 t:LUT2 +select -assert-count 13 t:LUT4 +select -assert-count 6 t:LUT5 +select -assert-count 82 t:LUT6 select -assert-count 65 t:MUXCY -select -assert-count 39 t:MUXF7 -select -assert-count 15 t:MUXF8 +select -assert-count 37 t:MUXF7 +select -assert-count 11 t:MUXF8 select -assert-count 28 t:XORCY select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D -- cgit v1.2.3 From 5b7bc3ab85d31920883995636d26dc5b971ca24d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:38:06 -0700 Subject: Update mul test to DSP48E1 --- tests/xilinx/mul.ys | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys index ec30c9c2c..f5306e848 100644 --- a/tests/xilinx/mul.ys +++ b/tests/xilinx/mul.ys @@ -4,12 +4,5 @@ equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 12 t:LUT2 -select -assert-count 1 t:LUT3 -select -assert-count 6 t:LUT4 -select -assert-count 1 t:LUT5 -select -assert-count 33 t:LUT6 -select -assert-count 11 t:MUXCY -select -assert-count 1 t:MUXF7 -select -assert-count 12 t:XORCY -select -assert-none t:FDRE t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:XORCY %% t:* %D +select -assert-count 1 t:DSP48E1 +select -assert-none t:DSP48E1 %% t:* %D -- cgit v1.2.3 From 8422ad3e3a5db583f59906f8a5d81587dd777f6d Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 14:56:19 -0700 Subject: Use built-in async2sync call as per #1417 --- tests/xilinx/latches.ys | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 1f643cb4e..795ac9074 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -4,11 +4,7 @@ design -save read proc async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock flatten -synth_xilinx equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) - -design -load read synth_xilinx flatten -- cgit v1.2.3 From 3b4408432073ec4d9a2b8995b8e08a5bf6175f39 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Mon, 30 Sep 2019 19:57:26 -0700 Subject: Add -assert --- tests/xilinx/counter.ys | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index b602b74d7..3bb3a8eb0 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -- cgit v1.2.3 From a7fbc8c3fe1e2ad867ffc3456943644e70ab2575 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:19:26 +0200 Subject: Test per flip-flop type --- tests/xilinx/adffs.v | 40 ---------------------------------------- tests/xilinx/adffs.ys | 44 +++++++++++++++++++++++++++++++++++++------- 2 files changed, 37 insertions(+), 47 deletions(-) diff --git a/tests/xilinx/adffs.v b/tests/xilinx/adffs.v index 05e68caf7..223b52d21 100644 --- a/tests/xilinx/adffs.v +++ b/tests/xilinx/adffs.v @@ -45,43 +45,3 @@ module ndffnr else q <= d; endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 961e08ae9..7edab67c7 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,14 +1,44 @@ read_verilog adffs.v +design -save read + proc -flatten -equiv_opt -multiclock -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +hierarchy -top adff +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDCE +select -assert-none t:BUFG t:FDCE %% t:* %D + +design -load read +proc +hierarchy -top adffn +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDCE +select -assert-count 1 t:LUT1 +select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D +design -load read +proc +hierarchy -top dffs +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 2 t:FDCE select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT2 +select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D + +design -load read +proc +hierarchy -top ndffnr +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 -select -assert-count 1 t:LUT1 -select -assert-count 2 t:LUT2 -select -assert-none t:BUFG t:FDCE t:FDRE t:FDRE_1 t:LUT1 t:LUT2 %% t:* %D +select -assert-count 1 t:LUT2 +select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D \ No newline at end of file -- cgit v1.2.3 From d37cd267a56295737e95f5bc5e6f446c27605639 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:24:37 +0200 Subject: Removed alu and div_mod test as agreed, ignore generated files --- tests/xilinx/.gitignore | 1 + tests/xilinx/alu.v | 19 ------------------- tests/xilinx/alu.ys | 21 --------------------- tests/xilinx/div_mod.v | 13 ------------- tests/xilinx/div_mod.ys | 17 ----------------- 5 files changed, 1 insertion(+), 70 deletions(-) delete mode 100644 tests/xilinx/alu.v delete mode 100644 tests/xilinx/alu.ys delete mode 100644 tests/xilinx/div_mod.v delete mode 100644 tests/xilinx/div_mod.ys diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore index 54733fb71..89879f209 100644 --- a/tests/xilinx/.gitignore +++ b/tests/xilinx/.gitignore @@ -2,3 +2,4 @@ /*.out /run-test.mk /*_uut.v +/test_macc \ No newline at end of file diff --git a/tests/xilinx/alu.v b/tests/xilinx/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/xilinx/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/xilinx/alu.ys b/tests/xilinx/alu.ys deleted file mode 100644 index f85f03928..000000000 --- a/tests/xilinx/alu.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - - -select -assert-count 1 t:BUFG -select -assert-count 32 t:LUT1 -select -assert-count 142 t:LUT2 -select -assert-count 55 t:LUT3 -select -assert-count 70 t:LUT4 -select -assert-count 46 t:LUT5 -select -assert-count 625 t:LUT6 -select -assert-count 62 t:MUXCY -select -assert-count 265 t:MUXF7 -select -assert-count 79 t:MUXF8 -select -assert-count 64 t:XORCY -select -assert-none t:BUFG t:FDRE t:LUT1 t:LUT2 t:LUT3 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D diff --git a/tests/xilinx/div_mod.v b/tests/xilinx/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/xilinx/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/xilinx/div_mod.ys b/tests/xilinx/div_mod.ys deleted file mode 100644 index da7e60a9a..000000000 --- a/tests/xilinx/div_mod.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 12 t:LUT1 -select -assert-count 19 t:LUT2 -select -assert-count 13 t:LUT4 -select -assert-count 6 t:LUT5 -select -assert-count 82 t:LUT6 -select -assert-count 65 t:MUXCY -select -assert-count 37 t:MUXF7 -select -assert-count 11 t:MUXF8 -select -assert-count 28 t:XORCY -select -assert-none t:LUT1 t:LUT2 t:LUT4 t:LUT5 t:LUT6 t:MUXCY t:MUXF7 t:MUXF8 t:XORCY %% t:* %D -- cgit v1.2.3 From 53bc499a907cc3bfbeb91866d8839286ae0dfdf1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 08:27:49 +0200 Subject: Clean verilog code from not used define block --- tests/xilinx/shifter.v | 6 ------ tests/xilinx/tribuf.v | 6 ------ 2 files changed, 12 deletions(-) diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v index c55632552..04ae49d83 100644 --- a/tests/xilinx/shifter.v +++ b/tests/xilinx/shifter.v @@ -9,14 +9,8 @@ in always @(posedge clk) begin -`ifndef BUG out <= out >> 1; out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif end endmodule diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v index 3fa6eb6c6..75149d8ba 100644 --- a/tests/xilinx/tribuf.v +++ b/tests/xilinx/tribuf.v @@ -2,15 +2,9 @@ module tristate (en, i, o); input en; input i; output reg o; -`ifndef BUG always @(en or i) o <= (en)? i : 1'bZ; -`else - - always @(en or i) - o <= (en)? ~i : 1'bZ; -`endif endmodule -- cgit v1.2.3 From fba6229718a45188514e016eec8678f1facb82a4 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:19:17 +0200 Subject: Fix formatting --- tests/xilinx/adffs.ys | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 7edab67c7..2d23749ac 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -8,8 +8,10 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE + select -assert-none t:BUFG t:FDCE %% t:* %D + design -load read proc hierarchy -top adffn @@ -19,8 +21,10 @@ cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDCE select -assert-count 1 t:LUT1 + select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D + design -load read proc hierarchy -top dffs @@ -30,8 +34,10 @@ cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE select -assert-count 1 t:LUT2 + select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D + design -load read proc hierarchy -top ndffnr @@ -41,4 +47,5 @@ cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 1 t:FDRE_1 select -assert-count 1 t:LUT2 -select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D \ No newline at end of file + +select -assert-none t:BUFG t:FDRE_1 t:LUT2 %% t:* %D -- cgit v1.2.3 From 487b38b124cbb388bd680cb54cb43c58829ca1d3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:24:22 +0200 Subject: Split latches into separete tests --- tests/xilinx/latches.v | 34 ---------------------------------- tests/xilinx/latches.ys | 35 +++++++++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 42 deletions(-) diff --git a/tests/xilinx/latches.v b/tests/xilinx/latches.v index 9dc43e4c2..adb5d5319 100644 --- a/tests/xilinx/latches.v +++ b/tests/xilinx/latches.v @@ -22,37 +22,3 @@ module latchsr else if ( en ) q <= d; endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 795ac9074..68ca42b10 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -2,15 +2,34 @@ read_verilog latches.v design -save read proc -async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock -flatten +hierarchy -top latchp equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE -synth_xilinx -flatten -cd top +select -assert-none t:LDCE %% t:* %D + + +design -load read +proc +hierarchy -top latchn +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE select -assert-count 1 t:LUT1 + +select -assert-none t:LDCE t:LUT1 %% t:* %D + + +design -load read +proc +hierarchy -top latchsr +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:LDCE select -assert-count 2 t:LUT3 -#Xilinx Vivado synthesizes LDCE cell for this case. Need support it. -select -assert-count 3 t:$_DLATCH_P_ -select -assert-none t:LUT1 t:LUT3 t:$_DLATCH_P_ %% t:* %D + +select -assert-none t:LDCE t:LUT3 %% t:* %D -- cgit v1.2.3 From 36af10280136f0fda7b743075ac52e48576abf26 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:28:18 +0200 Subject: Test dffs separetely --- tests/xilinx/dffs.v | 22 ---------------------- tests/xilinx/dffs.ys | 23 +++++++++++++++++++---- 2 files changed, 19 insertions(+), 26 deletions(-) diff --git a/tests/xilinx/dffs.v b/tests/xilinx/dffs.v index d97840c43..3418787c9 100644 --- a/tests/xilinx/dffs.v +++ b/tests/xilinx/dffs.v @@ -13,25 +13,3 @@ module dffe if ( en ) q <= d; endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys index 6a98994c0..2d48a816c 100644 --- a/tests/xilinx/dffs.ys +++ b/tests/xilinx/dffs.ys @@ -1,10 +1,25 @@ read_verilog dffs.v -hierarchy -top top +design -save read + proc -flatten +hierarchy -top dff equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG -select -assert-count 2 t:FDRE +select -assert-count 1 t:FDRE + select -assert-none t:BUFG t:FDRE %% t:* %D + + +design -load read +proc +hierarchy -top dffe +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE + +select -assert-none t:BUFG t:FDRE %% t:* %D + -- cgit v1.2.3 From a198bcdd4ffe6b09787ea5bf2e69528ace375020 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:39:22 +0200 Subject: split muxes synth per type --- tests/xilinx/mux.v | 35 ----------------------------------- tests/xilinx/mux.ys | 43 +++++++++++++++++++++++++++++++++++++++---- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v index 0814b733e..27bc0bf0b 100644 --- a/tests/xilinx/mux.v +++ b/tests/xilinx/mux.v @@ -63,38 +63,3 @@ module mux16 (D, S, Y); assign Y = D[S]; endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys index 6ecee58f5..4cdb12e47 100644 --- a/tests/xilinx/mux.ys +++ b/tests/xilinx/mux.ys @@ -1,10 +1,45 @@ read_verilog mux.v +design -save read + +proc +hierarchy -top mux2 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 + +select -assert-none t:LUT3 %% t:* %D + + +design -load read proc -flatten +hierarchy -top mux4 equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D + + +design -load read +proc +hierarchy -top mux8 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT6 -select -assert-count 2 t:LUT3 -select -assert-count 5 t:LUT6 select -assert-none t:LUT3 t:LUT6 %% t:* %D + + +design -load read +proc +hierarchy -top mux16 +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D -- cgit v1.2.3 From 1a399c6456b6ca7becf89a5c825b2c8d7b34dc3e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:39:34 +0200 Subject: remove not needed top module --- tests/xilinx/tribuf.v | 15 --------------- tests/xilinx/tribuf.ys | 4 ++-- 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v index 75149d8ba..c64468253 100644 --- a/tests/xilinx/tribuf.v +++ b/tests/xilinx/tribuf.v @@ -6,18 +6,3 @@ module tristate (en, i, o); always @(en or i) o <= (en)? i : 1'bZ; endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys index 696be2620..c9cfb8546 100644 --- a/tests/xilinx/tribuf.ys +++ b/tests/xilinx/tribuf.ys @@ -1,12 +1,12 @@ read_verilog tribuf.v -hierarchy -top top +hierarchy -top tristate proc tribuf flatten synth equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module # TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D -- cgit v1.2.3 From b2f0d75807c99c74f9860098b74e8300514ba9e5 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 4 Oct 2019 09:41:45 +0200 Subject: remove not needed top module --- tests/xilinx/fsm.v | 18 ------------------ tests/xilinx/fsm.ys | 4 ++-- 2 files changed, 2 insertions(+), 20 deletions(-) diff --git a/tests/xilinx/fsm.v b/tests/xilinx/fsm.v index 0605bd102..368fbaace 100644 --- a/tests/xilinx/fsm.v +++ b/tests/xilinx/fsm.v @@ -52,22 +52,4 @@ endcase end - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - endmodule diff --git a/tests/xilinx/fsm.ys b/tests/xilinx/fsm.ys index 3b73891c2..a9e94c2c0 100644 --- a/tests/xilinx/fsm.ys +++ b/tests/xilinx/fsm.ys @@ -1,10 +1,10 @@ read_verilog fsm.v -hierarchy -top top +hierarchy -top fsm proc flatten equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG select -assert-count 5 t:FDRE -- cgit v1.2.3 From 980df499abb63e5dfadc29b3326032b55b6dbf18 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 17 Oct 2019 17:24:53 +0200 Subject: Make equivalence work with latest master --- tests/xilinx/adffs.ys | 8 ++++---- tests/xilinx/counter.ys | 2 +- tests/xilinx/latches.ys | 6 +++--- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 2d23749ac..9e8ba44ab 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -3,7 +3,7 @@ design -save read proc hierarchy -top adff -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -15,7 +15,7 @@ select -assert-none t:BUFG t:FDCE %% t:* %D design -load read proc hierarchy -top adffn -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -28,7 +28,7 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D design -load read proc hierarchy -top dffs -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG @@ -41,7 +41,7 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D design -load read proc hierarchy -top ndffnr -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:BUFG diff --git a/tests/xilinx/counter.ys b/tests/xilinx/counter.ys index 3bb3a8eb0..459541656 100644 --- a/tests/xilinx/counter.ys +++ b/tests/xilinx/counter.ys @@ -2,7 +2,7 @@ read_verilog counter.v hierarchy -top top proc flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 68ca42b10..52e96834d 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -3,7 +3,7 @@ design -save read proc hierarchy -top latchp -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchp # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -14,7 +14,7 @@ select -assert-none t:LDCE %% t:* %D design -load read proc hierarchy -top latchn -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE @@ -26,7 +26,7 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D design -load read proc hierarchy -top latchsr -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module select -assert-count 1 t:LDCE -- cgit v1.2.3 From 3b405d985e789ecf0082f724d2d62d3752e4b60c Mon Sep 17 00:00:00 2001 From: "N. Engelhardt" Date: Thu, 17 Oct 2019 21:33:54 +0200 Subject: Call memory_dff before DSP mapping to reserve registers (fixes #1447) --- techlibs/ice40/synth_ice40.cc | 1 + techlibs/xilinx/synth_xilinx.cc | 1 + 2 files changed, 2 insertions(+) diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index b66c6bf57..c942126e1 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -273,6 +273,7 @@ struct SynthIce40Pass : public ScriptPass run("opt_expr"); run("opt_clean"); if (help_mode || dsp) { + run("memory_dff"); run("techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 " "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 " "-D DSP_NAME=$__MUL16X16", "(if -dsp)"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index f13740865..6f8254b59 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -341,6 +341,7 @@ struct SynthXilinxPass : public ScriptPass if (check_label("map_dsp", "(skip if '-nodsp')")) { if (!nodsp || help_mode) { + run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first // NB: Xilinx multipliers are signed only run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 " "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally -- cgit v1.2.3 From e6ad714d20134612521e995c72e4fa06ed791dd3 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 08:06:57 +0200 Subject: hierarchy - proc reorder --- tests/xilinx/.gitignore | 2 +- tests/xilinx/add_sub.ys | 1 + tests/xilinx/adffs.ys | 8 ++++---- tests/xilinx/dffs.ys | 4 ++-- tests/xilinx/latches.ys | 6 +++--- tests/xilinx/logic.ys | 1 + tests/xilinx/macc.ys | 4 ++-- tests/xilinx/mul.ys | 1 + tests/xilinx/mul_unsigned.ys | 3 ++- tests/xilinx/mux.ys | 8 ++++---- 10 files changed, 21 insertions(+), 17 deletions(-) diff --git a/tests/xilinx/.gitignore b/tests/xilinx/.gitignore index 89879f209..c99b79371 100644 --- a/tests/xilinx/.gitignore +++ b/tests/xilinx/.gitignore @@ -2,4 +2,4 @@ /*.out /run-test.mk /*_uut.v -/test_macc \ No newline at end of file +/test_macc diff --git a/tests/xilinx/add_sub.ys b/tests/xilinx/add_sub.ys index 821341f20..f06e7fa01 100644 --- a/tests/xilinx/add_sub.ys +++ b/tests/xilinx/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/adffs.ys b/tests/xilinx/adffs.ys index 9e8ba44ab..1923b9802 100644 --- a/tests/xilinx/adffs.ys +++ b/tests/xilinx/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDCE %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -26,8 +26,8 @@ select -assert-none t:BUFG t:FDCE t:LUT1 %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -39,8 +39,8 @@ select -assert-none t:BUFG t:FDRE t:LUT2 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/xilinx/dffs.ys b/tests/xilinx/dffs.ys index 2d48a816c..f1716dabb 100644 --- a/tests/xilinx/dffs.ys +++ b/tests/xilinx/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:BUFG t:FDRE %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/xilinx/latches.ys b/tests/xilinx/latches.ys index 52e96834d..3eb550a42 100644 --- a/tests/xilinx/latches.ys +++ b/tests/xilinx/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:LDCE %% t:* %D design -load read -proc hierarchy -top latchn +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchn # Constrain all select calls below inside the top module @@ -24,8 +24,8 @@ select -assert-none t:LDCE t:LUT1 %% t:* %D design -load read -proc hierarchy -top latchsr +proc equiv_opt -async2sync -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/xilinx/logic.ys b/tests/xilinx/logic.ys index e138ae6a3..9ae5993aa 100644 --- a/tests/xilinx/logic.ys +++ b/tests/xilinx/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys index 417a3b21b..6e884b35a 100644 --- a/tests/xilinx/macc.ys +++ b/tests/xilinx/macc.ys @@ -1,8 +1,8 @@ read_verilog macc.v design -save read -proc hierarchy -top macc +proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter @@ -15,8 +15,8 @@ select -assert-count 1 t:DSP48E1 select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D design -load read -proc hierarchy -top macc2 +proc #equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx miter -equiv -flatten -make_assert -make_outputs gold gate miter diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys index f5306e848..66a06efdc 100644 --- a/tests/xilinx/mul.ys +++ b/tests/xilinx/mul.ys @@ -1,5 +1,6 @@ read_verilog mul.v hierarchy -top top +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys index 77990bd68..62495b90c 100644 --- a/tests/xilinx/mul_unsigned.ys +++ b/tests/xilinx/mul_unsigned.ys @@ -1,6 +1,7 @@ read_verilog mul_unsigned.v -proc hierarchy -top mul_unsigned +proc + equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mul_unsigned # Constrain all select calls below inside the top module diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys index 4cdb12e47..420dece4e 100644 --- a/tests/xilinx/mux.ys +++ b/tests/xilinx/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:LUT3 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:LUT6 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -35,8 +35,8 @@ select -assert-none t:LUT3 t:LUT6 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -- cgit v1.2.3 From 0d60902fd97bba4f231f8f600434b8a69562ffff Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:04:02 +0200 Subject: hierarchy - proc reorder --- tests/ecp5/add_sub.ys | 1 + tests/ecp5/adffs.ys | 8 ++++---- tests/ecp5/dffs.ys | 4 ++-- tests/ecp5/latches.ys | 6 +++--- tests/ecp5/logic.ys | 1 + tests/ecp5/macc.ys | 2 +- tests/ecp5/mul.ys | 1 + tests/ecp5/mux.ys | 8 ++++---- tests/ecp5/rom.ys | 1 + 9 files changed, 18 insertions(+), 14 deletions(-) diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys index 03aec6694..ee72d732f 100644 --- a/tests/ecp5/add_sub.ys +++ b/tests/ecp5/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index 658f302d0..b129419d3 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -20,8 +20,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -30,8 +30,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys index 93b8595ad..a4f45d2fb 100644 --- a/tests/ecp5/dffs.ys +++ b/tests/ecp5/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:TRELLIS_FF select -assert-none t:TRELLIS_FF %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/ecp5/latches.ys b/tests/ecp5/latches.ys index f32998232..fc15a6910 100644 --- a/tests/ecp5/latches.ys +++ b/tests/ecp5/latches.ys @@ -2,8 +2,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchp # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchn # Constrain all select calls below inside the top module @@ -24,8 +24,8 @@ select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_ecp5 cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/ecp5/logic.ys b/tests/ecp5/logic.ys index 34125fea9..4f113a130 100644 --- a/tests/ecp5/logic.ys +++ b/tests/ecp5/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index f60281a54..1863ea4d2 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,6 +1,6 @@ read_verilog macc.v -proc hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/ecp5/mul.ys b/tests/ecp5/mul.ys index 132340664..0a91f892e 100644 --- a/tests/ecp5/mul.ys +++ b/tests/ecp5/mul.ys @@ -1,5 +1,6 @@ read_verilog mul.v hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/ecp5/mux.ys b/tests/ecp5/mux.ys index eada276ba..8cfbd541b 100644 --- a/tests/ecp5/mux.ys +++ b/tests/ecp5/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:LUT4 select -assert-none t:LUT4 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -22,8 +22,8 @@ select -assert-count 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -34,8 +34,8 @@ select -assert-count 2 t:PFUMX select -assert-none t:LUT4 t:L6MUX21 t:PFUMX %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module diff --git a/tests/ecp5/rom.ys b/tests/ecp5/rom.ys index 8a52749a1..98645ae43 100644 --- a/tests/ecp5/rom.ys +++ b/tests/ecp5/rom.ys @@ -1,4 +1,5 @@ read_verilog rom.v +hierarchy -top top proc flatten equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -- cgit v1.2.3 From 46af9a0ff7727c2d47b1dc12501e3328cba1f2e9 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:06:43 +0200 Subject: hierarchy - proc reorder --- tests/anlogic/add_sub.ys | 1 + tests/anlogic/dffs.ys | 4 ++-- tests/anlogic/latches.ys | 6 +++--- tests/anlogic/mux.ys | 8 ++++---- 4 files changed, 10 insertions(+), 9 deletions(-) diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys index 994cd0d03..b8b67cc46 100644 --- a/tests/anlogic/add_sub.ys +++ b/tests/anlogic/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys index 38dffa326..9cbe5fce7 100644 --- a/tests/anlogic/dffs.ys +++ b/tests/anlogic/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -10,8 +10,8 @@ select -assert-count 1 t:AL_MAP_SEQ select -assert-none t:AL_MAP_SEQ %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys index ae9e15ff8..c00c7a25d 100644 --- a/tests/anlogic/latches.ys +++ b/tests/anlogic/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchn # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_anlogic cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys index 354fc836c..64ed2a2bd 100644 --- a/tests/anlogic/mux.ys +++ b/tests/anlogic/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -11,8 +11,8 @@ select -assert-count 1 t:AL_MAP_LUT3 select -assert-none t:AL_MAP_LUT3 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -21,8 +21,8 @@ select -assert-count 1 t:AL_MAP_LUT6 select -assert-none t:AL_MAP_LUT6 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -32,8 +32,8 @@ select -assert-count 1 t:AL_MAP_LUT6 select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -- cgit v1.2.3 From b659082e4a72209af62a19668800bb6334a437d7 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 09:13:06 +0200 Subject: hierarchy - proc reorder --- tests/efinix/add_sub.ys | 1 + tests/efinix/adffs.ys | 8 ++++---- tests/efinix/dffs.ys | 4 ++-- tests/efinix/latches.ys | 6 +++--- tests/efinix/logic.ys | 1 + tests/efinix/mux.ys | 8 ++++---- 6 files changed, 15 insertions(+), 13 deletions(-) diff --git a/tests/efinix/add_sub.ys b/tests/efinix/add_sub.ys index 67fa9f2e7..8bd28c68e 100644 --- a/tests/efinix/add_sub.ys +++ b/tests/efinix/add_sub.ys @@ -1,5 +1,6 @@ read_verilog add_sub.v hierarchy -top top +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys index 3471a0a80..791626428 100644 --- a/tests/efinix/adffs.ys +++ b/tests/efinix/adffs.ys @@ -1,8 +1,8 @@ read_verilog adffs.v design -save read -proc hierarchy -top adff +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module @@ -13,8 +13,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read -proc hierarchy -top adffn +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module @@ -25,8 +25,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read -proc hierarchy -top dffs +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module @@ -38,8 +38,8 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top ndffnr +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys index fe8d93123..cdd288233 100644 --- a/tests/efinix/dffs.ys +++ b/tests/efinix/dffs.ys @@ -1,8 +1,8 @@ read_verilog dffs.v design -save read -proc hierarchy -top dff +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dff # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-count 1 t:EFX_GBUFCE select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read -proc hierarchy -top dffe +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffe # Constrain all select calls below inside the top module diff --git a/tests/efinix/latches.ys b/tests/efinix/latches.ys index f729c3bd9..899d024ce 100644 --- a/tests/efinix/latches.ys +++ b/tests/efinix/latches.ys @@ -1,8 +1,8 @@ read_verilog latches.v design -save read -proc hierarchy -top latchp +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_efinix cd latchp # Constrain all select calls below inside the top module @@ -12,8 +12,8 @@ select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top latchn +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_efinix cd latchn # Constrain all select calls below inside the top module @@ -23,8 +23,8 @@ select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top latchsr +proc # Can't run any sort of equivalence check because latches are blown to LUTs synth_efinix cd latchsr # Constrain all select calls below inside the top module diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys index c2a7f5169..fdedb337b 100644 --- a/tests/efinix/logic.ys +++ b/tests/efinix/logic.ys @@ -1,5 +1,6 @@ read_verilog logic.v hierarchy -top top +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module diff --git a/tests/efinix/mux.ys b/tests/efinix/mux.ys index efe27583d..71a9681de 100644 --- a/tests/efinix/mux.ys +++ b/tests/efinix/mux.ys @@ -1,8 +1,8 @@ read_verilog mux.v design -save read -proc hierarchy -top mux2 +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux2 # Constrain all select calls below inside the top module @@ -11,8 +11,8 @@ select -assert-count 1 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top mux4 +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module @@ -21,8 +21,8 @@ select -assert-count 2 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top mux8 +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module @@ -31,8 +31,8 @@ select -assert-count 5 t:EFX_LUT4 select -assert-none t:EFX_LUT4 %% t:* %D design -load read -proc hierarchy -top mux16 +proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -- cgit v1.2.3 From 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:00:27 +0200 Subject: Add async2sync --- tests/ecp5/adffs.ys | 8 ++++---- tests/efinix/adffs.ys | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys index b129419d3..c6780e565 100644 --- a/tests/ecp5/adffs.ys +++ b/tests/ecp5/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -12,7 +12,7 @@ select -assert-none t:TRELLIS_FF %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -22,7 +22,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF @@ -32,7 +32,7 @@ select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:TRELLIS_FF diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys index 791626428..1069c6c5c 100644 --- a/tests/efinix/adffs.ys +++ b/tests/efinix/adffs.ys @@ -3,7 +3,7 @@ design -save read hierarchy -top adff proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adff # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_FF @@ -15,7 +15,7 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read hierarchy -top adffn proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd adffn # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_FF @@ -27,7 +27,7 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D design -load read hierarchy -top dffs proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd dffs # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_FF @@ -40,7 +40,7 @@ select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D design -load read hierarchy -top ndffnr proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd ndffnr # Constrain all select calls below inside the top module select -assert-count 1 t:EFX_FF -- cgit v1.2.3 From c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:06:12 +0200 Subject: Moved all tests in arch sub directory --- Makefile | 10 ++-- tests/anlogic/.gitignore | 4 -- tests/anlogic/add_sub.v | 13 ----- tests/anlogic/add_sub.ys | 10 ---- tests/anlogic/counter.v | 17 ------ tests/anlogic/counter.ys | 11 ---- tests/anlogic/dffs.v | 15 ----- tests/anlogic/dffs.ys | 20 ------- tests/anlogic/fsm.v | 55 ------------------- tests/anlogic/fsm.ys | 15 ----- tests/anlogic/latches.v | 24 -------- tests/anlogic/latches.ys | 33 ----------- tests/anlogic/memory.v | 21 ------- tests/anlogic/memory.ys | 21 ------- tests/anlogic/mux.v | 65 ---------------------- tests/anlogic/mux.ys | 42 -------------- tests/anlogic/run-test.sh | 20 ------- tests/anlogic/shifter.v | 16 ------ tests/anlogic/shifter.ys | 10 ---- tests/anlogic/tribuf.v | 8 --- tests/anlogic/tribuf.ys | 9 --- tests/arch/anlogic/.gitignore | 4 ++ tests/arch/anlogic/add_sub.v | 13 +++++ tests/arch/anlogic/add_sub.ys | 10 ++++ tests/arch/anlogic/counter.v | 17 ++++++ tests/arch/anlogic/counter.ys | 11 ++++ tests/arch/anlogic/dffs.v | 15 +++++ tests/arch/anlogic/dffs.ys | 20 +++++++ tests/arch/anlogic/fsm.v | 55 +++++++++++++++++++ tests/arch/anlogic/fsm.ys | 15 +++++ tests/arch/anlogic/latches.v | 24 ++++++++ tests/arch/anlogic/latches.ys | 33 +++++++++++ tests/arch/anlogic/memory.v | 21 +++++++ tests/arch/anlogic/memory.ys | 21 +++++++ tests/arch/anlogic/mux.v | 65 ++++++++++++++++++++++ tests/arch/anlogic/mux.ys | 42 ++++++++++++++ tests/arch/anlogic/run-test.sh | 20 +++++++ tests/arch/anlogic/shifter.v | 16 ++++++ tests/arch/anlogic/shifter.ys | 10 ++++ tests/arch/anlogic/tribuf.v | 8 +++ tests/arch/anlogic/tribuf.ys | 9 +++ tests/arch/ecp5/.gitignore | 2 + tests/arch/ecp5/add_sub.v | 13 +++++ tests/arch/ecp5/add_sub.ys | 9 +++ tests/arch/ecp5/adffs.v | 47 ++++++++++++++++ tests/arch/ecp5/adffs.ys | 40 ++++++++++++++ tests/arch/ecp5/counter.v | 17 ++++++ tests/arch/ecp5/counter.ys | 10 ++++ tests/arch/ecp5/dffs.v | 15 +++++ tests/arch/ecp5/dffs.ys | 19 +++++++ tests/arch/ecp5/dpram.v | 23 ++++++++ tests/arch/ecp5/dpram.ys | 18 ++++++ tests/arch/ecp5/fsm.v | 55 +++++++++++++++++++ tests/arch/ecp5/fsm.ys | 12 ++++ tests/arch/ecp5/latches.v | 24 ++++++++ tests/arch/ecp5/latches.ys | 35 ++++++++++++ tests/arch/ecp5/logic.v | 18 ++++++ tests/arch/ecp5/logic.ys | 8 +++ tests/arch/ecp5/macc.v | 25 +++++++++ tests/arch/ecp5/macc.ys | 13 +++++ tests/arch/ecp5/memory.v | 21 +++++++ tests/arch/ecp5/memory.ys | 19 +++++++ tests/arch/ecp5/mul.v | 11 ++++ tests/arch/ecp5/mul.ys | 11 ++++ tests/arch/ecp5/mux.v | 66 ++++++++++++++++++++++ tests/arch/ecp5/mux.ys | 46 ++++++++++++++++ tests/arch/ecp5/rom.v | 18 ++++++ tests/arch/ecp5/rom.ys | 10 ++++ tests/arch/ecp5/run-test.sh | 20 +++++++ tests/arch/ecp5/shifter.v | 16 ++++++ tests/arch/ecp5/shifter.ys | 10 ++++ tests/arch/ecp5/tribuf.v | 8 +++ tests/arch/ecp5/tribuf.ys | 9 +++ tests/arch/efinix/.gitignore | 3 + tests/arch/efinix/add_sub.v | 13 +++++ tests/arch/efinix/add_sub.ys | 10 ++++ tests/arch/efinix/adffs.v | 47 ++++++++++++++++ tests/arch/efinix/adffs.ys | 50 +++++++++++++++++ tests/arch/efinix/counter.v | 17 ++++++ tests/arch/efinix/counter.ys | 12 ++++ tests/arch/efinix/dffs.v | 15 +++++ tests/arch/efinix/dffs.ys | 24 ++++++++ tests/arch/efinix/fsm.v | 55 +++++++++++++++++++ tests/arch/efinix/fsm.ys | 14 +++++ tests/arch/efinix/latches.v | 24 ++++++++ tests/arch/efinix/latches.ys | 33 +++++++++++ tests/arch/efinix/logic.v | 18 ++++++ tests/arch/efinix/logic.ys | 9 +++ tests/arch/efinix/memory.v | 21 +++++++ tests/arch/efinix/memory.ys | 18 ++++++ tests/arch/efinix/mux.v | 65 ++++++++++++++++++++++ tests/arch/efinix/mux.ys | 41 ++++++++++++++ tests/arch/efinix/run-test.sh | 20 +++++++ tests/arch/efinix/shifter.v | 16 ++++++ tests/arch/efinix/shifter.ys | 11 ++++ tests/arch/efinix/tribuf.v | 8 +++ tests/arch/efinix/tribuf.ys | 12 ++++ tests/arch/ice40/.gitignore | 4 ++ tests/arch/ice40/add_sub.v | 13 +++++ tests/arch/ice40/add_sub.ys | 9 +++ tests/arch/ice40/adffs.v | 87 +++++++++++++++++++++++++++++ tests/arch/ice40/adffs.ys | 11 ++++ tests/arch/ice40/alu.v | 19 +++++++ tests/arch/ice40/alu.ys | 11 ++++ tests/arch/ice40/counter.v | 17 ++++++ tests/arch/ice40/counter.ys | 11 ++++ tests/arch/ice40/dffs.v | 37 +++++++++++++ tests/arch/ice40/dffs.ys | 10 ++++ tests/arch/ice40/div_mod.v | 13 +++++ tests/arch/ice40/div_mod.ys | 9 +++ tests/arch/ice40/dpram.v | 23 ++++++++ tests/arch/ice40/dpram.ys | 15 +++++ tests/arch/ice40/fsm.v | 73 +++++++++++++++++++++++++ tests/arch/ice40/fsm.ys | 13 +++++ tests/arch/ice40/ice40_opt.ys | 26 +++++++++ tests/arch/ice40/latches.v | 58 ++++++++++++++++++++ tests/arch/ice40/latches.ys | 12 ++++ tests/arch/ice40/logic.v | 18 ++++++ tests/arch/ice40/logic.ys | 7 +++ tests/arch/ice40/macc.v | 47 ++++++++++++++++ tests/arch/ice40/macc.ys | 25 +++++++++ tests/arch/ice40/memory.v | 21 +++++++ tests/arch/ice40/memory.ys | 15 +++++ tests/arch/ice40/mul.v | 11 ++++ tests/arch/ice40/mul.ys | 7 +++ tests/arch/ice40/mux.v | 100 ++++++++++++++++++++++++++++++++++ tests/arch/ice40/mux.ys | 8 +++ tests/arch/ice40/rom.v | 18 ++++++ tests/arch/ice40/rom.ys | 8 +++ tests/arch/ice40/run-test.sh | 20 +++++++ tests/arch/ice40/shifter.v | 22 ++++++++ tests/arch/ice40/shifter.ys | 9 +++ tests/arch/ice40/tribuf.v | 23 ++++++++ tests/arch/ice40/tribuf.ys | 9 +++ tests/arch/ice40/wrapcarry.ys | 22 ++++++++ tests/arch/xilinx/.gitignore | 5 ++ tests/arch/xilinx/add_sub.v | 13 +++++ tests/arch/xilinx/add_sub.ys | 11 ++++ tests/arch/xilinx/adffs.v | 47 ++++++++++++++++ tests/arch/xilinx/adffs.ys | 51 +++++++++++++++++ tests/arch/xilinx/counter.v | 17 ++++++ tests/arch/xilinx/counter.ys | 14 +++++ tests/arch/xilinx/dffs.v | 15 +++++ tests/arch/xilinx/dffs.ys | 25 +++++++++ tests/arch/xilinx/dsp_simd.ys | 25 +++++++++ tests/arch/xilinx/fsm.v | 55 +++++++++++++++++++ tests/arch/xilinx/fsm.ys | 14 +++++ tests/arch/xilinx/latches.v | 24 ++++++++ tests/arch/xilinx/latches.ys | 35 ++++++++++++ tests/arch/xilinx/logic.v | 18 ++++++ tests/arch/xilinx/logic.ys | 11 ++++ tests/arch/xilinx/macc.sh | 3 + tests/arch/xilinx/macc.v | 84 ++++++++++++++++++++++++++++ tests/arch/xilinx/macc.ys | 31 +++++++++++ tests/arch/xilinx/macc_tb.v | 96 ++++++++++++++++++++++++++++++++ tests/arch/xilinx/memory.v | 21 +++++++ tests/arch/xilinx/memory.ys | 17 ++++++ tests/arch/xilinx/mul.v | 11 ++++ tests/arch/xilinx/mul.ys | 9 +++ tests/arch/xilinx/mul_unsigned.v | 30 ++++++++++ tests/arch/xilinx/mul_unsigned.ys | 11 ++++ tests/arch/xilinx/mux.v | 65 ++++++++++++++++++++++ tests/arch/xilinx/mux.ys | 45 +++++++++++++++ tests/arch/xilinx/pmgen_xilinx_srl.ys | 57 +++++++++++++++++++ tests/arch/xilinx/run-test.sh | 20 +++++++ tests/arch/xilinx/shifter.v | 16 ++++++ tests/arch/xilinx/shifter.ys | 11 ++++ tests/arch/xilinx/tribuf.v | 8 +++ tests/arch/xilinx/tribuf.ys | 12 ++++ tests/arch/xilinx/xilinx_srl.v | 40 ++++++++++++++ tests/arch/xilinx/xilinx_srl.ys | 67 +++++++++++++++++++++++ tests/ecp5/.gitignore | 2 - tests/ecp5/add_sub.v | 13 ----- tests/ecp5/add_sub.ys | 9 --- tests/ecp5/adffs.v | 47 ---------------- tests/ecp5/adffs.ys | 40 -------------- tests/ecp5/counter.v | 17 ------ tests/ecp5/counter.ys | 10 ---- tests/ecp5/dffs.v | 15 ----- tests/ecp5/dffs.ys | 19 ------- tests/ecp5/dpram.v | 23 -------- tests/ecp5/dpram.ys | 18 ------ tests/ecp5/fsm.v | 55 ------------------- tests/ecp5/fsm.ys | 12 ---- tests/ecp5/latches.v | 24 -------- tests/ecp5/latches.ys | 35 ------------ tests/ecp5/logic.v | 18 ------ tests/ecp5/logic.ys | 8 --- tests/ecp5/macc.v | 25 --------- tests/ecp5/macc.ys | 13 ----- tests/ecp5/memory.v | 21 ------- tests/ecp5/memory.ys | 19 ------- tests/ecp5/mul.v | 11 ---- tests/ecp5/mul.ys | 11 ---- tests/ecp5/mux.v | 66 ---------------------- tests/ecp5/mux.ys | 46 ---------------- tests/ecp5/rom.v | 18 ------ tests/ecp5/rom.ys | 10 ---- tests/ecp5/run-test.sh | 20 ------- tests/ecp5/shifter.v | 16 ------ tests/ecp5/shifter.ys | 10 ---- tests/ecp5/tribuf.v | 8 --- tests/ecp5/tribuf.ys | 9 --- tests/efinix/.gitignore | 3 - tests/efinix/add_sub.v | 13 ----- tests/efinix/add_sub.ys | 10 ---- tests/efinix/adffs.v | 47 ---------------- tests/efinix/adffs.ys | 50 ----------------- tests/efinix/counter.v | 17 ------ tests/efinix/counter.ys | 12 ---- tests/efinix/dffs.v | 15 ----- tests/efinix/dffs.ys | 24 -------- tests/efinix/fsm.v | 55 ------------------- tests/efinix/fsm.ys | 14 ----- tests/efinix/latches.v | 24 -------- tests/efinix/latches.ys | 33 ----------- tests/efinix/logic.v | 18 ------ tests/efinix/logic.ys | 9 --- tests/efinix/memory.v | 21 ------- tests/efinix/memory.ys | 18 ------ tests/efinix/mux.v | 65 ---------------------- tests/efinix/mux.ys | 41 -------------- tests/efinix/run-test.sh | 20 ------- tests/efinix/shifter.v | 16 ------ tests/efinix/shifter.ys | 11 ---- tests/efinix/tribuf.v | 8 --- tests/efinix/tribuf.ys | 12 ---- tests/ice40/.gitignore | 4 -- tests/ice40/add_sub.v | 13 ----- tests/ice40/add_sub.ys | 9 --- tests/ice40/adffs.v | 87 ----------------------------- tests/ice40/adffs.ys | 11 ---- tests/ice40/alu.v | 19 ------- tests/ice40/alu.ys | 11 ---- tests/ice40/counter.v | 17 ------ tests/ice40/counter.ys | 11 ---- tests/ice40/dffs.v | 37 ------------- tests/ice40/dffs.ys | 10 ---- tests/ice40/div_mod.v | 13 ----- tests/ice40/div_mod.ys | 9 --- tests/ice40/dpram.v | 23 -------- tests/ice40/dpram.ys | 15 ----- tests/ice40/fsm.v | 73 ------------------------- tests/ice40/fsm.ys | 13 ----- tests/ice40/ice40_opt.ys | 26 --------- tests/ice40/latches.v | 58 -------------------- tests/ice40/latches.ys | 12 ---- tests/ice40/logic.v | 18 ------ tests/ice40/logic.ys | 7 --- tests/ice40/macc.v | 47 ---------------- tests/ice40/macc.ys | 25 --------- tests/ice40/memory.v | 21 ------- tests/ice40/memory.ys | 15 ----- tests/ice40/mul.v | 11 ---- tests/ice40/mul.ys | 7 --- tests/ice40/mux.v | 100 ---------------------------------- tests/ice40/mux.ys | 8 --- tests/ice40/rom.v | 18 ------ tests/ice40/rom.ys | 8 --- tests/ice40/run-test.sh | 20 ------- tests/ice40/shifter.v | 22 -------- tests/ice40/shifter.ys | 9 --- tests/ice40/tribuf.v | 23 -------- tests/ice40/tribuf.ys | 9 --- tests/ice40/wrapcarry.ys | 22 -------- tests/xilinx/.gitignore | 5 -- tests/xilinx/add_sub.v | 13 ----- tests/xilinx/add_sub.ys | 11 ---- tests/xilinx/adffs.v | 47 ---------------- tests/xilinx/adffs.ys | 51 ----------------- tests/xilinx/counter.v | 17 ------ tests/xilinx/counter.ys | 14 ----- tests/xilinx/dffs.v | 15 ----- tests/xilinx/dffs.ys | 25 --------- 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tests/xilinx/tribuf.v delete mode 100644 tests/xilinx/tribuf.ys delete mode 100644 tests/xilinx/xilinx_srl.v delete mode 100644 tests/xilinx/xilinx_srl.ys diff --git a/Makefile b/Makefile index 70d683c34..a24f19b6a 100644 --- a/Makefile +++ b/Makefile @@ -713,12 +713,12 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/opt && bash run-test.sh +cd tests/aiger && bash run-test.sh $(ABCOPT) +cd tests/arch && bash run-test.sh - +cd tests/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/ice40 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/xilinx && bash run-test.sh $(SEEDOPT) + +cd tests/arch/ecp5 && bash run-test.sh $(SEEDOPT) + +cd tests/arch/efinix && bash run-test.sh $(SEEDOPT) + +cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh - +cd tests/efinix && bash run-test.sh $(SEEDOPT) - +cd tests/anlogic && bash run-test.sh $(SEEDOPT) - +cd tests/ecp5 && bash run-test.sh $(SEEDOPT) - +cd tests/xilinx && bash run-test.sh $(SEEDOPT) @echo "" @echo " Passed \"make test\"." @echo "" diff --git a/tests/anlogic/.gitignore b/tests/anlogic/.gitignore deleted file mode 100644 index 9a71dca69..000000000 --- a/tests/anlogic/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.log -/run-test.mk -+*_synth.v -+*_testbench diff --git a/tests/anlogic/add_sub.v b/tests/anlogic/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/anlogic/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/anlogic/add_sub.ys b/tests/anlogic/add_sub.ys deleted file mode 100644 index b8b67cc46..000000000 --- a/tests/anlogic/add_sub.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:AL_MAP_ADDER -select -assert-count 4 t:AL_MAP_LUT1 - -select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/counter.v b/tests/anlogic/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/anlogic/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/anlogic/counter.ys b/tests/anlogic/counter.ys deleted file mode 100644 index 036fdba46..000000000 --- a/tests/anlogic/counter.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog counter.v -hierarchy -top top -proc -flatten -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 9 t:AL_MAP_ADDER -select -assert-count 8 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/anlogic/dffs.v b/tests/anlogic/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/anlogic/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/anlogic/dffs.ys b/tests/anlogic/dffs.ys deleted file mode 100644 index 9cbe5fce7..000000000 --- a/tests/anlogic/dffs.ys +++ /dev/null @@ -1,20 +0,0 @@ -read_verilog dffs.v -design -save read - -hierarchy -top dff -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_SEQ %% t:* %D - -design -load read -hierarchy -top dffe -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-count 1 t:AL_MAP_SEQ -select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/anlogic/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys deleted file mode 100644 index 452ef9251..000000000 --- a/tests/anlogic/fsm.ys +++ /dev/null @@ -1,15 +0,0 @@ -read_verilog fsm.v -hierarchy -top fsm -proc -#flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd fsm # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT2 -select -assert-count 5 t:AL_MAP_LUT5 -select -assert-count 1 t:AL_MAP_LUT6 -select -assert-count 6 t:AL_MAP_SEQ - -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/latches.v b/tests/anlogic/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/anlogic/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/anlogic/latches.ys b/tests/anlogic/latches.ys deleted file mode 100644 index c00c7a25d..000000000 --- a/tests/anlogic/latches.ys +++ /dev/null @@ -1,33 +0,0 @@ -read_verilog latches.v -design -save read - -hierarchy -top latchp -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic -cd latchp # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 - -select -assert-none t:AL_MAP_LUT3 %% t:* %D - - -design -load read -hierarchy -top latchn -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic -cd latchn # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 - -select -assert-none t:AL_MAP_LUT3 %% t:* %D - - -design -load read -hierarchy -top latchsr -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic -cd latchsr # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT5 - -select -assert-none t:AL_MAP_LUT5 %% t:* %D diff --git a/tests/anlogic/memory.v b/tests/anlogic/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/anlogic/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/anlogic/memory.ys b/tests/anlogic/memory.ys deleted file mode 100644 index 8c0ce844e..000000000 --- a/tests/anlogic/memory.ys +++ /dev/null @@ -1,21 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. -#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top - -select -assert-count 8 t:AL_MAP_LUT2 -select -assert-count 8 t:AL_MAP_LUT4 -select -assert-count 8 t:AL_MAP_LUT5 -select -assert-count 36 t:AL_MAP_SEQ -select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? -select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/anlogic/mux.v b/tests/anlogic/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/anlogic/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/anlogic/mux.ys b/tests/anlogic/mux.ys deleted file mode 100644 index 64ed2a2bd..000000000 --- a/tests/anlogic/mux.ys +++ /dev/null @@ -1,42 +0,0 @@ -read_verilog mux.v -design -save read - -hierarchy -top mux2 -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux2 # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 - -select -assert-none t:AL_MAP_LUT3 %% t:* %D - -design -load read -hierarchy -top mux4 -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux4 # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT6 - -select -assert-none t:AL_MAP_LUT6 %% t:* %D - -design -load read -hierarchy -top mux8 -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux8 # Constrain all select calls below inside the top module -select -assert-count 3 t:AL_MAP_LUT4 -select -assert-count 1 t:AL_MAP_LUT6 - -select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D - -design -load read -hierarchy -top mux16 -proc -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:AL_MAP_LUT6 - -select -assert-none t:AL_MAP_LUT6 %% t:* %D diff --git a/tests/anlogic/run-test.sh b/tests/anlogic/run-test.sh deleted file mode 100755 index 46716f9a0..000000000 --- a/tests/anlogic/run-test.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env bash -set -e -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" -done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/anlogic/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/anlogic/shifter.ys b/tests/anlogic/shifter.ys deleted file mode 100644 index 5eaed30a3..000000000 --- a/tests/anlogic/shifter.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:AL_MAP_SEQ - -select -assert-none t:AL_MAP_SEQ %% t:* %D diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v deleted file mode 100644 index 90dd314e4..000000000 --- a/tests/anlogic/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys deleted file mode 100644 index 0eb1338ac..000000000 --- a/tests/anlogic/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top tristate -proc -flatten -equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/anlogic/.gitignore b/tests/arch/anlogic/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/arch/anlogic/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/arch/anlogic/add_sub.v b/tests/arch/anlogic/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/anlogic/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys new file mode 100644 index 000000000..b8b67cc46 --- /dev/null +++ b/tests/arch/anlogic/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:AL_MAP_ADDER +select -assert-count 4 t:AL_MAP_LUT1 + +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D diff --git a/tests/arch/anlogic/counter.v b/tests/arch/anlogic/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/anlogic/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys new file mode 100644 index 000000000..036fdba46 --- /dev/null +++ b/tests/arch/anlogic/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:AL_MAP_ADDER +select -assert-count 8 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D diff --git a/tests/arch/anlogic/dffs.v b/tests/arch/anlogic/dffs.v new file mode 100644 index 000000000..3418787c9 --- /dev/null +++ b/tests/arch/anlogic/dffs.v @@ -0,0 +1,15 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys new file mode 100644 index 000000000..9cbe5fce7 --- /dev/null +++ b/tests/arch/anlogic/dffs.ys @@ -0,0 +1,20 @@ +read_verilog dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/anlogic/fsm.v b/tests/arch/anlogic/fsm.v new file mode 100644 index 000000000..368fbaace --- /dev/null +++ b/tests/arch/anlogic/fsm.v @@ -0,0 +1,55 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + +endmodule diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys new file mode 100644 index 000000000..452ef9251 --- /dev/null +++ b/tests/arch/anlogic/fsm.ys @@ -0,0 +1,15 @@ +read_verilog fsm.v +hierarchy -top fsm +proc +#flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT2 +select -assert-count 5 t:AL_MAP_LUT5 +select -assert-count 1 t:AL_MAP_LUT6 +select -assert-count 6 t:AL_MAP_SEQ + +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/anlogic/latches.v b/tests/arch/anlogic/latches.v new file mode 100644 index 000000000..adb5d5319 --- /dev/null +++ b/tests/arch/anlogic/latches.v @@ -0,0 +1,24 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys new file mode 100644 index 000000000..c00c7a25d --- /dev/null +++ b/tests/arch/anlogic/latches.ys @@ -0,0 +1,33 @@ +read_verilog latches.v +design -save read + +hierarchy -top latchp +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_anlogic +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT5 + +select -assert-none t:AL_MAP_LUT5 %% t:* %D diff --git a/tests/arch/anlogic/memory.v b/tests/arch/anlogic/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/arch/anlogic/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys new file mode 100644 index 000000000..8c0ce844e --- /dev/null +++ b/tests/arch/anlogic/memory.ys @@ -0,0 +1,21 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database. +#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top + +select -assert-count 8 t:AL_MAP_LUT2 +select -assert-count 8 t:AL_MAP_LUT4 +select -assert-count 8 t:AL_MAP_LUT5 +select -assert-count 36 t:AL_MAP_SEQ +select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM? +select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D diff --git a/tests/arch/anlogic/mux.v b/tests/arch/anlogic/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/arch/anlogic/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys new file mode 100644 index 000000000..64ed2a2bd --- /dev/null +++ b/tests/arch/anlogic/mux.ys @@ -0,0 +1,42 @@ +read_verilog mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT3 + +select -assert-none t:AL_MAP_LUT3 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT6 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 3 t:AL_MAP_LUT4 +select -assert-count 1 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT6 %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:AL_MAP_LUT6 + +select -assert-none t:AL_MAP_LUT6 %% t:* %D diff --git a/tests/arch/anlogic/run-test.sh b/tests/arch/anlogic/run-test.sh new file mode 100755 index 000000000..46716f9a0 --- /dev/null +++ b/tests/arch/anlogic/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/anlogic/shifter.v b/tests/arch/anlogic/shifter.v new file mode 100644 index 000000000..04ae49d83 --- /dev/null +++ b/tests/arch/anlogic/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys new file mode 100644 index 000000000..5eaed30a3 --- /dev/null +++ b/tests/arch/anlogic/shifter.ys @@ -0,0 +1,10 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:AL_MAP_SEQ + +select -assert-none t:AL_MAP_SEQ %% t:* %D diff --git a/tests/arch/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v new file mode 100644 index 000000000..90dd314e4 --- /dev/null +++ b/tests/arch/anlogic/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule diff --git a/tests/arch/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys new file mode 100644 index 000000000..0eb1338ac --- /dev/null +++ b/tests/arch/anlogic/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +flatten +equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/ecp5/.gitignore b/tests/arch/ecp5/.gitignore new file mode 100644 index 000000000..1d329c933 --- /dev/null +++ b/tests/arch/ecp5/.gitignore @@ -0,0 +1,2 @@ +*.log +/run-test.mk diff --git a/tests/arch/ecp5/add_sub.v b/tests/arch/ecp5/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/ecp5/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys new file mode 100644 index 000000000..ee72d732f --- /dev/null +++ b/tests/arch/ecp5/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:LUT4 +select -assert-none t:LUT4 %% t:* %D + diff --git a/tests/arch/ecp5/adffs.v b/tests/arch/ecp5/adffs.v new file mode 100644 index 000000000..223b52d21 --- /dev/null +++ b/tests/arch/ecp5/adffs.v @@ -0,0 +1,47 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule diff --git a/tests/arch/ecp5/adffs.ys b/tests/arch/ecp5/adffs.ys new file mode 100644 index 000000000..c6780e565 --- /dev/null +++ b/tests/arch/ecp5/adffs.ys @@ -0,0 +1,40 @@ +read_verilog adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-count 1 t:LUT4 +select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/arch/ecp5/counter.v b/tests/arch/ecp5/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/ecp5/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys new file mode 100644 index 000000000..8ef70778f --- /dev/null +++ b/tests/arch/ecp5/counter.ys @@ -0,0 +1,10 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 4 t:CCU2C +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ecp5/dffs.v b/tests/arch/ecp5/dffs.v new file mode 100644 index 000000000..3418787c9 --- /dev/null +++ b/tests/arch/ecp5/dffs.v @@ -0,0 +1,15 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule diff --git a/tests/arch/ecp5/dffs.ys b/tests/arch/ecp5/dffs.ys new file mode 100644 index 000000000..a4f45d2fb --- /dev/null +++ b/tests/arch/ecp5/dffs.ys @@ -0,0 +1,19 @@ +read_verilog dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D \ No newline at end of file diff --git a/tests/arch/ecp5/dpram.v b/tests/arch/ecp5/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/arch/ecp5/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/ecp5/shifter.v b/tests/arch/ecp5/shifter.v new file mode 100644 index 000000000..04ae49d83 --- /dev/null +++ b/tests/arch/ecp5/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/ecp5/shifter.ys b/tests/arch/ecp5/shifter.ys new file mode 100644 index 000000000..e1901e1a8 --- /dev/null +++ b/tests/arch/ecp5/shifter.ys @@ -0,0 +1,10 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:TRELLIS_FF +select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/ecp5/tribuf.v b/tests/arch/ecp5/tribuf.v new file mode 100644 index 000000000..90dd314e4 --- /dev/null +++ b/tests/arch/ecp5/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule diff --git a/tests/arch/ecp5/tribuf.ys b/tests/arch/ecp5/tribuf.ys new file mode 100644 index 000000000..a6e9c9598 --- /dev/null +++ b/tests/arch/ecp5/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +flatten +equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/efinix/.gitignore b/tests/arch/efinix/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/arch/efinix/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/arch/efinix/add_sub.v b/tests/arch/efinix/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/efinix/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/efinix/add_sub.ys b/tests/arch/efinix/add_sub.ys new file mode 100644 index 000000000..8bd28c68e --- /dev/null +++ b/tests/arch/efinix/add_sub.ys @@ -0,0 +1,10 @@ +read_verilog add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 10 t:EFX_ADD +select -assert-count 4 t:EFX_LUT4 +select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D + diff --git a/tests/arch/efinix/adffs.v b/tests/arch/efinix/adffs.v new file mode 100644 index 000000000..223b52d21 --- /dev/null +++ b/tests/arch/efinix/adffs.v @@ -0,0 +1,47 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule diff --git a/tests/arch/efinix/adffs.ys b/tests/arch/efinix/adffs.ys new file mode 100644 index 000000000..1069c6c5c --- /dev/null +++ b/tests/arch/efinix/adffs.ys @@ -0,0 +1,50 @@ +read_verilog adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE + +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE + +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/counter.v b/tests/arch/efinix/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/efinix/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys new file mode 100644 index 000000000..82e61d39b --- /dev/null +++ b/tests/arch/efinix/counter.ys @@ -0,0 +1,12 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 8 t:EFX_FF +select -assert-count 9 t:EFX_ADD +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D diff --git a/tests/arch/efinix/dffs.v b/tests/arch/efinix/dffs.v new file mode 100644 index 000000000..3418787c9 --- /dev/null +++ b/tests/arch/efinix/dffs.v @@ -0,0 +1,15 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule diff --git a/tests/arch/efinix/dffs.ys b/tests/arch/efinix/dffs.ys new file mode 100644 index 000000000..cdd288233 --- /dev/null +++ b/tests/arch/efinix/dffs.ys @@ -0,0 +1,24 @@ +read_verilog dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE + +select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_FF +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/fsm.v b/tests/arch/efinix/fsm.v new file mode 100644 index 000000000..368fbaace --- /dev/null +++ b/tests/arch/efinix/fsm.v @@ -0,0 +1,55 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + +endmodule diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys new file mode 100644 index 000000000..2ec75215d --- /dev/null +++ b/tests/arch/efinix/fsm.ys @@ -0,0 +1,14 @@ +read_verilog fsm.v +hierarchy -top fsm +proc +flatten +#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. +#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd fsm # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 6 t:EFX_FF +select -assert-count 15 t:EFX_LUT4 +select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/latches.v b/tests/arch/efinix/latches.v new file mode 100644 index 000000000..adb5d5319 --- /dev/null +++ b/tests/arch/efinix/latches.v @@ -0,0 +1,24 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule diff --git a/tests/arch/efinix/latches.ys b/tests/arch/efinix/latches.ys new file mode 100644 index 000000000..899d024ce --- /dev/null +++ b/tests/arch/efinix/latches.ys @@ -0,0 +1,33 @@ +read_verilog latches.v +design -save read + +hierarchy -top latchp +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_efinix +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/logic.v b/tests/arch/efinix/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/arch/efinix/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys new file mode 100644 index 000000000..fdedb337b --- /dev/null +++ b/tests/arch/efinix/logic.ys @@ -0,0 +1,9 @@ +read_verilog logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 9 t:EFX_LUT4 +select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/memory.v b/tests/arch/efinix/memory.v new file mode 100644 index 000000000..5634d6507 --- /dev/null +++ b/tests/arch/efinix/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [8:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys new file mode 100644 index 000000000..fe24b0a9b --- /dev/null +++ b/tests/arch/efinix/memory.ys @@ -0,0 +1,18 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 1 t:EFX_RAM_5K +select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/arch/efinix/mux.v b/tests/arch/efinix/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/arch/efinix/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys new file mode 100644 index 000000000..71a9681de --- /dev/null +++ b/tests/arch/efinix/mux.ys @@ -0,0 +1,41 @@ +read_verilog mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 12 t:EFX_LUT4 + +select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/arch/efinix/run-test.sh b/tests/arch/efinix/run-test.sh new file mode 100755 index 000000000..46716f9a0 --- /dev/null +++ b/tests/arch/efinix/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/efinix/shifter.v b/tests/arch/efinix/shifter.v new file mode 100644 index 000000000..ce2c81dd2 --- /dev/null +++ b/tests/arch/efinix/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out << 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/efinix/shifter.ys b/tests/arch/efinix/shifter.ys new file mode 100644 index 000000000..1a6b5565c --- /dev/null +++ b/tests/arch/efinix/shifter.ys @@ -0,0 +1,11 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:EFX_GBUFCE +select -assert-count 8 t:EFX_FF +select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D diff --git a/tests/arch/efinix/tribuf.v b/tests/arch/efinix/tribuf.v new file mode 100644 index 000000000..c64468253 --- /dev/null +++ b/tests/arch/efinix/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule diff --git a/tests/arch/efinix/tribuf.ys b/tests/arch/efinix/tribuf.ys new file mode 100644 index 000000000..2e2ab9e65 --- /dev/null +++ b/tests/arch/efinix/tribuf.ys @@ -0,0 +1,12 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/ice40/.gitignore b/tests/arch/ice40/.gitignore new file mode 100644 index 000000000..9a71dca69 --- /dev/null +++ b/tests/arch/ice40/.gitignore @@ -0,0 +1,4 @@ +*.log +/run-test.mk ++*_synth.v ++*_testbench diff --git a/tests/arch/ice40/add_sub.v b/tests/arch/ice40/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/ice40/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys new file mode 100644 index 000000000..4a998d98d --- /dev/null +++ b/tests/arch/ice40/add_sub.ys @@ -0,0 +1,9 @@ +read_verilog add_sub.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 +select -assert-count 6 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D + diff --git a/tests/arch/ice40/adffs.v b/tests/arch/ice40/adffs.v new file mode 100644 index 000000000..09dc36001 --- /dev/null +++ b/tests/arch/ice40/adffs.v @@ -0,0 +1,87 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge pre ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk, negedge pre ) + if ( !pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2,b3 +); + +dffs u_dffs ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b ) + ); + +ndffnr u_ndffnr ( + .clk (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b1 ) + ); + +adff u_adff ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b2 ) + ); + +adffn u_adffn ( + .clk (clk ), + .clr (clr), + .d (a ), + .q (b3 ) + ); + +endmodule diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys new file mode 100644 index 000000000..548060b66 --- /dev/null +++ b/tests/arch/ice40/adffs.ys @@ -0,0 +1,11 @@ +read_verilog adffs.v +proc +flatten +equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFNS +select -assert-count 2 t:SB_DFFR +select -assert-count 1 t:SB_DFFS +select -assert-count 2 t:SB_LUT4 +select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/alu.v b/tests/arch/ice40/alu.v new file mode 100644 index 000000000..f82cc2e21 --- /dev/null +++ b/tests/arch/ice40/alu.v @@ -0,0 +1,19 @@ +module top ( + input clock, + input [31:0] dinA, dinB, + input [2:0] opcode, + output reg [31:0] dout +); + always @(posedge clock) begin + case (opcode) + 0: dout <= dinA + dinB; + 1: dout <= dinA - dinB; + 2: dout <= dinA >> dinB; + 3: dout <= $signed(dinA) >>> dinB; + 4: dout <= dinA << dinB; + 5: dout <= dinA & dinB; + 6: dout <= dinA | dinB; + 7: dout <= dinA ^ dinB; + endcase + end +endmodule diff --git a/tests/arch/ice40/alu.ys b/tests/arch/ice40/alu.ys new file mode 100644 index 000000000..bd859efc4 --- /dev/null +++ b/tests/arch/ice40/alu.ys @@ -0,0 +1,11 @@ +read_verilog alu.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 62 t:SB_CARRY +select -assert-count 32 t:SB_DFF +select -assert-count 655 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/counter.v b/tests/arch/ice40/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/ice40/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys new file mode 100644 index 000000000..c65c21622 --- /dev/null +++ b/tests/arch/ice40/counter.ys @@ -0,0 +1,11 @@ +read_verilog counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 6 t:SB_CARRY +select -assert-count 8 t:SB_DFFR +select -assert-count 8 t:SB_LUT4 +select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/dffs.v b/tests/arch/ice40/dffs.v new file mode 100644 index 000000000..d97840c43 --- /dev/null +++ b/tests/arch/ice40/dffs.v @@ -0,0 +1,37 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule + +module top ( +input clk, +input en, +input a, +output b,b1, +); + +dff u_dff ( + .clk (clk ), + .d (a ), + .q (b ) + ); + +dffe u_ndffe ( + .clk (clk ), + .en (en), + .d (a ), + .q (b1 ) + ); + +endmodule diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys new file mode 100644 index 000000000..ee7f884b1 --- /dev/null +++ b/tests/arch/ice40/dffs.ys @@ -0,0 +1,10 @@ +read_verilog dffs.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFF +select -assert-count 1 t:SB_DFFE +select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D diff --git a/tests/arch/ice40/div_mod.v b/tests/arch/ice40/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/arch/ice40/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule diff --git a/tests/arch/ice40/div_mod.ys b/tests/arch/ice40/div_mod.ys new file mode 100644 index 000000000..821d6c301 --- /dev/null +++ b/tests/arch/ice40/div_mod.ys @@ -0,0 +1,9 @@ +read_verilog div_mod.v +hierarchy -top top +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 59 t:SB_LUT4 +select -assert-count 41 t:SB_CARRY +select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/arch/ice40/dpram.v b/tests/arch/ice40/dpram.v new file mode 100644 index 000000000..3ea4c1f27 --- /dev/null +++ b/tests/arch/ice40/dpram.v @@ -0,0 +1,23 @@ +/* +Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. +*/ +module top (din, write_en, waddr, wclk, raddr, rclk, dout); +parameter addr_width = 8; +parameter data_width = 8; +input [addr_width-1:0] waddr, raddr; +input [data_width-1:0] din; +input write_en, wclk, rclk; +output [data_width-1:0] dout; +reg [data_width-1:0] dout; +reg [data_width-1:0] mem [(1< run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/ice40/shifter.v b/tests/arch/ice40/shifter.v new file mode 100644 index 000000000..c55632552 --- /dev/null +++ b/tests/arch/ice40/shifter.v @@ -0,0 +1,22 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin +`ifndef BUG + out <= out >> 1; + out[7] <= in; +`else + + out <= out << 1; + out[7] <= in; +`endif + end + +endmodule diff --git a/tests/arch/ice40/shifter.ys b/tests/arch/ice40/shifter.ys new file mode 100644 index 000000000..47d95d298 --- /dev/null +++ b/tests/arch/ice40/shifter.ys @@ -0,0 +1,9 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/arch/ice40/tribuf.v b/tests/arch/ice40/tribuf.v new file mode 100644 index 000000000..870a02584 --- /dev/null +++ b/tests/arch/ice40/tribuf.v @@ -0,0 +1,23 @@ +module tristate (en, i, o); + input en; + input i; + output o; + + assign o = en ? i : 1'bz; + +endmodule + + +module top ( +input en, +input a, +output b +); + +tristate u_tri ( + .en (en ), + .i (a ), + .o (b ) + ); + +endmodule diff --git a/tests/arch/ice40/tribuf.ys b/tests/arch/ice40/tribuf.ys new file mode 100644 index 000000000..d1e1b3108 --- /dev/null +++ b/tests/arch/ice40/tribuf.ys @@ -0,0 +1,9 @@ +read_verilog tribuf.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/ice40/wrapcarry.ys b/tests/arch/ice40/wrapcarry.ys new file mode 100644 index 000000000..10c029e68 --- /dev/null +++ b/tests/arch/ice40/wrapcarry.ys @@ -0,0 +1,22 @@ +read_verilog <= 2**(SIZEOUT-1)) | overflow_reg; + +// Output accumulation result +assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out; + +endmodule diff --git a/tests/arch/xilinx/macc.ys b/tests/arch/xilinx/macc.ys new file mode 100644 index 000000000..6e884b35a --- /dev/null +++ b/tests/arch/xilinx/macc.ys @@ -0,0 +1,31 @@ +read_verilog macc.v +design -save read + +hierarchy -top macc +proc +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:FDRE +select -assert-count 1 t:DSP48E1 +select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D + +design -load read +hierarchy -top macc2 +proc +#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd macc2 # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 1 t:FDRE +select -assert-count 1 t:LUT2 +select -assert-count 41 t:LUT3 +select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/arch/xilinx/macc_tb.v b/tests/arch/xilinx/macc_tb.v new file mode 100644 index 000000000..64aed05c4 --- /dev/null +++ b/tests/arch/xilinx/macc_tb.v @@ -0,0 +1,96 @@ +`timescale 1ns / 1ps + +module testbench; + + parameter SIZEIN = 16, SIZEOUT = 40; + reg clk, ce, rst; + reg signed [SIZEIN-1:0] a, b; + output signed [SIZEOUT-1:0] REF_accum_out, accum_out; + output REF_overflow, overflow; + + integer errcount = 0; + + reg ERROR_FLAG = 0; + + task clkcycle; + begin + #5; + clk = ~clk; + #10; + clk = ~clk; + #2; + ERROR_FLAG = 0; + if (REF_accum_out !== accum_out) begin + $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + if (REF_overflow !== overflow) begin + $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow); + errcount = errcount + 1; + ERROR_FLAG = 1; + end + #3; + end + endtask + + initial begin + //$dumpfile("test_macc.vcd"); + //$dumpvars(0, testbench); + + #2; + clk = 1'b0; + ce = 1'b0; + a = 0; + b = 0; + + rst = 1'b1; + repeat (10) begin + #10; + clk = 1'b1; + #10; + clk = 1'b0; + #10; + clk = 1'b1; + #10; + clk = 1'b0; + end + rst = 1'b0; + + repeat (10000) begin + clkcycle; + ce = 1; //$urandom & $urandom; + //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; + a = $urandom & ~(1 << (SIZEIN-1)); + b = $urandom & ~(1 << (SIZEIN-1)); + end + + if (errcount == 0) begin + $display("All tests passed."); + $finish; + end else begin + $display("Caught %1d errors.", errcount); + $stop; + end + end + + macc2 ref ( + .clk(clk), + .ce(ce), + .rst(rst), + .a(a), + .b(b), + .accum_out(REF_accum_out), + .overflow(REF_overflow) + ); + + macc2_uut uut ( + .clk(clk), + .ce(ce), + .rst(rst), + .a(a), + .b(b), + .accum_out(accum_out), + .overflow(overflow) + ); +endmodule diff --git a/tests/arch/xilinx/memory.v b/tests/arch/xilinx/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/arch/xilinx/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys new file mode 100644 index 000000000..5402513a2 --- /dev/null +++ b/tests/arch/xilinx/memory.ys @@ -0,0 +1,17 @@ +read_verilog memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-count 8 t:RAM64X1D +select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D diff --git a/tests/arch/xilinx/mul.v b/tests/arch/xilinx/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/arch/xilinx/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys new file mode 100644 index 000000000..66a06efdc --- /dev/null +++ b/tests/arch/xilinx/mul.ys @@ -0,0 +1,9 @@ +read_verilog mul.v +hierarchy -top top +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:DSP48E1 +select -assert-none t:DSP48E1 %% t:* %D diff --git a/tests/arch/xilinx/mul_unsigned.v b/tests/arch/xilinx/mul_unsigned.v new file mode 100644 index 000000000..e3713a642 --- /dev/null +++ b/tests/arch/xilinx/mul_unsigned.v @@ -0,0 +1,30 @@ +/* +Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89]. +*/ + +// Unsigned 16x24-bit Multiplier +// 1 latency stage on operands +// 3 latency stage after the multiplication +// File: multipliers2.v +// +module mul_unsigned (clk, A, B, RES); +parameter WIDTHA = /*16*/ 6; +parameter WIDTHB = /*24*/ 9; +input clk; +input [WIDTHA-1:0] A; +input [WIDTHB-1:0] B; +output [WIDTHA+WIDTHB-1:0] RES; +reg [WIDTHA-1:0] rA; +reg [WIDTHB-1:0] rB; +reg [WIDTHA+WIDTHB-1:0] M [3:0]; +integer i; +always @(posedge clk) + begin + rA <= A; + rB <= B; + M[0] <= rA * rB; + for (i = 0; i < 3; i = i+1) + M[i+1] <= M[i]; + end +assign RES = M[3]; +endmodule diff --git a/tests/arch/xilinx/mul_unsigned.ys b/tests/arch/xilinx/mul_unsigned.ys new file mode 100644 index 000000000..62495b90c --- /dev/null +++ b/tests/arch/xilinx/mul_unsigned.ys @@ -0,0 +1,11 @@ +read_verilog mul_unsigned.v +hierarchy -top mul_unsigned +proc + +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mul_unsigned # Constrain all select calls below inside the top module +select -assert-count 1 t:BUFG +select -assert-count 1 t:DSP48E1 +select -assert-count 30 t:FDRE +select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D diff --git a/tests/arch/xilinx/mux.v b/tests/arch/xilinx/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/arch/xilinx/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys new file mode 100644 index 000000000..420dece4e --- /dev/null +++ b/tests/arch/xilinx/mux.ys @@ -0,0 +1,45 @@ +read_verilog mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 + +select -assert-none t:LUT3 %% t:* %D + + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D + + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 2 t:LUT6 + +select -assert-none t:LUT3 t:LUT6 %% t:* %D + + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 5 t:LUT6 + +select -assert-none t:LUT6 %% t:* %D diff --git a/tests/arch/xilinx/pmgen_xilinx_srl.ys b/tests/arch/xilinx/pmgen_xilinx_srl.ys new file mode 100644 index 000000000..ea2f20487 --- /dev/null +++ b/tests/arch/xilinx/pmgen_xilinx_srl.ys @@ -0,0 +1,57 @@ +read_verilog -icells < run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/xilinx/shifter.v b/tests/arch/xilinx/shifter.v new file mode 100644 index 000000000..04ae49d83 --- /dev/null +++ b/tests/arch/xilinx/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys new file mode 100644 index 000000000..84e16f41e --- /dev/null +++ b/tests/arch/xilinx/shifter.ys @@ -0,0 +1,11 @@ +read_verilog shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:BUFG +select -assert-count 8 t:FDRE +select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/arch/xilinx/tribuf.v b/tests/arch/xilinx/tribuf.v new file mode 100644 index 000000000..c64468253 --- /dev/null +++ b/tests/arch/xilinx/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys new file mode 100644 index 000000000..c9cfb8546 --- /dev/null +++ b/tests/arch/xilinx/tribuf.ys @@ -0,0 +1,12 @@ +read_verilog tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 +select -assert-count 1 t:$_TBUF_ +select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/xilinx/xilinx_srl.v b/tests/arch/xilinx/xilinx_srl.v new file mode 100644 index 000000000..bc2a15ab2 --- /dev/null +++ b/tests/arch/xilinx/xilinx_srl.v @@ -0,0 +1,40 @@ +module xilinx_srl_static_test(input i, clk, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[3], shift1[3]}; +endmodule + +module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); +reg head = 1'b0; +reg [3:0] shift1 = 4'b0000; +reg [3:0] shift2 = 4'b0000; + +always @(posedge clk) begin + head <= i; + shift1 <= {shift1[2:0], head}; + shift2 <= {shift2[2:0], head}; +end + +assign q = {shift2[l2], shift1[l1]}; +endmodule + +module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); +parameter CLKPOL = 1; +parameter ENPOL = 1; +parameter DEPTH = 1; +parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; +reg [DEPTH-1:0] r = INIT; +wire clk = C ^ CLKPOL; +always @(posedge C) + if (E) + r <= { r[DEPTH-2:0], D }; +assign Q = r[L]; +endmodule diff --git a/tests/arch/xilinx/xilinx_srl.ys b/tests/arch/xilinx/xilinx_srl.ys new file mode 100644 index 000000000..b8df0e55a --- /dev/null +++ b/tests/arch/xilinx/xilinx_srl.ys @@ -0,0 +1,67 @@ +read_verilog xilinx_srl.v +design -save read + +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_static_test +prep +design -save gold + +techmap +xilinx_srl -fixed +opt + +# stat +# show -width +select -assert-count 1 t:$_DFF_P_ +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +dump gate +sat -verify -prove-asserts -show-ports -seq 5 miter + +#design -load gold +#stat + +#design -load gate +#stat + +########## + +design -load read +design -copy-to model $__XILINX_SHREG_ +hierarchy -top xilinx_srl_variable_test +prep +design -save gold + +xilinx_srl -variable +opt + +#stat +# show -width +# write_verilog -noexpr -norename +select -assert-count 1 t:$dff +select -assert-count 1 t:$dff r:WIDTH=1 %i +select -assert-count 2 t:$__XILINX_SHREG_ + +design -stash gate + +design -import gold -as gold +design -import gate -as gate +design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ +prep + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +sat -verify -prove-asserts -show-ports -seq 5 miter + +# design -load gold +# stat + +# design -load gate +# stat diff --git a/tests/ecp5/.gitignore b/tests/ecp5/.gitignore deleted file mode 100644 index 1d329c933..000000000 --- a/tests/ecp5/.gitignore +++ /dev/null @@ -1,2 +0,0 @@ -*.log -/run-test.mk diff --git a/tests/ecp5/add_sub.v b/tests/ecp5/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ecp5/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ecp5/add_sub.ys b/tests/ecp5/add_sub.ys deleted file mode 100644 index ee72d732f..000000000 --- a/tests/ecp5/add_sub.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-none t:LUT4 %% t:* %D - diff --git a/tests/ecp5/adffs.v b/tests/ecp5/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/ecp5/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/ecp5/adffs.ys b/tests/ecp5/adffs.ys deleted file mode 100644 index c6780e565..000000000 --- a/tests/ecp5/adffs.ys +++ /dev/null @@ -1,40 +0,0 @@ -read_verilog adffs.v -design -save read - -hierarchy -top adff -proc -equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd adff # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-none t:TRELLIS_FF %% t:* %D - -design -load read -hierarchy -top adffn -proc -equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd adffn # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-count 1 t:LUT4 -select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D - -design -load read -hierarchy -top dffs -proc -equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffs # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-count 1 t:LUT4 -select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D - -design -load read -hierarchy -top ndffnr -proc -equiv_opt -async2sync -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd ndffnr # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-count 1 t:LUT4 -select -assert-none t:TRELLIS_FF t:LUT4 %% t:* %D diff --git a/tests/ecp5/counter.v b/tests/ecp5/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/ecp5/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/ecp5/counter.ys b/tests/ecp5/counter.ys deleted file mode 100644 index 8ef70778f..000000000 --- a/tests/ecp5/counter.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog counter.v -hierarchy -top top -proc -flatten -equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 4 t:CCU2C -select -assert-count 8 t:TRELLIS_FF -select -assert-none t:CCU2C t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/dffs.v b/tests/ecp5/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/ecp5/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/ecp5/dffs.ys b/tests/ecp5/dffs.ys deleted file mode 100644 index a4f45d2fb..000000000 --- a/tests/ecp5/dffs.ys +++ /dev/null @@ -1,19 +0,0 @@ -read_verilog dffs.v -design -save read - -hierarchy -top dff -proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-none t:TRELLIS_FF %% t:* %D - -design -load read -hierarchy -top dffe -proc -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module -select -assert-count 1 t:TRELLIS_FF -select -assert-none t:TRELLIS_FF %% t:* %D \ No newline at end of file diff --git a/tests/ecp5/dpram.v b/tests/ecp5/dpram.v deleted file mode 100644 index 3ea4c1f27..000000000 --- a/tests/ecp5/dpram.v +++ /dev/null @@ -1,23 +0,0 @@ -/* -Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. -*/ -module top (din, write_en, waddr, wclk, raddr, rclk, dout); -parameter addr_width = 8; -parameter data_width = 8; -input [addr_width-1:0] waddr, raddr; -input [data_width-1:0] din; -input write_en, wclk, rclk; -output [data_width-1:0] dout; -reg [data_width-1:0] dout; -reg [data_width-1:0] mem [(1< run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ecp5/shifter.v b/tests/ecp5/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/ecp5/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/ecp5/shifter.ys b/tests/ecp5/shifter.ys deleted file mode 100644 index e1901e1a8..000000000 --- a/tests/ecp5/shifter.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 8 t:TRELLIS_FF -select -assert-none t:TRELLIS_FF %% t:* %D diff --git a/tests/ecp5/tribuf.v b/tests/ecp5/tribuf.v deleted file mode 100644 index 90dd314e4..000000000 --- a/tests/ecp5/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule diff --git a/tests/ecp5/tribuf.ys b/tests/ecp5/tribuf.ys deleted file mode 100644 index a6e9c9598..000000000 --- a/tests/ecp5/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top tristate -proc -flatten -equiv_opt -assert -map +/ecp5/cells_sim.v -map +/simcells.v synth_ecp5 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/efinix/.gitignore b/tests/efinix/.gitignore deleted file mode 100644 index b48f808a1..000000000 --- a/tests/efinix/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -/*.log -/*.out -/run-test.mk diff --git a/tests/efinix/add_sub.v b/tests/efinix/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/efinix/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/efinix/add_sub.ys b/tests/efinix/add_sub.ys deleted file mode 100644 index 8bd28c68e..000000000 --- a/tests/efinix/add_sub.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 10 t:EFX_ADD -select -assert-count 4 t:EFX_LUT4 -select -assert-none t:EFX_ADD t:EFX_LUT4 %% t:* %D - diff --git a/tests/efinix/adffs.v b/tests/efinix/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/efinix/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/efinix/adffs.ys b/tests/efinix/adffs.ys deleted file mode 100644 index 1069c6c5c..000000000 --- a/tests/efinix/adffs.ys +++ /dev/null @@ -1,50 +0,0 @@ -read_verilog adffs.v -design -save read - -hierarchy -top adff -proc -equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd adff # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE - -select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D - - -design -load read -hierarchy -top adffn -proc -equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd adffn # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE - -select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D - - -design -load read -hierarchy -top dffs -proc -equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffs # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D - - -design -load read -hierarchy -top ndffnr -proc -equiv_opt -async2sync -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd ndffnr # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/counter.v b/tests/efinix/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/efinix/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/efinix/counter.ys b/tests/efinix/counter.ys deleted file mode 100644 index 82e61d39b..000000000 --- a/tests/efinix/counter.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog counter.v -hierarchy -top top -proc -flatten -equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 8 t:EFX_FF -select -assert-count 9 t:EFX_ADD -select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_ADD %% t:* %D diff --git a/tests/efinix/dffs.v b/tests/efinix/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/efinix/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/efinix/dffs.ys b/tests/efinix/dffs.ys deleted file mode 100644 index cdd288233..000000000 --- a/tests/efinix/dffs.ys +++ /dev/null @@ -1,24 +0,0 @@ -read_verilog dffs.v -design -save read - -hierarchy -top dff -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dff # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE - -select -assert-none t:EFX_FF t:EFX_GBUFCE %% t:* %D - -design -load read -hierarchy -top dffe -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd dffe # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_FF -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_FF t:EFX_GBUFCE t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/fsm.v b/tests/efinix/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/efinix/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/efinix/fsm.ys b/tests/efinix/fsm.ys deleted file mode 100644 index 2ec75215d..000000000 --- a/tests/efinix/fsm.ys +++ /dev/null @@ -1,14 +0,0 @@ -read_verilog fsm.v -hierarchy -top fsm -proc -flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd fsm # Constrain all select calls below inside the top module - -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 6 t:EFX_FF -select -assert-count 15 t:EFX_LUT4 -select -assert-none t:EFX_GBUFCE t:EFX_FF t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/latches.v b/tests/efinix/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/efinix/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/efinix/latches.ys b/tests/efinix/latches.ys deleted file mode 100644 index 899d024ce..000000000 --- a/tests/efinix/latches.ys +++ /dev/null @@ -1,33 +0,0 @@ -read_verilog latches.v -design -save read - -hierarchy -top latchp -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix -cd latchp # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - - -design -load read -hierarchy -top latchn -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix -cd latchn # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - - -design -load read -hierarchy -top latchsr -proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_efinix -cd latchsr # Constrain all select calls below inside the top module -select -assert-count 2 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/logic.v b/tests/efinix/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/efinix/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys deleted file mode 100644 index fdedb337b..000000000 --- a/tests/efinix/logic.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog logic.v -hierarchy -top top -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 9 t:EFX_LUT4 -select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/memory.v b/tests/efinix/memory.v deleted file mode 100644 index 5634d6507..000000000 --- a/tests/efinix/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [8:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/efinix/memory.ys b/tests/efinix/memory.ys deleted file mode 100644 index fe24b0a9b..000000000 --- a/tests/efinix/memory.ys +++ /dev/null @@ -1,18 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -#ERROR: Called with -verify and proof did fail! -#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter -sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 1 t:EFX_RAM_5K -select -assert-none t:EFX_GBUFCE t:EFX_RAM_5K %% t:* %D diff --git a/tests/efinix/mux.v b/tests/efinix/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/efinix/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/efinix/mux.ys b/tests/efinix/mux.ys deleted file mode 100644 index 71a9681de..000000000 --- a/tests/efinix/mux.ys +++ /dev/null @@ -1,41 +0,0 @@ -read_verilog mux.v -design -save read - -hierarchy -top mux2 -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux2 # Constrain all select calls below inside the top module -select -assert-count 1 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - -design -load read -hierarchy -top mux4 -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - -design -load read -hierarchy -top mux8 -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D - -design -load read -hierarchy -top mux16 -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux16 # Constrain all select calls below inside the top module -select -assert-count 12 t:EFX_LUT4 - -select -assert-none t:EFX_LUT4 %% t:* %D diff --git a/tests/efinix/run-test.sh b/tests/efinix/run-test.sh deleted file mode 100755 index 46716f9a0..000000000 --- a/tests/efinix/run-test.sh +++ /dev/null @@ -1,20 +0,0 @@ -#!/usr/bin/env bash -set -e -{ -echo "all::" -for x in *.ys; do - echo "all:: run-$x" - echo "run-$x:" - echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" -done -for s in *.sh; do - if [ "$s" != "run-test.sh" ]; then - echo "all:: run-$s" - echo "run-$s:" - echo " @echo 'Running $s..'" - echo " @bash $s" - fi -done -} > run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/efinix/shifter.v b/tests/efinix/shifter.v deleted file mode 100644 index ce2c81dd2..000000000 --- a/tests/efinix/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out << 1; - out[7] <= in; - end - -endmodule diff --git a/tests/efinix/shifter.ys b/tests/efinix/shifter.ys deleted file mode 100644 index 1a6b5565c..000000000 --- a/tests/efinix/shifter.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:EFX_GBUFCE -select -assert-count 8 t:EFX_FF -select -assert-none t:EFX_GBUFCE t:EFX_FF %% t:* %D diff --git a/tests/efinix/tribuf.v b/tests/efinix/tribuf.v deleted file mode 100644 index c64468253..000000000 --- a/tests/efinix/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output reg o; - - always @(en or i) - o <= (en)? i : 1'bZ; -endmodule diff --git a/tests/efinix/tribuf.ys b/tests/efinix/tribuf.ys deleted file mode 100644 index 2e2ab9e65..000000000 --- a/tests/efinix/tribuf.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog tribuf.v -hierarchy -top tristate -proc -tribuf -flatten -synth -equiv_opt -assert -map +/efinix/cells_sim.v -map +/simcells.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -#Internal cell type used. Need support it. -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/ice40/.gitignore b/tests/ice40/.gitignore deleted file mode 100644 index 9a71dca69..000000000 --- a/tests/ice40/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -*.log -/run-test.mk -+*_synth.v -+*_testbench diff --git a/tests/ice40/add_sub.v b/tests/ice40/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/ice40/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/ice40/add_sub.ys b/tests/ice40/add_sub.ys deleted file mode 100644 index 4a998d98d..000000000 --- a/tests/ice40/add_sub.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog add_sub.v -hierarchy -top top -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 11 t:SB_LUT4 -select -assert-count 6 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D - diff --git a/tests/ice40/adffs.v b/tests/ice40/adffs.v deleted file mode 100644 index 09dc36001..000000000 --- a/tests/ice40/adffs.v +++ /dev/null @@ -1,87 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre ) - if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/ice40/adffs.ys b/tests/ice40/adffs.ys deleted file mode 100644 index 548060b66..000000000 --- a/tests/ice40/adffs.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog adffs.v -proc -flatten -equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFFNS -select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFS -select -assert-count 2 t:SB_LUT4 -select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/alu.v b/tests/ice40/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/ice40/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/ice40/alu.ys b/tests/ice40/alu.ys deleted file mode 100644 index bd859efc4..000000000 --- a/tests/ice40/alu.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/ice40/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/ice40/counter.ys b/tests/ice40/counter.ys deleted file mode 100644 index c65c21622..000000000 --- a/tests/ice40/counter.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog counter.v -hierarchy -top top -proc -flatten -equiv_opt -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 6 t:SB_CARRY -select -assert-count 8 t:SB_DFFR -select -assert-count 8 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFFR t:SB_LUT4 %% t:* %D diff --git a/tests/ice40/dffs.v b/tests/ice40/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/ice40/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/ice40/dffs.ys b/tests/ice40/dffs.ys deleted file mode 100644 index ee7f884b1..000000000 --- a/tests/ice40/dffs.ys +++ /dev/null @@ -1,10 +0,0 @@ -read_verilog dffs.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFF -select -assert-count 1 t:SB_DFFE -select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D diff --git a/tests/ice40/div_mod.v b/tests/ice40/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/ice40/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/ice40/div_mod.ys b/tests/ice40/div_mod.ys deleted file mode 100644 index 821d6c301..000000000 --- a/tests/ice40/div_mod.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 59 t:SB_LUT4 -select -assert-count 41 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D diff --git a/tests/ice40/dpram.v b/tests/ice40/dpram.v deleted file mode 100644 index 3ea4c1f27..000000000 --- a/tests/ice40/dpram.v +++ /dev/null @@ -1,23 +0,0 @@ -/* -Example from: https://www.latticesemi.com/-/media/LatticeSemi/Documents/UserManuals/EI/iCEcube201701UserGuide.ashx?document_id=52071 [p. 72]. -*/ -module top (din, write_en, waddr, wclk, raddr, rclk, dout); -parameter addr_width = 8; -parameter data_width = 8; -input [addr_width-1:0] waddr, raddr; -input [data_width-1:0] din; -input write_en, wclk, rclk; -output [data_width-1:0] dout; -reg [data_width-1:0] dout; -reg [data_width-1:0] mem [(1< run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/ice40/shifter.v b/tests/ice40/shifter.v deleted file mode 100644 index c55632552..000000000 --- a/tests/ice40/shifter.v +++ /dev/null @@ -1,22 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin -`ifndef BUG - out <= out >> 1; - out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif - end - -endmodule diff --git a/tests/ice40/shifter.ys b/tests/ice40/shifter.ys deleted file mode 100644 index 47d95d298..000000000 --- a/tests/ice40/shifter.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 8 t:SB_DFF -select -assert-none t:SB_DFF %% t:* %D diff --git a/tests/ice40/tribuf.v b/tests/ice40/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/ice40/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys deleted file mode 100644 index d1e1b3108..000000000 --- a/tests/ice40/tribuf.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog tribuf.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/ice40/wrapcarry.ys b/tests/ice40/wrapcarry.ys deleted file mode 100644 index 10c029e68..000000000 --- a/tests/ice40/wrapcarry.ys +++ /dev/null @@ -1,22 +0,0 @@ -read_verilog <= 2**(SIZEOUT-1)) | overflow_reg; - -// Output accumulation result -assign accum_out = overflow ? 2**(SIZEOUT-1)-1 : adder_out; - -endmodule diff --git a/tests/xilinx/macc.ys b/tests/xilinx/macc.ys deleted file mode 100644 index 6e884b35a..000000000 --- a/tests/xilinx/macc.ys +++ /dev/null @@ -1,31 +0,0 @@ -read_verilog macc.v -design -save read - -hierarchy -top macc -proc -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd macc # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:FDRE -select -assert-count 1 t:DSP48E1 -select -assert-none t:BUFG t:FDRE t:DSP48E1 %% t:* %D - -design -load read -hierarchy -top macc2 -proc -#equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx ### TODO -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 10 -show-inputs -show-outputs miter -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd macc2 # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:DSP48E1 -select -assert-count 1 t:FDRE -select -assert-count 1 t:LUT2 -select -assert-count 41 t:LUT3 -select -assert-none t:BUFG t:DSP48E1 t:FDRE t:LUT2 t:LUT3 %% t:* %D diff --git a/tests/xilinx/macc_tb.v b/tests/xilinx/macc_tb.v deleted file mode 100644 index 64aed05c4..000000000 --- a/tests/xilinx/macc_tb.v +++ /dev/null @@ -1,96 +0,0 @@ -`timescale 1ns / 1ps - -module testbench; - - parameter SIZEIN = 16, SIZEOUT = 40; - reg clk, ce, rst; - reg signed [SIZEIN-1:0] a, b; - output signed [SIZEOUT-1:0] REF_accum_out, accum_out; - output REF_overflow, overflow; - - integer errcount = 0; - - reg ERROR_FLAG = 0; - - task clkcycle; - begin - #5; - clk = ~clk; - #10; - clk = ~clk; - #2; - ERROR_FLAG = 0; - if (REF_accum_out !== accum_out) begin - $display("ERROR at %1t: REF_accum_out=%b UUT_accum_out=%b DIFF=%b", $time, REF_accum_out, accum_out, REF_accum_out ^ accum_out); - errcount = errcount + 1; - ERROR_FLAG = 1; - end - if (REF_overflow !== overflow) begin - $display("ERROR at %1t: REF_overflow=%b UUT_overflow=%b DIFF=%b", $time, REF_overflow, overflow, REF_overflow ^ overflow); - errcount = errcount + 1; - ERROR_FLAG = 1; - end - #3; - end - endtask - - initial begin - //$dumpfile("test_macc.vcd"); - //$dumpvars(0, testbench); - - #2; - clk = 1'b0; - ce = 1'b0; - a = 0; - b = 0; - - rst = 1'b1; - repeat (10) begin - #10; - clk = 1'b1; - #10; - clk = 1'b0; - #10; - clk = 1'b1; - #10; - clk = 1'b0; - end - rst = 1'b0; - - repeat (10000) begin - clkcycle; - ce = 1; //$urandom & $urandom; - //rst = $urandom & $urandom & $urandom & $urandom & $urandom & $urandom; - a = $urandom & ~(1 << (SIZEIN-1)); - b = $urandom & ~(1 << (SIZEIN-1)); - end - - if (errcount == 0) begin - $display("All tests passed."); - $finish; - end else begin - $display("Caught %1d errors.", errcount); - $stop; - end - end - - macc2 ref ( - .clk(clk), - .ce(ce), - .rst(rst), - .a(a), - .b(b), - .accum_out(REF_accum_out), - .overflow(REF_overflow) - ); - - macc2_uut uut ( - .clk(clk), - .ce(ce), - .rst(rst), - .a(a), - .b(b), - .accum_out(accum_out), - .overflow(overflow) - ); -endmodule diff --git a/tests/xilinx/memory.v b/tests/xilinx/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/xilinx/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/xilinx/memory.ys b/tests/xilinx/memory.ys deleted file mode 100644 index 5402513a2..000000000 --- a/tests/xilinx/memory.ys +++ /dev/null @@ -1,17 +0,0 @@ -read_verilog memory.v -hierarchy -top top -proc -memory -nomap -equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx -memory -opt -full - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter - -design -load postopt -cd top -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-count 8 t:RAM64X1D -select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D diff --git a/tests/xilinx/mul.v b/tests/xilinx/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/xilinx/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/xilinx/mul.ys b/tests/xilinx/mul.ys deleted file mode 100644 index 66a06efdc..000000000 --- a/tests/xilinx/mul.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog mul.v -hierarchy -top top -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:DSP48E1 -select -assert-none t:DSP48E1 %% t:* %D diff --git a/tests/xilinx/mul_unsigned.v b/tests/xilinx/mul_unsigned.v deleted file mode 100644 index e3713a642..000000000 --- a/tests/xilinx/mul_unsigned.v +++ /dev/null @@ -1,30 +0,0 @@ -/* -Example from: https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_1/ug901-vivado-synthesis.pdf [p. 89]. -*/ - -// Unsigned 16x24-bit Multiplier -// 1 latency stage on operands -// 3 latency stage after the multiplication -// File: multipliers2.v -// -module mul_unsigned (clk, A, B, RES); -parameter WIDTHA = /*16*/ 6; -parameter WIDTHB = /*24*/ 9; -input clk; -input [WIDTHA-1:0] A; -input [WIDTHB-1:0] B; -output [WIDTHA+WIDTHB-1:0] RES; -reg [WIDTHA-1:0] rA; -reg [WIDTHB-1:0] rB; -reg [WIDTHA+WIDTHB-1:0] M [3:0]; -integer i; -always @(posedge clk) - begin - rA <= A; - rB <= B; - M[0] <= rA * rB; - for (i = 0; i < 3; i = i+1) - M[i+1] <= M[i]; - end -assign RES = M[3]; -endmodule diff --git a/tests/xilinx/mul_unsigned.ys b/tests/xilinx/mul_unsigned.ys deleted file mode 100644 index 62495b90c..000000000 --- a/tests/xilinx/mul_unsigned.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog mul_unsigned.v -hierarchy -top mul_unsigned -proc - -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mul_unsigned # Constrain all select calls below inside the top module -select -assert-count 1 t:BUFG -select -assert-count 1 t:DSP48E1 -select -assert-count 30 t:FDRE -select -assert-none t:DSP48E1 t:FDRE t:BUFG %% t:* %D diff --git a/tests/xilinx/mux.v b/tests/xilinx/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/xilinx/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/xilinx/mux.ys b/tests/xilinx/mux.ys deleted file mode 100644 index 420dece4e..000000000 --- a/tests/xilinx/mux.ys +++ /dev/null @@ -1,45 +0,0 @@ -read_verilog mux.v -design -save read - -hierarchy -top mux2 -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux2 # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT3 - -select -assert-none t:LUT3 %% t:* %D - - -design -load read -hierarchy -top mux4 -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux4 # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT6 - -select -assert-none t:LUT6 %% t:* %D - - -design -load read -hierarchy -top mux8 -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux8 # Constrain all select calls below inside the top module -select -assert-count 1 t:LUT3 -select -assert-count 2 t:LUT6 - -select -assert-none t:LUT3 t:LUT6 %% t:* %D - - -design -load read -hierarchy -top mux16 -proc -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd mux16 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT6 - -select -assert-none t:LUT6 %% t:* %D diff --git a/tests/xilinx/pmgen_xilinx_srl.ys b/tests/xilinx/pmgen_xilinx_srl.ys deleted file mode 100644 index ea2f20487..000000000 --- a/tests/xilinx/pmgen_xilinx_srl.ys +++ /dev/null @@ -1,57 +0,0 @@ -read_verilog -icells < run-test.mk -exec ${MAKE:-make} -f run-test.mk diff --git a/tests/xilinx/shifter.v b/tests/xilinx/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/xilinx/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/xilinx/shifter.ys b/tests/xilinx/shifter.ys deleted file mode 100644 index 84e16f41e..000000000 --- a/tests/xilinx/shifter.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog shifter.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 1 t:BUFG -select -assert-count 8 t:FDRE -select -assert-none t:BUFG t:FDRE %% t:* %D diff --git a/tests/xilinx/tribuf.v b/tests/xilinx/tribuf.v deleted file mode 100644 index c64468253..000000000 --- a/tests/xilinx/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output reg o; - - always @(en or i) - o <= (en)? i : 1'bZ; -endmodule diff --git a/tests/xilinx/tribuf.ys b/tests/xilinx/tribuf.ys deleted file mode 100644 index c9cfb8546..000000000 --- a/tests/xilinx/tribuf.ys +++ /dev/null @@ -1,12 +0,0 @@ -read_verilog tribuf.v -hierarchy -top tristate -proc -tribuf -flatten -synth -equiv_opt -assert -map +/xilinx/cells_sim.v -map +/simcells.v synth_xilinx # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd tristate # Constrain all select calls below inside the top module -# TODO :: Tristate logic not yet supported; see https://github.com/YosysHQ/yosys/issues/1225 -select -assert-count 1 t:$_TBUF_ -select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/xilinx/xilinx_srl.v b/tests/xilinx/xilinx_srl.v deleted file mode 100644 index bc2a15ab2..000000000 --- a/tests/xilinx/xilinx_srl.v +++ /dev/null @@ -1,40 +0,0 @@ -module xilinx_srl_static_test(input i, clk, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[3], shift1[3]}; -endmodule - -module xilinx_srl_variable_test(input i, clk, input [1:0] l1, l2, output [1:0] q); -reg head = 1'b0; -reg [3:0] shift1 = 4'b0000; -reg [3:0] shift2 = 4'b0000; - -always @(posedge clk) begin - head <= i; - shift1 <= {shift1[2:0], head}; - shift2 <= {shift2[2:0], head}; -end - -assign q = {shift2[l2], shift1[l1]}; -endmodule - -module $__XILINX_SHREG_(input C, D, E, input [1:0] L, output Q); -parameter CLKPOL = 1; -parameter ENPOL = 1; -parameter DEPTH = 1; -parameter [DEPTH-1:0] INIT = {DEPTH{1'b0}}; -reg [DEPTH-1:0] r = INIT; -wire clk = C ^ CLKPOL; -always @(posedge C) - if (E) - r <= { r[DEPTH-2:0], D }; -assign Q = r[L]; -endmodule diff --git a/tests/xilinx/xilinx_srl.ys b/tests/xilinx/xilinx_srl.ys deleted file mode 100644 index b8df0e55a..000000000 --- a/tests/xilinx/xilinx_srl.ys +++ /dev/null @@ -1,67 +0,0 @@ -read_verilog xilinx_srl.v -design -save read - -design -copy-to model $__XILINX_SHREG_ -hierarchy -top xilinx_srl_static_test -prep -design -save gold - -techmap -xilinx_srl -fixed -opt - -# stat -# show -width -select -assert-count 1 t:$_DFF_P_ -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -dump gate -sat -verify -prove-asserts -show-ports -seq 5 miter - -#design -load gold -#stat - -#design -load gate -#stat - -########## - -design -load read -design -copy-to model $__XILINX_SHREG_ -hierarchy -top xilinx_srl_variable_test -prep -design -save gold - -xilinx_srl -variable -opt - -#stat -# show -width -# write_verilog -noexpr -norename -select -assert-count 1 t:$dff -select -assert-count 1 t:$dff r:WIDTH=1 %i -select -assert-count 2 t:$__XILINX_SHREG_ - -design -stash gate - -design -import gold -as gold -design -import gate -as gate -design -copy-from model -as $__XILINX_SHREG_ \$__XILINX_SHREG_ -prep - -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -verify -prove-asserts -show-ports -seq 5 miter - -# design -load gold -# stat - -# design -load gate -# stat -- cgit v1.2.3 From 56f94826753c1f26c9026493a40ecef14806d779 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:12:03 +0200 Subject: Fix path to yosys --- tests/arch/anlogic/run-test.sh | 2 +- tests/arch/ecp5/run-test.sh | 2 +- tests/arch/efinix/run-test.sh | 2 +- tests/arch/ice40/run-test.sh | 2 +- tests/arch/xilinx/run-test.sh | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/tests/arch/anlogic/run-test.sh b/tests/arch/anlogic/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/anlogic/run-test.sh +++ b/tests/arch/anlogic/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/arch/ecp5/run-test.sh b/tests/arch/ecp5/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/ecp5/run-test.sh +++ b/tests/arch/ecp5/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/arch/efinix/run-test.sh b/tests/arch/efinix/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/efinix/run-test.sh +++ b/tests/arch/efinix/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/arch/ice40/run-test.sh b/tests/arch/ice40/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/ice40/run-test.sh +++ b/tests/arch/ice40/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then diff --git a/tests/arch/xilinx/run-test.sh b/tests/arch/xilinx/run-test.sh index 46716f9a0..bf19b887d 100755 --- a/tests/arch/xilinx/run-test.sh +++ b/tests/arch/xilinx/run-test.sh @@ -6,7 +6,7 @@ for x in *.ys; do echo "all:: run-$x" echo "run-$x:" echo " @echo 'Running $x..'" - echo " @../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" done for s in *.sh; do if [ "$s" != "run-test.sh" ]; then -- cgit v1.2.3 From ab98f2dccf52a1bba396fe313ea0670603dc45ca Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 11:18:53 +0200 Subject: fix yosys path --- tests/arch/xilinx/macc.sh | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 86e4c2bb6..2272679ee 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,3 +1,3 @@ -../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v -iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../techlibs/xilinx/cells_sim.v +../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" macc.v -o macc_uut.v +iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc -- cgit v1.2.3 From 5603595e5c0efd2afc9ba810e6e5992e5d81d44c Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:19:59 +0200 Subject: Share common tests --- tests/arch/anlogic/add_sub.v | 13 ------ tests/arch/anlogic/add_sub.ys | 2 +- tests/arch/anlogic/counter.v | 17 ------- tests/arch/anlogic/counter.ys | 2 +- tests/arch/anlogic/dffs.v | 15 ------- tests/arch/anlogic/dffs.ys | 2 +- tests/arch/anlogic/fsm.v | 55 ----------------------- tests/arch/anlogic/fsm.ys | 2 +- tests/arch/anlogic/latches.v | 24 ---------- tests/arch/anlogic/latches.ys | 2 +- tests/arch/anlogic/logic.ys | 11 +++++ tests/arch/anlogic/mux.v | 65 --------------------------- tests/arch/anlogic/mux.ys | 2 +- tests/arch/anlogic/shifter.v | 16 ------- tests/arch/anlogic/shifter.ys | 2 +- tests/arch/anlogic/tribuf.v | 8 ---- tests/arch/anlogic/tribuf.ys | 2 +- tests/arch/common/add_sub.v | 13 ++++++ tests/arch/common/adffs.v | 47 ++++++++++++++++++++ tests/arch/common/counter.v | 17 +++++++ tests/arch/common/dffs.v | 15 +++++++ tests/arch/common/fsm.v | 55 +++++++++++++++++++++++ tests/arch/common/latches.v | 24 ++++++++++ tests/arch/common/logic.v | 18 ++++++++ tests/arch/common/mul.v | 11 +++++ tests/arch/common/mux.v | 65 +++++++++++++++++++++++++++ tests/arch/common/shifter.v | 16 +++++++ tests/arch/common/tribuf.v | 8 ++++ tests/arch/ecp5/add_sub.v | 13 ------ tests/arch/ecp5/add_sub.ys | 2 +- tests/arch/ecp5/adffs.v | 47 -------------------- tests/arch/ecp5/adffs.ys | 2 +- tests/arch/ecp5/counter.v | 17 ------- tests/arch/ecp5/counter.ys | 2 +- tests/arch/ecp5/dffs.v | 15 ------- tests/arch/ecp5/dffs.ys | 2 +- tests/arch/ecp5/fsm.v | 55 ----------------------- tests/arch/ecp5/fsm.ys | 2 +- tests/arch/ecp5/latches.v | 24 ---------- tests/arch/ecp5/latches.ys | 3 +- tests/arch/ecp5/logic.v | 18 -------- tests/arch/ecp5/logic.ys | 2 +- tests/arch/ecp5/mul.v | 11 ----- tests/arch/ecp5/mul.ys | 2 +- tests/arch/ecp5/mux.v | 66 ---------------------------- tests/arch/ecp5/mux.ys | 2 +- tests/arch/ecp5/shifter.v | 16 ------- tests/arch/ecp5/shifter.ys | 2 +- tests/arch/ecp5/tribuf.v | 8 ---- tests/arch/ecp5/tribuf.ys | 2 +- tests/arch/efinix/add_sub.v | 13 ------ tests/arch/efinix/add_sub.ys | 2 +- tests/arch/efinix/adffs.v | 47 -------------------- tests/arch/efinix/adffs.ys | 2 +- tests/arch/efinix/counter.v | 17 ------- tests/arch/efinix/counter.ys | 2 +- tests/arch/efinix/dffs.v | 15 ------- tests/arch/efinix/dffs.ys | 2 +- tests/arch/efinix/fsm.v | 55 ----------------------- tests/arch/efinix/fsm.ys | 2 +- tests/arch/efinix/latches.v | 24 ---------- tests/arch/efinix/latches.ys | 2 +- tests/arch/efinix/logic.v | 18 -------- tests/arch/efinix/logic.ys | 2 +- tests/arch/efinix/mux.v | 65 --------------------------- tests/arch/efinix/mux.ys | 2 +- tests/arch/efinix/shifter.v | 16 ------- tests/arch/efinix/shifter.ys | 2 +- tests/arch/efinix/tribuf.v | 8 ---- tests/arch/efinix/tribuf.ys | 2 +- tests/arch/ice40/add_sub.v | 13 ------ tests/arch/ice40/add_sub.ys | 2 +- tests/arch/ice40/adffs.v | 87 ------------------------------------ tests/arch/ice40/adffs.ys | 46 +++++++++++++++---- tests/arch/ice40/counter.v | 17 ------- tests/arch/ice40/counter.ys | 2 +- tests/arch/ice40/dffs.v | 37 ---------------- tests/arch/ice40/dffs.ys | 19 +++++--- tests/arch/ice40/fsm.v | 73 ------------------------------ tests/arch/ice40/fsm.ys | 6 +-- tests/arch/ice40/latches.v | 58 ------------------------ tests/arch/ice40/latches.ys | 33 +++++++++++--- tests/arch/ice40/logic.v | 18 -------- tests/arch/ice40/logic.ys | 2 +- tests/arch/ice40/mul.v | 11 ----- tests/arch/ice40/mul.ys | 2 +- tests/arch/ice40/mux.v | 100 ------------------------------------------ tests/arch/ice40/mux.ys | 40 +++++++++++++++-- tests/arch/ice40/shifter.v | 22 ---------- tests/arch/ice40/shifter.ys | 2 +- tests/arch/ice40/tribuf.v | 23 ---------- tests/arch/ice40/tribuf.ys | 8 ++-- tests/arch/xilinx/add_sub.v | 13 ------ tests/arch/xilinx/add_sub.ys | 2 +- tests/arch/xilinx/adffs.v | 47 -------------------- tests/arch/xilinx/adffs.ys | 2 +- tests/arch/xilinx/counter.v | 17 ------- tests/arch/xilinx/counter.ys | 2 +- tests/arch/xilinx/dffs.v | 15 ------- tests/arch/xilinx/dffs.ys | 2 +- tests/arch/xilinx/fsm.v | 55 ----------------------- tests/arch/xilinx/fsm.ys | 2 +- tests/arch/xilinx/latches.v | 24 ---------- tests/arch/xilinx/latches.ys | 2 +- tests/arch/xilinx/logic.v | 18 -------- tests/arch/xilinx/logic.ys | 2 +- tests/arch/xilinx/mul.v | 11 ----- tests/arch/xilinx/mul.ys | 2 +- tests/arch/xilinx/mux.v | 65 --------------------------- tests/arch/xilinx/mux.ys | 2 +- tests/arch/xilinx/shifter.v | 16 ------- tests/arch/xilinx/shifter.ys | 2 +- tests/arch/xilinx/tribuf.v | 8 ---- tests/arch/xilinx/tribuf.ys | 2 +- 114 files changed, 467 insertions(+), 1605 deletions(-) delete mode 100644 tests/arch/anlogic/add_sub.v delete mode 100644 tests/arch/anlogic/counter.v delete mode 100644 tests/arch/anlogic/dffs.v delete mode 100644 tests/arch/anlogic/fsm.v delete mode 100644 tests/arch/anlogic/latches.v create mode 100644 tests/arch/anlogic/logic.ys delete mode 100644 tests/arch/anlogic/mux.v delete mode 100644 tests/arch/anlogic/shifter.v delete mode 100644 tests/arch/anlogic/tribuf.v create mode 100644 tests/arch/common/add_sub.v create mode 100644 tests/arch/common/adffs.v create mode 100644 tests/arch/common/counter.v create mode 100644 tests/arch/common/dffs.v create mode 100644 tests/arch/common/fsm.v create mode 100644 tests/arch/common/latches.v create mode 100644 tests/arch/common/logic.v create mode 100644 tests/arch/common/mul.v create mode 100644 tests/arch/common/mux.v create mode 100644 tests/arch/common/shifter.v create mode 100644 tests/arch/common/tribuf.v delete mode 100644 tests/arch/ecp5/add_sub.v delete mode 100644 tests/arch/ecp5/adffs.v delete mode 100644 tests/arch/ecp5/counter.v delete mode 100644 tests/arch/ecp5/dffs.v delete mode 100644 tests/arch/ecp5/fsm.v delete mode 100644 tests/arch/ecp5/latches.v delete mode 100644 tests/arch/ecp5/logic.v delete mode 100644 tests/arch/ecp5/mul.v delete mode 100644 tests/arch/ecp5/mux.v delete mode 100644 tests/arch/ecp5/shifter.v delete mode 100644 tests/arch/ecp5/tribuf.v delete mode 100644 tests/arch/efinix/add_sub.v delete mode 100644 tests/arch/efinix/adffs.v delete mode 100644 tests/arch/efinix/counter.v delete mode 100644 tests/arch/efinix/dffs.v delete mode 100644 tests/arch/efinix/fsm.v delete mode 100644 tests/arch/efinix/latches.v delete mode 100644 tests/arch/efinix/logic.v delete mode 100644 tests/arch/efinix/mux.v delete mode 100644 tests/arch/efinix/shifter.v delete mode 100644 tests/arch/efinix/tribuf.v delete mode 100644 tests/arch/ice40/add_sub.v delete mode 100644 tests/arch/ice40/adffs.v delete mode 100644 tests/arch/ice40/counter.v delete mode 100644 tests/arch/ice40/dffs.v delete mode 100644 tests/arch/ice40/fsm.v delete mode 100644 tests/arch/ice40/latches.v delete mode 100644 tests/arch/ice40/logic.v delete mode 100644 tests/arch/ice40/mul.v delete mode 100644 tests/arch/ice40/mux.v delete mode 100644 tests/arch/ice40/shifter.v delete mode 100644 tests/arch/ice40/tribuf.v delete mode 100644 tests/arch/xilinx/add_sub.v delete mode 100644 tests/arch/xilinx/adffs.v delete mode 100644 tests/arch/xilinx/counter.v delete mode 100644 tests/arch/xilinx/dffs.v delete mode 100644 tests/arch/xilinx/fsm.v delete mode 100644 tests/arch/xilinx/latches.v delete mode 100644 tests/arch/xilinx/logic.v delete mode 100644 tests/arch/xilinx/mul.v delete mode 100644 tests/arch/xilinx/mux.v delete mode 100644 tests/arch/xilinx/shifter.v delete mode 100644 tests/arch/xilinx/tribuf.v diff --git a/tests/arch/anlogic/add_sub.v b/tests/arch/anlogic/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/anlogic/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/anlogic/add_sub.ys b/tests/arch/anlogic/add_sub.ys index b8b67cc46..5396ce7ec 100644 --- a/tests/arch/anlogic/add_sub.ys +++ b/tests/arch/anlogic/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check diff --git a/tests/arch/anlogic/counter.v b/tests/arch/anlogic/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/anlogic/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/anlogic/counter.ys b/tests/arch/anlogic/counter.ys index 036fdba46..d363ec24e 100644 --- a/tests/arch/anlogic/counter.ys +++ b/tests/arch/anlogic/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/anlogic/dffs.v b/tests/arch/anlogic/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/arch/anlogic/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/arch/anlogic/dffs.ys b/tests/arch/anlogic/dffs.ys index 9cbe5fce7..d3281ab89 100644 --- a/tests/arch/anlogic/dffs.ys +++ b/tests/arch/anlogic/dffs.ys @@ -1,4 +1,4 @@ -read_verilog dffs.v +read_verilog ../common/dffs.v design -save read hierarchy -top dff diff --git a/tests/arch/anlogic/fsm.v b/tests/arch/anlogic/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/arch/anlogic/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys index 452ef9251..f45951b13 100644 --- a/tests/arch/anlogic/fsm.ys +++ b/tests/arch/anlogic/fsm.ys @@ -1,4 +1,4 @@ -read_verilog fsm.v +read_verilog ../common/fsm.v hierarchy -top fsm proc #flatten diff --git a/tests/arch/anlogic/latches.v b/tests/arch/anlogic/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/arch/anlogic/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys index c00c7a25d..8d66f77b3 100644 --- a/tests/arch/anlogic/latches.ys +++ b/tests/arch/anlogic/latches.ys @@ -1,4 +1,4 @@ -read_verilog latches.v +read_verilog ../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/anlogic/logic.ys b/tests/arch/anlogic/logic.ys new file mode 100644 index 000000000..125ee5d0f --- /dev/null +++ b/tests/arch/anlogic/logic.ys @@ -0,0 +1,11 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:AL_MAP_LUT1 +select -assert-count 6 t:AL_MAP_LUT2 +select -assert-count 2 t:AL_MAP_LUT4 +select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D diff --git a/tests/arch/anlogic/mux.v b/tests/arch/anlogic/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/arch/anlogic/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys index 64ed2a2bd..3d5fe7c9a 100644 --- a/tests/arch/anlogic/mux.ys +++ b/tests/arch/anlogic/mux.ys @@ -1,4 +1,4 @@ -read_verilog mux.v +read_verilog ../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/anlogic/shifter.v b/tests/arch/anlogic/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/arch/anlogic/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/arch/anlogic/shifter.ys b/tests/arch/anlogic/shifter.ys index 5eaed30a3..12df44b2a 100644 --- a/tests/arch/anlogic/shifter.ys +++ b/tests/arch/anlogic/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/anlogic/tribuf.v b/tests/arch/anlogic/tribuf.v deleted file mode 100644 index 90dd314e4..000000000 --- a/tests/arch/anlogic/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule diff --git a/tests/arch/anlogic/tribuf.ys b/tests/arch/anlogic/tribuf.ys index 0eb1338ac..eaa073750 100644 --- a/tests/arch/anlogic/tribuf.ys +++ b/tests/arch/anlogic/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog tribuf.v +read_verilog ../common/tribuf.v hierarchy -top tristate proc flatten diff --git a/tests/arch/common/add_sub.v b/tests/arch/common/add_sub.v new file mode 100644 index 000000000..177c32e30 --- /dev/null +++ b/tests/arch/common/add_sub.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x + y; +assign B = x - y; + +endmodule diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v new file mode 100644 index 000000000..223b52d21 --- /dev/null +++ b/tests/arch/common/adffs.v @@ -0,0 +1,47 @@ +module adff + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module adffn + ( input d, clk, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule + +module dffs + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; +endmodule + +module ndffnr + ( input d, clk, pre, clr, output reg q ); + initial begin + q = 0; + end + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; +endmodule diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/arch/common/counter.v @@ -0,0 +1,17 @@ +module top ( +out, +clk, +reset +); + output [7:0] out; + input clk, reset; + reg [7:0] out; + + always @(posedge clk, posedge reset) + if (reset) begin + out <= 8'b0 ; + end else + out <= out + 1; + + +endmodule diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v new file mode 100644 index 000000000..3418787c9 --- /dev/null +++ b/tests/arch/common/dffs.v @@ -0,0 +1,15 @@ +module dff + ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; +endmodule + +module dffe + ( input d, clk, en, output reg q ); + initial begin + q = 0; + end + always @( posedge clk ) + if ( en ) + q <= d; +endmodule diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v new file mode 100644 index 000000000..368fbaace --- /dev/null +++ b/tests/arch/common/fsm.v @@ -0,0 +1,55 @@ + module fsm ( + clock, + reset, + req_0, + req_1, + gnt_0, + gnt_1 + ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; + + parameter SIZE = 3 ; + parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end + +endmodule diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v new file mode 100644 index 000000000..adb5d5319 --- /dev/null +++ b/tests/arch/common/latches.v @@ -0,0 +1,24 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v new file mode 100644 index 000000000..e5343cae0 --- /dev/null +++ b/tests/arch/common/logic.v @@ -0,0 +1,18 @@ +module top +( + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 + ); + + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; + +endmodule diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v new file mode 100644 index 000000000..d5b48b1d7 --- /dev/null +++ b/tests/arch/common/mul.v @@ -0,0 +1,11 @@ +module top +( + input [5:0] x, + input [5:0] y, + + output [11:0] A, + ); + +assign A = x * y; + +endmodule diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v new file mode 100644 index 000000000..27bc0bf0b --- /dev/null +++ b/tests/arch/common/mux.v @@ -0,0 +1,65 @@ +module mux2 (S,A,B,Y); + input S; + input A,B; + output reg Y; + + always @(*) + Y = (S)? B : A; +endmodule + +module mux4 ( S, D, Y ); + +input[1:0] S; +input[3:0] D; +output Y; + +reg Y; +wire[1:0] S; +wire[3:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase +end + +endmodule + +module mux8 ( S, D, Y ); + +input[2:0] S; +input[7:0] D; +output Y; + +reg Y; +wire[2:0] S; +wire[7:0] D; + +always @* +begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase +end + +endmodule + +module mux16 (D, S, Y); + input [15:0] D; + input [3:0] S; + output Y; + +assign Y = D[S]; + +endmodule diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v new file mode 100644 index 000000000..04ae49d83 --- /dev/null +++ b/tests/arch/common/shifter.v @@ -0,0 +1,16 @@ +module top ( +out, +clk, +in +); + output [7:0] out; + input signed clk, in; + reg signed [7:0] out = 0; + + always @(posedge clk) + begin + out <= out >> 1; + out[7] <= in; + end + +endmodule diff --git a/tests/arch/common/tribuf.v b/tests/arch/common/tribuf.v new file mode 100644 index 000000000..c64468253 --- /dev/null +++ b/tests/arch/common/tribuf.v @@ -0,0 +1,8 @@ +module tristate (en, i, o); + input en; + input i; + output reg o; + + always @(en or i) + o <= (en)? i : 1'bZ; +endmodule diff --git a/tests/arch/ecp5/add_sub.v b/tests/arch/ecp5/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/ecp5/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys index ee72d732f..d85ce792e 100644 --- a/tests/arch/ecp5/add_sub.ys +++ b/tests/arch/ecp5/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/arch/ecp5/adffs.v b/tests/arch/ecp5/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/arch/ecp5/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/arch/ecp5/adffs.ys b/tests/arch/ecp5/adffs.ys index c6780e565..01605df70 100644 --- a/tests/arch/ecp5/adffs.ys +++ b/tests/arch/ecp5/adffs.ys @@ -1,4 +1,4 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v design -save read hierarchy -top adff diff --git a/tests/arch/ecp5/counter.v b/tests/arch/ecp5/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/ecp5/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/ecp5/counter.ys b/tests/arch/ecp5/counter.ys index 8ef70778f..f9f60fbff 100644 --- a/tests/arch/ecp5/counter.ys +++ b/tests/arch/ecp5/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/ecp5/dffs.v b/tests/arch/ecp5/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/arch/ecp5/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/arch/ecp5/dffs.ys b/tests/arch/ecp5/dffs.ys index a4f45d2fb..be97972db 100644 --- a/tests/arch/ecp5/dffs.ys +++ b/tests/arch/ecp5/dffs.ys @@ -1,4 +1,4 @@ -read_verilog dffs.v +read_verilog ../common/dffs.v design -save read hierarchy -top dff diff --git a/tests/arch/ecp5/fsm.v b/tests/arch/ecp5/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/arch/ecp5/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/arch/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys index ded91e5f7..f834a4c6b 100644 --- a/tests/arch/ecp5/fsm.ys +++ b/tests/arch/ecp5/fsm.ys @@ -1,4 +1,4 @@ -read_verilog fsm.v +read_verilog ../common/fsm.v hierarchy -top fsm proc flatten diff --git a/tests/arch/ecp5/latches.v b/tests/arch/ecp5/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/arch/ecp5/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/arch/ecp5/latches.ys b/tests/arch/ecp5/latches.ys index fc15a6910..3d011d74f 100644 --- a/tests/arch/ecp5/latches.ys +++ b/tests/arch/ecp5/latches.ys @@ -1,5 +1,4 @@ - -read_verilog latches.v +read_verilog ../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/ecp5/logic.v b/tests/arch/ecp5/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/arch/ecp5/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/arch/ecp5/logic.ys b/tests/arch/ecp5/logic.ys index 4f113a130..3298b198f 100644 --- a/tests/arch/ecp5/logic.ys +++ b/tests/arch/ecp5/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check diff --git a/tests/arch/ecp5/mul.v b/tests/arch/ecp5/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/arch/ecp5/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/arch/ecp5/mul.ys b/tests/arch/ecp5/mul.ys index 0a91f892e..2105be52c 100644 --- a/tests/arch/ecp5/mul.ys +++ b/tests/arch/ecp5/mul.ys @@ -1,4 +1,4 @@ -read_verilog mul.v +read_verilog ../common/mul.v hierarchy -top top proc # Blocked by issue #1358 (Missing ECP5 simulation models) diff --git a/tests/arch/ecp5/mux.v b/tests/arch/ecp5/mux.v deleted file mode 100644 index 782424a9b..000000000 --- a/tests/arch/ecp5/mux.v +++ /dev/null @@ -1,66 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - diff --git a/tests/arch/ecp5/mux.ys b/tests/arch/ecp5/mux.ys index 8cfbd541b..92463aa32 100644 --- a/tests/arch/ecp5/mux.ys +++ b/tests/arch/ecp5/mux.ys @@ -1,4 +1,4 @@ -read_verilog mux.v +read_verilog ../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/ecp5/shifter.v b/tests/arch/ecp5/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/arch/ecp5/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/arch/ecp5/shifter.ys b/tests/arch/ecp5/shifter.ys index e1901e1a8..3f0079f4a 100644 --- a/tests/arch/ecp5/shifter.ys +++ b/tests/arch/ecp5/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/ecp5/tribuf.v b/tests/arch/ecp5/tribuf.v deleted file mode 100644 index 90dd314e4..000000000 --- a/tests/arch/ecp5/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule diff --git a/tests/arch/ecp5/tribuf.ys b/tests/arch/ecp5/tribuf.ys index a6e9c9598..0118705a2 100644 --- a/tests/arch/ecp5/tribuf.ys +++ b/tests/arch/ecp5/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog tribuf.v +read_verilog ../common/tribuf.v hierarchy -top tristate proc flatten diff --git a/tests/arch/efinix/add_sub.v b/tests/arch/efinix/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/efinix/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/efinix/add_sub.ys b/tests/arch/efinix/add_sub.ys index 8bd28c68e..20523c059 100644 --- a/tests/arch/efinix/add_sub.ys +++ b/tests/arch/efinix/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check diff --git a/tests/arch/efinix/adffs.v b/tests/arch/efinix/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/arch/efinix/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/arch/efinix/adffs.ys b/tests/arch/efinix/adffs.ys index 1069c6c5c..49dc7f256 100644 --- a/tests/arch/efinix/adffs.ys +++ b/tests/arch/efinix/adffs.ys @@ -1,4 +1,4 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v design -save read hierarchy -top adff diff --git a/tests/arch/efinix/counter.v b/tests/arch/efinix/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/efinix/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/efinix/counter.ys b/tests/arch/efinix/counter.ys index 82e61d39b..d20b8ae27 100644 --- a/tests/arch/efinix/counter.ys +++ b/tests/arch/efinix/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/efinix/dffs.v b/tests/arch/efinix/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/arch/efinix/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/arch/efinix/dffs.ys b/tests/arch/efinix/dffs.ys index cdd288233..af787ab67 100644 --- a/tests/arch/efinix/dffs.ys +++ b/tests/arch/efinix/dffs.ys @@ -1,4 +1,4 @@ -read_verilog dffs.v +read_verilog ../common/dffs.v design -save read hierarchy -top dff diff --git a/tests/arch/efinix/fsm.v b/tests/arch/efinix/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/arch/efinix/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys index 2ec75215d..a8ba70fdb 100644 --- a/tests/arch/efinix/fsm.ys +++ b/tests/arch/efinix/fsm.ys @@ -1,4 +1,4 @@ -read_verilog fsm.v +read_verilog ../common/fsm.v hierarchy -top fsm proc flatten diff --git a/tests/arch/efinix/latches.v b/tests/arch/efinix/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/arch/efinix/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/arch/efinix/latches.ys b/tests/arch/efinix/latches.ys index 899d024ce..1b1c00023 100644 --- a/tests/arch/efinix/latches.ys +++ b/tests/arch/efinix/latches.ys @@ -1,4 +1,4 @@ -read_verilog latches.v +read_verilog ../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/efinix/logic.v b/tests/arch/efinix/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/arch/efinix/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/arch/efinix/logic.ys b/tests/arch/efinix/logic.ys index fdedb337b..76e98e079 100644 --- a/tests/arch/efinix/logic.ys +++ b/tests/arch/efinix/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check diff --git a/tests/arch/efinix/mux.v b/tests/arch/efinix/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/arch/efinix/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/arch/efinix/mux.ys b/tests/arch/efinix/mux.ys index 71a9681de..b46f641e1 100644 --- a/tests/arch/efinix/mux.ys +++ b/tests/arch/efinix/mux.ys @@ -1,4 +1,4 @@ -read_verilog mux.v +read_verilog ../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/efinix/shifter.v b/tests/arch/efinix/shifter.v deleted file mode 100644 index ce2c81dd2..000000000 --- a/tests/arch/efinix/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out << 1; - out[7] <= in; - end - -endmodule diff --git a/tests/arch/efinix/shifter.ys b/tests/arch/efinix/shifter.ys index 1a6b5565c..54f71167f 100644 --- a/tests/arch/efinix/shifter.ys +++ b/tests/arch/efinix/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/efinix/tribuf.v b/tests/arch/efinix/tribuf.v deleted file mode 100644 index c64468253..000000000 --- a/tests/arch/efinix/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output reg o; - - always @(en or i) - o <= (en)? i : 1'bZ; -endmodule diff --git a/tests/arch/efinix/tribuf.ys b/tests/arch/efinix/tribuf.ys index 2e2ab9e65..47904f2d5 100644 --- a/tests/arch/efinix/tribuf.ys +++ b/tests/arch/efinix/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog tribuf.v +read_verilog ../common/tribuf.v hierarchy -top tristate proc tribuf diff --git a/tests/arch/ice40/add_sub.v b/tests/arch/ice40/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/ice40/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/ice40/add_sub.ys b/tests/arch/ice40/add_sub.ys index 4a998d98d..578ec0803 100644 --- a/tests/arch/ice40/add_sub.ys +++ b/tests/arch/ice40/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/adffs.v b/tests/arch/ice40/adffs.v deleted file mode 100644 index 09dc36001..000000000 --- a/tests/arch/ice40/adffs.v +++ /dev/null @@ -1,87 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge pre ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk, negedge pre ) - if ( !pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2,b3 -); - -dffs u_dffs ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b ) - ); - -ndffnr u_ndffnr ( - .clk (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b1 ) - ); - -adff u_adff ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b2 ) - ); - -adffn u_adffn ( - .clk (clk ), - .clr (clr), - .d (a ), - .q (b3 ) - ); - -endmodule diff --git a/tests/arch/ice40/adffs.ys b/tests/arch/ice40/adffs.ys index 548060b66..e5dbabb43 100644 --- a/tests/arch/ice40/adffs.ys +++ b/tests/arch/ice40/adffs.ys @@ -1,11 +1,39 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff proc -flatten -equiv_opt -multiclock -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 1 t:SB_DFFNS -select -assert-count 2 t:SB_DFFR -select -assert-count 1 t:SB_DFFS -select -assert-count 2 t:SB_LUT4 -select -assert-none t:SB_DFFNS t:SB_DFFR t:SB_DFFS t:SB_LUT4 %% t:* %D +cd adff # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFR +select -assert-none t:SB_DFFR %% t:* %D + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFR +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFR t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFSS +select -assert-none t:SB_DFFSS %% t:* %D + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_DFFNSR +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_DFFNSR t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/counter.v b/tests/arch/ice40/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/ice40/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/ice40/counter.ys b/tests/arch/ice40/counter.ys index c65c21622..f112eb97d 100644 --- a/tests/arch/ice40/counter.ys +++ b/tests/arch/ice40/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/ice40/dffs.v b/tests/arch/ice40/dffs.v deleted file mode 100644 index d97840c43..000000000 --- a/tests/arch/ice40/dffs.v +++ /dev/null @@ -1,37 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule - -module top ( -input clk, -input en, -input a, -output b,b1, -); - -dff u_dff ( - .clk (clk ), - .d (a ), - .q (b ) - ); - -dffe u_ndffe ( - .clk (clk ), - .en (en), - .d (a ), - .q (b1 ) - ); - -endmodule diff --git a/tests/arch/ice40/dffs.ys b/tests/arch/ice40/dffs.ys index ee7f884b1..b28a5a91f 100644 --- a/tests/arch/ice40/dffs.ys +++ b/tests/arch/ice40/dffs.ys @@ -1,10 +1,19 @@ -read_verilog dffs.v -hierarchy -top top +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff proc -flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd dff # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFF +select -assert-none t:SB_DFF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module select -assert-count 1 t:SB_DFFE -select -assert-none t:SB_DFF t:SB_DFFE %% t:* %D +select -assert-none t:SB_DFFE %% t:* %D \ No newline at end of file diff --git a/tests/arch/ice40/fsm.v b/tests/arch/ice40/fsm.v deleted file mode 100644 index 0605bd102..000000000 --- a/tests/arch/ice40/fsm.v +++ /dev/null @@ -1,73 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - - endmodule - - module top ( -input clk, -input rst, -input a, -input b, -output g0, -output g1 -); - -fsm u_fsm ( .clock(clk), - .reset(rst), - .req_0(a), - .req_1(b), - .gnt_0(g0), - .gnt_1(g1)); - -endmodule diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys index 4cc8629d6..5aacc6c73 100644 --- a/tests/arch/ice40/fsm.ys +++ b/tests/arch/ice40/fsm.ys @@ -1,10 +1,10 @@ -read_verilog fsm.v -hierarchy -top top +read_verilog ../common/fsm.v +hierarchy -top fsm proc flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd fsm # Constrain all select calls below inside the top module select -assert-count 2 t:SB_DFFESR select -assert-count 2 t:SB_DFFSR diff --git a/tests/arch/ice40/latches.v b/tests/arch/ice40/latches.v deleted file mode 100644 index 9dc43e4c2..000000000 --- a/tests/arch/ice40/latches.v +++ /dev/null @@ -1,58 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule - - -module top ( -input clk, -input clr, -input pre, -input a, -output b,b1,b2 -); - - -latchp u_latchp ( - .en (clk ), - .d (a ), - .q (b ) - ); - - -latchn u_latchn ( - .en (clk ), - .d (a ), - .q (b1 ) - ); - - -latchsr u_latchsr ( - .en (clk ), - .clr (clr), - .pre (pre), - .d (a ), - .q (b2 ) - ); - -endmodule diff --git a/tests/arch/ice40/latches.ys b/tests/arch/ice40/latches.ys index 708734e44..b06dd630b 100644 --- a/tests/arch/ice40/latches.ys +++ b/tests/arch/ice40/latches.ys @@ -1,12 +1,33 @@ -read_verilog latches.v +read_verilog ../common/latches.v +design -save read +hierarchy -top latchp proc -flatten # Can't run any sort of equivalence check because latches are blown to LUTs -#equiv_opt -async2sync -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +synth_ice40 +cd latchp # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + + +design -load read +hierarchy -top latchn +proc +# Can't run any sort of equivalence check because latches are blown to LUTs +synth_ice40 +cd latchn # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + -#design -load preopt +design -load read +hierarchy -top latchsr +proc +# Can't run any sort of equivalence check because latches are blown to LUTs synth_ice40 -cd top -select -assert-count 4 t:SB_LUT4 +cd latchsr # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/logic.v b/tests/arch/ice40/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/arch/ice40/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/arch/ice40/logic.ys b/tests/arch/ice40/logic.ys index fc5e5b1d8..7432f5b1f 100644 --- a/tests/arch/ice40/logic.ys +++ b/tests/arch/ice40/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/mul.v b/tests/arch/ice40/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/arch/ice40/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/arch/ice40/mul.ys b/tests/arch/ice40/mul.ys index 8a0822a84..9891b77d6 100644 --- a/tests/arch/ice40/mul.ys +++ b/tests/arch/ice40/mul.ys @@ -1,4 +1,4 @@ -read_verilog mul.v +read_verilog ../common/mul.v hierarchy -top top equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -dsp # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) diff --git a/tests/arch/ice40/mux.v b/tests/arch/ice40/mux.v deleted file mode 100644 index 0814b733e..000000000 --- a/tests/arch/ice40/mux.v +++ /dev/null @@ -1,100 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule - - -module top ( -input [3:0] S, -input [15:0] D, -output M2,M4,M8,M16 -); - -mux2 u_mux2 ( - .S (S[0]), - .A (D[0]), - .B (D[1]), - .Y (M2) - ); - - -mux4 u_mux4 ( - .S (S[1:0]), - .D (D[3:0]), - .Y (M4) - ); - -mux8 u_mux8 ( - .S (S[2:0]), - .D (D[7:0]), - .Y (M8) - ); - -mux16 u_mux16 ( - .S (S[3:0]), - .D (D[15:0]), - .Y (M16) - ); - -endmodule diff --git a/tests/arch/ice40/mux.ys b/tests/arch/ice40/mux.ys index 182b49499..99822391d 100644 --- a/tests/arch/ice40/mux.ys +++ b/tests/arch/ice40/mux.ys @@ -1,8 +1,40 @@ -read_verilog mux.v +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 proc -flatten equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 19 t:SB_LUT4 +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:SB_LUT4 + +select -assert-none t:SB_LUT4 %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 11 t:SB_LUT4 + select -assert-none t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/shifter.v b/tests/arch/ice40/shifter.v deleted file mode 100644 index c55632552..000000000 --- a/tests/arch/ice40/shifter.v +++ /dev/null @@ -1,22 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin -`ifndef BUG - out <= out >> 1; - out[7] <= in; -`else - - out <= out << 1; - out[7] <= in; -`endif - end - -endmodule diff --git a/tests/arch/ice40/shifter.ys b/tests/arch/ice40/shifter.ys index 47d95d298..08ea64f3d 100644 --- a/tests/arch/ice40/shifter.ys +++ b/tests/arch/ice40/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/ice40/tribuf.v b/tests/arch/ice40/tribuf.v deleted file mode 100644 index 870a02584..000000000 --- a/tests/arch/ice40/tribuf.v +++ /dev/null @@ -1,23 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output o; - - assign o = en ? i : 1'bz; - -endmodule - - -module top ( -input en, -input a, -output b -); - -tristate u_tri ( - .en (en ), - .i (a ), - .o (b ) - ); - -endmodule diff --git a/tests/arch/ice40/tribuf.ys b/tests/arch/ice40/tribuf.ys index d1e1b3108..10cded954 100644 --- a/tests/arch/ice40/tribuf.ys +++ b/tests/arch/ice40/tribuf.ys @@ -1,9 +1,11 @@ -read_verilog tribuf.v -hierarchy -top top +read_verilog ../common/tribuf.v +hierarchy -top tristate proc +tribuf flatten +synth equiv_opt -assert -map +/ice40/cells_sim.v -map +/simcells.v synth_ice40 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module +cd tristate # Constrain all select calls below inside the top module select -assert-count 1 t:$_TBUF_ select -assert-none t:$_TBUF_ %% t:* %D diff --git a/tests/arch/xilinx/add_sub.v b/tests/arch/xilinx/add_sub.v deleted file mode 100644 index 177c32e30..000000000 --- a/tests/arch/xilinx/add_sub.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; - -endmodule diff --git a/tests/arch/xilinx/add_sub.ys b/tests/arch/xilinx/add_sub.ys index f06e7fa01..9dbddce47 100644 --- a/tests/arch/xilinx/add_sub.ys +++ b/tests/arch/xilinx/add_sub.ys @@ -1,4 +1,4 @@ -read_verilog add_sub.v +read_verilog ../common/add_sub.v hierarchy -top top proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/arch/xilinx/adffs.v b/tests/arch/xilinx/adffs.v deleted file mode 100644 index 223b52d21..000000000 --- a/tests/arch/xilinx/adffs.v +++ /dev/null @@ -1,47 +0,0 @@ -module adff - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module adffn - ( input d, clk, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule - -module dffs - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; -endmodule - -module ndffnr - ( input d, clk, pre, clr, output reg q ); - initial begin - q = 0; - end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; -endmodule diff --git a/tests/arch/xilinx/adffs.ys b/tests/arch/xilinx/adffs.ys index 1923b9802..12c34415e 100644 --- a/tests/arch/xilinx/adffs.ys +++ b/tests/arch/xilinx/adffs.ys @@ -1,4 +1,4 @@ -read_verilog adffs.v +read_verilog ../common/adffs.v design -save read hierarchy -top adff diff --git a/tests/arch/xilinx/counter.v b/tests/arch/xilinx/counter.v deleted file mode 100644 index 52852f8ac..000000000 --- a/tests/arch/xilinx/counter.v +++ /dev/null @@ -1,17 +0,0 @@ -module top ( -out, -clk, -reset -); - output [7:0] out; - input clk, reset; - reg [7:0] out; - - always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - -endmodule diff --git a/tests/arch/xilinx/counter.ys b/tests/arch/xilinx/counter.ys index 459541656..57b645d19 100644 --- a/tests/arch/xilinx/counter.ys +++ b/tests/arch/xilinx/counter.ys @@ -1,4 +1,4 @@ -read_verilog counter.v +read_verilog ../common/counter.v hierarchy -top top proc flatten diff --git a/tests/arch/xilinx/dffs.v b/tests/arch/xilinx/dffs.v deleted file mode 100644 index 3418787c9..000000000 --- a/tests/arch/xilinx/dffs.v +++ /dev/null @@ -1,15 +0,0 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; -endmodule - -module dffe - ( input d, clk, en, output reg q ); - initial begin - q = 0; - end - always @( posedge clk ) - if ( en ) - q <= d; -endmodule diff --git a/tests/arch/xilinx/dffs.ys b/tests/arch/xilinx/dffs.ys index f1716dabb..0bba4858f 100644 --- a/tests/arch/xilinx/dffs.ys +++ b/tests/arch/xilinx/dffs.ys @@ -1,4 +1,4 @@ -read_verilog dffs.v +read_verilog ../common/dffs.v design -save read hierarchy -top dff diff --git a/tests/arch/xilinx/fsm.v b/tests/arch/xilinx/fsm.v deleted file mode 100644 index 368fbaace..000000000 --- a/tests/arch/xilinx/fsm.v +++ /dev/null @@ -1,55 +0,0 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; - - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; - - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end - -endmodule diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index a9e94c2c0..d2b481421 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -1,4 +1,4 @@ -read_verilog fsm.v +read_verilog ../common/fsm.v hierarchy -top fsm proc flatten diff --git a/tests/arch/xilinx/latches.v b/tests/arch/xilinx/latches.v deleted file mode 100644 index adb5d5319..000000000 --- a/tests/arch/xilinx/latches.v +++ /dev/null @@ -1,24 +0,0 @@ -module latchp - ( input d, clk, en, output reg q ); - always @* - if ( en ) - q <= d; -endmodule - -module latchn - ( input d, clk, en, output reg q ); - always @* - if ( !en ) - q <= d; -endmodule - -module latchsr - ( input d, clk, en, clr, pre, output reg q ); - always @* - if ( clr ) - q <= 1'b0; - else if ( pre ) - q <= 1'b1; - else if ( en ) - q <= d; -endmodule diff --git a/tests/arch/xilinx/latches.ys b/tests/arch/xilinx/latches.ys index 3eb550a42..fe7887e8d 100644 --- a/tests/arch/xilinx/latches.ys +++ b/tests/arch/xilinx/latches.ys @@ -1,4 +1,4 @@ -read_verilog latches.v +read_verilog ../common/latches.v design -save read hierarchy -top latchp diff --git a/tests/arch/xilinx/logic.v b/tests/arch/xilinx/logic.v deleted file mode 100644 index e5343cae0..000000000 --- a/tests/arch/xilinx/logic.v +++ /dev/null @@ -1,18 +0,0 @@ -module top -( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - -endmodule diff --git a/tests/arch/xilinx/logic.ys b/tests/arch/xilinx/logic.ys index 9ae5993aa..c0f6da302 100644 --- a/tests/arch/xilinx/logic.ys +++ b/tests/arch/xilinx/logic.ys @@ -1,4 +1,4 @@ -read_verilog logic.v +read_verilog ../common/logic.v hierarchy -top top proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/arch/xilinx/mul.v b/tests/arch/xilinx/mul.v deleted file mode 100644 index d5b48b1d7..000000000 --- a/tests/arch/xilinx/mul.v +++ /dev/null @@ -1,11 +0,0 @@ -module top -( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; - -endmodule diff --git a/tests/arch/xilinx/mul.ys b/tests/arch/xilinx/mul.ys index 66a06efdc..d76814966 100644 --- a/tests/arch/xilinx/mul.ys +++ b/tests/arch/xilinx/mul.ys @@ -1,4 +1,4 @@ -read_verilog mul.v +read_verilog ../common/mul.v hierarchy -top top proc equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check diff --git a/tests/arch/xilinx/mux.v b/tests/arch/xilinx/mux.v deleted file mode 100644 index 27bc0bf0b..000000000 --- a/tests/arch/xilinx/mux.v +++ /dev/null @@ -1,65 +0,0 @@ -module mux2 (S,A,B,Y); - input S; - input A,B; - output reg Y; - - always @(*) - Y = (S)? B : A; -endmodule - -module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - -endmodule - -module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - -endmodule - -module mux16 (D, S, Y); - input [15:0] D; - input [3:0] S; - output Y; - -assign Y = D[S]; - -endmodule diff --git a/tests/arch/xilinx/mux.ys b/tests/arch/xilinx/mux.ys index 420dece4e..821d0fab7 100644 --- a/tests/arch/xilinx/mux.ys +++ b/tests/arch/xilinx/mux.ys @@ -1,4 +1,4 @@ -read_verilog mux.v +read_verilog ../common/mux.v design -save read hierarchy -top mux2 diff --git a/tests/arch/xilinx/shifter.v b/tests/arch/xilinx/shifter.v deleted file mode 100644 index 04ae49d83..000000000 --- a/tests/arch/xilinx/shifter.v +++ /dev/null @@ -1,16 +0,0 @@ -module top ( -out, -clk, -in -); - output [7:0] out; - input signed clk, in; - reg signed [7:0] out = 0; - - always @(posedge clk) - begin - out <= out >> 1; - out[7] <= in; - end - -endmodule diff --git a/tests/arch/xilinx/shifter.ys b/tests/arch/xilinx/shifter.ys index 84e16f41e..455437f18 100644 --- a/tests/arch/xilinx/shifter.ys +++ b/tests/arch/xilinx/shifter.ys @@ -1,4 +1,4 @@ -read_verilog shifter.v +read_verilog ../common/shifter.v hierarchy -top top proc flatten diff --git a/tests/arch/xilinx/tribuf.v b/tests/arch/xilinx/tribuf.v deleted file mode 100644 index c64468253..000000000 --- a/tests/arch/xilinx/tribuf.v +++ /dev/null @@ -1,8 +0,0 @@ -module tristate (en, i, o); - input en; - input i; - output reg o; - - always @(en or i) - o <= (en)? i : 1'bZ; -endmodule diff --git a/tests/arch/xilinx/tribuf.ys b/tests/arch/xilinx/tribuf.ys index c9cfb8546..4697703ca 100644 --- a/tests/arch/xilinx/tribuf.ys +++ b/tests/arch/xilinx/tribuf.ys @@ -1,4 +1,4 @@ -read_verilog tribuf.v +read_verilog ../common/tribuf.v hierarchy -top tristate proc tribuf -- cgit v1.2.3 From 477702b8c91bb7780ac80b25c8ad659cd40b445d Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:20:35 +0200 Subject: Remove not needed tests --- tests/arch/ice40/alu.v | 19 ------------------- tests/arch/ice40/alu.ys | 11 ----------- tests/arch/ice40/div_mod.v | 13 ------------- tests/arch/ice40/div_mod.ys | 9 --------- 4 files changed, 52 deletions(-) delete mode 100644 tests/arch/ice40/alu.v delete mode 100644 tests/arch/ice40/alu.ys delete mode 100644 tests/arch/ice40/div_mod.v delete mode 100644 tests/arch/ice40/div_mod.ys diff --git a/tests/arch/ice40/alu.v b/tests/arch/ice40/alu.v deleted file mode 100644 index f82cc2e21..000000000 --- a/tests/arch/ice40/alu.v +++ /dev/null @@ -1,19 +0,0 @@ -module top ( - input clock, - input [31:0] dinA, dinB, - input [2:0] opcode, - output reg [31:0] dout -); - always @(posedge clock) begin - case (opcode) - 0: dout <= dinA + dinB; - 1: dout <= dinA - dinB; - 2: dout <= dinA >> dinB; - 3: dout <= $signed(dinA) >>> dinB; - 4: dout <= dinA << dinB; - 5: dout <= dinA & dinB; - 6: dout <= dinA | dinB; - 7: dout <= dinA ^ dinB; - endcase - end -endmodule diff --git a/tests/arch/ice40/alu.ys b/tests/arch/ice40/alu.ys deleted file mode 100644 index bd859efc4..000000000 --- a/tests/arch/ice40/alu.ys +++ /dev/null @@ -1,11 +0,0 @@ -read_verilog alu.v -hierarchy -top top -proc -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 62 t:SB_CARRY -select -assert-count 32 t:SB_DFF -select -assert-count 655 t:SB_LUT4 -select -assert-none t:SB_CARRY t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/ice40/div_mod.v b/tests/arch/ice40/div_mod.v deleted file mode 100644 index 64a36707d..000000000 --- a/tests/arch/ice40/div_mod.v +++ /dev/null @@ -1,13 +0,0 @@ -module top -( - input [3:0] x, - input [3:0] y, - - output [3:0] A, - output [3:0] B - ); - -assign A = x % y; -assign B = x / y; - -endmodule diff --git a/tests/arch/ice40/div_mod.ys b/tests/arch/ice40/div_mod.ys deleted file mode 100644 index 821d6c301..000000000 --- a/tests/arch/ice40/div_mod.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog div_mod.v -hierarchy -top top -flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module -select -assert-count 59 t:SB_LUT4 -select -assert-count 41 t:SB_CARRY -select -assert-none t:SB_LUT4 t:SB_CARRY %% t:* %D -- cgit v1.2.3 From 12383f37b2e1d72784e01db0431efc8882f25430 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:33:35 +0200 Subject: Common memory test now shared --- tests/arch/anlogic/memory.v | 21 --------------------- tests/arch/anlogic/memory.ys | 2 +- tests/arch/common/memory.v | 21 +++++++++++++++++++++ tests/arch/ecp5/memory.v | 21 --------------------- tests/arch/ecp5/memory.ys | 2 +- tests/arch/efinix/memory.v | 21 --------------------- tests/arch/efinix/memory.ys | 2 +- tests/arch/ice40/memory.v | 21 --------------------- tests/arch/ice40/memory.ys | 2 +- tests/arch/xilinx/memory.v | 21 --------------------- tests/arch/xilinx/memory.ys | 2 +- 11 files changed, 26 insertions(+), 110 deletions(-) delete mode 100644 tests/arch/anlogic/memory.v create mode 100644 tests/arch/common/memory.v delete mode 100644 tests/arch/ecp5/memory.v delete mode 100644 tests/arch/efinix/memory.v delete mode 100644 tests/arch/ice40/memory.v delete mode 100644 tests/arch/xilinx/memory.v diff --git a/tests/arch/anlogic/memory.v b/tests/arch/anlogic/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/anlogic/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/anlogic/memory.ys b/tests/arch/anlogic/memory.ys index 8c0ce844e..87b93c2fe 100644 --- a/tests/arch/anlogic/memory.ys +++ b/tests/arch/anlogic/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/common/memory.v b/tests/arch/common/memory.v new file mode 100644 index 000000000..cb7753f7b --- /dev/null +++ b/tests/arch/common/memory.v @@ -0,0 +1,21 @@ +module top +( + input [7:0] data_a, + input [6:1] addr_a, + input we_a, clk, + output reg [7:0] q_a +); + // Declare the RAM variable + reg [7:0] ram[63:0]; + + // Port A + always @ (posedge clk) + begin + if (we_a) + begin + ram[addr_a] <= data_a; + q_a <= data_a; + end + q_a <= ram[addr_a]; + end +endmodule diff --git a/tests/arch/ecp5/memory.v b/tests/arch/ecp5/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/ecp5/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ecp5/memory.ys b/tests/arch/ecp5/memory.ys index 9b475f122..c82b7b405 100644 --- a/tests/arch/ecp5/memory.ys +++ b/tests/arch/ecp5/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/efinix/memory.v b/tests/arch/efinix/memory.v deleted file mode 100644 index 5634d6507..000000000 --- a/tests/arch/efinix/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [8:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/efinix/memory.ys b/tests/arch/efinix/memory.ys index fe24b0a9b..6f6acdcde 100644 --- a/tests/arch/efinix/memory.ys +++ b/tests/arch/efinix/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/ice40/memory.v b/tests/arch/ice40/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/ice40/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/ice40/memory.ys b/tests/arch/ice40/memory.ys index a66afbae6..c356e67fb 100644 --- a/tests/arch/ice40/memory.ys +++ b/tests/arch/ice40/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap diff --git a/tests/arch/xilinx/memory.v b/tests/arch/xilinx/memory.v deleted file mode 100644 index cb7753f7b..000000000 --- a/tests/arch/xilinx/memory.v +++ /dev/null @@ -1,21 +0,0 @@ -module top -( - input [7:0] data_a, - input [6:1] addr_a, - input we_a, clk, - output reg [7:0] q_a -); - // Declare the RAM variable - reg [7:0] ram[63:0]; - - // Port A - always @ (posedge clk) - begin - if (we_a) - begin - ram[addr_a] <= data_a; - q_a <= data_a; - end - q_a <= ram[addr_a]; - end -endmodule diff --git a/tests/arch/xilinx/memory.ys b/tests/arch/xilinx/memory.ys index 5402513a2..da1ed0e49 100644 --- a/tests/arch/xilinx/memory.ys +++ b/tests/arch/xilinx/memory.ys @@ -1,4 +1,4 @@ -read_verilog memory.v +read_verilog ../common/memory.v hierarchy -top top proc memory -nomap -- cgit v1.2.3 From 9bd9db56c8ef8ca413f97086fd53609c50df343b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 12:50:24 +0200 Subject: Unify verilog style --- tests/arch/common/add_sub.v | 15 ++++--- tests/arch/common/adffs.v | 54 ++++++++++++------------- tests/arch/common/counter.v | 16 +++----- tests/arch/common/dffs.v | 18 ++++----- tests/arch/common/fsm.v | 98 ++++++++++++++++++++++----------------------- tests/arch/common/latches.v | 9 ++--- tests/arch/common/logic.v | 28 ++++++------- tests/arch/common/mul.v | 12 +++--- tests/arch/common/mux.v | 83 ++++++++++++++++++-------------------- tests/arch/common/shifter.v | 9 +---- tests/arch/common/tribuf.v | 6 +-- 11 files changed, 157 insertions(+), 191 deletions(-) diff --git a/tests/arch/common/add_sub.v b/tests/arch/common/add_sub.v index 177c32e30..77e5f5745 100644 --- a/tests/arch/common/add_sub.v +++ b/tests/arch/common/add_sub.v @@ -1,13 +1,12 @@ module top ( - input [3:0] x, - input [3:0] y, + input [3:0] x, + input [3:0] y, - output [3:0] A, - output [3:0] B - ); - -assign A = x + y; -assign B = x - y; + output [3:0] A, + output [3:0] B +); + assign A = x + y; + assign B = x - y; endmodule diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v index 223b52d21..576bd81a6 100644 --- a/tests/arch/common/adffs.v +++ b/tests/arch/common/adffs.v @@ -1,47 +1,43 @@ -module adff - ( input d, clk, clr, output reg q ); +module adff( input d, clk, clr, output reg q ); initial begin - q = 0; + q = 0; end - always @( posedge clk, posedge clr ) - if ( clr ) - q <= 1'b0; - else - q <= d; + always @( posedge clk, posedge clr ) + if ( clr ) + q <= 1'b0; + else + q <= d; endmodule -module adffn - ( input d, clk, clr, output reg q ); +module adffn( input d, clk, clr, output reg q ); initial begin q = 0; end - always @( posedge clk, negedge clr ) - if ( !clr ) - q <= 1'b0; - else - q <= d; + always @( posedge clk, negedge clr ) + if ( !clr ) + q <= 1'b0; + else + q <= d; endmodule -module dffs - ( input d, clk, pre, clr, output reg q ); +module dffs( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( posedge clk ) - if ( pre ) - q <= 1'b1; - else - q <= d; + always @( posedge clk ) + if ( pre ) + q <= 1'b1; + else + q <= d; endmodule -module ndffnr - ( input d, clk, pre, clr, output reg q ); +module ndffnr( input d, clk, pre, clr, output reg q ); initial begin q = 0; end - always @( negedge clk ) - if ( !clr ) - q <= 1'b0; - else - q <= d; + always @( negedge clk ) + if ( !clr ) + q <= 1'b0; + else + q <= d; endmodule diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 52852f8ac..97604d3d8 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -1,17 +1,11 @@ -module top ( -out, -clk, -reset -); +module top ( out, clk, reset ); output [7:0] out; input clk, reset; reg [7:0] out; always @(posedge clk, posedge reset) - if (reset) begin - out <= 8'b0 ; - end else - out <= out + 1; - - + if (reset) + out <= 8'b0; + end + out <= out + 1; endmodule diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v index 3418787c9..636252d16 100644 --- a/tests/arch/common/dffs.v +++ b/tests/arch/common/dffs.v @@ -1,15 +1,13 @@ -module dff - ( input d, clk, output reg q ); - always @( posedge clk ) - q <= d; +module dff ( input d, clk, output reg q ); + always @( posedge clk ) + q <= d; endmodule -module dffe - ( input d, clk, en, output reg q ); +module dffe( input d, clk, en, output reg q ); initial begin - q = 0; + q = 0; end - always @( posedge clk ) - if ( en ) - q <= d; + always @( posedge clk ) + if ( en ) + q <= d; endmodule diff --git a/tests/arch/common/fsm.v b/tests/arch/common/fsm.v index 368fbaace..9d3fbb64a 100644 --- a/tests/arch/common/fsm.v +++ b/tests/arch/common/fsm.v @@ -1,55 +1,51 @@ - module fsm ( - clock, - reset, - req_0, - req_1, - gnt_0, - gnt_1 - ); - input clock,reset,req_0,req_1; - output gnt_0,gnt_1; - wire clock,reset,req_0,req_1; - reg gnt_0,gnt_1; + module fsm ( clock, reset, req_0, req_1, gnt_0, gnt_1 ); + input clock,reset,req_0,req_1; + output gnt_0,gnt_1; + wire clock,reset,req_0,req_1; + reg gnt_0,gnt_1; - parameter SIZE = 3 ; - parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ; + parameter SIZE = 3; + parameter IDLE = 3'b001; + parameter GNT0 = 3'b010; + parameter GNT1 = 3'b100; + parameter GNT2 = 3'b101; - reg [SIZE-1:0] state; - reg [SIZE-1:0] next_state; - - always @ (posedge clock) - begin : FSM - if (reset == 1'b1) begin - state <= #1 IDLE; - gnt_0 <= 0; - gnt_1 <= 0; - end else - case(state) - IDLE : if (req_0 == 1'b1) begin - state <= #1 GNT0; - gnt_0 <= 1; - end else if (req_1 == 1'b1) begin - gnt_1 <= 1; - state <= #1 GNT0; - end else begin - state <= #1 IDLE; - end - GNT0 : if (req_0 == 1'b1) begin - state <= #1 GNT0; - end else begin - gnt_0 <= 0; - state <= #1 IDLE; - end - GNT1 : if (req_1 == 1'b1) begin - state <= #1 GNT2; - gnt_1 <= req_0; - end - GNT2 : if (req_0 == 1'b1) begin - state <= #1 GNT1; - gnt_1 <= req_1; - end - default : state <= #1 IDLE; - endcase - end + reg [SIZE-1:0] state; + reg [SIZE-1:0] next_state; + always @ (posedge clock) + begin : FSM + if (reset == 1'b1) begin + state <= #1 IDLE; + gnt_0 <= 0; + gnt_1 <= 0; + end + else + case(state) + IDLE : if (req_0 == 1'b1) begin + state <= #1 GNT0; + gnt_0 <= 1; + end else if (req_1 == 1'b1) begin + gnt_1 <= 1; + state <= #1 GNT0; + end else begin + state <= #1 IDLE; + end + GNT0 : if (req_0 == 1'b1) begin + state <= #1 GNT0; + end else begin + gnt_0 <= 0; + state <= #1 IDLE; + end + GNT1 : if (req_1 == 1'b1) begin + state <= #1 GNT2; + gnt_1 <= req_0; + end + GNT2 : if (req_0 == 1'b1) begin + state <= #1 GNT1; + gnt_1 <= req_1; + end + default : state <= #1 IDLE; + endcase + end endmodule diff --git a/tests/arch/common/latches.v b/tests/arch/common/latches.v index adb5d5319..60b757103 100644 --- a/tests/arch/common/latches.v +++ b/tests/arch/common/latches.v @@ -1,19 +1,16 @@ -module latchp - ( input d, clk, en, output reg q ); +module latchp ( input d, clk, en, output reg q ); always @* if ( en ) q <= d; endmodule -module latchn - ( input d, clk, en, output reg q ); +module latchn ( input d, clk, en, output reg q ); always @* if ( !en ) q <= d; endmodule -module latchsr - ( input d, clk, en, clr, pre, output reg q ); +module latchsr ( input d, clk, en, clr, pre, output reg q ); always @* if ( clr ) q <= 1'b0; diff --git a/tests/arch/common/logic.v b/tests/arch/common/logic.v index e5343cae0..c17899fa0 100644 --- a/tests/arch/common/logic.v +++ b/tests/arch/common/logic.v @@ -1,18 +1,16 @@ module top ( - input [0:7] in, - output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 - ); - - assign B1 = in[0] & in[1]; - assign B2 = in[0] | in[1]; - assign B3 = in[0] ~& in[1]; - assign B4 = in[0] ~| in[1]; - assign B5 = in[0] ^ in[1]; - assign B6 = in[0] ~^ in[1]; - assign B7 = ~in[0]; - assign B8 = in[0]; - assign B9 = in[0:1] && in [2:3]; - assign B10 = in[0:1] || in [2:3]; - + input [0:7] in, + output B1,B2,B3,B4,B5,B6,B7,B8,B9,B10 +); + assign B1 = in[0] & in[1]; + assign B2 = in[0] | in[1]; + assign B3 = in[0] ~& in[1]; + assign B4 = in[0] ~| in[1]; + assign B5 = in[0] ^ in[1]; + assign B6 = in[0] ~^ in[1]; + assign B7 = ~in[0]; + assign B8 = in[0]; + assign B9 = in[0:1] && in [2:3]; + assign B10 = in[0:1] || in [2:3]; endmodule diff --git a/tests/arch/common/mul.v b/tests/arch/common/mul.v index d5b48b1d7..437a91cfc 100644 --- a/tests/arch/common/mul.v +++ b/tests/arch/common/mul.v @@ -1,11 +1,9 @@ module top ( - input [5:0] x, - input [5:0] y, - - output [11:0] A, - ); - -assign A = x * y; + input [5:0] x, + input [5:0] y, + output [11:0] A, +); + assign A = x * y; endmodule diff --git a/tests/arch/common/mux.v b/tests/arch/common/mux.v index 27bc0bf0b..71c1ac7f2 100644 --- a/tests/arch/common/mux.v +++ b/tests/arch/common/mux.v @@ -8,51 +8,47 @@ module mux2 (S,A,B,Y); endmodule module mux4 ( S, D, Y ); - -input[1:0] S; -input[3:0] D; -output Y; - -reg Y; -wire[1:0] S; -wire[3:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - endcase -end - + input[1:0] S; + input[3:0] D; + output Y; + + reg Y; + wire[1:0] S; + wire[3:0] D; + + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + endcase + end endmodule module mux8 ( S, D, Y ); - -input[2:0] S; -input[7:0] D; -output Y; - -reg Y; -wire[2:0] S; -wire[7:0] D; - -always @* -begin - case( S ) - 0 : Y = D[0]; - 1 : Y = D[1]; - 2 : Y = D[2]; - 3 : Y = D[3]; - 4 : Y = D[4]; - 5 : Y = D[5]; - 6 : Y = D[6]; - 7 : Y = D[7]; - endcase -end - + input[2:0] S; + input[7:0] D; + output Y; + + reg Y; + wire[2:0] S; + wire[7:0] D; + + always @* + begin + case( S ) + 0 : Y = D[0]; + 1 : Y = D[1]; + 2 : Y = D[2]; + 3 : Y = D[3]; + 4 : Y = D[4]; + 5 : Y = D[5]; + 6 : Y = D[6]; + 7 : Y = D[7]; + endcase + end endmodule module mux16 (D, S, Y); @@ -60,6 +56,5 @@ module mux16 (D, S, Y); input [3:0] S; output Y; -assign Y = D[S]; - + assign Y = D[S]; endmodule diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v index 04ae49d83..cace3b588 100644 --- a/tests/arch/common/shifter.v +++ b/tests/arch/common/shifter.v @@ -1,8 +1,4 @@ -module top ( -out, -clk, -in -); +module top(out, clk, in); output [7:0] out; input signed clk, in; reg signed [7:0] out = 0; @@ -11,6 +7,5 @@ in begin out <= out >> 1; out[7] <= in; - end - + end endmodule diff --git a/tests/arch/common/tribuf.v b/tests/arch/common/tribuf.v index c64468253..e1d701611 100644 --- a/tests/arch/common/tribuf.v +++ b/tests/arch/common/tribuf.v @@ -1,8 +1,8 @@ -module tristate (en, i, o); +module tristate(en, i, o); input en; input i; output reg o; - + always @(en or i) - o <= (en)? i : 1'bZ; + o <= (en)? i : 1'bZ; endmodule -- cgit v1.2.3 From 190b40341abd73ab5edf0e6740b6526e9575253b Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 18 Oct 2019 13:15:36 +0200 Subject: fixed error --- tests/arch/common/counter.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tests/arch/common/counter.v b/tests/arch/common/counter.v index 97604d3d8..9746fd701 100644 --- a/tests/arch/common/counter.v +++ b/tests/arch/common/counter.v @@ -6,6 +6,6 @@ module top ( out, clk, reset ); always @(posedge clk, posedge reset) if (reset) out <= 8'b0; - end + else out <= out + 1; endmodule -- cgit v1.2.3 From 82f60ba938749ab20694f9070f1046e393f16f3c Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Sat, 19 Oct 2019 14:04:52 +0800 Subject: Makefile: don't assume python is called `python3` On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross --- Makefile | 2 +- passes/pmgen/Makefile.inc | 4 ++-- techlibs/common/Makefile.inc | 4 ++-- techlibs/ecp5/Makefile.inc | 4 ++-- techlibs/ice40/Makefile.inc | 2 +- techlibs/xilinx/Makefile.inc | 2 +- 6 files changed, 9 insertions(+), 9 deletions(-) diff --git a/Makefile b/Makefile index a24f19b6a..845a97b50 100644 --- a/Makefile +++ b/Makefile @@ -147,9 +147,9 @@ $(info $(subst $$--$$,$(newline),$(shell sed 's,^,[Makefile.conf] ,; s,$$,$$--$$ include Makefile.conf endif +PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi) ifeq ($(ENABLE_PYOSYS),1) PYTHON_VERSION_TESTCODE := "import sys;t='{v[0]}.{v[1]}'.format(v=list(sys.version_info[:2]));print(t)" -PYTHON_EXECUTABLE := $(shell if python3 -c ""; then echo "python3"; else echo "python"; fi) PYTHON_VERSION := $(shell $(PYTHON_EXECUTABLE) -c ""$(PYTHON_VERSION_TESTCODE)"") PYTHON_MAJOR_VERSION := $(shell echo $(PYTHON_VERSION) | cut -f1 -d.) PYTHON_PREFIX := $(shell $(PYTHON_EXECUTABLE)-config --prefix) diff --git a/passes/pmgen/Makefile.inc b/passes/pmgen/Makefile.inc index 366c37943..145d2ebf9 100644 --- a/passes/pmgen/Makefile.inc +++ b/passes/pmgen/Makefile.inc @@ -1,5 +1,5 @@ %_pm.h: passes/pmgen/pmgen.py %.pmg - $(P) mkdir -p passes/pmgen && python3 $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) + $(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p $(subst _pm.h,,$(notdir $@)) $(filter-out $<,$^) # -------------------------------------- @@ -38,7 +38,7 @@ PEEPOPT_PATTERN += passes/pmgen/peepopt_muldiv.pmg PEEPOPT_PATTERN += passes/pmgen/peepopt_dffmux.pmg passes/pmgen/peepopt_pm.h: passes/pmgen/pmgen.py $(PEEPOPT_PATTERN) - $(P) mkdir -p passes/pmgen && python3 $< -o $@ -p peepopt $(filter-out $<,$^) + $(P) mkdir -p passes/pmgen && $(PYTHON_EXECUTABLE) $< -o $@ -p peepopt $(filter-out $<,$^) # -------------------------------------- diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index 6c0a4fe66..a42f63128 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -9,12 +9,12 @@ GENFILES += techlibs/common/simcells_help.inc techlibs/common/simlib_help.inc: techlibs/common/cellhelp.py techlibs/common/simlib.v $(Q) mkdir -p techlibs/common - $(P) python3 $^ > $@.new + $(P) $(PYTHON_EXECUTABLE) $^ > $@.new $(Q) mv $@.new $@ techlibs/common/simcells_help.inc: techlibs/common/cellhelp.py techlibs/common/simcells.v $(Q) mkdir -p techlibs/common - $(P) python3 $^ > $@.new + $(P) $(PYTHON_EXECUTABLE) $^ > $@.new $(Q) mv $@.new $@ kernel/register.o: techlibs/common/simlib_help.inc techlibs/common/simcells_help.inc diff --git a/techlibs/ecp5/Makefile.inc b/techlibs/ecp5/Makefile.inc index 5832d07ee..46463f510 100644 --- a/techlibs/ecp5/Makefile.inc +++ b/techlibs/ecp5/Makefile.inc @@ -27,12 +27,12 @@ EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk techlibs/ecp5/brams_init.mk: techlibs/ecp5/brams_init.py $(Q) mkdir -p techlibs/ecp5 - $(P) python3 $< + $(P) $(PYTHON_EXECUTABLE) $< $(Q) touch $@ techlibs/ecp5/brams_connect.mk: techlibs/ecp5/brams_connect.py $(Q) mkdir -p techlibs/ecp5 - $(P) python3 $< + $(P) $(PYTHON_EXECUTABLE) $< $(Q) touch $@ diff --git a/techlibs/ice40/Makefile.inc b/techlibs/ice40/Makefile.inc index 3c33fcb06..31478e80e 100644 --- a/techlibs/ice40/Makefile.inc +++ b/techlibs/ice40/Makefile.inc @@ -14,7 +14,7 @@ EXTRA_OBJS += techlibs/ice40/brams_init.mk techlibs/ice40/brams_init.mk: techlibs/ice40/brams_init.py $(Q) mkdir -p techlibs/ice40 - $(P) python3 $< + $(P) $(PYTHON_EXECUTABLE) $< $(Q) touch techlibs/ice40/brams_init.mk techlibs/ice40/brams_init1.vh: techlibs/ice40/brams_init.mk diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 0ae67d9e7..1e59f0a1b 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -13,7 +13,7 @@ EXTRA_OBJS += techlibs/xilinx/brams_init.mk techlibs/xilinx/brams_init.mk: techlibs/xilinx/brams_init.py $(Q) mkdir -p techlibs/xilinx - $(P) python3 $< + $(P) $(PYTHON_EXECUTABLE) $< $(Q) touch $@ techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk -- cgit v1.2.3 From fa989e59e5a37d804d8a82050e022b8f4b7070d8 Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 20 Oct 2019 10:30:41 +0100 Subject: ecp5: Pass -nomfs to abc9 Fixes #1459 Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index a79dee31f..800a8ce22 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -314,9 +314,9 @@ struct SynthEcp5Pass : public ScriptPass if (abc9) { run("read_verilog -icells -lib +/ecp5/abc9_model.v"); if (nowidelut) - run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200"); + run("abc9 -lut +/ecp5/abc9_5g_nowide.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); else - run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200"); + run("abc9 -lut +/ecp5/abc9_5g.lut -box +/ecp5/abc9_5g.box -W 200 -nomfs"); run("techmap -map +/ecp5/abc9_unmap.v"); } else { if (nowidelut) -- cgit v1.2.3 From af7bdd598e017b0e8887d893c901ae93935d20b2 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 21 Oct 2019 12:00:27 +0200 Subject: use ADDSUB ALU mode to remove inverters --- techlibs/gowin/arith_map.v | 6 ++-- techlibs/gowin/cells_sim.v | 78 +++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 77 insertions(+), 7 deletions(-) diff --git a/techlibs/gowin/arith_map.v b/techlibs/gowin/arith_map.v index af805b254..b6f9e8c38 100644 --- a/techlibs/gowin/arith_map.v +++ b/techlibs/gowin/arith_map.v @@ -40,15 +40,15 @@ module _80_gw1n_alu(A, B, CI, BI, X, Y, CO); \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); wire [Y_WIDTH-1:0] AA = A_buf; - wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH-1:0] BB = B_buf; wire [Y_WIDTH-1:0] C = {CO, CI}; genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin:slice - ALU #(.ALU_MODE(0)) + ALU #(.ALU_MODE(2)) // ADDSUB I3 ? add : sub alu(.I0(AA[i]), .I1(BB[i]), - .I3(1'b0), + .I3(~BI), .CIN(C[i]), .COUT(CO[i]), .SUM(Y[i]) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index de0cfa9f3..a392f5580 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -166,10 +166,80 @@ module GSR (input GSRI); wire GSRO = GSRI; endmodule -module ALU (input I0, input I1, input I3, input CIN, output COUT, output SUM); - parameter [3:0] ALU_MODE = 0; // default 0 = ADD - assign {COUT, SUM} = CIN + I1 + I0; -endmodule // alu +module ALU (SUM, COUT, I0, I1, I3, CIN); + +input I0; +input I1; +input I3; +input CIN; +output SUM; +output COUT; + +parameter ADD = 0; +parameter SUB = 1; +parameter ADDSUB = 2; +parameter NE = 3; +parameter GE = 4; +parameter LE = 5; +parameter CUP = 6; +parameter CDN = 7; +parameter CUPCDN = 8; +parameter MULT = 9; + +parameter ALU_MODE = 0; + +reg S, C; + +assign SUM = S ^ CIN; +assign COUT = S? CIN : C; + +always @(I0, I1, I3,CIN) begin + case (ALU_MODE) + ADD: begin + S = I0 ^ I1; + C = I0; + end + SUB: begin + S = I0 ^ ~I1; + C = I0; + end + ADDSUB: begin + S = I3? I0 ^ I1 : I0 ^ ~I1; + C = I0; + end + NE: begin + S = I0 ^ ~I1; + C = 1'b1; + end + GE: begin + S = I0 ^ ~I1; + C = I0; + end + LE: begin + S = ~I0 ^ I1; + C = I1; + end + CUP: begin + S = I0; + C = 1'b0; + end + CDN: begin + S = ~I0; + C = 1'b1; + end + CUPCDN: begin + S = I3? I0 : ~I0; + C = I0; + end + MULT: begin + S = I0 & I1; + C = I0 & I1; + end + endcase +end + +endmodule + module RAM16S4 (DO, DI, AD, WRE, CLK); parameter WIDTH = 4; -- cgit v1.2.3 From 8a2699c40c9b60d28ab69c1e87629b467ccc9890 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 21 Oct 2019 12:31:11 +0200 Subject: add negedge DFF --- techlibs/gowin/cells_map.v | 33 ++++++++++--- techlibs/gowin/cells_sim.v | 121 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 139 insertions(+), 15 deletions(-) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index dc0e16db8..e485feebd 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -3,15 +3,8 @@ // DFFSE D Flip-Flop with Clock Enable and Synchronous Set // DFFRE D Flip-Flop with Clock Enable and Synchronous Reset -// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set // DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set -// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset // DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset -// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset -// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset -// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear -// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear - //TODO all DFF* have INIT // DFFN D Flip-Flop with Negative-Edge Clock @@ -31,24 +24,50 @@ module \$_DFFE_NN_ (input D, C, E, output Q); DFFNE _TECHMAP_REPLACE_ (.D(D), . module \$__DFFS_PN0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule +// DFFNR D Flip-Flop with Negative-Edge Clock and Synchronous Reset +module \$__DFFS_NN0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule +module \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule + // DFFS D Flip-Flop with Synchronous Set module \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule +// DFFNS D Flip-Flop with Negative-Edge Clock and Synchronous Set +module \$__DFFS_NN1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule +module \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule + // DFFP D Flip-Flop with Asynchronous Preset module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule module \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule + +// DFFNP D Flip-Flop with Negative-Edge Clock and Asynchronous Preset +module \$_DFF_NP1_ (input D, C, R, output Q); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule +module \$_DFF_NN1_ (input D, C, R, output Q); DFFNP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule + // DFFC D Flip-Flop with Asynchronous Clear module \$_DFF_PP0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule module \$_DFF_PN0_ (input D, C, R, output Q); DFFC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule +// DFFNC D Flip-Flop with Negative-Edge Clock and Asynchronous Clear +module \$_DFF_NP0_ (input D, C, R, output Q); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R)); endmodule +module \$_DFF_NN0_ (input D, C, R, output Q); DFFNC _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R)); endmodule + // DFFPE D Flip-Flop with Clock Enable and Asynchronous Preset module \$__DFFE_PP1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule module \$__DFFE_PN1 (input D, C, R, E, output Q); DFFPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule + +// DFFNPE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Asynchronous Preset +module \$__DFFE_NP1 (input D, C, R, E, output Q); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R), .CE(E)); endmodule +module \$__DFFE_NN1 (input D, C, R, E, output Q); DFFNPE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R), .CE(E)); endmodule + // DFFCE D Flip-Flop with Clock Enable and Asynchronous Clear module \$__DFFE_PP0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule module \$__DFFE_PN0 (input D, C, R, E, output Q); DFFCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule +// DFFNCE D Flip-Flop with Negative-Edge Clock,Clock Enable and Asynchronous Clear +module \$__DFFE_NP0 (input D, C, R, E, output Q); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(R), .CE(E)); endmodule +module \$__DFFE_NN0 (input D, C, R, E, output Q); DFFNCE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CLEAR(!R), .CE(E)); endmodule + module \$lut (A, Y); parameter WIDTH = 0; diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index a392f5580..8280982d6 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -31,14 +31,6 @@ module DFF (output reg Q, input CLK, D); Q <= D; endmodule -module DFFN (output reg Q, input CLK, D); - parameter [0:0] INIT = 1'b0; - initial Q = INIT; - always @(negedge CLK) - Q <= D; -endmodule - - module DFFE (output reg Q, input D, CLK, CE); parameter [0:0] INIT = 1'b0; initial Q = INIT; @@ -144,6 +136,119 @@ module DFFCE (output reg Q, input D, CLK, CE, CLEAR); end endmodule // DFFCE (positive clock edge; asynchronous clear; clock enable) + +module DFFN (output reg Q, input CLK, D); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) + Q <= D; +endmodule + +module DFFNE (output reg Q, input D, CLK, CE); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (CE) + Q <= D; + end +endmodule // DFFNE (negative clock edge; clock enable) + + +module DFFNS (output reg Q, input D, CLK, SET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (SET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFNS (negative clock edge; synchronous set) + + +module DFFNSE (output reg Q, input D, CLK, CE, SET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (SET) + Q <= 1'b1; + else if (CE) + Q <= D; +end +endmodule // DFFNSE (negative clock edge; synchronous set takes precedence over clock enable) + + +module DFFNR (output reg Q, input D, CLK, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (RESET) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFNR (negative clock edge; synchronous reset) + + +module DFFNRE (output reg Q, input D, CLK, CE, RESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK) begin + if (RESET) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFNRE (negative clock edge; synchronous reset takes precedence over clock enable) + + +module DFFNP (output reg Q, input D, CLK, PRESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else + Q <= D; + end +endmodule // DFFNP (negative clock edge; asynchronous preset) + + +module DFFNPE (output reg Q, input D, CLK, CE, PRESET); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK or posedge PRESET) begin + if(PRESET) + Q <= 1'b1; + else if (CE) + Q <= D; + end +endmodule // DFFNPE (negative clock edge; asynchronous preset; clock enable) + + +module DFFNC (output reg Q, input D, CLK, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else + Q <= D; + end +endmodule // DFFNC (negative clock edge; asynchronous clear) + + +module DFFNCE (output reg Q, input D, CLK, CE, CLEAR); + parameter [0:0] INIT = 1'b0; + initial Q = INIT; + always @(negedge CLK or posedge CLEAR) begin + if(CLEAR) + Q <= 1'b0; + else if (CE) + Q <= D; + end +endmodule // DFFNCE (negative clock edge; asynchronous clear; clock enable) + // TODO add more DFF sim cells module VCC(output V); -- cgit v1.2.3 From 4033ff8c2ed2d312b0dc54940502c6ff9c34ebe7 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Oct 2019 12:39:28 +0200 Subject: Fix handling of "restrict" in Verific front-end Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c5eef4b55..9f9eeb764 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1256,7 +1256,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se if (inst->Type() == PRIM_SVA_ASSERT || inst->Type() == PRIM_SVA_IMMEDIATE_ASSERT) sva_asserts.insert(inst); - if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME) + if (inst->Type() == PRIM_SVA_ASSUME || inst->Type() == PRIM_SVA_IMMEDIATE_ASSUME || inst->Type() == PRIM_SVA_RESTRICT) sva_assumes.insert(inst); if (inst->Type() == PRIM_SVA_COVER || inst->Type() == PRIM_SVA_IMMEDIATE_COVER) -- cgit v1.2.3 From 5025aab8c9b47e2a201f7ffd494475882db92398 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 21 Oct 2019 13:35:31 +0200 Subject: Add "verilog_defines -list" and "verilog_defines -reset" Signed-off-by: Clifford Wolf --- frontends/verilog/verilog_frontend.cc | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc index 0e2bead6f..058d750c3 100644 --- a/frontends/verilog/verilog_frontend.cc +++ b/frontends/verilog/verilog_frontend.cc @@ -553,6 +553,12 @@ struct VerilogDefines : public Pass { log(" -Uname[=definition]\n"); log(" undefine the preprocessor symbol 'name'\n"); log("\n"); + log(" -reset\n"); + log(" clear list of defined preprocessor symbols\n"); + log("\n"); + log(" -list\n"); + log(" list currently defined preprocessor symbols\n"); + log("\n"); } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE { @@ -588,6 +594,16 @@ struct VerilogDefines : public Pass { design->verilog_defines.erase(name); continue; } + if (arg == "-reset") { + design->verilog_defines.clear(); + continue; + } + if (arg == "-list") { + for (auto &it : design->verilog_defines) { + log("`define %s%s %s\n", it.first.c_str(), it.second.second ? "()" : "", it.second.first.c_str()); + } + continue; + } break; } -- cgit v1.2.3 From 03457ee13e36574add688a9c2c5c0641a4d6df05 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 21 Oct 2019 16:08:13 +0200 Subject: add a few more missing dff --- techlibs/gowin/cells_map.v | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index e485feebd..425cf7f59 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -1,10 +1,3 @@ -// TODO add these DFF types -// Primitive Description -// DFFSE D Flip-Flop with Clock Enable and Synchronous Set -// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset - -// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set -// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset //TODO all DFF* have INIT // DFFN D Flip-Flop with Negative-Edge Clock @@ -28,6 +21,14 @@ module \$__DFFS_PP0_ (input D, C, R, output Q); DFFR _TECHMAP_REPLACE_ (.D(D), module \$__DFFS_NN0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R)); endmodule module \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R)); endmodule +// DFFRE D Flip-Flop with Clock Enable and Synchronous Reset +module \$__DFFSE_PN0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule +module \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule + +// DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset +module \$__DFFNSE_PN0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule +module \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule + // DFFS D Flip-Flop with Synchronous Set module \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule @@ -36,6 +37,14 @@ module \$__DFFS_PP1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), module \$__DFFS_NN1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule module \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R)); endmodule +// DFFSE D Flip-Flop with Clock Enable and Synchronous Set +module \$__DFFSE_PN1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule +module \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule + +// DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set +module \$__DFFSE_NN1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule +module \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule + // DFFP D Flip-Flop with Asynchronous Preset module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule module \$_DFF_PN1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(!R)); endmodule -- cgit v1.2.3 From 83fbfe0964dc7315ca6d508e6069507250d9f093 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 21 Oct 2019 16:25:15 +0200 Subject: Add some tests Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram --- tests/arch/gowin/.gitignore | 3 +++ tests/arch/gowin/add_sub.ys | 13 +++++++++++ tests/arch/gowin/adffs.ys | 55 ++++++++++++++++++++++++++++++++++++++++++++ tests/arch/gowin/counter.ys | 15 ++++++++++++ tests/arch/gowin/dffs.ys | 25 ++++++++++++++++++++ tests/arch/gowin/logic.ys | 13 +++++++++++ tests/arch/gowin/memory.ys | 18 +++++++++++++++ tests/arch/gowin/mux.ys | 50 ++++++++++++++++++++++++++++++++++++++++ tests/arch/gowin/run-test.sh | 20 ++++++++++++++++ tests/arch/gowin/shifter.ys | 12 ++++++++++ 10 files changed, 224 insertions(+) create mode 100644 tests/arch/gowin/.gitignore create mode 100644 tests/arch/gowin/add_sub.ys create mode 100644 tests/arch/gowin/adffs.ys create mode 100644 tests/arch/gowin/counter.ys create mode 100644 tests/arch/gowin/dffs.ys create mode 100644 tests/arch/gowin/logic.ys create mode 100644 tests/arch/gowin/memory.ys create mode 100644 tests/arch/gowin/mux.ys create mode 100755 tests/arch/gowin/run-test.sh create mode 100644 tests/arch/gowin/shifter.ys diff --git a/tests/arch/gowin/.gitignore b/tests/arch/gowin/.gitignore new file mode 100644 index 000000000..b48f808a1 --- /dev/null +++ b/tests/arch/gowin/.gitignore @@ -0,0 +1,3 @@ +/*.log +/*.out +/run-test.mk diff --git a/tests/arch/gowin/add_sub.ys b/tests/arch/gowin/add_sub.ys new file mode 100644 index 000000000..9b53dc0a9 --- /dev/null +++ b/tests/arch/gowin/add_sub.ys @@ -0,0 +1,13 @@ +read_verilog ../common/add_sub.v +hierarchy -top top +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 8 t:ALU +select -assert-count 8 t:OBUF +select -assert-count 8 t:IBUF +select -assert-count 1 t:GND +select -assert-count 1 t:VCC +select -assert-none t:ALU t:OBUF t:IBUF t:GND t:VCC %% t:* %D + diff --git a/tests/arch/gowin/adffs.ys b/tests/arch/gowin/adffs.ys new file mode 100644 index 000000000..fc7ee01f2 --- /dev/null +++ b/tests/arch/gowin/adffs.ys @@ -0,0 +1,55 @@ +read_verilog ../common/adffs.v +design -save read + +hierarchy -top adff +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adff # Constrain all select calls below inside the top module +stat +select -assert-count 1 t:DFFC +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFC t:IBUF t:OBUF %% t:* %D + + +design -load read +hierarchy -top adffn +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd adffn # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFC +select -assert-count 1 t:LUT1 +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFC t:IBUF t:OBUF t:LUT1 %% t:* %D + + +design -load read +hierarchy -top dffs +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffs # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFS +select -assert-count 4 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFS t:IBUF t:OBUF %% t:* %D + + +design -load read +hierarchy -top ndffnr +proc +equiv_opt -async2sync -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd ndffnr # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFNR +select -assert-count 1 t:LUT1 +select -assert-count 4 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFNR t:IBUF t:OBUF t:LUT1 %% t:* %D diff --git a/tests/arch/gowin/counter.ys b/tests/arch/gowin/counter.ys new file mode 100644 index 000000000..920479d44 --- /dev/null +++ b/tests/arch/gowin/counter.ys @@ -0,0 +1,15 @@ +read_verilog ../common/counter.v +hierarchy -top top +proc +flatten +equiv_opt -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:DFFC +select -assert-count 8 t:ALU +select -assert-count 1 t:GND +select -assert-count 1 t:VCC +select -assert-count 2 t:IBUF +select -assert-count 8 t:OBUF +select -assert-none t:DFFC t:ALU t:GND t:VCC t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/dffs.ys b/tests/arch/gowin/dffs.ys new file mode 100644 index 000000000..9c012213f --- /dev/null +++ b/tests/arch/gowin/dffs.ys @@ -0,0 +1,25 @@ +read_verilog ../common/dffs.v +design -save read + +hierarchy -top dff +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dff # Constrain all select calls below inside the top module +select -assert-count 1 t:DFF +select -assert-count 2 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D + +design -load read +hierarchy -top dffe +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd dffe # Constrain all select calls below inside the top module +select -assert-count 1 t:DFFE +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:DFFE t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/logic.ys b/tests/arch/gowin/logic.ys new file mode 100644 index 000000000..d2b9e4540 --- /dev/null +++ b/tests/arch/gowin/logic.ys @@ -0,0 +1,13 @@ +read_verilog ../common/logic.v +hierarchy -top top +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 1 t:LUT1 +select -assert-count 6 t:LUT2 +select -assert-count 2 t:LUT4 +select -assert-count 8 t:IBUF +select -assert-count 10 t:OBUF +select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/memory.ys b/tests/arch/gowin/memory.ys new file mode 100644 index 000000000..8f88cdd7c --- /dev/null +++ b/tests/arch/gowin/memory.ys @@ -0,0 +1,18 @@ +read_verilog ../common/memory.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin +memory +opt -full + +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#ERROR: Called with -verify and proof did fail! +#sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter +sat -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 8 t:RAM16S4 +# other logic present that is not simple +#select -assert-none t:RAM16S4 %% t:* %D diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys new file mode 100644 index 000000000..c9c85019b --- /dev/null +++ b/tests/arch/gowin/mux.ys @@ -0,0 +1,50 @@ +read_verilog ../common/mux.v +design -save read + +hierarchy -top mux2 +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux2 # Constrain all select calls below inside the top module +select -assert-count 1 t:LUT3 +select -assert-count 3 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D + +design -load read +hierarchy -top mux4 +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux4 # Constrain all select calls below inside the top module +select -assert-count 2 t:LUT4 +select -assert-count 6 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D + +design -load read +hierarchy -top mux8 +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux8 # Constrain all select calls below inside the top module +select -assert-count 5 t:LUT4 +select -assert-count 11 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D + +design -load read +hierarchy -top mux16 +proc +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd mux16 # Constrain all select calls below inside the top module +select -assert-count 9 t:LUT4 +select -assert-count 3 t:LUT3 +select -assert-count 20 t:IBUF +select -assert-count 1 t:OBUF + +select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/run-test.sh b/tests/arch/gowin/run-test.sh new file mode 100755 index 000000000..bf19b887d --- /dev/null +++ b/tests/arch/gowin/run-test.sh @@ -0,0 +1,20 @@ +#!/usr/bin/env bash +set -e +{ +echo "all::" +for x in *.ys; do + echo "all:: run-$x" + echo "run-$x:" + echo " @echo 'Running $x..'" + echo " @../../../yosys -ql ${x%.ys}.log -w 'Yosys has only limited support for tri-state logic at the moment.' $x" +done +for s in *.sh; do + if [ "$s" != "run-test.sh" ]; then + echo "all:: run-$s" + echo "run-$s:" + echo " @echo 'Running $s..'" + echo " @bash $s" + fi +done +} > run-test.mk +exec ${MAKE:-make} -f run-test.mk diff --git a/tests/arch/gowin/shifter.ys b/tests/arch/gowin/shifter.ys new file mode 100644 index 000000000..b43b1e869 --- /dev/null +++ b/tests/arch/gowin/shifter.ys @@ -0,0 +1,12 @@ +read_verilog ../common/shifter.v +hierarchy -top top +proc +flatten +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module + +select -assert-count 8 t:DFF +select -assert-count 2 t:IBUF +select -assert-count 8 t:OBUF +select -assert-none t:DFF t:IBUF t:OBUF %% t:* %D -- cgit v1.2.3 From 7b350cacd410b16fdac5a6933aea1bb009b83621 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Tue, 8 Oct 2019 17:00:30 +0000 Subject: xilinx: Support multiplier mapping for all families. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This supports several older families that are not yet supported for actual logic synthesis — the intention is to add them soon. --- techlibs/xilinx/Makefile.inc | 8 +++++- techlibs/xilinx/dsp_map.v | 49 ------------------------------------- techlibs/xilinx/synth_xilinx.cc | 53 ++++++++++++++++++++++++++++++++++------ techlibs/xilinx/xc3s_mult_map.v | 14 +++++++++++ techlibs/xilinx/xc3sda_dsp_map.v | 34 ++++++++++++++++++++++++++ techlibs/xilinx/xc4v_dsp_map.v | 38 ++++++++++++++++++++++++++++ techlibs/xilinx/xc5v_dsp_map.v | 45 ++++++++++++++++++++++++++++++++++ techlibs/xilinx/xc6s_dsp_map.v | 35 ++++++++++++++++++++++++++ techlibs/xilinx/xc7_dsp_map.v | 49 +++++++++++++++++++++++++++++++++++++ techlibs/xilinx/xcu_dsp_map.v | 51 ++++++++++++++++++++++++++++++++++++++ 10 files changed, 318 insertions(+), 58 deletions(-) delete mode 100644 techlibs/xilinx/dsp_map.v create mode 100644 techlibs/xilinx/xc3s_mult_map.v create mode 100644 techlibs/xilinx/xc3sda_dsp_map.v create mode 100644 techlibs/xilinx/xc4v_dsp_map.v create mode 100644 techlibs/xilinx/xc5v_dsp_map.v create mode 100644 techlibs/xilinx/xc6s_dsp_map.v create mode 100644 techlibs/xilinx/xc7_dsp_map.v create mode 100644 techlibs/xilinx/xcu_dsp_map.v diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 1e59f0a1b..3354605ef 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -42,7 +42,13 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3s_mult_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc3sda_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc4v_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc5v_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_dsp_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_dsp_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc9_unmap.v)) diff --git a/techlibs/xilinx/dsp_map.v b/techlibs/xilinx/dsp_map.v deleted file mode 100644 index a4256eb92..000000000 --- a/techlibs/xilinx/dsp_map.v +++ /dev/null @@ -1,49 +0,0 @@ -module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); - parameter A_SIGNED = 0; - parameter B_SIGNED = 0; - parameter A_WIDTH = 0; - parameter B_WIDTH = 0; - parameter Y_WIDTH = 0; - - wire [47:0] P_48; - DSP48E1 #( - // Disable all registers - .ACASCREG(0), - .ADREG(0), - .A_INPUT("DIRECT"), - .ALUMODEREG(0), - .AREG(0), - .BCASCREG(0), - .B_INPUT("DIRECT"), - .BREG(0), - .CARRYINREG(0), - .CARRYINSELREG(0), - .CREG(0), - .DREG(0), - .INMODEREG(0), - .MREG(0), - .OPMODEREG(0), - .PREG(0), - .USE_MULT("MULTIPLY"), - .USE_SIMD("ONE48"), - .USE_DPORT("FALSE") - ) _TECHMAP_REPLACE_ ( - //Data path - .A({{5{A[24]}}, A}), - .B(B), - .C(48'b0), - .D(25'b0), - .P(P_48), - - .INMODE(5'b00000), - .ALUMODE(4'b0000), - .OPMODE(7'b000101), - .CARRYINSEL(3'b000), - - .ACIN(30'b0), - .BCIN(18'b0), - .PCIN(48'b0), - .CARRYIN(1'b0) - ); - assign Y = P_48; -endmodule diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6f8254b59..6566da832 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -343,14 +343,51 @@ struct SynthXilinxPass : public ScriptPass if (!nodsp || help_mode) { run("memory_dff"); // xilinx_dsp will merge registers, reserve memory port registers first // NB: Xilinx multipliers are signed only - run("techmap -map +/mul2dsp.v -map +/xilinx/dsp_map.v -D DSP_A_MAXWIDTH=25 " - "-D DSP_A_MAXWIDTH_PARTIAL=18 -D DSP_B_MAXWIDTH=18 " // Partial multipliers are intentionally - // limited to 18x18 in order to take - // advantage of the (PCOUT << 17) -> PCIN - // dedicated cascade chain capability - "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers - "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller - "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + if (help_mode) + run("techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}"); + else if (family == "xc2v" || family == "xc3s" || family == "xc3se" || family == "xc3sa") + run("techmap -map +/mul2dsp.v -map +/xilinx/xc3s_mult_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 " + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18"); + else if (family == "xc3sda") + run("techmap -map +/mul2dsp.v -map +/xilinx/xc3sda_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 " + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18"); + else if (family == "xc6s") + run("techmap -map +/mul2dsp.v -map +/xilinx/xc6s_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 " + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18"); + else if (family == "xc4v") + run("techmap -map +/mul2dsp.v -map +/xilinx/xc4v_dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18 " + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL18X18"); + else if (family == "xc5v") + run("techmap -map +/mul2dsp.v -map +/xilinx/xc5v_dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 " + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + else if (family == "xc6v" || family == "xc7") + run("techmap -map +/mul2dsp.v -map +/xilinx/xc7_dsp_map.v -D DSP_A_MAXWIDTH=25 -D DSP_B_MAXWIDTH=18 " + "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally + // limited to 18x18 in order to take + // advantage of the (PCOUT << 17) -> PCIN + // dedicated cascade chain capability + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL25X18"); + else if (family == "xcu" || family == "xcup") + run("techmap -map +/mul2dsp.v -map +/xilinx/xcu_dsp_map.v -D DSP_A_MAXWIDTH=27 -D DSP_B_MAXWIDTH=18 " + "-D DSP_A_MAXWIDTH_PARTIAL=18 " // Partial multipliers are intentionally + // limited to 18x18 in order to take + // advantage of the (PCOUT << 17) -> PCIN + // dedicated cascade chain capability + "-D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 " // Blocks Nx1 multipliers + "-D DSP_Y_MINWIDTH=9 " // UG901 suggests small multiplies are those 4x4 and smaller + "-D DSP_SIGNEDONLY=1 -D DSP_NAME=$__MUL27X18"); run("select a:mul2dsp"); run("setattr -unset mul2dsp"); run("opt_expr -fine"); diff --git a/techlibs/xilinx/xc3s_mult_map.v b/techlibs/xilinx/xc3s_mult_map.v new file mode 100644 index 000000000..67cd4ac60 --- /dev/null +++ b/techlibs/xilinx/xc3s_mult_map.v @@ -0,0 +1,14 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + MULT18X18 _TECHMAP_REPLACE_ ( + .A(A), + .B(B), + .P(Y) + ); +endmodule + diff --git a/techlibs/xilinx/xc3sda_dsp_map.v b/techlibs/xilinx/xc3sda_dsp_map.v new file mode 100644 index 000000000..87348a173 --- /dev/null +++ b/techlibs/xilinx/xc3sda_dsp_map.v @@ -0,0 +1,34 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48A #( + // Disable all registers + .A0REG(0), + .A1REG(0), + .B0REG(0), + .B1REG(0), + .CARRYINREG(0), + .CARRYINSEL("OPMODE5"), + .CREG(0), + .DREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0) + ) _TECHMAP_REPLACE_ ( + //Data path + .A(A), + .B(B), + .C(48'b0), + .D(18'b0), + .P(P_48), + + .OPMODE(8'b0000010) + ); + assign Y = P_48; +endmodule + diff --git a/techlibs/xilinx/xc4v_dsp_map.v b/techlibs/xilinx/xc4v_dsp_map.v new file mode 100644 index 000000000..69c42f343 --- /dev/null +++ b/techlibs/xilinx/xc4v_dsp_map.v @@ -0,0 +1,38 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48 #( + // Disable all registers + .AREG(0), + .BREG(0), + .B_INPUT("DIRECT"), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0), + .SUBTRACTREG(0), + .LEGACY_MODE("MULT18X18") + ) _TECHMAP_REPLACE_ ( + //Data path + .A(A), + .B(B), + .C(48'b0), + .P(P_48), + + .SUBTRACT(1'b0), + .OPMODE(7'b000101), + .CARRYINSEL(2'b00), + + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule diff --git a/techlibs/xilinx/xc5v_dsp_map.v b/techlibs/xilinx/xc5v_dsp_map.v new file mode 100644 index 000000000..fc7ba46cc --- /dev/null +++ b/techlibs/xilinx/xc5v_dsp_map.v @@ -0,0 +1,45 @@ +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48E #( + // Disable all registers + .ACASCREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .MULTCARRYINREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0), + .USE_MULT("MULT"), + .USE_SIMD("ONE48") + ) _TECHMAP_REPLACE_ ( + //Data path + .A({{5{A[24]}}, A}), + .B(B), + .C(48'b0), + .P(P_48), + + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule + diff --git a/techlibs/xilinx/xc6s_dsp_map.v b/techlibs/xilinx/xc6s_dsp_map.v new file mode 100644 index 000000000..e8705723b --- /dev/null +++ b/techlibs/xilinx/xc6s_dsp_map.v @@ -0,0 +1,35 @@ +module \$__MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48A1 #( + // Disable all registers + .A0REG(0), + .A1REG(0), + .B0REG(0), + .B1REG(0), + .CARRYINREG(0), + .CARRYINSEL("OPMODE5"), + .CREG(0), + .DREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0) + ) _TECHMAP_REPLACE_ ( + //Data path + .A(A), + .B(B), + .C(48'b0), + .D(18'b0), + .P(P_48), + + .OPMODE(8'b0000010) + ); + assign Y = P_48; +endmodule + + diff --git a/techlibs/xilinx/xc7_dsp_map.v b/techlibs/xilinx/xc7_dsp_map.v new file mode 100644 index 000000000..a4256eb92 --- /dev/null +++ b/techlibs/xilinx/xc7_dsp_map.v @@ -0,0 +1,49 @@ +module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48E1 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0), + .USE_MULT("MULTIPLY"), + .USE_SIMD("ONE48"), + .USE_DPORT("FALSE") + ) _TECHMAP_REPLACE_ ( + //Data path + .A({{5{A[24]}}, A}), + .B(B), + .C(48'b0), + .D(25'b0), + .P(P_48), + + .INMODE(5'b00000), + .ALUMODE(4'b0000), + .OPMODE(7'b000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule diff --git a/techlibs/xilinx/xcu_dsp_map.v b/techlibs/xilinx/xcu_dsp_map.v new file mode 100644 index 000000000..fa95a5776 --- /dev/null +++ b/techlibs/xilinx/xcu_dsp_map.v @@ -0,0 +1,51 @@ +module \$__MUL27X18 (input [26:0] A, input [17:0] B, output [44:0] Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + wire [47:0] P_48; + DSP48E2 #( + // Disable all registers + .ACASCREG(0), + .ADREG(0), + .A_INPUT("DIRECT"), + .ALUMODEREG(0), + .AREG(0), + .BCASCREG(0), + .B_INPUT("DIRECT"), + .BREG(0), + .CARRYINREG(0), + .CARRYINSELREG(0), + .CREG(0), + .DREG(0), + .INMODEREG(0), + .MREG(0), + .OPMODEREG(0), + .PREG(0), + .USE_MULT("MULTIPLY"), + .USE_SIMD("ONE48"), + .AMULTSEL("A"), + .BMULTSEL("B") + ) _TECHMAP_REPLACE_ ( + //Data path + .A({{3{A[26]}}, A}), + .B(B), + .C(48'b0), + .D(27'b0), + .P(P_48), + + .INMODE(5'b00000), + .ALUMODE(4'b0000), + .OPMODE(9'b00000101), + .CARRYINSEL(3'b000), + + .ACIN(30'b0), + .BCIN(18'b0), + .PCIN(48'b0), + .CARRYIN(1'b0) + ); + assign Y = P_48; +endmodule + -- cgit v1.2.3 From f02623abb5d8338f034d7069844418af8912ab0f Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 23 Oct 2019 00:04:34 +0200 Subject: Bugfix in smtio vcd handling of $-identifiers Signed-off-by: Clifford Wolf --- backends/smt2/smtio.py | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/backends/smt2/smtio.py b/backends/smt2/smtio.py index bac68ac70..1df996aa7 100644 --- a/backends/smt2/smtio.py +++ b/backends/smt2/smtio.py @@ -1032,12 +1032,17 @@ class MkVcd: print("$var integer 32 t smt_step $end", file=self.f) print("$var event 1 ! smt_clock $end", file=self.f) + def vcdescape(n): + if n.startswith("$") or ":" in n: + return "\\" + n + return n + scope = [] for path in sorted(self.nets): key, width = self.nets[path] uipath = list(path) - if "." in uipath[-1]: + if "." in uipath[-1] and not uipath[-1].startswith("$"): uipath = uipath[0:-1] + uipath[-1].split(".") for i in range(len(uipath)): uipath[i] = re.sub(r"\[([^\]]*)\]", r"<\1>", uipath[i]) @@ -1048,15 +1053,13 @@ class MkVcd: while uipath[:-1] != scope: scopename = uipath[len(scope)] - if scopename.startswith("$"): - scopename = "\\" + scopename - print("$scope module %s $end" % scopename, file=self.f) + print("$scope module %s $end" % vcdescape(scopename), file=self.f) scope.append(uipath[len(scope)]) if path in self.clocks and self.clocks[path][1] == "event": - print("$var event 1 %s %s $end" % (key, uipath[-1]), file=self.f) + print("$var event 1 %s %s $end" % (key, vcdescape(uipath[-1])), file=self.f) else: - print("$var wire %d %s %s $end" % (width, key, uipath[-1]), file=self.f) + print("$var wire %d %s %s $end" % (width, key, vcdescape(uipath[-1])), file=self.f) for i in range(len(scope)): print("$upscope $end", file=self.f) -- cgit v1.2.3 From 6769d31ddbab341940af9b42b538fca60797fdf4 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 18 Oct 2019 13:24:19 +0100 Subject: xilinx: Add support for UltraScale[+] BRAM mapping Signed-off-by: David Shah --- techlibs/xilinx/Makefile.inc | 4 +- techlibs/xilinx/cells_xtra.py | 22 +- techlibs/xilinx/synth_xilinx.cc | 7 +- techlibs/xilinx/xc7_brams.txt | 105 ------ techlibs/xilinx/xc7_xcu_brams.txt | 105 ++++++ techlibs/xilinx/xcu_brams_bb.v | 405 +++++++++++++++++++++++ techlibs/xilinx/xcu_brams_map.v | 384 ++++++++++++++++++++++ techlibs/xilinx/xcu_cells_xtra.v | 656 +++++++++++++++----------------------- 8 files changed, 1167 insertions(+), 521 deletions(-) delete mode 100644 techlibs/xilinx/xc7_brams.txt create mode 100644 techlibs/xilinx/xc7_xcu_brams.txt create mode 100644 techlibs/xilinx/xcu_brams_bb.v create mode 100644 techlibs/xilinx/xcu_brams_map.v diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 3354605ef..6fc41f591 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -32,9 +32,11 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 9a4747ff3..7cf1162bd 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -228,8 +228,8 @@ XC6V_CELLS = [ # Cell('FDSE'), Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - Cell('LDCE'), - Cell('LDPE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), # Slice/CLB primitives. @@ -378,8 +378,8 @@ XC7_CELLS = [ # Cell('FDSE'), Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - Cell('LDCE'), - Cell('LDPE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), # Slice/CLB primitives. @@ -435,8 +435,8 @@ XCU_CELLS = [ # Blockram. Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + #Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + #Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}), Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), @@ -491,6 +491,12 @@ XCU_CELLS = [ Cell('PLLE3_BASE'), Cell('PLLE4_ADV'), Cell('PLLE4_BASE'), + # the "E2" variants are not strictly speaking UltraScale[+] cells + # but are automatically upgraded for backwards compatibility purposes + Cell('MMCME2_ADV'), + Cell('MMCME2_BASE'), + Cell('PLLE2_ADV'), + Cell('PLLE2_BASE'), # Configuration. Cell('BSCANE2', keep=True), @@ -562,8 +568,8 @@ XCU_CELLS = [ # Cell('FDSE'), Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}), Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - Cell('LDCE'), - Cell('LDPE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}), # NOTE: not in the official library guide! diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 6566da832..825addf84 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -305,6 +305,8 @@ struct SynthXilinxPass : public ScriptPass run("read_verilog -lib +/xilinx/xc6s_brams_bb.v"); } else if (family == "xc6v" || family == "xc7") { run("read_verilog -lib +/xilinx/xc7_brams_bb.v"); + } else if (family == "xcu" || family == "xcup") { + run("read_verilog -lib +/xilinx/xcu_brams_bb.v"); } run(stringf("hierarchy -check %s", top_opt.c_str())); @@ -417,8 +419,11 @@ struct SynthXilinxPass : public ScriptPass run("memory_bram -rules +/xilinx/xc6s_brams.txt"); run("techmap -map +/xilinx/xc6s_brams_map.v"); } else if (family == "xc6v" || family == "xc7") { - run("memory_bram -rules +/xilinx/xc7_brams.txt"); + run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt"); run("techmap -map +/xilinx/xc7_brams_map.v"); + } else if (family == "xcu" || family == "xcup") { + run("memory_bram -rules +/xilinx/xc7_xcu_brams.txt"); + run("techmap -map +/xilinx/xcu_brams_map.v"); } else { log_warning("Block RAM inference not yet supported for family %s.\n", family.c_str()); } diff --git a/techlibs/xilinx/xc7_brams.txt b/techlibs/xilinx/xc7_brams.txt deleted file mode 100644 index f1161114e..000000000 --- a/techlibs/xilinx/xc7_brams.txt +++ /dev/null @@ -1,105 +0,0 @@ - -bram $__XILINX_RAMB36_SDP - init 1 - abits 9 - dbits 72 - groups 2 - ports 1 1 - wrmode 0 1 - enable 1 8 - transp 0 0 - clocks 2 3 - clkpol 2 3 -endbram - -bram $__XILINX_RAMB18_SDP - init 1 - abits 9 - dbits 36 - groups 2 - ports 1 1 - wrmode 0 1 - enable 1 4 - transp 0 0 - clocks 2 3 - clkpol 2 3 -endbram - -bram $__XILINX_RAMB36_TDP - init 1 - abits 10 @a10d36 - dbits 36 @a10d36 - abits 11 @a11d18 - dbits 18 @a11d18 - abits 12 @a12d9 - dbits 9 @a12d9 - abits 13 @a13d4 - dbits 4 @a13d4 - abits 14 @a14d2 - dbits 2 @a14d2 - abits 15 @a15d1 - dbits 1 @a15d1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 1 4 @a10d36 - enable 1 2 @a11d18 - enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1 - transp 0 0 - clocks 2 3 - clkpol 2 3 -endbram - -bram $__XILINX_RAMB18_TDP - init 1 - abits 10 @a10d18 - dbits 18 @a10d18 - abits 11 @a11d9 - dbits 9 @a11d9 - abits 12 @a12d4 - dbits 4 @a12d4 - abits 13 @a13d2 - dbits 2 @a13d2 - abits 14 @a14d1 - dbits 1 @a14d1 - groups 2 - ports 1 1 - wrmode 0 1 - enable 1 2 @a10d18 - enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 - transp 0 0 - clocks 2 3 - clkpol 2 3 -endbram - -match $__XILINX_RAMB36_SDP - min bits 4096 - min efficiency 5 - shuffle_enable B - make_transp - or_next_if_better -endmatch - -match $__XILINX_RAMB18_SDP - min bits 4096 - min efficiency 5 - shuffle_enable B - make_transp - or_next_if_better -endmatch - -match $__XILINX_RAMB36_TDP - min bits 4096 - min efficiency 5 - shuffle_enable B - make_transp - or_next_if_better -endmatch - -match $__XILINX_RAMB18_TDP - min bits 4096 - min efficiency 5 - shuffle_enable B - make_transp -endmatch - diff --git a/techlibs/xilinx/xc7_xcu_brams.txt b/techlibs/xilinx/xc7_xcu_brams.txt new file mode 100644 index 000000000..f1161114e --- /dev/null +++ b/techlibs/xilinx/xc7_xcu_brams.txt @@ -0,0 +1,105 @@ + +bram $__XILINX_RAMB36_SDP + init 1 + abits 9 + dbits 72 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 8 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB18_SDP + init 1 + abits 9 + dbits 36 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 4 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB36_TDP + init 1 + abits 10 @a10d36 + dbits 36 @a10d36 + abits 11 @a11d18 + dbits 18 @a11d18 + abits 12 @a12d9 + dbits 9 @a12d9 + abits 13 @a13d4 + dbits 4 @a13d4 + abits 14 @a14d2 + dbits 2 @a14d2 + abits 15 @a15d1 + dbits 1 @a15d1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 4 @a10d36 + enable 1 2 @a11d18 + enable 1 1 @a12d9 @a13d4 @a14d2 @a15d1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +bram $__XILINX_RAMB18_TDP + init 1 + abits 10 @a10d18 + dbits 18 @a10d18 + abits 11 @a11d9 + dbits 9 @a11d9 + abits 12 @a12d4 + dbits 4 @a12d4 + abits 13 @a13d2 + dbits 2 @a13d2 + abits 14 @a14d1 + dbits 1 @a14d1 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 2 @a10d18 + enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 + transp 0 0 + clocks 2 3 + clkpol 2 3 +endbram + +match $__XILINX_RAMB36_SDP + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_SDP + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB36_TDP + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp + or_next_if_better +endmatch + +match $__XILINX_RAMB18_TDP + min bits 4096 + min efficiency 5 + shuffle_enable B + make_transp +endmatch + diff --git a/techlibs/xilinx/xcu_brams_bb.v b/techlibs/xilinx/xcu_brams_bb.v new file mode 100644 index 000000000..f3e43d0d6 --- /dev/null +++ b/techlibs/xilinx/xcu_brams_bb.v @@ -0,0 +1,405 @@ +module RAMB18E2 (...); + parameter CASCADE_ORDER_A = "NONE"; + parameter CASCADE_ORDER_B = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter integer DOA_REG = 1; + parameter integer DOB_REG = 1; + parameter ENADDRENA = "FALSE"; + parameter ENADDRENB = "FALSE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [17:0] INIT_A = 18'h00000; + parameter [17:0] INIT_B = 18'h00000; + parameter INIT_FILE = "NONE"; + parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; + parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; + parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; + parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; + parameter RDADDRCHANGEA = "FALSE"; + parameter RDADDRCHANGEB = "FALSE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [17:0] SRVAL_A = 18'h00000; + parameter [17:0] SRVAL_B = 18'h00000; + parameter WRITE_MODE_A = "NO_CHANGE"; + parameter WRITE_MODE_B = "NO_CHANGE"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output [15:0] CASDOUTA; + output [15:0] CASDOUTB; + output [1:0] CASDOUTPA; + output [1:0] CASDOUTPB; + output [15:0] DOUTADOUT; + output [15:0] DOUTBDOUT; + output [1:0] DOUTPADOUTP; + output [1:0] DOUTPBDOUTP; + input [13:0] ADDRARDADDR; + input [13:0] ADDRBWRADDR; + input ADDRENA; + input ADDRENB; + input CASDIMUXA; + input CASDIMUXB; + input [15:0] CASDINA; + input [15:0] CASDINB; + input [1:0] CASDINPA; + input [1:0] CASDINPB; + input CASDOMUXA; + input CASDOMUXB; + input CASDOMUXEN_A; + input CASDOMUXEN_B; + input CASOREGIMUXA; + input CASOREGIMUXB; + input CASOREGIMUXEN_A; + input CASOREGIMUXEN_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK; + input [15:0] DINADIN; + input [15:0] DINBDIN; + input [1:0] DINPADINP; + input [1:0] DINPBDINP; + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN; + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN; + input REGCEAREGCE; + input REGCEB; + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM; + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB; + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG; + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB; + input SLEEP; + input [1:0] WEA; + input [3:0] WEBWE; +endmodule + +module RAMB36E2 (...); + parameter CASCADE_ORDER_A = "NONE"; + parameter CASCADE_ORDER_B = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter integer DOA_REG = 1; + parameter integer DOB_REG = 1; + parameter ENADDRENA = "FALSE"; + parameter ENADDRENB = "FALSE"; + parameter EN_ECC_PIPE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h000000000; + parameter [35:0] INIT_B = 36'h000000000; + parameter INIT_FILE = "NONE"; + parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; + parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; + parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; + parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; + parameter RDADDRCHANGEA = "FALSE"; + parameter RDADDRCHANGEB = "FALSE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [35:0] SRVAL_A = 36'h000000000; + parameter [35:0] SRVAL_B = 36'h000000000; + parameter WRITE_MODE_A = "NO_CHANGE"; + parameter WRITE_MODE_B = "NO_CHANGE"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output [31:0] CASDOUTA; + output [31:0] CASDOUTB; + output [3:0] CASDOUTPA; + output [3:0] CASDOUTPB; + output CASOUTDBITERR; + output CASOUTSBITERR; + output DBITERR; + output [31:0] DOUTADOUT; + output [31:0] DOUTBDOUT; + output [3:0] DOUTPADOUTP; + output [3:0] DOUTPBDOUTP; + output [7:0] ECCPARITY; + output [8:0] RDADDRECC; + output SBITERR; + input [14:0] ADDRARDADDR; + input [14:0] ADDRBWRADDR; + input ADDRENA; + input ADDRENB; + input CASDIMUXA; + input CASDIMUXB; + input [31:0] CASDINA; + input [31:0] CASDINB; + input [3:0] CASDINPA; + input [3:0] CASDINPB; + input CASDOMUXA; + input CASDOMUXB; + input CASDOMUXEN_A; + input CASDOMUXEN_B; + input CASINDBITERR; + input CASINSBITERR; + input CASOREGIMUXA; + input CASOREGIMUXB; + input CASOREGIMUXEN_A; + input CASOREGIMUXEN_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK; + input [31:0] DINADIN; + input [31:0] DINBDIN; + input [3:0] DINPADINP; + input [3:0] DINPBDINP; + input ECCPIPECE; + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN; + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN; + input INJECTDBITERR; + input INJECTSBITERR; + input REGCEAREGCE; + input REGCEB; + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM; + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB; + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG; + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB; + input SLEEP; + input [3:0] WEA; + input [7:0] WEBWE; +endmodule \ No newline at end of file diff --git a/techlibs/xilinx/xcu_brams_map.v b/techlibs/xilinx/xcu_brams_map.v new file mode 100644 index 000000000..6e7925b57 --- /dev/null +++ b/techlibs/xilinx/xcu_brams_map.v @@ -0,0 +1,384 @@ +module \$__XILINX_RAMB36_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [36863:0] INIT = 36864'bx; + + input CLK2; + input CLK3; + + input [8:0] A1ADDR; + output [71:0] A1DATA; + input A1EN; + + input [8:0] B1ADDR; + input [71:0] B1DATA; + input [7:0] B1EN; + + wire [15:0] A1ADDR_16 = {A1ADDR, 6'b0}; + wire [15:0] B1ADDR_16 = {B1ADDR, 6'b0}; + + wire [7:0] DIP, DOP; + wire [63:0] DI, DO; + + assign A1DATA = { DOP[7], DO[63:56], DOP[6], DO[55:48], DOP[5], DO[47:40], DOP[4], DO[39:32], + DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; + + assign { DIP[7], DI[63:56], DIP[6], DI[55:48], DIP[5], DI[47:40], DIP[4], DI[39:32], + DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; + + RAMB36E2 #( + .READ_WIDTH_A(72), + .WRITE_WIDTH_B(72), + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST"), + .DOA_REG(0), + .DOB_REG(0), + .IS_CLKARDCLK_INVERTED(!CLKPOL2), + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + `include "brams_init_36.vh" + ) _TECHMAP_REPLACE_ ( + .DOUTBDOUT(DO[63:32]), + .DOUTADOUT(DO[31:0]), + .DOUTPBDOUTP(DOP[7:4]), + .DOUTPADOUTP(DOP[3:0]), + .DINBDIN(DI[63:32]), + .DINADIN(DI[31:0]), + .DINPBDINP(DIP[7:4]), + .DINPADINP(DIP[3:0]), + + .ADDRARDADDR(A1ADDR_16), + .CLKARDCLK(CLK2), + .ENARDEN(A1EN), + .ADDRENA(|1), + .REGCEAREGCE(|1), + .RSTRAMARSTRAM(|0), + .RSTREGARSTREG(|0), + .WEA(4'b0), + + .ADDRBWRADDR(B1ADDR_16), + .CLKBWRCLK(CLK3), + .ENBWREN(|1), + .ADDRENB(|1), + .REGCEB(|1), + .RSTRAMB(|0), + .RSTREGB(|0), + .WEBWE(B1EN), + + .SLEEP(|0) + ); +endmodule + +// ------------------------------------------------------------------------ + +module \$__XILINX_RAMB18_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [18431:0] INIT = 18432'bx; + + input CLK2; + input CLK3; + + input [8:0] A1ADDR; + output [35:0] A1DATA; + input A1EN; + + input [8:0] B1ADDR; + input [35:0] B1DATA; + input [3:0] B1EN; + + wire [13:0] A1ADDR_14 = {A1ADDR, 5'b0}; + wire [13:0] B1ADDR_14 = {B1ADDR, 5'b0}; + + wire [3:0] DIP, DOP; + wire [31:0] DI, DO; + + assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; + assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; + + RAMB18E2 #( + .READ_WIDTH_A(36), + .WRITE_WIDTH_B(36), + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST"), + .DOA_REG(0), + .DOB_REG(0), + .IS_CLKARDCLK_INVERTED(!CLKPOL2), + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + `include "brams_init_18.vh" + ) _TECHMAP_REPLACE_ ( + .DOUTBDOUT(DO[31:16]), + .DOUTADOUT(DO[15:0]), + .DOUTPBDOUTP(DOP[3:2]), + .DOUTPADOUTP(DOP[1:0]), + .DINBDIN(DI[31:16]), + .DINADIN(DI[15:0]), + .DINPBDINP(DIP[3:2]), + .DINPADINP(DIP[1:0]), + + .ADDRARDADDR(A1ADDR_14), + .CLKARDCLK(CLK2), + .ENARDEN(A1EN), + .ADDRENA(|1), + .REGCEAREGCE(|1), + .RSTRAMARSTRAM(|0), + .RSTREGARSTREG(|0), + .WEA(2'b0), + + .ADDRBWRADDR(B1ADDR_14), + .CLKBWRCLK(CLK3), + .ENBWREN(|1), + .ADDRENB(|1), + .REGCEB(|1), + .RSTRAMB(|0), + .RSTREGB(|0), + .WEBWE(B1EN), + + .SLEEP(|0) + ); +endmodule + +// ------------------------------------------------------------------------ + +module \$__XILINX_RAMB36_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CFG_ABITS = 10; + parameter CFG_DBITS = 36; + parameter CFG_ENABLE_B = 4; + + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [36863:0] INIT = 36864'bx; + + input CLK2; + input CLK3; + + input [CFG_ABITS-1:0] A1ADDR; + output [CFG_DBITS-1:0] A1DATA; + input A1EN; + + input [CFG_ABITS-1:0] B1ADDR; + input [CFG_DBITS-1:0] B1DATA; + input [CFG_ENABLE_B-1:0] B1EN; + + wire [15:0] A1ADDR_16 = A1ADDR << (15 - CFG_ABITS); + wire [15:0] B1ADDR_16 = B1ADDR << (15 - CFG_ABITS); + wire [7:0] B1EN_8 = B1EN; + + wire [3:0] DIP, DOP; + wire [31:0] DI, DO; + + wire [31:0] DOBDO; + wire [3:0] DOPBDOP; + + assign A1DATA = { DOP[3], DO[31:24], DOP[2], DO[23:16], DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; + assign { DIP[3], DI[31:24], DIP[2], DI[23:16], DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; + + generate if (CFG_DBITS > 8) begin + RAMB36E2 #( + .READ_WIDTH_A(CFG_DBITS), + .READ_WIDTH_B(CFG_DBITS), + .WRITE_WIDTH_A(CFG_DBITS), + .WRITE_WIDTH_B(CFG_DBITS), + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST"), + .DOA_REG(0), + .DOB_REG(0), + .IS_CLKARDCLK_INVERTED(!CLKPOL2), + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + `include "brams_init_36.vh" + ) _TECHMAP_REPLACE_ ( + .DINADIN(32'hFFFFFFFF), + .DINPADINP(4'hF), + .DOUTADOUT(DO[31:0]), + .DOUTPADOUTP(DOP[3:0]), + .ADDRARDADDR(A1ADDR_16), + .CLKARDCLK(CLK2), + .ENARDEN(A1EN), + .ADDRENA(|1), + .REGCEAREGCE(|1), + .RSTRAMARSTRAM(|0), + .RSTREGARSTREG(|0), + .WEA(4'b0), + + .DINBDIN(DI), + .DINPBDINP(DIP), + .DOUTBDOUT(DOBDO), + .DOUTPBDOUTP(DOPBDOP), + .ADDRBWRADDR(B1ADDR_16), + .CLKBWRCLK(CLK3), + .ENBWREN(|1), + .ADDRENB(|1), + .REGCEB(|0), + .RSTRAMB(|0), + .RSTREGB(|0), + .WEBWE(B1EN_8), + + .SLEEP(|0) + ); + end else begin + RAMB36E2 #( + .READ_WIDTH_A(CFG_DBITS), + .READ_WIDTH_B(CFG_DBITS), + .WRITE_WIDTH_A(CFG_DBITS), + .WRITE_WIDTH_B(CFG_DBITS), + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST"), + .DOA_REG(0), + .DOB_REG(0), + .IS_CLKARDCLK_INVERTED(!CLKPOL2), + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + `include "brams_init_32.vh" + ) _TECHMAP_REPLACE_ ( + .DINADIN(32'hFFFFFFFF), + .DINPADINP(4'hF), + .DOUTADOUT(DO[31:0]), + .DOUTPADOUTP(DOP[3:0]), + .ADDRARDADDR(A1ADDR_16), + .CLKARDCLK(CLK2), + .ENARDEN(A1EN), + .ADDRENA(|1), + .REGCEAREGCE(|1), + .RSTRAMARSTRAM(|0), + .RSTREGARSTREG(|0), + .WEA(4'b0), + + .DINBDIN(DI), + .DINPBDINP(DIP), + .DOUTBDOUT(DOBDO), + .DOUTPBDOUTP(DOPBDOP), + .ADDRBWRADDR(B1ADDR_16), + .CLKBWRCLK(CLK3), + .ENBWREN(|1), + .ADDRENB(|1), + .REGCEB(|0), + .RSTRAMB(|0), + .RSTREGB(|0), + .WEBWE(B1EN_8), + + .SLEEP(|0) + ); + end endgenerate +endmodule + +// ------------------------------------------------------------------------ + +module \$__XILINX_RAMB18_TDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CFG_ABITS = 10; + parameter CFG_DBITS = 18; + parameter CFG_ENABLE_B = 2; + + parameter CLKPOL2 = 1; + parameter CLKPOL3 = 1; + parameter [18431:0] INIT = 18432'bx; + + input CLK2; + input CLK3; + + input [CFG_ABITS-1:0] A1ADDR; + output [CFG_DBITS-1:0] A1DATA; + input A1EN; + + input [CFG_ABITS-1:0] B1ADDR; + input [CFG_DBITS-1:0] B1DATA; + input [CFG_ENABLE_B-1:0] B1EN; + + wire [13:0] A1ADDR_14 = A1ADDR << (14 - CFG_ABITS); + wire [13:0] B1ADDR_14 = B1ADDR << (14 - CFG_ABITS); + wire [3:0] B1EN_4 = B1EN; + + wire [1:0] DIP, DOP; + wire [15:0] DI, DO; + + wire [15:0] DOBDO; + wire [1:0] DOPBDOP; + + assign A1DATA = { DOP[1], DO[15: 8], DOP[0], DO[ 7: 0] }; + assign { DIP[1], DI[15: 8], DIP[0], DI[ 7: 0] } = B1DATA; + + generate if (CFG_DBITS > 8) begin + RAMB18E2 #( + .READ_WIDTH_A(CFG_DBITS), + .READ_WIDTH_B(CFG_DBITS), + .WRITE_WIDTH_A(CFG_DBITS), + .WRITE_WIDTH_B(CFG_DBITS), + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST"), + .DOA_REG(0), + .DOB_REG(0), + .IS_CLKARDCLK_INVERTED(!CLKPOL2), + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + `include "brams_init_18.vh" + ) _TECHMAP_REPLACE_ ( + .DINADIN(16'hFFFF), + .DINPADINP(2'b11), + .DOUTADOUT(DO), + .DOUTPADOUTP(DOP), + .ADDRARDADDR(A1ADDR_14), + .CLKARDCLK(CLK2), + .ENARDEN(A1EN), + .ADDRENA(|1), + .REGCEAREGCE(|1), + .RSTRAMARSTRAM(|0), + .RSTREGARSTREG(|0), + .WEA(2'b0), + + .DINBDIN(DI), + .DINPBDINP(DIP), + .DOUTBDOUT(DOBDO), + .DOUTPBDOUTP(DOPBDOP), + .ADDRBWRADDR(B1ADDR_14), + .CLKBWRCLK(CLK3), + .ENBWREN(|1), + .ADDRENB(|1), + .REGCEB(|0), + .RSTRAMB(|0), + .RSTREGB(|0), + .WEBWE(B1EN_4), + + .SLEEP(|0) + ); + end else begin + RAMB18E2 #( + //.RAM_MODE("TDP"), + .READ_WIDTH_A(CFG_DBITS), + .READ_WIDTH_B(CFG_DBITS), + .WRITE_WIDTH_A(CFG_DBITS), + .WRITE_WIDTH_B(CFG_DBITS), + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST"), + .DOA_REG(0), + .DOB_REG(0), + .IS_CLKARDCLK_INVERTED(!CLKPOL2), + .IS_CLKBWRCLK_INVERTED(!CLKPOL3), + `include "brams_init_16.vh" + ) _TECHMAP_REPLACE_ ( + .DINADIN(16'hFFFF), + .DINPADINP(2'b11), + .DOUTADOUT(DO), + .DOUTPADOUTP(DOP), + .ADDRARDADDR(A1ADDR_14), + .CLKARDCLK(CLK2), + .ENARDEN(A1EN), + .ADDRENA(|1), + .REGCEAREGCE(|1), + .RSTRAMARSTRAM(|0), + .RSTREGARSTREG(|0), + .WEA(2'b0), + + .DINBDIN(DI), + .DINPBDINP(DIP), + .DOUTBDOUT(DOBDO), + .DOUTPBDOUTP(DOPBDOP), + .ADDRBWRADDR(B1ADDR_14), + .CLKBWRCLK(CLK3), + .ENBWREN(|1), + .ADDRENB(|1), + .REGCEB(|0), + .RSTRAMB(|0), + .RSTREGB(|0), + .WEBWE(B1EN_4), + + .SLEEP(|0) + ); + end endgenerate +endmodule + diff --git a/techlibs/xilinx/xcu_cells_xtra.v b/techlibs/xilinx/xcu_cells_xtra.v index 4523b5210..3c83e0ef1 100644 --- a/techlibs/xilinx/xcu_cells_xtra.v +++ b/techlibs/xilinx/xcu_cells_xtra.v @@ -8330,412 +8330,6 @@ module FIFO36E2 (...); input WREN; endmodule -module RAMB18E2 (...); - parameter CASCADE_ORDER_A = "NONE"; - parameter CASCADE_ORDER_B = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter integer DOA_REG = 1; - parameter integer DOB_REG = 1; - parameter ENADDRENA = "FALSE"; - parameter ENADDRENB = "FALSE"; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [17:0] INIT_A = 18'h00000; - parameter [17:0] INIT_B = 18'h00000; - parameter INIT_FILE = "NONE"; - parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; - parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; - parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; - parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; - parameter RDADDRCHANGEA = "FALSE"; - parameter RDADDRCHANGEB = "FALSE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [17:0] SRVAL_A = 18'h00000; - parameter [17:0] SRVAL_B = 18'h00000; - parameter WRITE_MODE_A = "NO_CHANGE"; - parameter WRITE_MODE_B = "NO_CHANGE"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output [15:0] CASDOUTA; - output [15:0] CASDOUTB; - output [1:0] CASDOUTPA; - output [1:0] CASDOUTPB; - output [15:0] DOUTADOUT; - output [15:0] DOUTBDOUT; - output [1:0] DOUTPADOUTP; - output [1:0] DOUTPBDOUTP; - input [13:0] ADDRARDADDR; - input [13:0] ADDRBWRADDR; - input ADDRENA; - input ADDRENB; - input CASDIMUXA; - input CASDIMUXB; - input [15:0] CASDINA; - input [15:0] CASDINB; - input [1:0] CASDINPA; - input [1:0] CASDINPB; - input CASDOMUXA; - input CASDOMUXB; - input CASDOMUXEN_A; - input CASDOMUXEN_B; - input CASOREGIMUXA; - input CASOREGIMUXB; - input CASOREGIMUXEN_A; - input CASOREGIMUXEN_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK; - input [15:0] DINADIN; - input [15:0] DINBDIN; - input [1:0] DINPADINP; - input [1:0] DINPBDINP; - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN; - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN; - input REGCEAREGCE; - input REGCEB; - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM; - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB; - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG; - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB; - input SLEEP; - input [1:0] WEA; - input [3:0] WEBWE; -endmodule - -module RAMB36E2 (...); - parameter CASCADE_ORDER_A = "NONE"; - parameter CASCADE_ORDER_B = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter integer DOA_REG = 1; - parameter integer DOB_REG = 1; - parameter ENADDRENA = "FALSE"; - parameter ENADDRENB = "FALSE"; - parameter EN_ECC_PIPE = "FALSE"; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [35:0] INIT_A = 36'h000000000; - parameter [35:0] INIT_B = 36'h000000000; - parameter INIT_FILE = "NONE"; - parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; - parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; - parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; - parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; - parameter RDADDRCHANGEA = "FALSE"; - parameter RDADDRCHANGEB = "FALSE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [35:0] SRVAL_A = 36'h000000000; - parameter [35:0] SRVAL_B = 36'h000000000; - parameter WRITE_MODE_A = "NO_CHANGE"; - parameter WRITE_MODE_B = "NO_CHANGE"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output [31:0] CASDOUTA; - output [31:0] CASDOUTB; - output [3:0] CASDOUTPA; - output [3:0] CASDOUTPB; - output CASOUTDBITERR; - output CASOUTSBITERR; - output DBITERR; - output [31:0] DOUTADOUT; - output [31:0] DOUTBDOUT; - output [3:0] DOUTPADOUTP; - output [3:0] DOUTPBDOUTP; - output [7:0] ECCPARITY; - output [8:0] RDADDRECC; - output SBITERR; - input [14:0] ADDRARDADDR; - input [14:0] ADDRBWRADDR; - input ADDRENA; - input ADDRENB; - input CASDIMUXA; - input CASDIMUXB; - input [31:0] CASDINA; - input [31:0] CASDINB; - input [3:0] CASDINPA; - input [3:0] CASDINPB; - input CASDOMUXA; - input CASDOMUXB; - input CASDOMUXEN_A; - input CASDOMUXEN_B; - input CASINDBITERR; - input CASINSBITERR; - input CASOREGIMUXA; - input CASOREGIMUXB; - input CASOREGIMUXEN_A; - input CASOREGIMUXEN_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK; - input [31:0] DINADIN; - input [31:0] DINBDIN; - input [3:0] DINPADINP; - input [3:0] DINPBDINP; - input ECCPIPECE; - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN; - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN; - input INJECTDBITERR; - input INJECTSBITERR; - input REGCEAREGCE; - input REGCEB; - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM; - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB; - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG; - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB; - input SLEEP; - input [3:0] WEA; - input [7:0] WEBWE; -endmodule - module URAM288 (...); parameter integer AUTO_SLEEP_LATENCY = 8; parameter integer AVG_CONS_INACTIVE_CYCLES = 10; @@ -9767,6 +9361,256 @@ module PLLE4_BASE (...); input RST; endmodule +module MMCME2_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter COMPENSATION = "ZHOLD"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PSEN_INVERTED = 1'b0; + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter SS_EN = "FALSE"; + parameter SS_MODE = "CENTER_HIGH"; + parameter integer SS_MOD_PERIOD = 10000; + parameter STARTUP_WAIT = "FALSE"; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 600.000; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output [15:0] DO; + output DRDY; + output LOCKED; + output PSDONE; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input PSCLK; + (* invertible_pin = "IS_PSEN_INVERTED" *) + input PSEN; + (* invertible_pin = "IS_PSINCDEC_INVERTED" *) + input PSINCDEC; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME2_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; +endmodule + +module PLLE2_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter COMPENSATION = "ZHOLD"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKOUT0_DIVIDE = 1; + parameter integer CLKOUT1_DIVIDE = 1; + parameter integer CLKOUT2_DIVIDE = 1; + parameter integer CLKOUT3_DIVIDE = 1; + parameter integer CLKOUT4_DIVIDE = 1; + parameter integer CLKOUT5_DIVIDE = 1; + parameter integer DIVCLK_DIVIDE = 1; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter real VCOCLK_FREQ_MAX = 2133.000; + parameter real VCOCLK_FREQ_MIN = 800.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 19.000; + parameter real CLKPFD_FREQ_MAX = 550.0; + parameter real CLKPFD_FREQ_MIN = 19.0; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output DRDY; + output LOCKED; + output [15:0] DO; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input DCLK; + input DEN; + input DWE; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input [15:0] DI; + input [6:0] DADDR; +endmodule + +module PLLE2_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output LOCKED; + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; +endmodule + (* keep *) module BSCANE2 (...); parameter DISABLE_JTAG = "FALSE"; -- cgit v1.2.3 From 3506eaf2904cddf5132c598a527e050a79a181d5 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 18 Oct 2019 14:02:57 +0100 Subject: xilinx: Add URAM288 mapping for xcup Signed-off-by: David Shah --- techlibs/xilinx/Makefile.inc | 2 ++ techlibs/xilinx/synth_xilinx.cc | 24 +++++++++++++++++++- techlibs/xilinx/xcu_brams_bb.v | 2 +- techlibs/xilinx/xcup_urams.txt | 19 ++++++++++++++++ techlibs/xilinx/xcup_urams_map.v | 47 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 techlibs/xilinx/xcup_urams.txt create mode 100644 techlibs/xilinx/xcup_urams_map.v diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 6fc41f591..debe8a6a0 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -37,6 +37,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_bb.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 825addf84..69b071d34 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -93,6 +93,9 @@ struct SynthXilinxPass : public ScriptPass log(" -noclkbuf\n"); log(" disable automatic clock buffer insertion\n"); log("\n"); + log(" -uram\n"); + log(" infer URAM288s for large memories (xcup only)\n"); + log("\n"); log(" -widemux \n"); log(" enable inference of hard multiplexer resources (MUXF[78]) for muxes at or\n"); log(" above this number of inputs (minimum value 2, recommended value >= 5).\n"); @@ -119,7 +122,7 @@ struct SynthXilinxPass : public ScriptPass } std::string top_opt, edif_file, blif_file, family; - bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, abc9; + bool flatten, retime, vpr, ise, iopad, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp, uram, abc9; bool flatten_before_abc; int widemux; @@ -143,6 +146,7 @@ struct SynthXilinxPass : public ScriptPass nocarry = false; nowidelut = false; nodsp = false; + uram = false; abc9 = false; flatten_before_abc = false; widemux = 0; @@ -248,6 +252,10 @@ struct SynthXilinxPass : public ScriptPass nodsp = true; continue; } + if (args[argidx] == "-uram") { + uram = true; + continue; + } break; } extra_args(args, argidx, design); @@ -410,6 +418,20 @@ struct SynthXilinxPass : public ScriptPass run("opt_clean"); } + if (check_label("map_uram", "(only if '-uram')")) { + if (help_mode) { + run("memory_bram -rules +/xilinx/{family}_urams.txt"); + run("techmap -map +/xilinx/{family}_urams_map.v"); + } else if (uram) { + if (family == "xcup") { + run("memory_bram -rules +/xilinx/xcup_urams.txt"); + run("techmap -map +/xilinx/xcup_urams_map.v"); + } else { + log_warning("UltraRAM inference not supported for family %s.\n", family.c_str()); + } + } + } + if (check_label("map_bram", "(skip if '-nobram')")) { if (help_mode) { run("memory_bram -rules +/xilinx/{family}_brams.txt"); diff --git a/techlibs/xilinx/xcu_brams_bb.v b/techlibs/xilinx/xcu_brams_bb.v index f3e43d0d6..cc70ce371 100644 --- a/techlibs/xilinx/xcu_brams_bb.v +++ b/techlibs/xilinx/xcu_brams_bb.v @@ -402,4 +402,4 @@ module RAMB36E2 (...); input SLEEP; input [3:0] WEA; input [7:0] WEBWE; -endmodule \ No newline at end of file +endmodule diff --git a/techlibs/xilinx/xcup_urams.txt b/techlibs/xilinx/xcup_urams.txt new file mode 100644 index 000000000..40c474239 --- /dev/null +++ b/techlibs/xilinx/xcup_urams.txt @@ -0,0 +1,19 @@ +bram $__XILINX_URAM288 + init 0 + abits 12 + dbits 72 + groups 2 + ports 1 1 + wrmode 0 1 + enable 1 9 + transp 0 0 + clocks 2 2 + clkpol 2 2 +endbram + +match $__XILINX_URAM288 + min bits 131072 + min efficiency 15 + shuffle_enable B + make_transp +endmatch diff --git a/techlibs/xilinx/xcup_urams_map.v b/techlibs/xilinx/xcup_urams_map.v new file mode 100644 index 000000000..f15211ba3 --- /dev/null +++ b/techlibs/xilinx/xcup_urams_map.v @@ -0,0 +1,47 @@ +module \$__XILINX_URAM288 (CLK2, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + parameter CLKPOL2 = 1; + + input CLK2; + + input [11:0] A1ADDR; + output [71:0] A1DATA; + input A1EN; + + input [11:0] B1ADDR; + input [71:0] B1DATA; + input [8:0] B1EN; + + + URAM288 #( + .BWE_MODE_A("PARITY_INDEPENDENT"), + .BWE_MODE_B("PARITY_INDEPENDENT"), + .EN_AUTO_SLEEP_MODE("FALSE"), + .IREG_PRE_A("FALSE"), + .IREG_PRE_B("FALSE"), + .IS_CLK_INVERTED(!CLKPOL2), + .OREG_A("FALSE"), + .OREG_B("FALSE") + ) _TECHMAP_REPLACE_ ( + .ADDR_A({11'b0, A1ADDR}), + .BWE_A(9'b0), + .DIN_A(72'b0), + .EN_A(A1EN), + .RDB_WR_A(1'b0), + .INJECT_DBITERR_A(1'b0), + .INJECT_SBITERR_A(1'b0), + .RST_A(1'b0), + .DOUT_A(A1DATA), + + .ADDR_B({11'b0, B1ADDR}), + .BWE_B(B1EN), + .DIN_B(B1DATA), + .EN_B(|B1EN), + .RDB_WR_B(1'b1), + .INJECT_DBITERR_B(1'b0), + .INJECT_SBITERR_B(1'b0), + .RST_B(1'b0), + + .CLK(CLK2), + .SLEEP(1'b0) + ); +endmodule -- cgit v1.2.3 From 37dd3ad3fe434243303e11c22831579569324def Mon Sep 17 00:00:00 2001 From: David Shah Date: Sun, 20 Oct 2019 10:24:47 +0100 Subject: ice40: Support for post-pnr timing simulation Signed-off-by: David Shah --- techlibs/ice40/cells_sim.v | 108 ++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 96 insertions(+), 12 deletions(-) diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index f9e79a61d..4e008ed5e 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1,4 +1,4 @@ - +`timescale 1ps / 1ps `define SB_DFF_REG reg Q = 0 // `define SB_DFF_REG reg Q @@ -81,6 +81,37 @@ module SB_IO ( if (PIN_TYPE[5:4] == 2'b11) assign PACKAGE_PIN = outena_q ? dout : 1'bz; endgenerate `endif +`ifdef TIMING +specify + (INPUT_CLK => D_IN_0) = (0:0:0, 0:0:0); + (INPUT_CLK => D_IN_1) = (0:0:0, 0:0:0); + (PACKAGE_PIN => D_IN_0) = (0:0:0, 0:0:0); + (OUTPUT_CLK => PACKAGE_PIN) = (0:0:0, 0:0:0); + (D_OUT_0 => PACKAGE_PIN) = (0:0:0, 0:0:0); + (OUTPUT_ENABLE => PACKAGE_PIN) = (0:0:0, 0:0:0); + + $setuphold(posedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, posedge D_OUT_0, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, negedge D_OUT_0, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, posedge D_OUT_1, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, negedge D_OUT_1, 0:0:0, 0:0:0); + $setuphold(posedge INPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge INPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, posedge CLOCK_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, negedge CLOCK_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0); + $setuphold(posedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0); + $setuphold(negedge INPUT_CLK, posedge PACKAGE_PIN, 0:0:0, 0:0:0); + $setuphold(negedge INPUT_CLK, negedge PACKAGE_PIN, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0); + $setuphold(posedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, posedge OUTPUT_ENABLE, 0:0:0, 0:0:0); + $setuphold(negedge OUTPUT_CLK, negedge OUTPUT_ENABLE, 0:0:0, 0:0:0); +endspecify +`endif endmodule module SB_GB_IO ( @@ -127,6 +158,11 @@ module SB_GB ( output GLOBAL_BUFFER_OUTPUT ); assign GLOBAL_BUFFER_OUTPUT = USER_SIGNAL_TO_GLOBAL_BUFFER; +`ifdef TIMING +specify + (USER_SIGNAL_TO_GLOBAL_BUFFER => GLOBAL_BUFFER_OUTPUT) = (0:0:0, 0:0:0); +endspecify +`endif endmodule // SiliconBlue Logic Cells @@ -830,33 +866,81 @@ module ICESTORM_LC ( parameter [0:0] CIN_CONST = 0; parameter [0:0] CIN_SET = 0; + wire I0_pd = (I0 === 1'bz) ? 1'b0 : I0; + wire I1_pd = (I1 === 1'bz) ? 1'b0 : I1; + wire I2_pd = (I2 === 1'bz) ? 1'b0 : I2; + wire I3_pd = (I3 === 1'bz) ? 1'b0 : I3; + wire SR_pd = (SR === 1'bz) ? 1'b0 : SR; + wire CEN_pu = (CEN === 1'bz) ? 1'b1 : CEN; + wire mux_cin = CIN_CONST ? CIN_SET : CIN; - assign COUT = CARRY_ENABLE ? (I1 && I2) || ((I1 || I2) && mux_cin) : 1'bx; + assign COUT = CARRY_ENABLE ? (I1_pd && I2_pd) || ((I1_pd || I2_pd) && mux_cin) : 1'bx; - wire [7:0] lut_s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0]; - wire [3:0] lut_s2 = I2 ? lut_s3[ 7:4] : lut_s3[3:0]; - wire [1:0] lut_s1 = I1 ? lut_s2[ 3:2] : lut_s2[1:0]; - wire lut_o = I0 ? lut_s1[ 1] : lut_s1[ 0]; + wire [7:0] lut_s3 = I3_pd ? LUT_INIT[15:8] : LUT_INIT[7:0]; + wire [3:0] lut_s2 = I2_pd ? lut_s3[ 7:4] : lut_s3[3:0]; + wire [1:0] lut_s1 = I1_pd ? lut_s2[ 3:2] : lut_s2[1:0]; + wire lut_o = I0_pd ? lut_s1[ 1] : lut_s1[ 0]; assign LO = lut_o; wire polarized_clk; assign polarized_clk = CLK ^ NEG_CLK; - reg o_reg; + reg o_reg = 1'b0; always @(posedge polarized_clk) - if (CEN) - o_reg <= SR ? SET_NORESET : lut_o; + if (CEN_pu) + o_reg <= SR_pd ? SET_NORESET : lut_o; - reg o_reg_async; + reg o_reg_async = 1'b0; always @(posedge polarized_clk, posedge SR) - if (SR) + if (SR_pd) o_reg <= SET_NORESET; - else if (CEN) + else if (CEN_pu) o_reg <= lut_o; assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o; +`ifdef TIMING +specify + (I0 => O) = (0:0:0, 0:0:0); + (I1 => O) = (0:0:0, 0:0:0); + (I2 => O) = (0:0:0, 0:0:0); + (I3 => O) = (0:0:0, 0:0:0); + (I0 => LO) = (0:0:0, 0:0:0); + (I1 => LO) = (0:0:0, 0:0:0); + (I2 => LO) = (0:0:0, 0:0:0); + (I3 => LO) = (0:0:0, 0:0:0); + (I1 => COUT) = (0:0:0, 0:0:0); + (I2 => COUT) = (0:0:0, 0:0:0); + (CIN => COUT) = (0:0:0, 0:0:0); + (CLK => O) = (0:0:0, 0:0:0); + (SR => O) = (0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge I0, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge I0, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge I0, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge I0, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge I1, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge I1, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge I1, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge I1, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge I2, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge I2, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge I2, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge I2, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge I3, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge I3, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge I3, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge I3, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge CEN, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge CEN, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge CEN, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge CEN, 0:0:0, 0:0:0); + $setuphold(posedge CLK, posedge SR, 0:0:0, 0:0:0); + $setuphold(posedge CLK, negedge SR, 0:0:0, 0:0:0); + $setuphold(negedge CLK, posedge SR, 0:0:0, 0:0:0); + $setuphold(negedge CLK, negedge SR, 0:0:0, 0:0:0); +endspecify +`endif endmodule // SiliconBlue PLL Cells -- cgit v1.2.3 From e135ed5d809ae97b0d4d25ff454456aea44af8fc Mon Sep 17 00:00:00 2001 From: David Shah Date: Wed, 23 Oct 2019 18:44:34 +0100 Subject: ice40: Add post-pnr ICESTORM_RAM model and fix FFs Signed-off-by: David Shah --- techlibs/ice40/cells_sim.v | 342 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 340 insertions(+), 2 deletions(-) diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 4e008ed5e..7d1b37fd6 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -895,9 +895,9 @@ module ICESTORM_LC ( reg o_reg_async = 1'b0; always @(posedge polarized_clk, posedge SR) if (SR_pd) - o_reg <= SET_NORESET; + o_reg_async <= SET_NORESET; else if (CEN_pu) - o_reg <= lut_o; + o_reg_async <= lut_o; assign O = DFF_ENABLE ? ASYNC_SR ? o_reg_async : o_reg : lut_o; `ifdef TIMING @@ -1660,3 +1660,341 @@ module SB_MAC16 ( assign LCI = (BOTADDSUB_CARRYSELECT == 0) ? 1'b0 : (BOTADDSUB_CARRYSELECT == 1) ? 1'b1 : (BOTADDSUB_CARRYSELECT == 2) ? ACCUMCI : CI; assign O = {Oh, Ol}; endmodule + +// Post-place-and-route RAM model +module ICESTORM_RAM( + output RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0, + input RCLK, RCLKE, RE, + input RADDR_10, RADDR_9, RADDR_8, RADDR_7, RADDR_6, RADDR_5, RADDR_4, RADDR_3, RADDR_2, RADDR_1, RADDR_0, + input WCLK, WCLKE, WE, + input WADDR_10, WADDR_9, WADDR_8, WADDR_7, WADDR_6, WADDR_5, WADDR_4, WADDR_3, WADDR_2, WADDR_1, WADDR_0, + input MASK_15, MASK_14, MASK_13, MASK_12, MASK_11, MASK_10, MASK_9, MASK_8, MASK_7, MASK_6, MASK_5, MASK_4, MASK_3, MASK_2, MASK_1, MASK_0, + input WDATA_15, WDATA_14, WDATA_13, WDATA_12, WDATA_11, WDATA_10, WDATA_9, WDATA_8, WDATA_7, WDATA_6, WDATA_5, WDATA_4, WDATA_3, WDATA_2, WDATA_1, WDATA_0 +); + parameter WRITE_MODE = 0; + parameter READ_MODE = 0; + + parameter NEG_CLK_R = 1'b0; + parameter NEG_CLK_W = 1'b0; + + parameter INIT_0 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_8 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_9 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + + // Pull-down and pull-up functions + function pd; + input x; + begin + pd = (x === 1'bz) ? 1'b0 : x; + end + endfunction + + function pu; + input x; + begin + pu = (x === 1'bz) ? 1'b1 : x; + end + endfunction + + SB_RAM40_4K #( + .WRITE_MODE(WRITE_MODE), + .READ_MODE (READ_MODE ), + .INIT_0 (INIT_0 ), + .INIT_1 (INIT_1 ), + .INIT_2 (INIT_2 ), + .INIT_3 (INIT_3 ), + .INIT_4 (INIT_4 ), + .INIT_5 (INIT_5 ), + .INIT_6 (INIT_6 ), + .INIT_7 (INIT_7 ), + .INIT_8 (INIT_8 ), + .INIT_9 (INIT_9 ), + .INIT_A (INIT_A ), + .INIT_B (INIT_B ), + .INIT_C (INIT_C ), + .INIT_D (INIT_D ), + .INIT_E (INIT_E ), + .INIT_F (INIT_F ) + ) RAM ( + .RDATA({RDATA_15, RDATA_14, RDATA_13, RDATA_12, RDATA_11, RDATA_10, RDATA_9, RDATA_8, RDATA_7, RDATA_6, RDATA_5, RDATA_4, RDATA_3, RDATA_2, RDATA_1, RDATA_0}), + .RCLK (pd(RCLK) ^ NEG_CLK_R), + .RCLKE(pu(RCLKE)), + .RE (pd(RE)), + .RADDR({pd(RADDR_10), pd(RADDR_9), pd(RADDR_8), pd(RADDR_7), pd(RADDR_6), pd(RADDR_5), pd(RADDR_4), pd(RADDR_3), pd(RADDR_2), pd(RADDR_1), pd(RADDR_0)}), + .WCLK (pd(WCLK) ^ NEG_CLK_W), + .WCLKE(pu(WCLKE)), + .WE (pd(WE)), + .WADDR({pd(WADDR_10), pd(WADDR_9), pd(WADDR_8), pd(WADDR_7), pd(WADDR_6), pd(WADDR_5), pd(WADDR_4), pd(WADDR_3), pd(WADDR_2), pd(WADDR_1), pd(WADDR_0)}), + .MASK ({pd(MASK_15), pd(MASK_14), pd(MASK_13), pd(MASK_12), pd(MASK_11), pd(MASK_10), pd(MASK_9), pd(MASK_8), + pd(MASK_7), pd(MASK_6), pd(MASK_5), pd(MASK_4), pd(MASK_3), pd(MASK_2), pd(MASK_1), pd(MASK_0)}), + .WDATA({pd(WDATA_15), pd(WDATA_14), pd(WDATA_13), pd(WDATA_12), pd(WDATA_11), pd(WDATA_10), pd(WDATA_9), pd(WDATA_8), + pd(WDATA_7), pd(WDATA_6), pd(WDATA_5), pd(WDATA_4), pd(WDATA_3), pd(WDATA_2), pd(WDATA_1), pd(WDATA_0)}) + ); + +`ifdef TIMING +specify + (RCLK => RDATA_15) = (0:0:0, 0:0:0); + (RCLK => RDATA_14) = (0:0:0, 0:0:0); + (RCLK => RDATA_13) = (0:0:0, 0:0:0); + (RCLK => RDATA_12) = (0:0:0, 0:0:0); + (RCLK => RDATA_11) = (0:0:0, 0:0:0); + (RCLK => RDATA_10) = (0:0:0, 0:0:0); + (RCLK => RDATA_9) = (0:0:0, 0:0:0); + (RCLK => RDATA_8) = (0:0:0, 0:0:0); + (RCLK => RDATA_7) = (0:0:0, 0:0:0); + (RCLK => RDATA_6) = (0:0:0, 0:0:0); + (RCLK => RDATA_5) = (0:0:0, 0:0:0); + (RCLK => RDATA_4) = (0:0:0, 0:0:0); + (RCLK => RDATA_3) = (0:0:0, 0:0:0); + (RCLK => RDATA_2) = (0:0:0, 0:0:0); + (RCLK => RDATA_1) = (0:0:0, 0:0:0); + (RCLK => RDATA_0) = (0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RCLKE, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RCLKE, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RCLKE, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RCLKE, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RE, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RE, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RE, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RE, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_10, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_10, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_9, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_9, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_8, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_8, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_7, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_7, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_6, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_6, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_5, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_5, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_4, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_4, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_3, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_3, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_2, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_2, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_1, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_1, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0); + $setuphold(posedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, posedge RADDR_0, 0:0:0, 0:0:0); + $setuphold(negedge RCLK, negedge RADDR_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WCLKE, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WCLKE, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WCLKE, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WCLKE, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WE, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WE, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WE, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WE, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WADDR_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WADDR_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_15, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_15, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_15, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_15, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_14, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_14, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_14, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_14, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_13, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_13, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_13, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_13, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_12, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_12, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_12, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_12, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_11, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_11, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_11, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_11, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge MASK_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge MASK_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge MASK_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge MASK_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_15, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_15, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_14, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_14, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_13, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_13, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_12, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_12, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_11, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_11, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_10, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_10, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_9, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_9, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_8, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_8, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_7, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_7, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_6, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_6, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_5, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_5, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_4, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_4, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_3, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_3, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_2, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_2, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_1, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_1, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0); + $setuphold(posedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, posedge WDATA_0, 0:0:0, 0:0:0); + $setuphold(negedge WCLK, negedge WDATA_0, 0:0:0, 0:0:0); + +endspecify +`endif +endmodule -- cgit v1.2.3 From d49c6b2cba0256573352ae4dd5669e94ef75b60e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Oct 2019 09:14:03 +0200 Subject: Add "verific -L" Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 9f9eeb764..c68390418 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1939,12 +1939,18 @@ struct VerificPass : public Pass { log("Load the specified VHDL files into Verific.\n"); log("\n"); log("\n"); - log(" verific -work {-sv|-vhdl|...} \n"); + log(" verific [-work ] {-sv|-vhdl|...} \n"); log("\n"); log("Load the specified Verilog/SystemVerilog/VHDL file into the specified library.\n"); log("(default library when -work is not present: \"work\")\n"); log("\n"); log("\n"); + log(" verific [-L ] {-sv|-vhdl|...} \n"); + log("\n"); + log("Look up external definitions in the specified library.\n"); + log("(-L may be used more than once)\n"); + log("\n"); + log("\n"); log(" verific -vlog-incdir ..\n"); log("\n"); log("Add Verilog include directories.\n"); @@ -2158,12 +2164,17 @@ struct VerificPass : public Pass { goto check_error; } + veri_file::RemoveAllLOptions(); for (; argidx < GetSize(args); argidx++) { if (args[argidx] == "-work" && argidx+1 < GetSize(args)) { work = args[++argidx]; continue; } + if (args[argidx] == "-L" && argidx+1 < GetSize(args)) { + veri_file::AddLOption(args[++argidx].c_str()); + continue; + } break; } -- cgit v1.2.3 From 84982b308343315c889d3d00116db820a51cad78 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 24 Oct 2019 12:13:37 +0200 Subject: Improve naming scheme for (VHDL) modules imported from Verific Signed-off-by: Clifford Wolf --- frontends/verific/verific.cc | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index c68390418..a5c4aa26a 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -787,7 +787,18 @@ void VerificImporter::merge_past_ffs(pool &candidates) void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::set &nl_todo) { std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name(); - std::string module_name = nl->IsOperator() ? "$verific$" + netlist_name : RTLIL::escape_id(netlist_name); + std::string module_name = netlist_name; + + if (nl->IsOperator()) { + module_name = "$verific$" + module_name; + } else { + if (*nl->Name()) { + module_name += "("; + module_name += nl->Name(); + module_name += ")"; + } + module_name = "\\" + module_name; + } netlist = nl; @@ -1396,8 +1407,20 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se import_verific_cells: nl_todo.insert(inst->View()); - RTLIL::Cell *cell = module->addCell(inst_name, inst->IsOperator() ? - std::string("$verific$") + inst->View()->Owner()->Name() : RTLIL::escape_id(inst->View()->Owner()->Name())); + std::string inst_type = inst->View()->Owner()->Name(); + + if (inst->View()->IsOperator()) { + inst_type = "$verific$" + inst_type; + } else { + if (*inst->View()->Name()) { + inst_type += "("; + inst_type += inst->View()->Name(); + inst_type += ")"; + } + inst_type = "\\" + inst_type; + } + + RTLIL::Cell *cell = module->addCell(inst_name, inst_type); if (inst->IsPrimitive() && mode_keep) cell->attributes["\\keep"] = 1; -- cgit v1.2.3 From 8226f2db0b65dffb59c4420de96dccd2e0be36ed Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Thu, 24 Oct 2019 13:39:43 +0200 Subject: ALU sim tweaks --- techlibs/gowin/cells_sim.v | 22 +++++++++++----------- tests/arch/gowin/mux.ys | 4 ++-- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 8280982d6..9dac2c2c2 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -280,16 +280,16 @@ input CIN; output SUM; output COUT; -parameter ADD = 0; -parameter SUB = 1; -parameter ADDSUB = 2; -parameter NE = 3; -parameter GE = 4; -parameter LE = 5; -parameter CUP = 6; -parameter CDN = 7; -parameter CUPCDN = 8; -parameter MULT = 9; +localparam ADD = 0; +localparam SUB = 1; +localparam ADDSUB = 2; +localparam NE = 3; +localparam GE = 4; +localparam LE = 5; +localparam CUP = 6; +localparam CDN = 7; +localparam CUPCDN = 8; +localparam MULT = 9; parameter ALU_MODE = 0; @@ -298,7 +298,7 @@ reg S, C; assign SUM = S ^ CIN; assign COUT = S? CIN : C; -always @(I0, I1, I3,CIN) begin +always @* begin case (ALU_MODE) ADD: begin S = I0 ^ I1; diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index c9c85019b..d612e4eaa 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -42,8 +42,8 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 9 t:LUT4 -select -assert-count 3 t:LUT3 +select -assert-count 10 t:LUT4 +select -assert-count 1 t:LUT3 select -assert-count 20 t:IBUF select -assert-count 1 t:OBUF -- cgit v1.2.3 From 5fad53b504a7ac05fb959f0ca84829bd550aac47 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 10:33:27 +0100 Subject: add 32-bit BRAM and byte-enables --- techlibs/gowin/bram.txt | 7 +++++-- techlibs/gowin/brams_map.v | 22 ++++++++++++++++++++-- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/techlibs/gowin/bram.txt b/techlibs/gowin/bram.txt index 366a7106e..e406f9c51 100644 --- a/techlibs/gowin/bram.txt +++ b/techlibs/gowin/bram.txt @@ -1,5 +1,7 @@ bram $__GW1NR_SDP init 1 + abits 9 @a9d36 + dbits 32 @a9d36 abits 10 @a10d18 dbits 16 @a10d18 abits 11 @a11d9 @@ -13,7 +15,8 @@ bram $__GW1NR_SDP groups 2 ports 1 1 wrmode 1 0 - enable 1 1 @a10d18 + enable 4 1 @a9d36 + enable 2 1 @a10d18 enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 transp 0 0 clocks 2 3 @@ -23,6 +26,6 @@ endbram match $__GW1NR_SDP min bits 2048 min efficiency 5 - shuffle_enable B + shuffle_enable A make_transp endmatch diff --git a/techlibs/gowin/brams_map.v b/techlibs/gowin/brams_map.v index 6c5e4733a..fbebc4af8 100644 --- a/techlibs/gowin/brams_map.v +++ b/techlibs/gowin/brams_map.v @@ -109,12 +109,30 @@ module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); .RESET_MODE("SYNC") ) _TECHMAP_REPLACE_ ( .CLKA(CLK2), .CLKB(CLK3), - .WREA(A1EN), .OCE(1'b0), + .WREA(|A1EN), .OCE(1'b0), .WREB(1'b0), .CEB(B1EN), .CEA(1'b1), .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), .DI({{(32-CFG_DBITS){1'b0}}, A1DATA}), .DO({open, B1DATA}), - .ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, 2'b11}), + .ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, A1EN}), + .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) + ); + end else if (CFG_DBITS <= 32) begin + SDP #( + `include "bram_init_16.vh" + .READ_MODE(0), + .BIT_WIDTH_0(32), + .BIT_WIDTH_1(32), + .BLK_SEL(3'b000), + .RESET_MODE("SYNC") + ) _TECHMAP_REPLACE_ ( + .CLKA(CLK2), .CLKB(CLK3), + .WREA(|A1EN), .OCE(1'b0), + .WREB(1'b0), .CEB(B1EN), .CEA(1'b1), + .RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000), + .DI(A1DATA), + .DO(B1DATA), + .ADA({A1ADDR, {(10-CFG_ABITS){1'b0}}, A1EN}), .ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}}) ); end else begin -- cgit v1.2.3 From f88335a8a5284a8e69230ec20eeeca6c02b055bf Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 12:49:08 +0100 Subject: add wide luts --- techlibs/gowin/cells_map.v | 24 +++++++++++ techlibs/gowin/cells_sim.v | 35 ++++++++++++++++ techlibs/gowin/synth_gowin.cc | 96 +++++++++++++++++++++++++++---------------- 3 files changed, 119 insertions(+), 36 deletions(-) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index 425cf7f59..62cb080d9 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -101,6 +101,30 @@ module \$lut (A, Y); if (WIDTH == 4) begin LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y), .I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3])); + end else + if (WIDTH == 5) begin + wire f0, f1; + \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0)); + \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1)); + MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y)); + end else + if (WIDTH == 6) begin + wire f0, f1; + \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0)); + \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1)); + MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y)); + end else + if (WIDTH == 7) begin + wire f0, f1; + \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0)); + \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1)); + MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y)); + end else + if (WIDTH == 8) begin + wire f0, f1; + \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0)); + \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1)); + MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y)); end else begin wire _TECHMAP_FAIL_ = 1; end diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 9dac2c2c2..0fe2c8c52 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -24,6 +24,41 @@ module LUT4(output F, input I0, I1, I2, I3); assign F = I0 ? s1[1] : s1[0]; endmodule +module MUX2 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + assign O = S0 ? I1 : I0; +endmodule + +module MUX2_LUT5 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + MUX2 mux2_lut5 (O, I0, I1, S0); +endmodule + +module MUX2_LUT6 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + MUX2 mux2_lut6 (O, I0, I1, S0); +endmodule + +module MUX2_LUT7 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + MUX2 mux2_lut7 (O, I0, I1, S0); +endmodule + +module MUX2_LUT8 (O, I0, I1, S0); + input I0,I1; + input S0; + output O; + MUX2 mux2_lut8 (O, I0, I1, S0); +endmodule + module DFF (output reg Q, input CLK, D); parameter [0:0] INIT = 1'b0; initial Q = INIT; diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index e93225fab..89cbc50ab 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -1,19 +1,19 @@ /* - * yosys -- Yosys Open SYnthesis Suite + * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2012 Clifford Wolf * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ @@ -31,38 +31,44 @@ struct SynthGowinPass : public ScriptPass void help() YS_OVERRIDE { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" synth_gowin [options]\n"); + log(" synth_gowin [options]\n"); log("\n"); log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); log("\n"); - log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); + log(" -top \n"); + log(" use the specified module as top module (default='top')\n"); log("\n"); - log(" -vout \n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); + log(" -vout \n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -71,7 +77,7 @@ struct SynthGowinPass : public ScriptPass } string top_opt, vout_file; - bool retime, nobram, nodram, flatten, nodffe; + bool retime, nobram, nodram, flatten, nodffe, nowidelut, abc9; void clear_flags() YS_OVERRIDE { @@ -82,6 +88,8 @@ struct SynthGowinPass : public ScriptPass nobram = false; nodffe = false; nodram = false; + nowidelut = false; + abc9 = false; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -128,6 +136,14 @@ struct SynthGowinPass : public ScriptPass flatten = false; continue; } + if (args[argidx] == "-nowidelut") { + nowidelut = true; + continue; + } + if (args[argidx] == "-abc9") { + abc9 = true; + continue; + } break; } extra_args(args, argidx, design); @@ -164,7 +180,7 @@ struct SynthGowinPass : public ScriptPass run("synth -run coarse"); } - if (!nobram && check_label("bram", "(skip if -nobram)")) + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/gowin/bram.txt"); run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v"); @@ -203,7 +219,15 @@ struct SynthGowinPass : public ScriptPass if (check_label("map_luts")) { - run("abc -lut 4"); + if (nowidelut && abc9) { + run("abc9 -lut 4"); + } else if (nowidelut && !abc9) { + run("abc -lut 4"); + } else if (!nowidelut && abc9) { + run("abc9 -lut 4:8"); + } else if (!nowidelut && !abc9) { + run("abc -lut 4:8"); + } run("clean"); } -- cgit v1.2.3 From 293b2c2de5c127d860d9ce0c7ac98908fa053520 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 12:57:12 +0100 Subject: undo formatting fuckup --- techlibs/gowin/synth_gowin.cc | 50 +++++++++++++++++++++---------------------- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index 89cbc50ab..a44bbe2f6 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -33,42 +33,42 @@ struct SynthGowinPass : public ScriptPass { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - log(" synth_gowin [options]\n"); + log(" synth_gowin [options]\n"); log("\n"); log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); log("\n"); - log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); + log(" -top \n"); + log(" use the specified module as top module (default='top')\n"); log("\n"); - log(" -vout \n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); + log(" -vout \n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); log("\n"); - log(" -nowidelut\n"); - log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -237,7 +237,7 @@ struct SynthGowinPass : public ScriptPass run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); + run("dffinit -ff DFF Q INIT"); run("clean"); } -- cgit v1.2.3 From c1921b45619fbca4cbcafe3cd9cfdc0fe29e251c Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 13:01:20 +0100 Subject: really really fix formatting maybe --- techlibs/gowin/synth_gowin.cc | 82 +++++++++++++++++++++---------------------- 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index a44bbe2f6..a95d81bfd 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -32,46 +32,46 @@ struct SynthGowinPass : public ScriptPass void help() YS_OVERRIDE { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" synth_gowin [options]\n"); - log("\n"); - log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); - log("\n"); - log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); - log("\n"); - log(" -vout \n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); - log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); - log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); - log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); - log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); - log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); - log("\n"); - log(" -nowidelut\n"); - log(" do not use muxes to implement LUTs larger than LUT4s\n"); - log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); - log("\n"); - log("\n"); - log("The following commands are executed by this synthesis command:\n"); + log("\n"); + log(" synth_gowin [options]\n"); + log("\n"); + log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module (default='top')\n"); + log("\n"); + log(" -vout \n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); + log("\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } @@ -237,7 +237,7 @@ struct SynthGowinPass : public ScriptPass run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); + run("dffinit -ff DFF Q INIT"); run("clean"); } -- cgit v1.2.3 From 2f5e9e9885df0011a3b70b0ab64f54fcd33ce347 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 13:10:12 +0100 Subject: More formatting --- techlibs/gowin/synth_gowin.cc | 104 ++++++++++++++++++++---------------------- 1 file changed, 49 insertions(+), 55 deletions(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index a95d81bfd..e9b2ccded 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -1,19 +1,19 @@ /* - * yosys -- Yosys Open SYnthesis Suite + * yosys -- Yosys Open SYnthesis Suite * - * Copyright (C) 2012 Clifford Wolf + * Copyright (C) 2012 Clifford Wolf * - * Permission to use, copy, modify, and/or distribute this software for any - * purpose with or without fee is hereby granted, provided that the above - * copyright notice and this permission notice appear in all copies. + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. * - * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES - * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR - * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES - * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN - * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF - * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * */ @@ -31,47 +31,41 @@ struct SynthGowinPass : public ScriptPass void help() YS_OVERRIDE { - // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| - log("\n"); - log(" synth_gowin [options]\n"); - log("\n"); - log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); - log("\n"); - log(" -top \n"); - log(" use the specified module as top module (default='top')\n"); - log("\n"); - log(" -vout \n"); - log(" write the design to the specified Verilog netlist file. writing of an\n"); - log(" output file is omitted if this parameter is not specified.\n"); - log("\n"); - log(" -run :\n"); - log(" only run the commands between the labels (see below). an empty\n"); - log(" from label is synonymous to 'begin', and empty to label is\n"); - log(" synonymous to the end of the command list.\n"); - log("\n"); - log(" -nodffe\n"); - log(" do not use flipflops with CE in output netlist\n"); - log("\n"); - log(" -nobram\n"); - log(" do not use BRAM cells in output netlist\n"); - log("\n"); - log(" -nodram\n"); - log(" do not use distributed RAM cells in output netlist\n"); - log("\n"); - log(" -noflatten\n"); - log(" do not flatten design before synthesis\n"); - log("\n"); - log(" -retime\n"); - log(" run 'abc' with -dff option\n"); - log("\n"); - log(" -nowidelut\n"); - log(" do not use muxes to implement LUTs larger than LUT4s\n"); - log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); - log("\n"); - log("\n"); - log("The following commands are executed by this synthesis command:\n"); + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" synth_gowin [options]\n"); + log("\n"); + log("This command runs synthesis for Gowin FPGAs. This work is experimental.\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module (default='top')\n"); + log("\n"); + log(" -vout \n"); + log(" write the design to the specified Verilog netlist file. writing of an\n"); + log(" output file is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -run :\n"); + log(" only run the commands between the labels (see below). an empty\n"); + log(" from label is synonymous to 'begin', and empty to label is\n"); + log(" synonymous to the end of the command list.\n"); + log("\n"); + log(" -nodffe\n"); + log(" do not use flipflops with CE in output netlist\n"); + log("\n"); + log(" -nobram\n"); + log(" do not use BRAM cells in output netlist\n"); + log("\n"); + log(" -nodram\n"); + log(" do not use distributed RAM cells in output netlist\n"); + log("\n"); + log(" -noflatten\n"); + log(" do not flatten design before synthesis\n"); + log("\n"); + log(" -retime\n"); + log(" run 'abc' with -dff option\n"); + log("\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } @@ -180,7 +174,7 @@ struct SynthGowinPass : public ScriptPass run("synth -run coarse"); } - if (!nobram && check_label("bram", "(skip if -nobram)")) + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/gowin/bram.txt"); run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v"); @@ -237,7 +231,7 @@ struct SynthGowinPass : public ScriptPass run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); + run("dffinit -ff DFF Q INIT"); run("clean"); } -- cgit v1.2.3 From 4ec4d5ec7e6c70c50c513de93c1d478ff76d8298 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 14:28:03 +0100 Subject: actually run the gowin tests --- Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/Makefile b/Makefile index 845a97b50..6e7681cf3 100644 --- a/Makefile +++ b/Makefile @@ -718,6 +718,7 @@ test: $(TARGETS) $(EXTRA_TARGETS) +cd tests/arch/ecp5 && bash run-test.sh $(SEEDOPT) +cd tests/arch/efinix && bash run-test.sh $(SEEDOPT) +cd tests/arch/anlogic && bash run-test.sh $(SEEDOPT) + +cd tests/arch/gowin && bash run-test.sh $(SEEDOPT) +cd tests/rpc && bash run-test.sh @echo "" @echo " Passed \"make test\"." -- cgit v1.2.3 From 9517525224c7bc4b8ac7d093066485888a337b76 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 14:40:12 +0100 Subject: do not use wide luts in testcase --- tests/arch/gowin/mux.ys | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index d612e4eaa..1cb3d53e6 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -15,7 +15,7 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module select -assert-count 2 t:LUT4 @@ -27,7 +27,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 5 t:LUT4 @@ -39,7 +39,7 @@ select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 10 t:LUT4 -- cgit v1.2.3 From 903f9973913371452005eb173ac50fec1d5d1447 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 15:18:01 +0100 Subject: add tristate buffer and test --- techlibs/gowin/cells_sim.v | 6 ++++++ techlibs/gowin/synth_gowin.cc | 4 ++-- tests/arch/gowin/tribuf.ys | 13 +++++++++++++ 3 files changed, 21 insertions(+), 2 deletions(-) create mode 100644 tests/arch/gowin/tribuf.ys diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 0fe2c8c52..cc1ac48e6 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -302,6 +302,12 @@ module OBUF(output O, input I); assign O = I; endmodule +module TBUF (O, I, OEN); + input I, OEN; + output O; + assign O = OEN ? I : 1'bz; +endmodule + module GSR (input GSRI); wire GSRO = GSRI; endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index e9b2ccded..d541edd84 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -174,7 +174,7 @@ struct SynthGowinPass : public ScriptPass run("synth -run coarse"); } - if (!nobram && check_label("bram", "(skip if -nobram)")) + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/gowin/bram.txt"); run("techmap -map +/gowin/brams_map.v -map +/gowin/cells_sim.v"); @@ -230,7 +230,7 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/gowin/cells_map.v"); run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); - run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O", "(unless -noiopads)"); + run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); run("clean"); diff --git a/tests/arch/gowin/tribuf.ys b/tests/arch/gowin/tribuf.ys new file mode 100644 index 000000000..5855b9d97 --- /dev/null +++ b/tests/arch/gowin/tribuf.ys @@ -0,0 +1,13 @@ +read_verilog ../common/tribuf.v +hierarchy -top tristate +proc +tribuf +flatten +synth +equiv_opt -assert -map +/gowin/cells_sim.v -map +/simcells.v synth_gowin # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd tristate # Constrain all select calls below inside the top module +#Internal cell type used. Need support it. +select -assert-count 1 t:TBUF +select -assert-count 2 t:IBUF +select -assert-none t:TBUF t:IBUF %% t:* %D -- cgit v1.2.3 From 0f6269b04c4a5f44b62021759507bcbe61a7c8d7 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 28 Oct 2019 15:33:05 +0100 Subject: add IOBUF --- techlibs/gowin/cells_sim.v | 8 ++++++++ techlibs/gowin/synth_gowin.cc | 3 ++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index cc1ac48e6..a67855dab 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -308,6 +308,14 @@ module TBUF (O, I, OEN); assign O = OEN ? I : 1'bz; endmodule +module IOBUF (O, IO, I, OEN); + input I,OEN; + output O; + inout IO; + assign IO = OEN ? I : 1'bz; + assign I = IO; +endmodule + module GSR (input GSRI); wire GSRO = GSRI; endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index d541edd84..a70ff93bb 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -230,7 +230,8 @@ struct SynthGowinPass : public ScriptPass run("techmap -map +/gowin/cells_map.v"); run("setundef -undriven -params -zero"); run("hilomap -singleton -hicell VCC V -locell GND G"); - run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O, -toutpad TBUF OEN:I:O", "(unless -noiopads)"); + run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " + "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)"); run("dffinit -ff DFF Q INIT"); run("clean"); -- cgit v1.2.3 From df8390f5df9868b583ce88a4d2ce41511fab2f7b Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 30 Oct 2019 14:58:25 +0100 Subject: don't cound exact luts in big muxes; futile and fragile --- tests/arch/gowin/mux.ys | 3 --- 1 file changed, 3 deletions(-) diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index 1cb3d53e6..f7e478c87 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -30,7 +30,6 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 5 t:LUT4 select -assert-count 11 t:IBUF select -assert-count 1 t:OBUF @@ -42,8 +41,6 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module -select -assert-count 10 t:LUT4 -select -assert-count 1 t:LUT3 select -assert-count 20 t:IBUF select -assert-count 1 t:OBUF -- cgit v1.2.3 From c3ad37520044d3de12fd1b3acc723cca75c3bb94 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 31 Oct 2019 10:46:20 +0100 Subject: Add CodingReadme section on script passes Signed-off-by: Clifford Wolf --- CodingReadme | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/CodingReadme b/CodingReadme index 8212436e5..7d4ded93d 100644 --- a/CodingReadme +++ b/CodingReadme @@ -202,6 +202,52 @@ of how to use the Yosys API: manual/PRESENTATION_Prog/my_cmd.cc +Script Passes +------------- + +The ScriptPass base class can be used to implement passes that just call other passes, +like a script. Examples for such passes are: + + techlibs/common/prep.cc + techlibs/common/synth.cc + +In some cases it is easier to implement such a pass as regular pass, for example when +ScriptPass doesn't provide the type of flow control desired. (But many of the +script passes in Yosys that don't use ScriptPass simply predate the ScriptPass base +class.) Examples for such passes are: + + passes/opt/opt.cc + passes/proc/proc.cc + +Whether they use the ScriptPass base-class or not, a pass should always either +call other passes without doing any non-trivial work itself, or should implement +a non-trivial algorithm but not call any other passes. The reason for this is that +this helps containing complexity in individual passes and simplifies debugging the +entire system. + +Exceptions to this rule should be rare and limited to cases where calling other +passes is optional and only happens when requested by the user (such as for +example `techmap -autoproc`), or where it is about commands that are "top-level +commands" in their own right, not components to be used in regular synthesis +flows (such as the `bugpoint` command). + +A pass that would "naturally" call other passes and also do some work itself +should be re-written in one of two ways: + +1) It could be re-written as script pass with the parts that are not calls +to other passes factored out into individual new passes. Usually in those +cases the new sub passes share the same prefix as the top-level script pass. + +2) It could be re-written so that it already expects the design in a certain +state, expecting the calling script to set up this state before calling the +pass in questions. + +Many back-ends are examples for the 2nd approach. For example, `write_aiger` +does not convert the design into AIG representation, but expects the design +to be already in this form, and prints an `Unsupported cell type` error +message otherwise. + + Notes on the existing codebase ------------------------------ -- cgit v1.2.3 From 5110a34dd74bc96c47d4aef47bc155110de2d87e Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 4 Nov 2019 14:25:13 +0100 Subject: Fix write_aiger bug added in 524af21 Signed-off-by: Clifford Wolf --- backends/aiger/aiger.cc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 3e8b14dee..44718baae 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -91,6 +91,9 @@ struct AigerWriter } else if (alias_map.count(bit)) { a = bit2aig(alias_map.at(bit)); + } else + if (initstate_bits.count(bit)) { + a = initstate_ff; } if (bit == State::Sx || bit == State::Sz) -- cgit v1.2.3 From c4bd318e76240d3e6a95109c19641cdfd86517b8 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Fri, 1 Nov 2019 14:00:15 +0000 Subject: synth_xilinx: Merge blackbox primitive libraries. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit First, there are no longer separate cell libraries for xc6s/xc7/xcu. Manually instantiating a primitive for a "wrong" family will result in yosys passing it straight through to the output, and it will be either upgraded or rejected by the P&R tool. Second, the blackbox library is expanded to cover many more families: everything from Spartan 3 up is included. Primitives for Virtex and Virtex 2 are listed in the Python file as well if we ever want to include them, but that would require having two different ISE versions (10.1 and 14.7) available when running cells_xtra.py, and so is probably more trouble than it's worth. Third, the blockram blackboxes are no longer in separate files — there is no practical reason to do so (from synthesis PoV, they are no different from any other cells_xtra blackbox), and they needlessly complicated the flow (among other things, merging them allows the user to use eg. Series 7 primitives and have them auto-upgraded to Ultrascale). Last, since xc5v logic synthesis appears to work reasonably well (the only major problem is lack of blockram inference support), xc5v is now an accepted setting for the -family option. --- techlibs/xilinx/Makefile.inc | 8 +- techlibs/xilinx/cells_xtra.py | 1017 +- techlibs/xilinx/cells_xtra.v | 29339 ++++++++++++++++++++++++++++++++++++ techlibs/xilinx/synth_xilinx.cc | 25 +- techlibs/xilinx/xc6s_brams_bb.v | 223 - techlibs/xilinx/xc6s_cells_xtra.v | 1819 --- techlibs/xilinx/xc6v_cells_xtra.v | 2592 ---- techlibs/xilinx/xc7_brams_bb.v | 349 - techlibs/xilinx/xc7_cells_xtra.v | 5717 ------- techlibs/xilinx/xcu_brams_bb.v | 405 - techlibs/xilinx/xcu_cells_xtra.v | 11612 -------------- 11 files changed, 29846 insertions(+), 23260 deletions(-) create mode 100644 techlibs/xilinx/cells_xtra.v delete mode 100644 techlibs/xilinx/xc6s_brams_bb.v delete mode 100644 techlibs/xilinx/xc6s_cells_xtra.v delete mode 100644 techlibs/xilinx/xc6v_cells_xtra.v delete mode 100644 techlibs/xilinx/xc7_brams_bb.v delete mode 100644 techlibs/xilinx/xc7_cells_xtra.v delete mode 100644 techlibs/xilinx/xcu_brams_bb.v delete mode 100644 techlibs/xilinx/xcu_cells_xtra.v diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index debe8a6a0..3ebc72fe8 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -25,18 +25,12 @@ techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_cells_xtra.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6v_cells_xtra.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_cells_xtra.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcup_urams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index 7cf1162bd..ef7ce856a 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -15,565 +15,560 @@ class Cell: self.port_attrs = port_attrs -XC6S_CELLS = [ - # Design elements types listed in Xilinx UG615. - - # Advanced. - Cell('MCB'), - Cell('PCIE_A1'), - - # Arithmetic functions. - Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), - - # Clock components. - # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), - Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), - Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}), - Cell('DCM_CLKGEN'), - Cell('DCM_SP'), - Cell('PLL_BASE'), - - # Config/BSCAN components. - Cell('BSCAN_SPARTAN6', keep=True), - Cell('DNA_PORT'), - Cell('ICAP_SPARTAN6', keep=True), - Cell('POST_CRC_INTERNAL'), - Cell('STARTUP_SPARTAN6', keep=True), - Cell('SUSPEND_SYNC', keep=True), - - # I/O components. - Cell('GTPA1_DUAL'), - # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), - Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), - Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), - Cell('ISERDES2', port_attrs={ - 'CLK0': ['clkbuf_sink'], - 'CLK1': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - Cell('KEEPER'), - # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), - Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), - Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OSERDES2', port_attrs={ - 'CLK0': ['clkbuf_sink'], - 'CLK1': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - Cell('PULLDOWN'), - Cell('PULLUP'), - - # RAM/ROM. - #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - # NOTE: not in the official library guide! - Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), +CELLS = [ + # Design element types listed in: + # - UG607 (Spartan 3) + # - UG613 (Spartan 3A) + # - UG617 (Spartan 3E) + # - UG615 (Spartan 6) + # - UG619 (Virtex 4) + # - UG621 (Virtex 5) + # - UG623 (Virtex 6) + # - UG953 (Series 7) + # - UG974 (Ultrascale) + + # CLB -- RAM/ROM. + Cell('RAM16X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM16X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # NOTE: not in the official library guide! - Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAMB8BWER', port_attrs={'CLKAWRCLK': ['clkbuf_sink'], 'CLKBRDCLK': ['clkbuf_sink']}), - # Cell('RAMB16BWER', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), - Cell('ROM128X1'), - Cell('ROM256X1'), - Cell('ROM32X1'), - Cell('ROM64X1'), - - # Registers/latches. - # Cell('FDCE'), - # Cell('FDPE'), - # Cell('FDRE'), - # Cell('FDSE'), - Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), - # Cell('LDCE'), - # Cell('LDPE'), - Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), - - # Slice/CLB primitives. - # Cell('CARRY4'), - Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('LUT1'), - # Cell('LUT2'), - # Cell('LUT3'), - # Cell('LUT4'), - # Cell('LUT5'), - # Cell('LUT6'), - # Cell('LUT6_2'), - # Cell('MUXF7'), - # Cell('MUXF8'), - # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}), -] - - -XC6V_CELLS = [ - # Design elements types listed in Xilinx UG623. - - # Advanced. - Cell('PCIE_2_0'), - Cell('SYSMON'), - - # Arithmetic functions. - #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), - - # Clock components. - # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}), - #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}), - #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}), - Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('MMCM_ADV'), - Cell('MMCM_BASE'), - - # Config/BSCAN components. - Cell('BSCAN_VIRTEX6', keep=True), - Cell('CAPTURE_VIRTEX6', keep=True), - Cell('DNA_PORT'), - Cell('EFUSE_USR'), - Cell('FRAME_ECC_VIRTEX6'), - Cell('ICAP_VIRTEX6', keep=True), - Cell('STARTUP_VIRTEX6', keep=True), - Cell('USR_ACCESS_VIRTEX6'), - - # I/O components. - Cell('DCIRESET', keep=True), - Cell('GTHE1_QUAD'), - Cell('GTXE1'), - # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), - Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}), - Cell('ISERDESE1', port_attrs={ - 'CLK': ['clkbuf_sink'], - 'CLKB': ['clkbuf_sink'], - 'OCLK': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - Cell('KEEPER'), - # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), - Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), - Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), - Cell('PULLDOWN'), - Cell('PULLUP'), - Cell('TEMAC_SINGLE'), - - # RAM/ROM. - Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM128X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM16X2S', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # NOTE: not in the official library guide! Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - Cell('ROM128X1'), - Cell('ROM256X1'), - Cell('ROM32X1'), - Cell('ROM64X1'), - - # Registers/latches. - # Cell('FDCE'), - # Cell('FDPE'), - # Cell('FDRE'), - # Cell('FDSE'), - Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), - Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - # Cell('LDCE'), - # Cell('LDPE'), - Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), - - # Slice/CLB primitives. - # Cell('CARRY4'), - Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('LUT1'), - # Cell('LUT2'), - # Cell('LUT3'), - # Cell('LUT4'), - # Cell('LUT5'), - # Cell('LUT6'), - # Cell('LUT6_2'), - # Cell('MUXF7'), - # Cell('MUXF8'), - # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}), -] - - -XC7_CELLS = [ - # Design elements types listed in Xilinx UG953. - - # Advanced. - Cell('GTHE2_CHANNEL'), - Cell('GTHE2_COMMON'), - Cell('GTPE2_CHANNEL'), - Cell('GTPE2_COMMON'), - Cell('GTXE2_CHANNEL'), - Cell('GTXE2_COMMON'), - Cell('PCIE_2_1'), - Cell('PCIE_3_0'), - Cell('XADC'), - - # Arithmetic functions. - #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), - - # Clock components. - # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}), - #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}), - #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}), - Cell('MMCME2_ADV'), - Cell('MMCME2_BASE'), - Cell('PLLE2_ADV'), - Cell('PLLE2_BASE'), - - # Config/BSCAN components. - Cell('BSCANE2', keep=True), - Cell('CAPTUREE2', keep=True), - Cell('DNA_PORT'), - Cell('EFUSE_USR'), - Cell('FRAME_ECCE2'), - Cell('ICAPE2', keep=True), - Cell('STARTUPE2', keep=True), - Cell('USR_ACCESSE2'), - - # I/O components. - Cell('DCIRESET', keep=True), - # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), - Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}), - Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('ISERDESE2', port_attrs={ - 'CLK': ['clkbuf_sink'], - 'CLKB': ['clkbuf_sink'], - 'OCLK': ['clkbuf_sink'], - 'OCLKB': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - 'CLKDIVP': ['clkbuf_sink'], - }), - Cell('KEEPER'), - # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), - Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), - Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}), - Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), - Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('PHASER_IN'), - Cell('PHASER_IN_PHY'), - Cell('PHASER_OUT'), - Cell('PHASER_OUT_PHY'), - Cell('PHASER_REF'), - Cell('PHY_CONTROL'), - Cell('PULLDOWN'), - Cell('PULLUP'), - - # RAM/ROM. - Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM16X4S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM32X4S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM16X8S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM32X8S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM16X1D', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM16X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('RAM32X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S_1', port_attrs={'WCLK': ['clkbuf_sink']}), - # NOTE: not in the official library guide! - Cell('RAM64X2S', port_attrs={'WCLK': ['clkbuf_sink']}), - # Cell('RAMB18E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - # Cell('RAMB36E1', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - Cell('ROM128X1'), - Cell('ROM256X1'), - Cell('ROM32X1'), - Cell('ROM64X1'), - - # Registers/latches. - # Cell('FDCE'), - # Cell('FDPE'), - # Cell('FDRE'), - # Cell('FDSE'), - Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), - Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - # Cell('LDCE'), - # Cell('LDPE'), - Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), - - # Slice/CLB primitives. - # Cell('CARRY4'), - Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('LUT1'), - # Cell('LUT2'), - # Cell('LUT3'), - # Cell('LUT4'), - # Cell('LUT5'), - # Cell('LUT6'), - # Cell('LUT6_2'), - # Cell('MUXF7'), - # Cell('MUXF8'), - # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}), - # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}), - - # NOTE: not in the official library guide! - Cell('PS7', keep=True), -] - - -XCU_CELLS = [ - # Design elements types listed in Xilinx UG974. - - # Advanced. - Cell('CMAC'), - Cell('CMACE4'), - Cell('GTHE3_CHANNEL'), - Cell('GTHE3_COMMON'), - Cell('GTHE4_CHANNEL'), - Cell('GTHE4_COMMON'), - Cell('GTYE3_CHANNEL'), - Cell('GTYE3_COMMON'), - Cell('GTYE4_CHANNEL'), - Cell('GTYE4_COMMON'), - Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('ILKN'), - Cell('ILKNE4'), - Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('PCIE40E4'), - Cell('PCIE_3_1'), - Cell('SYSMONE1'), - Cell('SYSMONE4'), - - # Arithmetic functions. - Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}), - - # Blockram. - Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), - #Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - #Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), - - # CLB. - # Cell('LUT6_2'), + Cell('RAM64X1D_1', port_attrs={'WCLK': ['clkbuf_sink']}), #Cell('RAM128X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM128X1S', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM256X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM256X1S', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM32M', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM32M16', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM32X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM32X1S', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM512X1S', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM64M', port_attrs={'WCLK': ['clkbuf_sink']}), Cell('RAM64M8', port_attrs={'WCLK': ['clkbuf_sink']}), - #Cell('RAM64X1D', port_attrs={'WCLK': ['clkbuf_sink']}), - Cell('RAM64X1S', port_attrs={'WCLK': ['clkbuf_sink']}), + Cell('ROM16X1'), + Cell('ROM32X1'), + Cell('ROM64X1'), + Cell('ROM128X1'), + Cell('ROM256X1'), + + # CLB -- registers/latches. + # Virtex 1/2/4/5, Spartan 3. + Cell('FDCPE', port_attrs={'C': ['clkbuf_sink']}), + Cell('FDRSE', port_attrs={'C': ['clkbuf_sink']}), + Cell('LDCPE', port_attrs={'C': ['clkbuf_sink']}), + # Virtex 6, Spartan 6, Series 7, Ultrascale. + # Cell('FDCE'), + # Cell('FDPE'), + # Cell('FDRE'), + # Cell('FDSE'), + # Cell('LDCE'), + # Cell('LDPE'), Cell('AND2B1L'), - Cell('CARRY8'), - Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('OR2L'), + + # CLB -- other. # Cell('LUT1'), # Cell('LUT2'), # Cell('LUT3'), # Cell('LUT4'), # Cell('LUT5'), # Cell('LUT6'), + # Cell('LUT6_2'), + Cell('MUXF5'), + Cell('MUXF6'), # Cell('MUXF7'), # Cell('MUXF8'), Cell('MUXF9'), - Cell('OR2L'), + # Cell('CARRY4'), + Cell('CARRY8'), + # Cell('MUXCY'), + # Cell('XORCY'), + Cell('ORCY'), + Cell('MULT_AND'), + Cell('SRL16', port_attrs={'CLK': ['clkbuf_sink']}), # Cell('SRL16E', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('SRLC16', port_attrs={'CLK': ['clkbuf_sink']}), + # Cell('SRLC16E', port_attrs={'CLK': ['clkbuf_sink']}), # Cell('SRLC32E', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('CFGLUT5', port_attrs={'CLK': ['clkbuf_sink']}), - # Clock. - # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFG_GT_SYNC'), - Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}), - #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}), - Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}), - Cell('MMCME3_ADV'), - Cell('MMCME3_BASE'), - Cell('MMCME4_ADV'), - Cell('MMCME4_BASE'), - Cell('PLLE3_ADV'), - Cell('PLLE3_BASE'), - Cell('PLLE4_ADV'), - Cell('PLLE4_BASE'), - # the "E2" variants are not strictly speaking UltraScale[+] cells - # but are automatically upgraded for backwards compatibility purposes - Cell('MMCME2_ADV'), - Cell('MMCME2_BASE'), - Cell('PLLE2_ADV'), - Cell('PLLE2_BASE'), + # Block RAM. + # Virtex. + # TODO: RAMB4_* + # Virtex 2, Spartan 3. + Cell('RAMB16_S1', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S2', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S4', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S9', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S18', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S36', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16_S1_S1', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S1_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S2', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S2_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S4_S4', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S4_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S4_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S4_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S9_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S9_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S9_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S18_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S18_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + # Spartan 3A (in addition to above). + Cell('RAMB16BWE_S18', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16BWE_S36', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('RAMB16BWE_S18_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16BWE_S18_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16BWE_S36_S9', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16BWE_S36_S18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB16BWE_S36_S36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + # Spartan 3A DSP. + Cell('RAMB16BWER', port_attrs={ + 'CLKA': ['clkbuf_sink'], + 'CLKB': ['clkbuf_sink'], + #'DOA': ['abc9_arrival='], + #'DOB': ['abc9_arrival='], + #'DOPA': ['abc9_arrival='], + #'DOPB': ['abc9_arrival='], + }), + # Spartan 6 (in addition to above). + Cell('RAMB8BWER', port_attrs={ + 'CLKAWRCLK': ['clkbuf_sink'], + 'CLKBRDCLK': ['clkbuf_sink'], + #'DOADO': ['abc9_arrival='], + #'DOBDO': ['abc9_arrival='], + #'DOPADOP': ['abc9_arrival='], + #'DOPBDOP': ['abc9_arrival='], + }), + # Virtex 4. + Cell('FIFO16', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB16', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB32_S64_ECC', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + # Virtex 5. + Cell('FIFO18', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO18_36', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36_72', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB18', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB36', port_attrs={'CLKA': ['clkbuf_sink'], 'CLKB': ['clkbuf_sink']}), + Cell('RAMB18SDP', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB36SDP', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + # Virtex 6 / Series 7. + Cell('FIFO18E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36E1', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB18E1', port_attrs={ + 'CLKARDCLK': ['clkbuf_sink'], + 'CLKBWRCLK': ['clkbuf_sink'], + 'DOADO': ['abc9_arrival=2454'], + 'DOBDO': ['abc9_arrival=2454'], + 'DOPADOP': ['abc9_arrival=2454'], + 'DOPBDOP': ['abc9_arrival=2454'], + }), + Cell('RAMB36E1', port_attrs={ + 'CLKARDCLK': ['clkbuf_sink'], + 'CLKBWRCLK': ['clkbuf_sink'], + 'DOADO': ['abc9_arrival=2454'], + 'DOBDO': ['abc9_arrival=2454'], + 'DOPADOP': ['abc9_arrival=2454'], + 'DOPBDOP': ['abc9_arrival=2454'], + }), + # Ultrascale. + Cell('FIFO18E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('FIFO36E2', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('RAMB18E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), + Cell('RAMB36E2', port_attrs={'CLKARDCLK': ['clkbuf_sink'], 'CLKBWRCLK': ['clkbuf_sink']}), - # Configuration. - Cell('BSCANE2', keep=True), - Cell('DNA_PORTE2'), - Cell('EFUSE_USR'), - Cell('FRAME_ECCE3'), - Cell('ICAPE3', keep=True), - Cell('MASTER_JTAG', keep=True), - Cell('STARTUPE3', keep=True), - Cell('USR_ACCESSE2'), + # Ultra RAM. + Cell('URAM288', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), - # I/O. + # Multipliers and DSP. + Cell('MULT18X18'), # Spartan 3 + Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 + Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E + Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP + Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 + Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4 + Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5 + #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7 + Cell('DSP48E2', port_attrs={'CLK': ['clkbuf_sink']}), # Ultrascale + + # I/O logic. + # Virtex 2, Spartan 3. + Cell('IFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}), + Cell('IFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'D': ['iopad_external_pin']}), + Cell('OFDDRCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}), + Cell('OFDDRRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'Q': ['iopad_external_pin']}), + Cell('OFDDRTCPE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'O': ['iopad_external_pin']}), + Cell('OFDDRTRSE', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink'], 'O': ['iopad_external_pin']}), + # Spartan 3E. + Cell('IDDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), + Cell('ODDR2', port_attrs={'C0': ['clkbuf_sink'], 'C1': ['clkbuf_sink']}), + # Virtex 4. + Cell('IDDR', port_attrs={'C': ['clkbuf_sink']}), + Cell('IDDR_2CLK', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), + Cell('ODDR', port_attrs={'C': ['clkbuf_sink']}), + Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), + Cell('IDELAY', port_attrs={'C': ['clkbuf_sink']}), + Cell('ISERDES', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + Cell('OSERDES', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + # Virtex 5. + Cell('IODELAY', port_attrs={'C': ['clkbuf_sink']}), + Cell('ISERDES_NODELAY', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLKB': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + # Virtex 6. + Cell('IODELAYE1', port_attrs={'C': ['clkbuf_sink']}), + Cell('ISERDESE1', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLKB': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + Cell('OSERDESE1', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + # Series 7. + Cell('IDELAYE2', port_attrs={'C': ['clkbuf_sink']}), + Cell('ODELAYE2', port_attrs={'C': ['clkbuf_sink']}), + Cell('ISERDESE2', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLKB': ['clkbuf_sink'], + 'OCLK': ['clkbuf_sink'], + 'OCLKB': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + 'CLKDIVP': ['clkbuf_sink'], + }), + Cell('OSERDESE2', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + Cell('PHASER_IN'), + Cell('PHASER_IN_PHY'), + Cell('PHASER_OUT'), + Cell('PHASER_OUT_PHY'), + Cell('PHASER_REF'), + Cell('PHY_CONTROL'), + # Ultrascale. + Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), + Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}), + Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('ISERDESE3', port_attrs={ + 'CLK': ['clkbuf_sink'], + 'CLK_B': ['clkbuf_sink'], + 'FIFO_RD_CLK': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), Cell('BITSLICE_CONTROL', keep=True), - Cell('DCIRESET', keep=True), - Cell('HPIO_VREF'), - # XXX + Cell('RIU_OR'), + Cell('RX_BITSLICE'), + Cell('RXTX_BITSLICE'), + Cell('TX_BITSLICE'), + Cell('TX_BITSLICE_TRI'), + # Spartan 6. + Cell('IODELAY2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), + Cell('IODRP2', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), + Cell('IODRP2_MCB', port_attrs={'IOCLK0': ['clkbuf_sink'], 'IOCLK1': ['clkbuf_sink'], 'CLK': ['clkbuf_sink']}), + Cell('ISERDES2', port_attrs={ + 'CLK0': ['clkbuf_sink'], + 'CLK1': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + Cell('OSERDES2', port_attrs={ + 'CLK0': ['clkbuf_sink'], + 'CLK1': ['clkbuf_sink'], + 'CLKDIV': ['clkbuf_sink'], + }), + + # I/O buffers. + # Input. # Cell('IBUF', port_attrs={'I': ['iopad_external_pin']}), - Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUF_DLY_ADJ', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUF_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUF_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUF_ANALOG', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}), Cell('IBUFDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_DLY_ADJ', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_DIFF_OUT_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_IBUFDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFDS_INTERMDISABLE', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), Cell('IBUFDSE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), - Cell('IBUFE3', port_attrs={'I': ['iopad_external_pin']}), - Cell('IDELAYCTRL', keep=True, port_attrs={'REFCLK': ['clkbuf_sink']}), - Cell('IDELAYE3', port_attrs={'CLK': ['clkbuf_sink']}), + Cell('IBUFDS_DPHY', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + # Cell('IBUFG', port_attrs={'I': ['iopad_external_pin']}), + Cell('IBUFGDS', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFGDS_DIFF_OUT', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + # I/O. Cell('IOBUF', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUF_DCIEN', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUF_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin']}), + Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUFDS', port_attrs={'IO': ['iopad_external_pin']}), Cell('IOBUFDS_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), + Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DIFF_OUT', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DIFF_OUT_DCIEN', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDS_DIFF_OUT_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), - Cell('IOBUFDS_INTERMDISABLE', port_attrs={'IO': ['iopad_external_pin'], 'IOB': ['iopad_external_pin']}), Cell('IOBUFDSE3', port_attrs={'IO': ['iopad_external_pin']}), - Cell('IOBUFE3', port_attrs={'IO': ['iopad_external_pin']}), - Cell('ISERDESE3', port_attrs={ - 'CLK': ['clkbuf_sink'], - 'CLK_B': ['clkbuf_sink'], - 'FIFO_RD_CLK': ['clkbuf_sink'], - 'CLKDIV': ['clkbuf_sink'], - }), - Cell('KEEPER'), + # Output. # Cell('OBUF', port_attrs={'O': ['iopad_external_pin']}), Cell('OBUFDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), Cell('OBUFDS_DPHY', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + # Output + tristate. Cell('OBUFT', port_attrs={'O': ['iopad_external_pin']}), Cell('OBUFTDS', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), - Cell('ODELAYE3', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('OSERDESE3', port_attrs={'CLK': ['clkbuf_sink'], 'CLKDIV': ['clkbuf_sink']}), + # Pulls. + Cell('KEEPER'), Cell('PULLDOWN'), Cell('PULLUP'), - Cell('RIU_OR'), - Cell('RX_BITSLICE'), - Cell('RXTX_BITSLICE'), - Cell('TX_BITSLICE'), - Cell('TX_BITSLICE_TRI'), + # Misc. + Cell('DCIRESET', keep=True), + Cell('HPIO_VREF'), # Ultrascale - # Registers. - # Cell('FDCE'), - # Cell('FDPE'), - # Cell('FDRE'), - # Cell('FDSE'), + # Clock buffers (global). + # Cell('BUFG', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGCE', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGCE_1', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX_1', port_attrs={'O': ['clkbuf_driver']}), + #Cell('BUFGCTRL', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX_CTRL', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGMUX_VIRTEX4', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFG_GT', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFG_GT_SYNC'), + Cell('BUFG_PS', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFGCE_DIV', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFH', port_attrs={'O': ['clkbuf_driver']}), + #Cell('BUFHCE', port_attrs={'O': ['clkbuf_driver']}), + + # Clock buffers (IO) -- Spartan 6. + Cell('BUFIO2', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), + Cell('BUFIO2_2CLK', port_attrs={'IOCLK': ['clkbuf_driver'], 'DIVCLK': ['clkbuf_driver']}), + Cell('BUFIO2FB', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFPLL_MCB', port_attrs={'IOCLK0': ['clkbuf_driver'], 'IOCLK1': ['clkbuf_driver']}), + + # Clock buffers (IO and regional) -- Virtex. + Cell('BUFIO', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFIODQS', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFR', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFMR', port_attrs={'O': ['clkbuf_driver']}), + Cell('BUFMRCE', port_attrs={'O': ['clkbuf_driver']}), + + # Clock components. + # VIrtex. + # TODO: CLKDLL + # TODO: CLKDLLE + # TODO: CLKDLLHF + # Virtex 2, Spartan 3. + Cell('DCM'), + # Spartan 3E. + Cell('DCM_SP'), + # Spartan 6 (also uses DCM_SP and PLL_BASE). + Cell('DCM_CLKGEN'), + # Virtex 4/5. + Cell('DCM_ADV'), + Cell('DCM_BASE'), + Cell('DCM_PS'), + # Virtex 4. + Cell('PMCD'), + # Virtex 5. + Cell('PLL_ADV'), + Cell('PLL_BASE'), + # Virtex 6. + Cell('MMCM_ADV'), + Cell('MMCM_BASE'), + # Series 7. + Cell('MMCME2_ADV'), + Cell('MMCME2_BASE'), + Cell('PLLE2_ADV'), + Cell('PLLE2_BASE'), + # Ultrascale. + Cell('MMCME3_ADV'), + Cell('MMCME3_BASE'), + Cell('PLLE3_ADV'), + Cell('PLLE3_BASE'), + # Ultrascale+. + Cell('MMCME4_ADV'), + Cell('MMCME4_BASE'), + Cell('PLLE4_ADV'), + Cell('PLLE4_BASE'), + + # Misc stuff. + Cell('BUFT'), + # Series 7 I/O FIFOs. + Cell('IN_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + Cell('OUT_FIFO', port_attrs={'RDCLK': ['clkbuf_sink'], 'WRCLK': ['clkbuf_sink']}), + # Ultrascale special synchronizer register. Cell('HARD_SYNC', port_attrs={'CLK': ['clkbuf_sink']}), - Cell('IDDRE1', port_attrs={'C': ['clkbuf_sink'], 'CB': ['clkbuf_sink']}), - # Cell('LDCE'), - # Cell('LDPE'), - Cell('ODDRE1', port_attrs={'C': ['clkbuf_sink']}), - # NOTE: not in the official library guide! - Cell('PS8', keep=True), + # Singletons. + # Startup. + # TODO: STARTUP_VIRTEX + # TODO: STARTUP_VIRTEX2 + Cell('STARTUP_SPARTAN3', keep=True), + Cell('STARTUP_SPARTAN3E', keep=True), + Cell('STARTUP_SPARTAN3A', keep=True), + Cell('STARTUP_SPARTAN6', keep=True), + Cell('STARTUP_VIRTEX4', keep=True), + Cell('STARTUP_VIRTEX5', keep=True), + Cell('STARTUP_VIRTEX6', keep=True), + Cell('STARTUPE2', keep=True), # Series 7 + Cell('STARTUPE3', keep=True), # Ultrascale + # Capture trigger. + # TODO: CAPTURE_VIRTEX + # TODO: CAPTURE_VIRTEX2 + Cell('CAPTURE_SPARTAN3', keep=True), + Cell('CAPTURE_SPARTAN3A', keep=True), + Cell('CAPTURE_VIRTEX4', keep=True), + Cell('CAPTURE_VIRTEX5', keep=True), + Cell('CAPTURE_VIRTEX6', keep=True), + Cell('CAPTUREE2', keep=True), # Series 7 + # Internal Configuration Access Port. + # TODO: ICAP_VIRTEX2 + Cell('ICAP_SPARTAN3A', keep=True), + Cell('ICAP_SPARTAN6', keep=True), + Cell('ICAP_VIRTEX4', keep=True), + Cell('ICAP_VIRTEX5', keep=True), + Cell('ICAP_VIRTEX6', keep=True), + Cell('ICAPE2', keep=True), # Series 7 + Cell('ICAPE3', keep=True), # Ultrascale + # JTAG. + # TODO: BSCAN_VIRTEX + # TODO: BSCAN_VIRTEX2 + Cell('BSCAN_SPARTAN3', keep=True), + Cell('BSCAN_SPARTAN3A', keep=True), + Cell('BSCAN_SPARTAN6', keep=True), + Cell('BSCAN_VIRTEX4', keep=True), + Cell('BSCAN_VIRTEX5', keep=True), + Cell('BSCAN_VIRTEX6', keep=True), + Cell('BSCANE2', keep=True), # Series 7, Ultrascale + # DNA port. + Cell('DNA_PORT'), # Virtex 5/6, Series 7, Spartan 3A/6 + Cell('DNA_PORTE2'), # Ultrascale + # Frame ECC. + Cell('FRAME_ECC_VIRTEX4'), + Cell('FRAME_ECC_VIRTEX5'), + Cell('FRAME_ECC_VIRTEX6'), + Cell('FRAME_ECCE2'), # Series 7 + Cell('FRAME_ECCE3'), # Ultrascale + # AXSS command access. + Cell('USR_ACCESS_VIRTEX4'), + Cell('USR_ACCESS_VIRTEX5'), + Cell('USR_ACCESS_VIRTEX6'), + Cell('USR_ACCESSE2'), # Series 7, Ultrascale + # Misc. + Cell('POST_CRC_INTERNAL'), # Spartan 6 + Cell('SUSPEND_SYNC', keep=True), # Spartan 6 + Cell('KEY_CLEAR', keep=True), # Virtex 5 + Cell('MASTER_JTAG', keep=True), # Ultrascale + Cell('SPI_ACCESS', keep=True), # Spartan 3AN + Cell('EFUSE_USR'), + + # ADC. + Cell('SYSMON'), # Virtex 5/6 + Cell('XADC'), # Series 7 + Cell('SYSMONE1'), # Ultrascale + Cell('SYSMONE4'), # Ultrascale+ + + # Gigabit transceivers. + # Spartan 6. + Cell('GTPA1_DUAL'), + # Virtex 2 Pro. + # TODO: GT_* + # TODO: GT10_* + # Virtex 4. + Cell('GT11_CUSTOM'), + Cell('GT11_DUAL'), + Cell('GT11CLK'), + Cell('GT11CLK_MGT'), + # Virtex 5. + Cell('GTP_DUAL'), + Cell('GTX_DUAL'), + Cell('CRC32', port_attrs={'CRCCLK': ['clkbuf_sink']}), + Cell('CRC64', port_attrs={'CRCCLK': ['clkbuf_sink']}), + # Virtex 6. + Cell('GTHE1_QUAD'), + Cell('GTXE1'), + Cell('IBUFDS_GTXE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_GTHE1', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + # Series 7. + Cell('GTHE2_CHANNEL'), + Cell('GTHE2_COMMON'), + Cell('GTPE2_CHANNEL'), + Cell('GTPE2_COMMON'), + Cell('GTXE2_CHANNEL'), + Cell('GTXE2_COMMON'), + Cell('IBUFDS_GTE2', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + # Ultrascale. + Cell('GTHE3_CHANNEL'), + Cell('GTHE3_COMMON'), + Cell('GTHE4_CHANNEL'), + Cell('GTHE4_COMMON'), + Cell('GTYE3_CHANNEL'), + Cell('GTYE3_COMMON'), + Cell('GTYE4_CHANNEL'), + Cell('GTYE4_COMMON'), + Cell('IBUFDS_GTE3', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('IBUFDS_GTE4', port_attrs={'I': ['iopad_external_pin'], 'IB': ['iopad_external_pin']}), + Cell('OBUFDS_GTE3', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFDS_GTE3_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFDS_GTE4', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + Cell('OBUFDS_GTE4_ADV', port_attrs={'O': ['iopad_external_pin'], 'OB': ['iopad_external_pin']}), + + # PCIE IP. + Cell('PCIE_A1'), # Spartan 6 + Cell('PCIE_EP'), # Virtex 5 + Cell('PCIE_2_0'), # Virtex 6 + Cell('PCIE_2_1'), # Series 7 + Cell('PCIE_3_0'), # Series 7 + Cell('PCIE_3_1'), # Ultrascale + Cell('PCIE40E4'), # Ultrascale+ + + # Ethernet IP. + Cell('EMAC'), # Virtex 4 + Cell('TEMAC'), # Virtex 5 + Cell('TEMAC_SINGLE'), # Virtex 6 + Cell('CMAC'), # Ultrascale + Cell('CMACE4'), # Ultrsacale+ + + # PowerPC. + # TODO PPC405 (Virtex 2) + Cell('PPC405_ADV'), # Virtex 4 + Cell('PPC440'), # Virtex 5 + + # Misc hard IP. + Cell('MCB'), # Spartan 6 Memory Controller Block + Cell('PS7', keep=True), # The Zynq 7000 ARM Processor System. + Cell('PS8', keep=True), # The Zynq Ultrascale+ ARM Processor System. + Cell('ILKN'), # Ultrascale Interlaken + Cell('ILKNE4'), # Ultrascale+ Interlaken ] @@ -698,17 +693,11 @@ if __name__ == '__main__': if not os.path.isdir(dir): print('{} is not a directory'.format(dir)) - for ofile, cells in [ - ('xc6s_cells_xtra.v', XC6S_CELLS), - ('xc6v_cells_xtra.v', XC6V_CELLS), - ('xc7_cells_xtra.v', XC7_CELLS), - ('xcu_cells_xtra.v', XCU_CELLS), - ]: - out = StringIO() - for cell in cells: - xtract_cell_decl(cell, dirs, out) - - with open(ofile, 'w') as f: - f.write('// Created by cells_xtra.py from Xilinx models\n') - f.write('\n') - f.write(out.getvalue()) + out = StringIO() + for cell in CELLS: + xtract_cell_decl(cell, dirs, out) + + with open('cells_xtra.v', 'w') as f: + f.write('// Created by cells_xtra.py from Xilinx models\n') + f.write('\n') + f.write(out.getvalue()) diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v new file mode 100644 index 000000000..72a3b6cbb --- /dev/null +++ b/techlibs/xilinx/cells_xtra.v @@ -0,0 +1,29339 @@ +// Created by cells_xtra.py from Xilinx models + +module RAM16X1S (...); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input A0; + input A1; + input A2; + input A3; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM16X1S_1 (...); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input A0; + input A1; + input A2; + input A3; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM32X1S (...); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM32X1S_1 (...); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM64X1S (...); + parameter [63:0] INIT = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM64X1S_1 (...); + parameter [63:0] INIT = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM128X1S (...); + parameter [127:0] INIT = 128'h00000000000000000000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input A6; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM128X1S_1 (...); + parameter [127:0] INIT = 128'h00000000000000000000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input A6; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM256X1S (...); + parameter [255:0] INIT = 256'h0; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input [7:0] A; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM512X1S (...); + parameter [511:0] INIT = 512'h0; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O; + input [8:0] A; + input D; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM16X2S (...); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O0; + output O1; + input A0; + input A1; + input A2; + input A3; + input D0; + input D1; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM32X2S (...); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O0; + output O1; + input A0; + input A1; + input A2; + input A3; + input A4; + input D0; + input D1; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM64X2S (...); + parameter [63:0] INIT_00 = 64'h0000000000000000; + parameter [63:0] INIT_01 = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O0; + output O1; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input D0; + input D1; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM16X4S (...); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [15:0] INIT_02 = 16'h0000; + parameter [15:0] INIT_03 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O0; + output O1; + output O2; + output O3; + input A0; + input A1; + input A2; + input A3; + input D0; + input D1; + input D2; + input D3; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM32X4S (...); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [31:0] INIT_02 = 32'h00000000; + parameter [31:0] INIT_03 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output O0; + output O1; + output O2; + output O3; + input A0; + input A1; + input A2; + input A3; + input A4; + input D0; + input D1; + input D2; + input D3; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM16X8S (...); + parameter [15:0] INIT_00 = 16'h0000; + parameter [15:0] INIT_01 = 16'h0000; + parameter [15:0] INIT_02 = 16'h0000; + parameter [15:0] INIT_03 = 16'h0000; + parameter [15:0] INIT_04 = 16'h0000; + parameter [15:0] INIT_05 = 16'h0000; + parameter [15:0] INIT_06 = 16'h0000; + parameter [15:0] INIT_07 = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output [7:0] O; + input A0; + input A1; + input A2; + input A3; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; + input [7:0] D; +endmodule + +module RAM32X8S (...); + parameter [31:0] INIT_00 = 32'h00000000; + parameter [31:0] INIT_01 = 32'h00000000; + parameter [31:0] INIT_02 = 32'h00000000; + parameter [31:0] INIT_03 = 32'h00000000; + parameter [31:0] INIT_04 = 32'h00000000; + parameter [31:0] INIT_05 = 32'h00000000; + parameter [31:0] INIT_06 = 32'h00000000; + parameter [31:0] INIT_07 = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output [7:0] O; + input A0; + input A1; + input A2; + input A3; + input A4; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; + input [7:0] D; +endmodule + +module RAM16X1D (...); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output DPO; + output SPO; + input A0; + input A1; + input A2; + input A3; + input D; + input DPRA0; + input DPRA1; + input DPRA2; + input DPRA3; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM16X1D_1 (...); + parameter [15:0] INIT = 16'h0000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output DPO; + output SPO; + input A0; + input A1; + input A2; + input A3; + input D; + input DPRA0; + input DPRA1; + input DPRA2; + input DPRA3; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM32X1D_1 (...); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output DPO; + output SPO; + input A0; + input A1; + input A2; + input A3; + input A4; + input D; + input DPRA0; + input DPRA1; + input DPRA2; + input DPRA3; + input DPRA4; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM64X1D_1 (...); + parameter [63:0] INIT = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output DPO; + output SPO; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input D; + input DPRA0; + input DPRA1; + input DPRA2; + input DPRA3; + input DPRA4; + input DPRA5; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM256X1D (...); + parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output DPO; + output SPO; + input [7:0] A; + input D; + input [7:0] DPRA; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM32M (...); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output [1:0] DOA; + output [1:0] DOB; + output [1:0] DOC; + output [1:0] DOD; + input [4:0] ADDRA; + input [4:0] ADDRB; + input [4:0] ADDRC; + input [4:0] ADDRD; + input [1:0] DIA; + input [1:0] DIB; + input [1:0] DIC; + input [1:0] DID; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM32M16 (...); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [63:0] INIT_E = 64'h0000000000000000; + parameter [63:0] INIT_F = 64'h0000000000000000; + parameter [63:0] INIT_G = 64'h0000000000000000; + parameter [63:0] INIT_H = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output [1:0] DOA; + output [1:0] DOB; + output [1:0] DOC; + output [1:0] DOD; + output [1:0] DOE; + output [1:0] DOF; + output [1:0] DOG; + output [1:0] DOH; + input [4:0] ADDRA; + input [4:0] ADDRB; + input [4:0] ADDRC; + input [4:0] ADDRD; + input [4:0] ADDRE; + input [4:0] ADDRF; + input [4:0] ADDRG; + input [4:0] ADDRH; + input [1:0] DIA; + input [1:0] DIB; + input [1:0] DIC; + input [1:0] DID; + input [1:0] DIE; + input [1:0] DIF; + input [1:0] DIG; + input [1:0] DIH; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM64M (...); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output DOA; + output DOB; + output DOC; + output DOD; + input [5:0] ADDRA; + input [5:0] ADDRB; + input [5:0] ADDRC; + input [5:0] ADDRD; + input DIA; + input DIB; + input DIC; + input DID; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module RAM64M8 (...); + parameter [63:0] INIT_A = 64'h0000000000000000; + parameter [63:0] INIT_B = 64'h0000000000000000; + parameter [63:0] INIT_C = 64'h0000000000000000; + parameter [63:0] INIT_D = 64'h0000000000000000; + parameter [63:0] INIT_E = 64'h0000000000000000; + parameter [63:0] INIT_F = 64'h0000000000000000; + parameter [63:0] INIT_G = 64'h0000000000000000; + parameter [63:0] INIT_H = 64'h0000000000000000; + parameter [0:0] IS_WCLK_INVERTED = 1'b0; + output DOA; + output DOB; + output DOC; + output DOD; + output DOE; + output DOF; + output DOG; + output DOH; + input [5:0] ADDRA; + input [5:0] ADDRB; + input [5:0] ADDRC; + input [5:0] ADDRD; + input [5:0] ADDRE; + input [5:0] ADDRF; + input [5:0] ADDRG; + input [5:0] ADDRH; + input DIA; + input DIB; + input DIC; + input DID; + input DIE; + input DIF; + input DIG; + input DIH; + (* clkbuf_sink *) + (* invertible_pin = "IS_WCLK_INVERTED" *) + input WCLK; + input WE; +endmodule + +module ROM16X1 (...); + parameter [127:0] INIT = 16'h0000; + output O; + input A0; + input A1; + input A2; + input A3; +endmodule + +module ROM32X1 (...); + parameter [31:0] INIT = 32'h00000000; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; +endmodule + +module ROM64X1 (...); + parameter [63:0] INIT = 64'h0000000000000000; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; +endmodule + +module ROM128X1 (...); + parameter [127:0] INIT = 128'h00000000000000000000000000000000; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input A6; +endmodule + +module ROM256X1 (...); + parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output O; + input A0; + input A1; + input A2; + input A3; + input A4; + input A5; + input A6; + input A7; +endmodule + +module FDCPE (...); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + output Q; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR; + input D; + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE; +endmodule + +module FDRSE (...); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_R_INVERTED = 1'b0; + parameter [0:0] IS_S_INVERTED = 1'b0; + output Q; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + (* invertible_pin = "IS_CE_INVERTED" *) + input CE; + (* invertible_pin = "IS_D_INVERTED" *) + input D; + (* invertible_pin = "IS_R_INVERTED" *) + input R; + (* invertible_pin = "IS_S_INVERTED" *) + input S; +endmodule + +module LDCPE (...); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_G_INVERTED = 1'b0; + parameter [0:0] IS_GE_INVERTED = 1'b0; + parameter [0:0] IS_PRE_INVERTED = 1'b0; + output Q; + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR; + (* invertible_pin = "IS_D_INVERTED" *) + input D; + (* invertible_pin = "IS_G_INVERTED" *) + input G; + (* invertible_pin = "IS_GE_INVERTED" *) + input GE; + (* invertible_pin = "IS_PRE_INVERTED" *) + input PRE; +endmodule + +module AND2B1L (...); + parameter [0:0] IS_SRI_INVERTED = 1'b0; + output O; + input DI; + (* invertible_pin = "IS_SRI_INVERTED" *) + input SRI; +endmodule + +module OR2L (...); + parameter [0:0] IS_SRI_INVERTED = 1'b0; + output O; + input DI; + (* invertible_pin = "IS_SRI_INVERTED" *) + input SRI; +endmodule + +module MUXF5 (...); + output O; + input I0; + input I1; + input S; +endmodule + +module MUXF6 (...); + output O; + input I0; + input I1; + input S; +endmodule + +module MUXF9 (...); + output O; + input I0; + input I1; + input S; +endmodule + +module CARRY8 (...); + parameter CARRY_TYPE = "SINGLE_CY8"; + output [7:0] CO; + output [7:0] O; + input CI; + input CI_TOP; + input [7:0] DI; + input [7:0] S; +endmodule + +module ORCY (...); + output O; + input CI; + input I; +endmodule + +module MULT_AND (...); + output LO; + input I0; + input I1; +endmodule + +module SRL16 (...); + parameter [15:0] INIT = 16'h0000; + output Q; + input A0; + input A1; + input A2; + input A3; + (* clkbuf_sink *) + input CLK; + input D; +endmodule + +module SRLC16 (...); + parameter [15:0] INIT = 16'h0000; + output Q; + output Q15; + input A0; + input A1; + input A2; + input A3; + (* clkbuf_sink *) + input CLK; + input D; +endmodule + +module CFGLUT5 (...); + parameter [31:0] INIT = 32'h00000000; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + output CDO; + output O5; + output O6; + input I4; + input I3; + input I2; + input I1; + input I0; + input CDI; + input CE; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; +endmodule + +module RAMB16_S1 (...); + parameter [0:0] INIT = 1'h0; + parameter [0:0] SRVAL = 1'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DO; + input [13:0] ADDR; + input [0:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S2 (...); + parameter [1:0] INIT = 2'h0; + parameter [1:0] SRVAL = 2'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DO; + input [12:0] ADDR; + input [1:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S4 (...); + parameter [3:0] INIT = 4'h0; + parameter [3:0] SRVAL = 4'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DO; + input [11:0] ADDR; + input [3:0] DI; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S9 (...); + parameter [8:0] INIT = 9'h0; + parameter [8:0] SRVAL = 9'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DO; + output [0:0] DOP; + input [10:0] ADDR; + input [7:0] DI; + input [0:0] DIP; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S18 (...); + parameter [17:0] INIT = 18'h0; + parameter [17:0] SRVAL = 18'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [15:0] DO; + output [1:0] DOP; + input [9:0] ADDR; + input [15:0] DI; + input [1:0] DIP; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S36 (...); + parameter [35:0] INIT = 36'h0; + parameter [35:0] SRVAL = 36'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [31:0] DO; + output [3:0] DOP; + input [8:0] ADDR; + input [31:0] DI; + input [3:0] DIP; + input EN; + (* clkbuf_sink *) + input CLK; + input WE; + input SSR; +endmodule + +module RAMB16_S1_S1 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [0:0] INIT_B = 1'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [0:0] SRVAL_B = 1'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [0:0] DOB; + input [13:0] ADDRB; + input [0:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S2 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [1:0] INIT_B = 2'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [1:0] SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [1:0] DOB; + input [12:0] ADDRB; + input [1:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S4 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [3:0] INIT_B = 4'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [3:0] SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [3:0] DOB; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S9 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [8:0] INIT_B = 9'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [7:0] DOB; + output [0:0] DOPB; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S18 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S1_S36 (...); + parameter [0:0] INIT_A = 1'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [0:0] SRVAL_A = 1'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [0:0] DOA; + input [13:0] ADDRA; + input [0:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S2 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [1:0] INIT_B = 2'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [1:0] SRVAL_B = 2'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [1:0] DOB; + input [12:0] ADDRB; + input [1:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S4 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [3:0] INIT_B = 4'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [3:0] SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [3:0] DOB; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S9 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [8:0] INIT_B = 9'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [7:0] DOB; + output [0:0] DOPB; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S18 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S2_S36 (...); + parameter [1:0] INIT_A = 2'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [1:0] SRVAL_A = 2'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [1:0] DOA; + input [12:0] ADDRA; + input [1:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S4_S4 (...); + parameter [3:0] INIT_A = 4'h0; + parameter [3:0] INIT_B = 4'h0; + parameter [3:0] SRVAL_A = 4'h0; + parameter [3:0] SRVAL_B = 4'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [11:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [3:0] DOB; + input [11:0] ADDRB; + input [3:0] DIB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S4_S9 (...); + parameter [3:0] INIT_A = 4'h0; + parameter [8:0] INIT_B = 9'h0; + parameter [3:0] SRVAL_A = 4'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [11:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [7:0] DOB; + output [0:0] DOPB; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S4_S18 (...); + parameter [3:0] INIT_A = 4'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [3:0] SRVAL_A = 4'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [11:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S4_S36 (...); + parameter [3:0] INIT_A = 4'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [3:0] SRVAL_A = 4'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [3:0] DOA; + input [11:0] ADDRA; + input [3:0] DIA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S9_S9 (...); + parameter [8:0] INIT_A = 9'h0; + parameter [8:0] INIT_B = 9'h0; + parameter [8:0] SRVAL_A = 9'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DOA; + output [0:0] DOPA; + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [7:0] DOB; + output [0:0] DOPB; + input [10:0] ADDRB; + input [7:0] DIB; + input [0:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S9_S18 (...); + parameter [8:0] INIT_A = 9'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [8:0] SRVAL_A = 9'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DOA; + output [0:0] DOPA; + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S9_S36 (...); + parameter [8:0] INIT_A = 9'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [8:0] SRVAL_A = 9'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [7:0] DOA; + output [0:0] DOPA; + input [10:0] ADDRA; + input [7:0] DIA; + input [0:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S18_S18 (...); + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [15:0] DOA; + output [1:0] DOPA; + input [9:0] ADDRA; + input [15:0] DIA; + input [1:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [15:0] DOB; + output [1:0] DOPB; + input [9:0] ADDRB; + input [15:0] DIB; + input [1:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S18_S36 (...); + parameter [17:0] INIT_A = 18'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [17:0] SRVAL_A = 18'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [15:0] DOA; + output [1:0] DOPA; + input [9:0] ADDRA; + input [15:0] DIA; + input [1:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16_S36_S36 (...); + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + output [31:0] DOA; + output [3:0] DOPA; + input [8:0] ADDRA; + input [31:0] DIA; + input [3:0] DIPA; + input ENA; + (* clkbuf_sink *) + input CLKA; + input WEA; + input SSRA; + output [31:0] DOB; + output [3:0] DOPB; + input [8:0] ADDRB; + input [31:0] DIB; + input [3:0] DIPB; + input ENB; + (* clkbuf_sink *) + input CLKB; + input WEB; + input SSRB; +endmodule + +module RAMB16BWE_S18 (...); + parameter [17:0] INIT = 18'h0; + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [17:0] SRVAL = 18'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + output [15:0] DO; + output [1:0] DOP; + (* clkbuf_sink *) + input CLK; + input EN; + input SSR; + input [1:0] WE; + input [15:0] DI; + input [1:0] DIP; + input [9:0] ADDR; +endmodule + +module RAMB16BWE_S36 (...); + parameter [35:0] INIT = 36'h0; + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [35:0] SRVAL = 36'h0; + parameter WRITE_MODE = "WRITE_FIRST"; + output [31:0] DO; + output [3:0] DOP; + (* clkbuf_sink *) + input CLK; + input EN; + input SSR; + input [3:0] WE; + input [31:0] DI; + input [3:0] DIP; + input [8:0] ADDR; +endmodule + +module RAMB16BWE_S18_S9 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [17:0] INIT_A = 18'h0; + parameter [8:0] INIT_B = 9'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [15:0] DOA; + output [7:0] DOB; + output [1:0] DOPA; + output [0:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input WEB; + input [1:0] WEA; + input [15:0] DIA; + input [7:0] DIB; + input [1:0] DIPA; + input [0:0] DIPB; + input [9:0] ADDRA; + input [10:0] ADDRB; +endmodule + +module RAMB16BWE_S18_S18 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [15:0] DOA; + output [15:0] DOB; + output [1:0] DOPA; + output [1:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [1:0] WEB; + input [1:0] WEA; + input [15:0] DIA; + input [15:0] DIB; + input [1:0] DIPA; + input [1:0] DIPB; + input [9:0] ADDRA; + input [9:0] ADDRB; +endmodule + +module RAMB16BWE_S36_S9 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [35:0] INIT_A = 36'h0; + parameter [8:0] INIT_B = 9'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [8:0] SRVAL_B = 9'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [31:0] DOA; + output [3:0] DOPA; + output [7:0] DOB; + output [0:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [3:0] WEA; + input WEB; + input [31:0] DIA; + input [3:0] DIPA; + input [7:0] DIB; + input [0:0] DIPB; + input [8:0] ADDRA; + input [10:0] ADDRB; +endmodule + +module RAMB16BWE_S36_S18 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [35:0] INIT_A = 36'h0; + parameter [17:0] INIT_B = 18'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [31:0] DOA; + output [3:0] DOPA; + output [15:0] DOB; + output [1:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [3:0] WEA; + input [1:0] WEB; + input [31:0] DIA; + input [3:0] DIPA; + input [15:0] DIB; + input [1:0] DIPB; + input [8:0] ADDRA; + input [9:0] ADDRB; +endmodule + +module RAMB16BWE_S36_S36 (...); + parameter [255:0] INITP_00 = 256'h0; + parameter [255:0] INITP_01 = 256'h0; + parameter [255:0] INITP_02 = 256'h0; + parameter [255:0] INITP_03 = 256'h0; + parameter [255:0] INITP_04 = 256'h0; + parameter [255:0] INITP_05 = 256'h0; + parameter [255:0] INITP_06 = 256'h0; + parameter [255:0] INITP_07 = 256'h0; + parameter [255:0] INIT_00 = 256'h0; + parameter [255:0] INIT_01 = 256'h0; + parameter [255:0] INIT_02 = 256'h0; + parameter [255:0] INIT_03 = 256'h0; + parameter [255:0] INIT_04 = 256'h0; + parameter [255:0] INIT_05 = 256'h0; + parameter [255:0] INIT_06 = 256'h0; + parameter [255:0] INIT_07 = 256'h0; + parameter [255:0] INIT_08 = 256'h0; + parameter [255:0] INIT_09 = 256'h0; + parameter [255:0] INIT_0A = 256'h0; + parameter [255:0] INIT_0B = 256'h0; + parameter [255:0] INIT_0C = 256'h0; + parameter [255:0] INIT_0D = 256'h0; + parameter [255:0] INIT_0E = 256'h0; + parameter [255:0] INIT_0F = 256'h0; + parameter [255:0] INIT_10 = 256'h0; + parameter [255:0] INIT_11 = 256'h0; + parameter [255:0] INIT_12 = 256'h0; + parameter [255:0] INIT_13 = 256'h0; + parameter [255:0] INIT_14 = 256'h0; + parameter [255:0] INIT_15 = 256'h0; + parameter [255:0] INIT_16 = 256'h0; + parameter [255:0] INIT_17 = 256'h0; + parameter [255:0] INIT_18 = 256'h0; + parameter [255:0] INIT_19 = 256'h0; + parameter [255:0] INIT_1A = 256'h0; + parameter [255:0] INIT_1B = 256'h0; + parameter [255:0] INIT_1C = 256'h0; + parameter [255:0] INIT_1D = 256'h0; + parameter [255:0] INIT_1E = 256'h0; + parameter [255:0] INIT_1F = 256'h0; + parameter [255:0] INIT_20 = 256'h0; + parameter [255:0] INIT_21 = 256'h0; + parameter [255:0] INIT_22 = 256'h0; + parameter [255:0] INIT_23 = 256'h0; + parameter [255:0] INIT_24 = 256'h0; + parameter [255:0] INIT_25 = 256'h0; + parameter [255:0] INIT_26 = 256'h0; + parameter [255:0] INIT_27 = 256'h0; + parameter [255:0] INIT_28 = 256'h0; + parameter [255:0] INIT_29 = 256'h0; + parameter [255:0] INIT_2A = 256'h0; + parameter [255:0] INIT_2B = 256'h0; + parameter [255:0] INIT_2C = 256'h0; + parameter [255:0] INIT_2D = 256'h0; + parameter [255:0] INIT_2E = 256'h0; + parameter [255:0] INIT_2F = 256'h0; + parameter [255:0] INIT_30 = 256'h0; + parameter [255:0] INIT_31 = 256'h0; + parameter [255:0] INIT_32 = 256'h0; + parameter [255:0] INIT_33 = 256'h0; + parameter [255:0] INIT_34 = 256'h0; + parameter [255:0] INIT_35 = 256'h0; + parameter [255:0] INIT_36 = 256'h0; + parameter [255:0] INIT_37 = 256'h0; + parameter [255:0] INIT_38 = 256'h0; + parameter [255:0] INIT_39 = 256'h0; + parameter [255:0] INIT_3A = 256'h0; + parameter [255:0] INIT_3B = 256'h0; + parameter [255:0] INIT_3C = 256'h0; + parameter [255:0] INIT_3D = 256'h0; + parameter [255:0] INIT_3E = 256'h0; + parameter [255:0] INIT_3F = 256'h0; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [31:0] DOA; + output [3:0] DOPA; + output [31:0] DOB; + output [3:0] DOPB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input ENA; + input ENB; + input SSRA; + input SSRB; + input [3:0] WEA; + input [3:0] WEB; + input [31:0] DIA; + input [3:0] DIPA; + input [31:0] DIB; + input [3:0] DIPB; + input [8:0] ADDRA; + input [8:0] ADDRB; +endmodule + +module RAMB16BWER (...); + parameter integer DATA_WIDTH_A = 0; + parameter integer DATA_WIDTH_B = 0; + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_RSTRAM_A = "TRUE"; + parameter EN_RSTRAM_B = "TRUE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RSTTYPE = "SYNC"; + parameter RST_PRIORITY_A = "CE"; + parameter RST_PRIORITY_B = "CE"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_DEVICE = "SPARTAN3ADSP"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + input [13:0] ADDRA; + input [13:0] ADDRB; + (* clkbuf_sink *) + input CLKA; + (* clkbuf_sink *) + input CLKB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input ENA; + input ENB; + input REGCEA; + input REGCEB; + input RSTA; + input RSTB; + input [3:0] WEA; + input [3:0] WEB; +endmodule + +module RAMB8BWER (...); + parameter integer DATA_WIDTH_A = 0; + parameter integer DATA_WIDTH_B = 0; + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_RSTRAM_A = "TRUE"; + parameter EN_RSTRAM_B = "TRUE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RSTTYPE = "SYNC"; + parameter RST_PRIORITY_A = "CE"; + parameter RST_PRIORITY_B = "CE"; + parameter SETUP_ALL = 1000; + parameter SETUP_READ_FIRST = 3000; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + output [15:0] DOADO; + output [15:0] DOBDO; + output [1:0] DOPADOP; + output [1:0] DOPBDOP; + input [12:0] ADDRAWRADDR; + input [12:0] ADDRBRDADDR; + (* clkbuf_sink *) + input CLKAWRCLK; + (* clkbuf_sink *) + input CLKBRDCLK; + input [15:0] DIADI; + input [15:0] DIBDI; + input [1:0] DIPADIP; + input [1:0] DIPBDIP; + input ENAWREN; + input ENBRDEN; + input REGCEA; + input REGCEBREGCE; + input RSTA; + input RSTBRST; + input [1:0] WEAWEL; + input [1:0] WEBWEU; +endmodule + +module FIFO16 (...); + parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; + parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; + parameter integer DATA_WIDTH = 36; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + input [31:0] DI; + input [3:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module RAMB16 (...); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter INVERT_CLK_DOA_REG = "FALSE"; + parameter INVERT_CLK_DOB_REG = "FALSE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output CASCADEOUTA; + output CASCADEOUTB; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + input ENA; + (* clkbuf_sink *) + input CLKA; + input SSRA; + input CASCADEINA; + input REGCEA; + input ENB; + (* clkbuf_sink *) + input CLKB; + input SSRB; + input CASCADEINB; + input REGCEB; + input [14:0] ADDRA; + input [14:0] ADDRB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input [3:0] WEA; + input [3:0] WEB; +endmodule + +module RAMB32_S64_ECC (...); + parameter DO_REG = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + output [1:0] STATUS; + output [63:0] DO; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input SSR; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [63:0] DI; + input [8:0] RDADDR; + input [8:0] WRADDR; +endmodule + +module FIFO18 (...); + parameter [11:0] ALMOST_EMPTY_OFFSET = 12'h080; + parameter [11:0] ALMOST_FULL_OFFSET = 12'h080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [15:0] DO; + output [1:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + input [15:0] DI; + input [1:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module FIFO18_36 (...); + parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; + parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [8:0] RDCOUNT; + output RDERR; + output [8:0] WRCOUNT; + output WRERR; + input [31:0] DI; + input [3:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module FIFO36 (...); + parameter [12:0] ALMOST_EMPTY_OFFSET = 13'h080; + parameter [12:0] ALMOST_FULL_OFFSET = 13'h080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output [12:0] WRCOUNT; + output WRERR; + input [31:0] DI; + input [3:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module FIFO36_72 (...); + parameter [8:0] ALMOST_EMPTY_OFFSET = 9'h080; + parameter [8:0] ALMOST_FULL_OFFSET = 9'h080; + parameter integer DO_REG = 1; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_SYN = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter SIM_MODE = "SAFE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [8:0] RDCOUNT; + output RDERR; + output SBITERR; + output [8:0] WRCOUNT; + output WRERR; + input [63:0] DI; + input [7:0] DIP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RST; + (* clkbuf_sink *) + input WRCLK; + input WREN; +endmodule + +module RAMB18 (...); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [17:0] INIT_A = 18'h0; + parameter [17:0] INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter [17:0] SRVAL_A = 18'h0; + parameter [17:0] SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output [15:0] DOA; + output [15:0] DOB; + output [1:0] DOPA; + output [1:0] DOPB; + input ENA; + (* clkbuf_sink *) + input CLKA; + input SSRA; + input REGCEA; + input ENB; + (* clkbuf_sink *) + input CLKB; + input SSRB; + input REGCEB; + input [13:0] ADDRA; + input [13:0] ADDRB; + input [15:0] DIA; + input [15:0] DIB; + input [1:0] DIPA; + input [1:0] DIPB; + input [1:0] WEA; + input [1:0] WEB; +endmodule + +module RAMB36 (...); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h0; + parameter [35:0] INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter [35:0] SRVAL_A = 36'h0; + parameter [35:0] SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output CASCADEOUTLATA; + output CASCADEOUTREGA; + output CASCADEOUTLATB; + output CASCADEOUTREGB; + output [31:0] DOA; + output [31:0] DOB; + output [3:0] DOPA; + output [3:0] DOPB; + input ENA; + (* clkbuf_sink *) + input CLKA; + input SSRA; + input CASCADEINLATA; + input CASCADEINREGA; + input REGCEA; + input ENB; + (* clkbuf_sink *) + input CLKB; + input SSRB; + input CASCADEINLATB; + input CASCADEINREGB; + input REGCEB; + input [15:0] ADDRA; + input [15:0] ADDRB; + input [31:0] DIA; + input [31:0] DIB; + input [3:0] DIPA; + input [3:0] DIPB; + input [3:0] WEA; + input [3:0] WEB; +endmodule + +module RAMB18SDP (...); + parameter integer DO_REG = 0; + parameter [35:0] INIT = 36'h0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_FILE = "NONE"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter [35:0] SRVAL = 36'h0; + output [31:0] DO; + output [3:0] DOP; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input REGCE; + input SSR; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [8:0] WRADDR; + input [8:0] RDADDR; + input [31:0] DI; + input [3:0] DIP; + input [3:0] WE; +endmodule + +module RAMB36SDP (...); + parameter integer DO_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_SCRUB = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter [71:0] INIT = 72'h0; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_FILE = "NONE"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_MODE = "SAFE"; + parameter [71:0] SRVAL = 72'h0; + output DBITERR; + output SBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input REGCE; + input SSR; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [8:0] WRADDR; + input [8:0] RDADDR; + input [63:0] DI; + input [7:0] DIP; + input [7:0] WE; +endmodule + +module FIFO18E1 (...); + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO18"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter INIT = 36'h0; + parameter SIM_DEVICE = "VIRTEX6"; + parameter SRVAL = 36'h0; + parameter IS_RDCLK_INVERTED = 1'b0; + parameter IS_RDEN_INVERTED = 1'b0; + parameter IS_RSTREG_INVERTED = 1'b0; + parameter IS_RST_INVERTED = 1'b0; + parameter IS_WRCLK_INVERTED = 1'b0; + parameter IS_WREN_INVERTED = 1'b0; + output ALMOSTEMPTY; + output ALMOSTFULL; + output [31:0] DO; + output [3:0] DOP; + output EMPTY; + output FULL; + output [11:0] RDCOUNT; + output RDERR; + output [11:0] WRCOUNT; + output WRERR; + input [31:0] DI; + input [3:0] DIP; + (* clkbuf_sink *) + (* invertible_pin = "IS_RDCLK_INVERTED" *) + input RDCLK; + (* invertible_pin = "IS_RDEN_INVERTED" *) + input RDEN; + input REGCE; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RSTREG_INVERTED" *) + input RSTREG; + (* clkbuf_sink *) + (* invertible_pin = "IS_WRCLK_INVERTED" *) + input WRCLK; + (* invertible_pin = "IS_WREN_INVERTED" *) + input WREN; +endmodule + +module FIFO36E1 (...); + parameter ALMOST_EMPTY_OFFSET = 13'h0080; + parameter ALMOST_FULL_OFFSET = 13'h0080; + parameter integer DATA_WIDTH = 4; + parameter integer DO_REG = 1; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter EN_SYN = "FALSE"; + parameter FIFO_MODE = "FIFO36"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter INIT = 72'h0; + parameter SIM_DEVICE = "VIRTEX6"; + parameter SRVAL = 72'h0; + parameter IS_RDCLK_INVERTED = 1'b0; + parameter IS_RDEN_INVERTED = 1'b0; + parameter IS_RSTREG_INVERTED = 1'b0; + parameter IS_RST_INVERTED = 1'b0; + parameter IS_WRCLK_INVERTED = 1'b0; + parameter IS_WREN_INVERTED = 1'b0; + output ALMOSTEMPTY; + output ALMOSTFULL; + output DBITERR; + output [63:0] DO; + output [7:0] DOP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output [12:0] RDCOUNT; + output RDERR; + output SBITERR; + output [12:0] WRCOUNT; + output WRERR; + input [63:0] DI; + input [7:0] DIP; + input INJECTDBITERR; + input INJECTSBITERR; + (* clkbuf_sink *) + (* invertible_pin = "IS_RDCLK_INVERTED" *) + input RDCLK; + (* invertible_pin = "IS_RDEN_INVERTED" *) + input RDEN; + input REGCE; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RSTREG_INVERTED" *) + input RSTREG; + (* clkbuf_sink *) + (* invertible_pin = "IS_WRCLK_INVERTED" *) + input WRCLK; + (* invertible_pin = "IS_WREN_INVERTED" *) + input WREN; +endmodule + +module RAMB18E1 (...); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 18'h0; + parameter INIT_B = 18'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_DEVICE = "VIRTEX6"; + parameter SRVAL_A = 18'h0; + parameter SRVAL_B = 18'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + parameter IS_CLKARDCLK_INVERTED = 1'b0; + parameter IS_CLKBWRCLK_INVERTED = 1'b0; + parameter IS_ENARDEN_INVERTED = 1'b0; + parameter IS_ENBWREN_INVERTED = 1'b0; + parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter IS_RSTRAMB_INVERTED = 1'b0; + parameter IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter IS_RSTREGB_INVERTED = 1'b0; + output [15:0] DOADO; + output [15:0] DOBDO; + output [1:0] DOPADOP; + output [1:0] DOPBDOP; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK; + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN; + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN; + input REGCEAREGCE; + input REGCEB; + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM; + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB; + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG; + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB; + input [13:0] ADDRARDADDR; + input [13:0] ADDRBWRADDR; + input [15:0] DIADI; + input [15:0] DIBDI; + input [1:0] DIPADIP; + input [1:0] DIPBDIP; + input [1:0] WEA; + input [3:0] WEBWE; +endmodule + +module RAMB36E1 (...); + parameter integer DOA_REG = 0; + parameter integer DOB_REG = 0; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter INIT_A = 36'h0; + parameter INIT_B = 36'h0; + parameter INIT_FILE = "NONE"; + parameter RAM_EXTENSION_A = "NONE"; + parameter RAM_EXTENSION_B = "NONE"; + parameter RAM_MODE = "TDP"; + parameter RDADDR_COLLISION_HWCONFIG = "DELAYED_WRITE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SIM_DEVICE = "VIRTEX6"; + parameter SRVAL_A = 36'h0; + parameter SRVAL_B = 36'h0; + parameter WRITE_MODE_A = "WRITE_FIRST"; + parameter WRITE_MODE_B = "WRITE_FIRST"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + parameter IS_CLKARDCLK_INVERTED = 1'b0; + parameter IS_CLKBWRCLK_INVERTED = 1'b0; + parameter IS_ENARDEN_INVERTED = 1'b0; + parameter IS_ENBWREN_INVERTED = 1'b0; + parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter IS_RSTRAMB_INVERTED = 1'b0; + parameter IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter IS_RSTREGB_INVERTED = 1'b0; + output CASCADEOUTA; + output CASCADEOUTB; + output [31:0] DOADO; + output [31:0] DOBDO; + output [3:0] DOPADOP; + output [3:0] DOPBDOP; + output [7:0] ECCPARITY; + output [8:0] RDADDRECC; + output SBITERR; + output DBITERR; + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK; + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM; + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG; + input CASCADEINA; + input REGCEAREGCE; + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK; + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB; + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB; + input CASCADEINB; + input REGCEB; + input INJECTDBITERR; + input INJECTSBITERR; + input [15:0] ADDRARDADDR; + input [15:0] ADDRBWRADDR; + input [31:0] DIADI; + input [31:0] DIBDI; + input [3:0] DIPADIP; + input [3:0] DIPBDIP; + input [3:0] WEA; + input [7:0] WEBWE; +endmodule + +module FIFO18E2 (...); + parameter CASCADE_ORDER = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter [35:0] INIT = 36'h000000000; + parameter [0:0] IS_RDCLK_INVERTED = 1'b0; + parameter [0:0] IS_RDEN_INVERTED = 1'b0; + parameter [0:0] IS_RSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter [0:0] IS_WRCLK_INVERTED = 1'b0; + parameter [0:0] IS_WREN_INVERTED = 1'b0; + parameter integer PROG_EMPTY_THRESH = 256; + parameter integer PROG_FULL_THRESH = 256; + parameter RDCOUNT_TYPE = "RAW_PNTR"; + parameter integer READ_WIDTH = 4; + parameter REGISTER_MODE = "UNREGISTERED"; + parameter RSTREG_PRIORITY = "RSTREG"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [35:0] SRVAL = 36'h000000000; + parameter WRCOUNT_TYPE = "RAW_PNTR"; + parameter integer WRITE_WIDTH = 4; + output [31:0] CASDOUT; + output [3:0] CASDOUTP; + output CASNXTEMPTY; + output CASPRVRDEN; + output [31:0] DOUT; + output [3:0] DOUTP; + output EMPTY; + output FULL; + output PROGEMPTY; + output PROGFULL; + output [12:0] RDCOUNT; + output RDERR; + output RDRSTBUSY; + output [12:0] WRCOUNT; + output WRERR; + output WRRSTBUSY; + input [31:0] CASDIN; + input [3:0] CASDINP; + input CASDOMUX; + input CASDOMUXEN; + input CASNXTRDEN; + input CASOREGIMUX; + input CASOREGIMUXEN; + input CASPRVEMPTY; + input [31:0] DIN; + input [3:0] DINP; + (* clkbuf_sink *) + (* invertible_pin = "IS_RDCLK_INVERTED" *) + input RDCLK; + (* invertible_pin = "IS_RDEN_INVERTED" *) + input RDEN; + input REGCE; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RSTREG_INVERTED" *) + input RSTREG; + input SLEEP; + (* clkbuf_sink *) + (* invertible_pin = "IS_WRCLK_INVERTED" *) + input WRCLK; + (* invertible_pin = "IS_WREN_INVERTED" *) + input WREN; +endmodule + +module FIFO36E2 (...); + parameter CASCADE_ORDER = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter EN_ECC_PIPE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter FIRST_WORD_FALL_THROUGH = "FALSE"; + parameter [71:0] INIT = 72'h000000000000000000; + parameter [0:0] IS_RDCLK_INVERTED = 1'b0; + parameter [0:0] IS_RDEN_INVERTED = 1'b0; + parameter [0:0] IS_RSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter [0:0] IS_WRCLK_INVERTED = 1'b0; + parameter [0:0] IS_WREN_INVERTED = 1'b0; + parameter integer PROG_EMPTY_THRESH = 256; + parameter integer PROG_FULL_THRESH = 256; + parameter RDCOUNT_TYPE = "RAW_PNTR"; + parameter integer READ_WIDTH = 4; + parameter REGISTER_MODE = "UNREGISTERED"; + parameter RSTREG_PRIORITY = "RSTREG"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [71:0] SRVAL = 72'h000000000000000000; + parameter WRCOUNT_TYPE = "RAW_PNTR"; + parameter integer WRITE_WIDTH = 4; + output [63:0] CASDOUT; + output [7:0] CASDOUTP; + output CASNXTEMPTY; + output CASPRVRDEN; + output DBITERR; + output [63:0] DOUT; + output [7:0] DOUTP; + output [7:0] ECCPARITY; + output EMPTY; + output FULL; + output PROGEMPTY; + output PROGFULL; + output [13:0] RDCOUNT; + output RDERR; + output RDRSTBUSY; + output SBITERR; + output [13:0] WRCOUNT; + output WRERR; + output WRRSTBUSY; + input [63:0] CASDIN; + input [7:0] CASDINP; + input CASDOMUX; + input CASDOMUXEN; + input CASNXTRDEN; + input CASOREGIMUX; + input CASOREGIMUXEN; + input CASPRVEMPTY; + input [63:0] DIN; + input [7:0] DINP; + input INJECTDBITERR; + input INJECTSBITERR; + (* clkbuf_sink *) + (* invertible_pin = "IS_RDCLK_INVERTED" *) + input RDCLK; + (* invertible_pin = "IS_RDEN_INVERTED" *) + input RDEN; + input REGCE; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RSTREG_INVERTED" *) + input RSTREG; + input SLEEP; + (* clkbuf_sink *) + (* invertible_pin = "IS_WRCLK_INVERTED" *) + input WRCLK; + (* invertible_pin = "IS_WREN_INVERTED" *) + input WREN; +endmodule + +module RAMB18E2 (...); + parameter CASCADE_ORDER_A = "NONE"; + parameter CASCADE_ORDER_B = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter integer DOA_REG = 1; + parameter integer DOB_REG = 1; + parameter ENADDRENA = "FALSE"; + parameter ENADDRENB = "FALSE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [17:0] INIT_A = 18'h00000; + parameter [17:0] INIT_B = 18'h00000; + parameter INIT_FILE = "NONE"; + parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; + parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; + parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; + parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; + parameter RDADDRCHANGEA = "FALSE"; + parameter RDADDRCHANGEB = "FALSE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [17:0] SRVAL_A = 18'h00000; + parameter [17:0] SRVAL_B = 18'h00000; + parameter WRITE_MODE_A = "NO_CHANGE"; + parameter WRITE_MODE_B = "NO_CHANGE"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output [15:0] CASDOUTA; + output [15:0] CASDOUTB; + output [1:0] CASDOUTPA; + output [1:0] CASDOUTPB; + output [15:0] DOUTADOUT; + output [15:0] DOUTBDOUT; + output [1:0] DOUTPADOUTP; + output [1:0] DOUTPBDOUTP; + input [13:0] ADDRARDADDR; + input [13:0] ADDRBWRADDR; + input ADDRENA; + input ADDRENB; + input CASDIMUXA; + input CASDIMUXB; + input [15:0] CASDINA; + input [15:0] CASDINB; + input [1:0] CASDINPA; + input [1:0] CASDINPB; + input CASDOMUXA; + input CASDOMUXB; + input CASDOMUXEN_A; + input CASDOMUXEN_B; + input CASOREGIMUXA; + input CASOREGIMUXB; + input CASOREGIMUXEN_A; + input CASOREGIMUXEN_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK; + input [15:0] DINADIN; + input [15:0] DINBDIN; + input [1:0] DINPADINP; + input [1:0] DINPBDINP; + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN; + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN; + input REGCEAREGCE; + input REGCEB; + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM; + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB; + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG; + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB; + input SLEEP; + input [1:0] WEA; + input [3:0] WEBWE; +endmodule + +module RAMB36E2 (...); + parameter CASCADE_ORDER_A = "NONE"; + parameter CASCADE_ORDER_B = "NONE"; + parameter CLOCK_DOMAINS = "INDEPENDENT"; + parameter integer DOA_REG = 1; + parameter integer DOB_REG = 1; + parameter ENADDRENA = "FALSE"; + parameter ENADDRENB = "FALSE"; + parameter EN_ECC_PIPE = "FALSE"; + parameter EN_ECC_READ = "FALSE"; + parameter EN_ECC_WRITE = "FALSE"; + parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; + parameter [35:0] INIT_A = 36'h000000000; + parameter [35:0] INIT_B = 36'h000000000; + parameter INIT_FILE = "NONE"; + parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; + parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; + parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; + parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; + parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; + parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; + parameter RDADDRCHANGEA = "FALSE"; + parameter RDADDRCHANGEB = "FALSE"; + parameter integer READ_WIDTH_A = 0; + parameter integer READ_WIDTH_B = 0; + parameter RSTREG_PRIORITY_A = "RSTREG"; + parameter RSTREG_PRIORITY_B = "RSTREG"; + parameter SIM_COLLISION_CHECK = "ALL"; + parameter SLEEP_ASYNC = "FALSE"; + parameter [35:0] SRVAL_A = 36'h000000000; + parameter [35:0] SRVAL_B = 36'h000000000; + parameter WRITE_MODE_A = "NO_CHANGE"; + parameter WRITE_MODE_B = "NO_CHANGE"; + parameter integer WRITE_WIDTH_A = 0; + parameter integer WRITE_WIDTH_B = 0; + output [31:0] CASDOUTA; + output [31:0] CASDOUTB; + output [3:0] CASDOUTPA; + output [3:0] CASDOUTPB; + output CASOUTDBITERR; + output CASOUTSBITERR; + output DBITERR; + output [31:0] DOUTADOUT; + output [31:0] DOUTBDOUT; + output [3:0] DOUTPADOUTP; + output [3:0] DOUTPBDOUTP; + output [7:0] ECCPARITY; + output [8:0] RDADDRECC; + output SBITERR; + input [14:0] ADDRARDADDR; + input [14:0] ADDRBWRADDR; + input ADDRENA; + input ADDRENB; + input CASDIMUXA; + input CASDIMUXB; + input [31:0] CASDINA; + input [31:0] CASDINB; + input [3:0] CASDINPA; + input [3:0] CASDINPB; + input CASDOMUXA; + input CASDOMUXB; + input CASDOMUXEN_A; + input CASDOMUXEN_B; + input CASINDBITERR; + input CASINSBITERR; + input CASOREGIMUXA; + input CASOREGIMUXB; + input CASOREGIMUXEN_A; + input CASOREGIMUXEN_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) + input CLKARDCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) + input CLKBWRCLK; + input [31:0] DINADIN; + input [31:0] DINBDIN; + input [3:0] DINPADINP; + input [3:0] DINPBDINP; + input ECCPIPECE; + (* invertible_pin = "IS_ENARDEN_INVERTED" *) + input ENARDEN; + (* invertible_pin = "IS_ENBWREN_INVERTED" *) + input ENBWREN; + input INJECTDBITERR; + input INJECTSBITERR; + input REGCEAREGCE; + input REGCEB; + (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) + input RSTRAMARSTRAM; + (* invertible_pin = "IS_RSTRAMB_INVERTED" *) + input RSTRAMB; + (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) + input RSTREGARSTREG; + (* invertible_pin = "IS_RSTREGB_INVERTED" *) + input RSTREGB; + input SLEEP; + input [3:0] WEA; + input [7:0] WEBWE; +endmodule + +module URAM288 (...); + parameter integer AUTO_SLEEP_LATENCY = 8; + parameter integer AVG_CONS_INACTIVE_CYCLES = 10; + parameter BWE_MODE_A = "PARITY_INTERLEAVED"; + parameter BWE_MODE_B = "PARITY_INTERLEAVED"; + parameter CASCADE_ORDER_A = "NONE"; + parameter CASCADE_ORDER_B = "NONE"; + parameter EN_AUTO_SLEEP_MODE = "FALSE"; + parameter EN_ECC_RD_A = "FALSE"; + parameter EN_ECC_RD_B = "FALSE"; + parameter EN_ECC_WR_A = "FALSE"; + parameter EN_ECC_WR_B = "FALSE"; + parameter IREG_PRE_A = "FALSE"; + parameter IREG_PRE_B = "FALSE"; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_EN_A_INVERTED = 1'b0; + parameter [0:0] IS_EN_B_INVERTED = 1'b0; + parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0; + parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0; + parameter [0:0] IS_RST_A_INVERTED = 1'b0; + parameter [0:0] IS_RST_B_INVERTED = 1'b0; + parameter MATRIX_ID = "NONE"; + parameter integer NUM_UNIQUE_SELF_ADDR_A = 1; + parameter integer NUM_UNIQUE_SELF_ADDR_B = 1; + parameter integer NUM_URAM_IN_MATRIX = 1; + parameter OREG_A = "FALSE"; + parameter OREG_B = "FALSE"; + parameter OREG_ECC_A = "FALSE"; + parameter OREG_ECC_B = "FALSE"; + parameter REG_CAS_A = "FALSE"; + parameter REG_CAS_B = "FALSE"; + parameter RST_MODE_A = "SYNC"; + parameter RST_MODE_B = "SYNC"; + parameter [10:0] SELF_ADDR_A = 11'h000; + parameter [10:0] SELF_ADDR_B = 11'h000; + parameter [10:0] SELF_MASK_A = 11'h7FF; + parameter [10:0] SELF_MASK_B = 11'h7FF; + parameter USE_EXT_CE_A = "FALSE"; + parameter USE_EXT_CE_B = "FALSE"; + output [22:0] CAS_OUT_ADDR_A; + output [22:0] CAS_OUT_ADDR_B; + output [8:0] CAS_OUT_BWE_A; + output [8:0] CAS_OUT_BWE_B; + output CAS_OUT_DBITERR_A; + output CAS_OUT_DBITERR_B; + output [71:0] CAS_OUT_DIN_A; + output [71:0] CAS_OUT_DIN_B; + output [71:0] CAS_OUT_DOUT_A; + output [71:0] CAS_OUT_DOUT_B; + output CAS_OUT_EN_A; + output CAS_OUT_EN_B; + output CAS_OUT_RDACCESS_A; + output CAS_OUT_RDACCESS_B; + output CAS_OUT_RDB_WR_A; + output CAS_OUT_RDB_WR_B; + output CAS_OUT_SBITERR_A; + output CAS_OUT_SBITERR_B; + output DBITERR_A; + output DBITERR_B; + output [71:0] DOUT_A; + output [71:0] DOUT_B; + output RDACCESS_A; + output RDACCESS_B; + output SBITERR_A; + output SBITERR_B; + input [22:0] ADDR_A; + input [22:0] ADDR_B; + input [8:0] BWE_A; + input [8:0] BWE_B; + input [22:0] CAS_IN_ADDR_A; + input [22:0] CAS_IN_ADDR_B; + input [8:0] CAS_IN_BWE_A; + input [8:0] CAS_IN_BWE_B; + input CAS_IN_DBITERR_A; + input CAS_IN_DBITERR_B; + input [71:0] CAS_IN_DIN_A; + input [71:0] CAS_IN_DIN_B; + input [71:0] CAS_IN_DOUT_A; + input [71:0] CAS_IN_DOUT_B; + input CAS_IN_EN_A; + input CAS_IN_EN_B; + input CAS_IN_RDACCESS_A; + input CAS_IN_RDACCESS_B; + input CAS_IN_RDB_WR_A; + input CAS_IN_RDB_WR_B; + input CAS_IN_SBITERR_A; + input CAS_IN_SBITERR_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [71:0] DIN_A; + input [71:0] DIN_B; + (* invertible_pin = "IS_EN_A_INVERTED" *) + input EN_A; + (* invertible_pin = "IS_EN_B_INVERTED" *) + input EN_B; + input INJECT_DBITERR_A; + input INJECT_DBITERR_B; + input INJECT_SBITERR_A; + input INJECT_SBITERR_B; + input OREG_CE_A; + input OREG_CE_B; + input OREG_ECC_CE_A; + input OREG_ECC_CE_B; + (* invertible_pin = "IS_RDB_WR_A_INVERTED" *) + input RDB_WR_A; + (* invertible_pin = "IS_RDB_WR_B_INVERTED" *) + input RDB_WR_B; + (* invertible_pin = "IS_RST_A_INVERTED" *) + input RST_A; + (* invertible_pin = "IS_RST_B_INVERTED" *) + input RST_B; + input SLEEP; +endmodule + +module URAM288_BASE (...); + parameter integer AUTO_SLEEP_LATENCY = 8; + parameter integer AVG_CONS_INACTIVE_CYCLES = 10; + parameter BWE_MODE_A = "PARITY_INTERLEAVED"; + parameter BWE_MODE_B = "PARITY_INTERLEAVED"; + parameter EN_AUTO_SLEEP_MODE = "FALSE"; + parameter EN_ECC_RD_A = "FALSE"; + parameter EN_ECC_RD_B = "FALSE"; + parameter EN_ECC_WR_A = "FALSE"; + parameter EN_ECC_WR_B = "FALSE"; + parameter IREG_PRE_A = "FALSE"; + parameter IREG_PRE_B = "FALSE"; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_EN_A_INVERTED = 1'b0; + parameter [0:0] IS_EN_B_INVERTED = 1'b0; + parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0; + parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0; + parameter [0:0] IS_RST_A_INVERTED = 1'b0; + parameter [0:0] IS_RST_B_INVERTED = 1'b0; + parameter OREG_A = "FALSE"; + parameter OREG_B = "FALSE"; + parameter OREG_ECC_A = "FALSE"; + parameter OREG_ECC_B = "FALSE"; + parameter RST_MODE_A = "SYNC"; + parameter RST_MODE_B = "SYNC"; + parameter USE_EXT_CE_A = "FALSE"; + parameter USE_EXT_CE_B = "FALSE"; + output DBITERR_A; + output DBITERR_B; + output [71:0] DOUT_A; + output [71:0] DOUT_B; + output SBITERR_A; + output SBITERR_B; + input [22:0] ADDR_A; + input [22:0] ADDR_B; + input [8:0] BWE_A; + input [8:0] BWE_B; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [71:0] DIN_A; + input [71:0] DIN_B; + (* invertible_pin = "IS_EN_A_INVERTED" *) + input EN_A; + (* invertible_pin = "IS_EN_B_INVERTED" *) + input EN_B; + input INJECT_DBITERR_A; + input INJECT_DBITERR_B; + input INJECT_SBITERR_A; + input INJECT_SBITERR_B; + input OREG_CE_A; + input OREG_CE_B; + input OREG_ECC_CE_A; + input OREG_ECC_CE_B; + (* invertible_pin = "IS_RDB_WR_A_INVERTED" *) + input RDB_WR_A; + (* invertible_pin = "IS_RDB_WR_B_INVERTED" *) + input RDB_WR_B; + (* invertible_pin = "IS_RST_A_INVERTED" *) + input RST_A; + (* invertible_pin = "IS_RST_B_INVERTED" *) + input RST_B; + input SLEEP; +endmodule + +module MULT18X18 (...); + output [35:0] P; + input [17:0] A; + input [17:0] B; +endmodule + +module MULT18X18S (...); + output [35:0] P; + input [17:0] A; + input [17:0] B; + (* clkbuf_sink *) + input C; + input CE; + input R; +endmodule + +module MULT18X18SIO (...); + parameter integer AREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer PREG = 1; + output [17:0] BCOUT; + output [35:0] P; + input [17:0] A; + input [17:0] B; + input [17:0] BCIN; + input CEA; + input CEB; + input CEP; + (* clkbuf_sink *) + input CLK; + input RSTA; + input RSTB; + input RSTP; +endmodule + +module DSP48A (...); + parameter integer A0REG = 0; + parameter integer A1REG = 1; + parameter integer B0REG = 0; + parameter integer B1REG = 1; + parameter integer CARRYINREG = 1; + parameter CARRYINSEL = "CARRYIN"; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter RSTTYPE = "SYNC"; + output [17:0] BCOUT; + output CARRYOUT; + output [47:0] P; + output [47:0] PCOUT; + input [17:0] A; + input [17:0] B; + input [47:0] C; + input CARRYIN; + input CEA; + input CEB; + input CEC; + input CECARRYIN; + input CED; + input CEM; + input CEOPMODE; + input CEP; + (* clkbuf_sink *) + input CLK; + input [17:0] D; + input [7:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTB; + input RSTC; + input RSTCARRYIN; + input RSTD; + input RSTM; + input RSTOPMODE; + input RSTP; +endmodule + +module DSP48A1 (...); + parameter integer A0REG = 0; + parameter integer A1REG = 1; + parameter integer B0REG = 0; + parameter integer B1REG = 1; + parameter integer CARRYINREG = 1; + parameter integer CARRYOUTREG = 1; + parameter CARRYINSEL = "OPMODE5"; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter RSTTYPE = "SYNC"; + output [17:0] BCOUT; + output CARRYOUT; + output CARRYOUTF; + output [35:0] M; + output [47:0] P; + output [47:0] PCOUT; + input [17:0] A; + input [17:0] B; + input [47:0] C; + input CARRYIN; + input CEA; + input CEB; + input CEC; + input CECARRYIN; + input CED; + input CEM; + input CEOPMODE; + input CEP; + (* clkbuf_sink *) + input CLK; + input [17:0] D; + input [7:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTB; + input RSTC; + input RSTCARRYIN; + input RSTD; + input RSTM; + input RSTOPMODE; + input RSTP; +endmodule + +module DSP48 (...); + parameter integer AREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter LEGACY_MODE = "MULT18X18S"; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter integer PREG = 1; + parameter integer SUBTRACTREG = 1; + output [17:0] BCOUT; + output [47:0] P; + output [47:0] PCOUT; + input [17:0] A; + input [17:0] B; + input [17:0] BCIN; + input [47:0] C; + input CARRYIN; + input [1:0] CARRYINSEL; + input CEA; + input CEB; + input CEC; + input CECARRYIN; + input CECINSUB; + input CECTRL; + input CEM; + input CEP; + (* clkbuf_sink *) + input CLK; + input [6:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTB; + input RSTC; + input RSTCARRYIN; + input RSTCTRL; + input RSTM; + input RSTP; + input SUBTRACT; +endmodule + +module DSP48E (...); + parameter SIM_MODE = "SAFE"; + parameter integer ACASCREG = 1; + parameter integer ALUMODEREG = 1; + parameter integer AREG = 1; + parameter AUTORESET_PATTERN_DETECT = "FALSE"; + parameter AUTORESET_PATTERN_DETECT_OPTINV = "MATCH"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter integer MREG = 1; + parameter integer MULTCARRYINREG = 1; + parameter integer OPMODEREG = 1; + parameter [47:0] PATTERN = 48'h000000000000; + parameter integer PREG = 1; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter SEL_ROUNDING_MASK = "SEL_MASK"; + parameter USE_MULT = "MULT_S"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + output [29:0] ACOUT; + output [17:0] BCOUT; + output CARRYCASCOUT; + output [3:0] CARRYOUT; + output MULTSIGNOUT; + output OVERFLOW; + output [47:0] P; + output PATTERNBDETECT; + output PATTERNDETECT; + output [47:0] PCOUT; + output UNDERFLOW; + input [29:0] A; + input [29:0] ACIN; + input [3:0] ALUMODE; + input [17:0] B; + input [17:0] BCIN; + input [47:0] C; + input CARRYCASCIN; + input CARRYIN; + input [2:0] CARRYINSEL; + input CEA1; + input CEA2; + input CEALUMODE; + input CEB1; + input CEB2; + input CEC; + input CECARRYIN; + input CECTRL; + input CEM; + input CEMULTCARRYIN; + input CEP; + (* clkbuf_sink *) + input CLK; + input MULTSIGNIN; + input [6:0] OPMODE; + input [47:0] PCIN; + input RSTA; + input RSTALLCARRYIN; + input RSTALUMODE; + input RSTB; + input RSTC; + input RSTCTRL; + input RSTM; + input RSTP; +endmodule + +module DSP48E2 (...); + parameter integer ACASCREG = 1; + parameter integer ADREG = 1; + parameter integer ALUMODEREG = 1; + parameter AMULTSEL = "A"; + parameter integer AREG = 1; + parameter AUTORESET_PATDET = "NO_RESET"; + parameter AUTORESET_PRIORITY = "RESET"; + parameter A_INPUT = "DIRECT"; + parameter integer BCASCREG = 1; + parameter BMULTSEL = "B"; + parameter integer BREG = 1; + parameter B_INPUT = "DIRECT"; + parameter integer CARRYINREG = 1; + parameter integer CARRYINSELREG = 1; + parameter integer CREG = 1; + parameter integer DREG = 1; + parameter integer INMODEREG = 1; + parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000; + parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [4:0] IS_INMODE_INVERTED = 5'b00000; + parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000; + parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0; + parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0; + parameter [0:0] IS_RSTA_INVERTED = 1'b0; + parameter [0:0] IS_RSTB_INVERTED = 1'b0; + parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0; + parameter [0:0] IS_RSTC_INVERTED = 1'b0; + parameter [0:0] IS_RSTD_INVERTED = 1'b0; + parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0; + parameter [0:0] IS_RSTM_INVERTED = 1'b0; + parameter [0:0] IS_RSTP_INVERTED = 1'b0; + parameter [47:0] MASK = 48'h3FFFFFFFFFFF; + parameter integer MREG = 1; + parameter integer OPMODEREG = 1; + parameter [47:0] PATTERN = 48'h000000000000; + parameter PREADDINSEL = "A"; + parameter integer PREG = 1; + parameter [47:0] RND = 48'h000000000000; + parameter SEL_MASK = "MASK"; + parameter SEL_PATTERN = "PATTERN"; + parameter USE_MULT = "MULTIPLY"; + parameter USE_PATTERN_DETECT = "NO_PATDET"; + parameter USE_SIMD = "ONE48"; + parameter USE_WIDEXOR = "FALSE"; + parameter XORSIMD = "XOR24_48_96"; + output [29:0] ACOUT; + output [17:0] BCOUT; + output CARRYCASCOUT; + output [3:0] CARRYOUT; + output MULTSIGNOUT; + output OVERFLOW; + output [47:0] P; + output PATTERNBDETECT; + output PATTERNDETECT; + output [47:0] PCOUT; + output UNDERFLOW; + output [7:0] XOROUT; + input [29:0] A; + input [29:0] ACIN; + (* invertible_pin = "IS_ALUMODE_INVERTED" *) + input [3:0] ALUMODE; + input [17:0] B; + input [17:0] BCIN; + input [47:0] C; + input CARRYCASCIN; + (* invertible_pin = "IS_CARRYIN_INVERTED" *) + input CARRYIN; + input [2:0] CARRYINSEL; + input CEA1; + input CEA2; + input CEAD; + input CEALUMODE; + input CEB1; + input CEB2; + input CEC; + input CECARRYIN; + input CECTRL; + input CED; + input CEINMODE; + input CEM; + input CEP; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [26:0] D; + (* invertible_pin = "IS_INMODE_INVERTED" *) + input [4:0] INMODE; + input MULTSIGNIN; + (* invertible_pin = "IS_OPMODE_INVERTED" *) + input [8:0] OPMODE; + input [47:0] PCIN; + (* invertible_pin = "IS_RSTA_INVERTED" *) + input RSTA; + (* invertible_pin = "IS_RSTALLCARRYIN_INVERTED" *) + input RSTALLCARRYIN; + (* invertible_pin = "IS_RSTALUMODE_INVERTED" *) + input RSTALUMODE; + (* invertible_pin = "IS_RSTB_INVERTED" *) + input RSTB; + (* invertible_pin = "IS_RSTC_INVERTED" *) + input RSTC; + (* invertible_pin = "IS_RSTCTRL_INVERTED" *) + input RSTCTRL; + (* invertible_pin = "IS_RSTD_INVERTED" *) + input RSTD; + (* invertible_pin = "IS_RSTINMODE_INVERTED" *) + input RSTINMODE; + (* invertible_pin = "IS_RSTM_INVERTED" *) + input RSTM; + (* invertible_pin = "IS_RSTP_INVERTED" *) + input RSTP; +endmodule + +module IFDDRCPE (...); + output Q0; + output Q1; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input CLR; + (* iopad_external_pin *) + input D; + input PRE; +endmodule + +module IFDDRRSE (...); + output Q0; + output Q1; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + (* iopad_external_pin *) + input D; + input R; + input S; +endmodule + +module OFDDRCPE (...); + (* iopad_external_pin *) + output Q; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input CLR; + input D0; + input D1; + input PRE; +endmodule + +module OFDDRRSE (...); + (* iopad_external_pin *) + output Q; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input R; + input S; +endmodule + +module OFDDRTCPE (...); + (* iopad_external_pin *) + output O; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input CLR; + input D0; + input D1; + input PRE; + input T; +endmodule + +module OFDDRTRSE (...); + (* iopad_external_pin *) + output O; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input R; + input S; + input T; +endmodule + +module IDDR2 (...); + parameter DDR_ALIGNMENT = "NONE"; + parameter [0:0] INIT_Q0 = 1'b0; + parameter [0:0] INIT_Q1 = 1'b0; + parameter SRTYPE = "SYNC"; + output Q0; + output Q1; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D; + input R; + input S; +endmodule + +module ODDR2 (...); + parameter DDR_ALIGNMENT = "NONE"; + parameter [0:0] INIT = 1'b0; + parameter SRTYPE = "SYNC"; + output Q; + (* clkbuf_sink *) + input C0; + (* clkbuf_sink *) + input C1; + input CE; + input D0; + input D1; + input R; + input S; +endmodule + +module IDDR (...); + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter SRTYPE = "SYNC"; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + output Q1; + output Q2; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + (* invertible_pin = "IS_D_INVERTED" *) + input D; + input R; + input S; +endmodule + +module IDDR_2CLK (...); + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter [0:0] IS_CB_INVERTED = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter SRTYPE = "SYNC"; + output Q1; + output Q2; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + (* clkbuf_sink *) + (* invertible_pin = "IS_CB_INVERTED" *) + input CB; + input CE; + (* invertible_pin = "IS_D_INVERTED" *) + input D; + input R; + input S; +endmodule + +module ODDR (...); + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + parameter SRTYPE = "SYNC"; + parameter MSGON = "TRUE"; + parameter XON = "TRUE"; + output Q; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + (* invertible_pin = "IS_D1_INVERTED" *) + input D1; + (* invertible_pin = "IS_D2_INVERTED" *) + input D2; + input R; + input S; +endmodule + +(* keep *) +module IDELAYCTRL (...); + parameter SIM_DEVICE = "7SERIES"; + output RDY; + (* clkbuf_sink *) + input REFCLK; + input RST; +endmodule + +module IDELAY (...); + parameter IOBDELAY_TYPE = "DEFAULT"; + parameter integer IOBDELAY_VALUE = 0; + output O; + (* clkbuf_sink *) + input C; + input CE; + input I; + input INC; + input RST; +endmodule + +module ISERDES (...); + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter IOBDELAY = "NONE"; + parameter IOBDELAY_TYPE = "DEFAULT"; + parameter integer IOBDELAY_VALUE = 0; + parameter integer NUM_CE = 2; + parameter SERDES_MODE = "MASTER"; + parameter integer SIM_DELAY_D = 0; + parameter integer SIM_SETUP_D_CLK = 0; + parameter integer SIM_HOLD_D_CLK = 0; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + input BITSLIP; + input CE1; + input CE2; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKDIV; + input D; + input DLYCE; + input DLYINC; + input DLYRST; + (* clkbuf_sink *) + input OCLK; + input REV; + input SHIFTIN1; + input SHIFTIN2; + input SR; +endmodule + +module OSERDES (...); + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter integer TRISTATE_WIDTH = 4; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TQ; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKDIV; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + input OCE; + input REV; + input SHIFTIN1; + input SHIFTIN2; + input SR; + input T1; + input T2; + input T3; + input T4; + input TCE; +endmodule + +module IODELAY (...); + parameter DELAY_SRC = "I"; + parameter HIGH_PERFORMANCE_MODE = "TRUE"; + parameter IDELAY_TYPE = "DEFAULT"; + parameter integer IDELAY_VALUE = 0; + parameter integer ODELAY_VALUE = 0; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + output DATAOUT; + (* clkbuf_sink *) + input C; + input CE; + input DATAIN; + input IDATAIN; + input INC; + input ODATAIN; + input RST; + input T; +endmodule + +module ISERDES_NODELAY (...); + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter INIT_Q1 = 1'b0; + parameter INIT_Q2 = 1'b0; + parameter INIT_Q3 = 1'b0; + parameter INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter integer NUM_CE = 2; + parameter SERDES_MODE = "MASTER"; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + input BITSLIP; + input CE1; + input CE2; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKB; + (* clkbuf_sink *) + input CLKDIV; + input D; + (* clkbuf_sink *) + input OCLK; + input RST; + input SHIFTIN1; + input SHIFTIN2; +endmodule + +module IODELAYE1 (...); + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "I"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter IDELAY_TYPE = "DEFAULT"; + parameter integer IDELAY_VALUE = 0; + parameter ODELAY_TYPE = "FIXED"; + parameter integer ODELAY_VALUE = 0; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + output [4:0] CNTVALUEOUT; + output DATAOUT; + (* clkbuf_sink *) + input C; + input CE; + input CINVCTRL; + input CLKIN; + input [4:0] CNTVALUEIN; + input DATAIN; + input IDATAIN; + input INC; + input ODATAIN; + input RST; + input T; +endmodule + +module ISERDESE1 (...); + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter DYN_CLKDIV_INV_EN = "FALSE"; + parameter DYN_CLK_INV_EN = "FALSE"; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter integer NUM_CE = 2; + parameter IOBDELAY = "NONE"; + parameter OFB_USED = "FALSE"; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output SHIFTOUT1; + output SHIFTOUT2; + input BITSLIP; + input CE1; + input CE2; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKB; + (* clkbuf_sink *) + input CLKDIV; + input D; + input DDLY; + input DYNCLKDIVSEL; + input DYNCLKSEL; + (* clkbuf_sink *) + input OCLK; + input OFB; + input RST; + input SHIFTIN1; + input SHIFTIN2; +endmodule + +module OSERDESE1 (...); + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter integer DDR3_DATA = 1; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter INTERFACE_TYPE = "DEFAULT"; + parameter integer ODELAY_USED = 0; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter integer TRISTATE_WIDTH = 4; + output OCBEXTEND; + output OFB; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TFB; + output TQ; + (* clkbuf_sink *) + input CLK; + (* clkbuf_sink *) + input CLKDIV; + input CLKPERF; + input CLKPERFDELAY; + input D1; + input D2; + input D3; + input D4; + input D5; + input D6; + input OCE; + input ODV; + input RST; + input SHIFTIN1; + input SHIFTIN2; + input T1; + input T2; + input T3; + input T4; + input TCE; + input WC; +endmodule + +module IDELAYE2 (...); + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "IDATAIN"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter IDELAY_TYPE = "FIXED"; + parameter integer IDELAY_VALUE = 0; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_DATAIN_INVERTED = 1'b0; + parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; + parameter PIPE_SEL = "FALSE"; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + parameter integer SIM_DELAY_D = 0; + output [4:0] CNTVALUEOUT; + output DATAOUT; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + input CINVCTRL; + input [4:0] CNTVALUEIN; + (* invertible_pin = "IS_DATAIN_INVERTED" *) + input DATAIN; + (* invertible_pin = "IS_IDATAIN_INVERTED" *) + input IDATAIN; + input INC; + input LD; + input LDPIPEEN; + input REGRST; +endmodule + +module ODELAYE2 (...); + parameter CINVCTRL_SEL = "FALSE"; + parameter DELAY_SRC = "ODATAIN"; + parameter HIGH_PERFORMANCE_MODE = "FALSE"; + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_ODATAIN_INVERTED = 1'b0; + parameter ODELAY_TYPE = "FIXED"; + parameter integer ODELAY_VALUE = 0; + parameter PIPE_SEL = "FALSE"; + parameter real REFCLK_FREQUENCY = 200.0; + parameter SIGNAL_PATTERN = "DATA"; + parameter integer SIM_DELAY_D = 0; + output [4:0] CNTVALUEOUT; + output DATAOUT; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + input CE; + input CINVCTRL; + input CLKIN; + input [4:0] CNTVALUEIN; + input INC; + input LD; + input LDPIPEEN; + (* invertible_pin = "IS_ODATAIN_INVERTED" *) + input ODATAIN; + input REGRST; +endmodule + +module ISERDESE2 (...); + parameter DATA_RATE = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter DYN_CLKDIV_INV_EN = "FALSE"; + parameter DYN_CLK_INV_EN = "FALSE"; + parameter [0:0] INIT_Q1 = 1'b0; + parameter [0:0] INIT_Q2 = 1'b0; + parameter [0:0] INIT_Q3 = 1'b0; + parameter [0:0] INIT_Q4 = 1'b0; + parameter INTERFACE_TYPE = "MEMORY"; + parameter IOBDELAY = "NONE"; + parameter [0:0] IS_CLKB_INVERTED = 1'b0; + parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0; + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_D_INVERTED = 1'b0; + parameter [0:0] IS_OCLKB_INVERTED = 1'b0; + parameter [0:0] IS_OCLK_INVERTED = 1'b0; + parameter integer NUM_CE = 2; + parameter OFB_USED = "FALSE"; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_Q1 = 1'b0; + parameter [0:0] SRVAL_Q2 = 1'b0; + parameter [0:0] SRVAL_Q3 = 1'b0; + parameter [0:0] SRVAL_Q4 = 1'b0; + output O; + output Q1; + output Q2; + output Q3; + output Q4; + output Q5; + output Q6; + output Q7; + output Q8; + output SHIFTOUT1; + output SHIFTOUT2; + input BITSLIP; + input CE1; + input CE2; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKB_INVERTED" *) + input CLKB; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKDIV_INVERTED" *) + input CLKDIV; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKDIVP_INVERTED" *) + input CLKDIVP; + (* invertible_pin = "IS_D_INVERTED" *) + input D; + input DDLY; + input DYNCLKDIVSEL; + input DYNCLKSEL; + (* clkbuf_sink *) + (* invertible_pin = "IS_OCLK_INVERTED" *) + input OCLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_OCLKB_INVERTED" *) + input OCLKB; + input OFB; + input RST; + input SHIFTIN1; + input SHIFTIN2; +endmodule + +module OSERDESE2 (...); + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_TQ = "DDR"; + parameter integer DATA_WIDTH = 4; + parameter [0:0] INIT_OQ = 1'b0; + parameter [0:0] INIT_TQ = 1'b0; + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + parameter [0:0] IS_D3_INVERTED = 1'b0; + parameter [0:0] IS_D4_INVERTED = 1'b0; + parameter [0:0] IS_D5_INVERTED = 1'b0; + parameter [0:0] IS_D6_INVERTED = 1'b0; + parameter [0:0] IS_D7_INVERTED = 1'b0; + parameter [0:0] IS_D8_INVERTED = 1'b0; + parameter [0:0] IS_T1_INVERTED = 1'b0; + parameter [0:0] IS_T2_INVERTED = 1'b0; + parameter [0:0] IS_T3_INVERTED = 1'b0; + parameter [0:0] IS_T4_INVERTED = 1'b0; + parameter SERDES_MODE = "MASTER"; + parameter [0:0] SRVAL_OQ = 1'b0; + parameter [0:0] SRVAL_TQ = 1'b0; + parameter TBYTE_CTL = "FALSE"; + parameter TBYTE_SRC = "FALSE"; + parameter integer TRISTATE_WIDTH = 4; + output OFB; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output TBYTEOUT; + output TFB; + output TQ; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKDIV_INVERTED" *) + input CLKDIV; + (* invertible_pin = "IS_D1_INVERTED" *) + input D1; + (* invertible_pin = "IS_D2_INVERTED" *) + input D2; + (* invertible_pin = "IS_D3_INVERTED" *) + input D3; + (* invertible_pin = "IS_D4_INVERTED" *) + input D4; + (* invertible_pin = "IS_D5_INVERTED" *) + input D5; + (* invertible_pin = "IS_D6_INVERTED" *) + input D6; + (* invertible_pin = "IS_D7_INVERTED" *) + input D7; + (* invertible_pin = "IS_D8_INVERTED" *) + input D8; + input OCE; + input RST; + input SHIFTIN1; + input SHIFTIN2; + (* invertible_pin = "IS_T1_INVERTED" *) + input T1; + (* invertible_pin = "IS_T2_INVERTED" *) + input T2; + (* invertible_pin = "IS_T3_INVERTED" *) + input T3; + (* invertible_pin = "IS_T4_INVERTED" *) + input T4; + input TBYTEIN; + input TCE; +endmodule + +module PHASER_IN (...); + parameter integer CLKOUT_DIV = 4; + parameter DQS_BIAS_MODE = "FALSE"; + parameter EN_ISERDES_RST = "FALSE"; + parameter integer FINE_DELAY = 0; + parameter FREQ_REF_DIV = "NONE"; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter real REFCLK_PERIOD = 0.000; + parameter integer SEL_CLK_OFFSET = 5; + parameter SYNC_IN_DIV_RST = "FALSE"; + output FINEOVERFLOW; + output ICLK; + output ICLKDIV; + output ISERDESRST; + output RCLK; + output [5:0] COUNTERREADVAL; + input COUNTERLOADEN; + input COUNTERREADEN; + input DIVIDERST; + input EDGEADV; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input SYNCIN; + input SYSCLK; + input [1:0] RANKSEL; + input [5:0] COUNTERLOADVAL; +endmodule + +module PHASER_IN_PHY (...); + parameter BURST_MODE = "FALSE"; + parameter integer CLKOUT_DIV = 4; + parameter [0:0] DQS_AUTO_RECAL = 1'b1; + parameter DQS_BIAS_MODE = "FALSE"; + parameter [2:0] DQS_FIND_PATTERN = 3'b001; + parameter integer FINE_DELAY = 0; + parameter FREQ_REF_DIV = "NONE"; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter real REFCLK_PERIOD = 0.000; + parameter integer SEL_CLK_OFFSET = 5; + parameter SYNC_IN_DIV_RST = "FALSE"; + parameter WR_CYCLES = "FALSE"; + output DQSFOUND; + output DQSOUTOFRANGE; + output FINEOVERFLOW; + output ICLK; + output ICLKDIV; + output ISERDESRST; + output PHASELOCKED; + output RCLK; + output WRENABLE; + output [5:0] COUNTERREADVAL; + input BURSTPENDINGPHY; + input COUNTERLOADEN; + input COUNTERREADEN; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input RSTDQSFIND; + input SYNCIN; + input SYSCLK; + input [1:0] ENCALIBPHY; + input [1:0] RANKSELPHY; + input [5:0] COUNTERLOADVAL; +endmodule + +module PHASER_OUT (...); + parameter integer CLKOUT_DIV = 4; + parameter COARSE_BYPASS = "FALSE"; + parameter integer COARSE_DELAY = 0; + parameter EN_OSERDES_RST = "FALSE"; + parameter integer FINE_DELAY = 0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OCLKDELAY_INV = "FALSE"; + parameter integer OCLK_DELAY = 0; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter [2:0] PO = 3'b000; + parameter real REFCLK_PERIOD = 0.000; + parameter SYNC_IN_DIV_RST = "FALSE"; + output COARSEOVERFLOW; + output FINEOVERFLOW; + output OCLK; + output OCLKDELAYED; + output OCLKDIV; + output OSERDESRST; + output [8:0] COUNTERREADVAL; + input COARSEENABLE; + input COARSEINC; + input COUNTERLOADEN; + input COUNTERREADEN; + input DIVIDERST; + input EDGEADV; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input SELFINEOCLKDELAY; + input SYNCIN; + input SYSCLK; + input [8:0] COUNTERLOADVAL; +endmodule + +module PHASER_OUT_PHY (...); + parameter integer CLKOUT_DIV = 4; + parameter COARSE_BYPASS = "FALSE"; + parameter integer COARSE_DELAY = 0; + parameter DATA_CTL_N = "FALSE"; + parameter DATA_RD_CYCLES = "FALSE"; + parameter integer FINE_DELAY = 0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real MEMREFCLK_PERIOD = 0.000; + parameter OCLKDELAY_INV = "FALSE"; + parameter integer OCLK_DELAY = 0; + parameter OUTPUT_CLK_SRC = "PHASE_REF"; + parameter real PHASEREFCLK_PERIOD = 0.000; + parameter [2:0] PO = 3'b000; + parameter real REFCLK_PERIOD = 0.000; + parameter SYNC_IN_DIV_RST = "FALSE"; + output COARSEOVERFLOW; + output FINEOVERFLOW; + output OCLK; + output OCLKDELAYED; + output OCLKDIV; + output OSERDESRST; + output RDENABLE; + output [1:0] CTSBUS; + output [1:0] DQSBUS; + output [1:0] DTSBUS; + output [8:0] COUNTERREADVAL; + input BURSTPENDINGPHY; + input COARSEENABLE; + input COARSEINC; + input COUNTERLOADEN; + input COUNTERREADEN; + input FINEENABLE; + input FINEINC; + input FREQREFCLK; + input MEMREFCLK; + input PHASEREFCLK; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input SELFINEOCLKDELAY; + input SYNCIN; + input SYSCLK; + input [1:0] ENCALIBPHY; + input [8:0] COUNTERLOADVAL; +endmodule + +module PHASER_REF (...); + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + output LOCKED; + input CLKIN; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PHY_CONTROL (...); + parameter integer AO_TOGGLE = 0; + parameter [3:0] AO_WRLVL_EN = 4'b0000; + parameter BURST_MODE = "FALSE"; + parameter integer CLK_RATIO = 1; + parameter integer CMD_OFFSET = 0; + parameter integer CO_DURATION = 0; + parameter DATA_CTL_A_N = "FALSE"; + parameter DATA_CTL_B_N = "FALSE"; + parameter DATA_CTL_C_N = "FALSE"; + parameter DATA_CTL_D_N = "FALSE"; + parameter DISABLE_SEQ_MATCH = "TRUE"; + parameter integer DI_DURATION = 0; + parameter integer DO_DURATION = 0; + parameter integer EVENTS_DELAY = 63; + parameter integer FOUR_WINDOW_CLOCKS = 63; + parameter MULTI_REGION = "FALSE"; + parameter PHY_COUNT_ENABLE = "FALSE"; + parameter integer RD_CMD_OFFSET_0 = 0; + parameter integer RD_CMD_OFFSET_1 = 00; + parameter integer RD_CMD_OFFSET_2 = 0; + parameter integer RD_CMD_OFFSET_3 = 0; + parameter integer RD_DURATION_0 = 0; + parameter integer RD_DURATION_1 = 0; + parameter integer RD_DURATION_2 = 0; + parameter integer RD_DURATION_3 = 0; + parameter SYNC_MODE = "FALSE"; + parameter integer WR_CMD_OFFSET_0 = 0; + parameter integer WR_CMD_OFFSET_1 = 0; + parameter integer WR_CMD_OFFSET_2 = 0; + parameter integer WR_CMD_OFFSET_3 = 0; + parameter integer WR_DURATION_0 = 0; + parameter integer WR_DURATION_1 = 0; + parameter integer WR_DURATION_2 = 0; + parameter integer WR_DURATION_3 = 0; + output PHYCTLALMOSTFULL; + output PHYCTLEMPTY; + output PHYCTLFULL; + output PHYCTLREADY; + output [1:0] INRANKA; + output [1:0] INRANKB; + output [1:0] INRANKC; + output [1:0] INRANKD; + output [1:0] PCENABLECALIB; + output [3:0] AUXOUTPUT; + output [3:0] INBURSTPENDING; + output [3:0] OUTBURSTPENDING; + input MEMREFCLK; + input PHYCLK; + input PHYCTLMSTREMPTY; + input PHYCTLWRENABLE; + input PLLLOCK; + input READCALIBENABLE; + input REFDLLLOCK; + input RESET; + input SYNCIN; + input WRITECALIBENABLE; + input [31:0] PHYCTLWD; +endmodule + +module IDDRE1 (...); + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter [0:0] IS_CB_INVERTED = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + output Q1; + output Q2; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + (* clkbuf_sink *) + (* invertible_pin = "IS_CB_INVERTED" *) + input CB; + input D; + input R; +endmodule + +module ODDRE1 (...); + parameter [0:0] IS_C_INVERTED = 1'b0; + parameter [0:0] IS_D1_INVERTED = 1'b0; + parameter [0:0] IS_D2_INVERTED = 1'b0; + parameter [0:0] SRVAL = 1'b0; + output Q; + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C; + (* invertible_pin = "IS_D1_INVERTED" *) + input D1; + (* invertible_pin = "IS_D2_INVERTED" *) + input D2; + input SR; +endmodule + +module IDELAYE3 (...); + parameter CASCADE = "NONE"; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_SRC = "IDATAIN"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter LOOPBACK = "FALSE"; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter UPDATE_MODE = "ASYNC"; + output CASC_OUT; + output [8:0] CNTVALUEOUT; + output DATAOUT; + input CASC_IN; + input CASC_RETURN; + input CE; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [8:0] CNTVALUEIN; + input DATAIN; + input EN_VTC; + input IDATAIN; + input INC; + input LOAD; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module ODELAYE3 (...); + parameter CASCADE = "NONE"; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter UPDATE_MODE = "ASYNC"; + output CASC_OUT; + output [8:0] CNTVALUEOUT; + output DATAOUT; + input CASC_IN; + input CASC_RETURN; + input CE; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [8:0] CNTVALUEIN; + input EN_VTC; + input INC; + input LOAD; + input ODATAIN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module ISERDESE3 (...); + parameter integer DATA_WIDTH = 8; + parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; + parameter FIFO_ENABLE = "FALSE"; + parameter FIFO_SYNC_MODE = "FALSE"; + parameter IDDR_MODE = "FALSE"; + parameter [0:0] IS_CLK_B_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + output FIFO_EMPTY; + output INTERNAL_DIVCLK; + output [7:0] Q; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* clkbuf_sink *) + input CLKDIV; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_B_INVERTED" *) + input CLK_B; + input D; + (* clkbuf_sink *) + input FIFO_RD_CLK; + input FIFO_RD_EN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module OSERDESE3 (...); + parameter integer DATA_WIDTH = 8; + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter ODDR_MODE = "FALSE"; + parameter OSERDES_D_BYPASS = "FALSE"; + parameter OSERDES_T_BYPASS = "FALSE"; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + output OQ; + output T_OUT; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLKDIV_INVERTED" *) + input CLKDIV; + input [7:0] D; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input T; +endmodule + +(* keep *) +module BITSLICE_CONTROL (...); + parameter CTRL_CLK = "EXTERNAL"; + parameter DIV_MODE = "DIV2"; + parameter EN_CLK_TO_EXT_NORTH = "DISABLE"; + parameter EN_CLK_TO_EXT_SOUTH = "DISABLE"; + parameter EN_DYN_ODLY_MODE = "FALSE"; + parameter EN_OTHER_NCLK = "FALSE"; + parameter EN_OTHER_PCLK = "FALSE"; + parameter IDLY_VT_TRACK = "TRUE"; + parameter INV_RXCLK = "FALSE"; + parameter ODLY_VT_TRACK = "TRUE"; + parameter QDLY_VT_TRACK = "TRUE"; + parameter [5:0] READ_IDLE_COUNT = 6'h00; + parameter REFCLK_SRC = "PLLCLK"; + parameter integer ROUNDING_FACTOR = 16; + parameter RXGATE_EXTEND = "FALSE"; + parameter RX_CLK_PHASE_N = "SHIFT_0"; + parameter RX_CLK_PHASE_P = "SHIFT_0"; + parameter RX_GATING = "DISABLE"; + parameter SELF_CALIBRATE = "ENABLE"; + parameter SERIAL_MODE = "FALSE"; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter SIM_SPEEDUP = "FAST"; + parameter real SIM_VERSION = 2.0; + parameter TX_GATING = "DISABLE"; + output CLK_TO_EXT_NORTH; + output CLK_TO_EXT_SOUTH; + output DLY_RDY; + output [6:0] DYN_DCI; + output NCLK_NIBBLE_OUT; + output PCLK_NIBBLE_OUT; + output [15:0] RIU_RD_DATA; + output RIU_VALID; + output [39:0] RX_BIT_CTRL_OUT0; + output [39:0] RX_BIT_CTRL_OUT1; + output [39:0] RX_BIT_CTRL_OUT2; + output [39:0] RX_BIT_CTRL_OUT3; + output [39:0] RX_BIT_CTRL_OUT4; + output [39:0] RX_BIT_CTRL_OUT5; + output [39:0] RX_BIT_CTRL_OUT6; + output [39:0] TX_BIT_CTRL_OUT0; + output [39:0] TX_BIT_CTRL_OUT1; + output [39:0] TX_BIT_CTRL_OUT2; + output [39:0] TX_BIT_CTRL_OUT3; + output [39:0] TX_BIT_CTRL_OUT4; + output [39:0] TX_BIT_CTRL_OUT5; + output [39:0] TX_BIT_CTRL_OUT6; + output [39:0] TX_BIT_CTRL_OUT_TRI; + output VTC_RDY; + input CLK_FROM_EXT; + input EN_VTC; + input NCLK_NIBBLE_IN; + input PCLK_NIBBLE_IN; + input [3:0] PHY_RDCS0; + input [3:0] PHY_RDCS1; + input [3:0] PHY_RDEN; + input [3:0] PHY_WRCS0; + input [3:0] PHY_WRCS1; + input PLL_CLK; + input REFCLK; + input [5:0] RIU_ADDR; + input RIU_CLK; + input RIU_NIBBLE_SEL; + input [15:0] RIU_WR_DATA; + input RIU_WR_EN; + input RST; + input [39:0] RX_BIT_CTRL_IN0; + input [39:0] RX_BIT_CTRL_IN1; + input [39:0] RX_BIT_CTRL_IN2; + input [39:0] RX_BIT_CTRL_IN3; + input [39:0] RX_BIT_CTRL_IN4; + input [39:0] RX_BIT_CTRL_IN5; + input [39:0] RX_BIT_CTRL_IN6; + input [3:0] TBYTE_IN; + input [39:0] TX_BIT_CTRL_IN0; + input [39:0] TX_BIT_CTRL_IN1; + input [39:0] TX_BIT_CTRL_IN2; + input [39:0] TX_BIT_CTRL_IN3; + input [39:0] TX_BIT_CTRL_IN4; + input [39:0] TX_BIT_CTRL_IN5; + input [39:0] TX_BIT_CTRL_IN6; + input [39:0] TX_BIT_CTRL_IN_TRI; +endmodule + +module RIU_OR (...); + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + output [15:0] RIU_RD_DATA; + output RIU_RD_VALID; + input [15:0] RIU_RD_DATA_LOW; + input [15:0] RIU_RD_DATA_UPP; + input RIU_RD_VALID_LOW; + input RIU_RD_VALID_UPP; +endmodule + +module RX_BITSLICE (...); + parameter CASCADE = "TRUE"; + parameter DATA_TYPE = "NONE"; + parameter integer DATA_WIDTH = 8; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter integer DELAY_VALUE_EXT = 0; + parameter FIFO_SYNC_MODE = "FALSE"; + parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0; + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter UPDATE_MODE = "ASYNC"; + parameter UPDATE_MODE_EXT = "ASYNC"; + output [8:0] CNTVALUEOUT; + output [8:0] CNTVALUEOUT_EXT; + output FIFO_EMPTY; + output FIFO_WRCLK_OUT; + output [7:0] Q; + output [39:0] RX_BIT_CTRL_OUT; + output [39:0] TX_BIT_CTRL_OUT; + input CE; + input CE_EXT; + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + (* invertible_pin = "IS_CLK_EXT_INVERTED" *) + input CLK_EXT; + input [8:0] CNTVALUEIN; + input [8:0] CNTVALUEIN_EXT; + input DATAIN; + input EN_VTC; + input EN_VTC_EXT; + input FIFO_RD_CLK; + input FIFO_RD_EN; + input INC; + input INC_EXT; + input LOAD; + input LOAD_EXT; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RST_DLY_INVERTED" *) + input RST_DLY; + (* invertible_pin = "IS_RST_DLY_EXT_INVERTED" *) + input RST_DLY_EXT; + input [39:0] RX_BIT_CTRL_IN; + input [39:0] TX_BIT_CTRL_IN; +endmodule + +module RXTX_BITSLICE (...); + parameter FIFO_SYNC_MODE = "FALSE"; + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_RX_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_RX_RST_INVERTED = 1'b0; + parameter [0:0] IS_TX_CLK_INVERTED = 1'b0; + parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_TX_RST_INVERTED = 1'b0; + parameter LOOPBACK = "FALSE"; + parameter NATIVE_ODELAY_BYPASS = "FALSE"; + parameter ENABLE_PRE_EMPHASIS = "FALSE"; + parameter RX_DATA_TYPE = "NONE"; + parameter integer RX_DATA_WIDTH = 8; + parameter RX_DELAY_FORMAT = "TIME"; + parameter RX_DELAY_TYPE = "FIXED"; + parameter integer RX_DELAY_VALUE = 0; + parameter real RX_REFCLK_FREQUENCY = 300.0; + parameter RX_UPDATE_MODE = "ASYNC"; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter TBYTE_CTL = "TBYTE_IN"; + parameter integer TX_DATA_WIDTH = 8; + parameter TX_DELAY_FORMAT = "TIME"; + parameter TX_DELAY_TYPE = "FIXED"; + parameter integer TX_DELAY_VALUE = 0; + parameter TX_OUTPUT_PHASE_90 = "FALSE"; + parameter real TX_REFCLK_FREQUENCY = 300.0; + parameter TX_UPDATE_MODE = "ASYNC"; + output FIFO_EMPTY; + output FIFO_WRCLK_OUT; + output O; + output [7:0] Q; + output [39:0] RX_BIT_CTRL_OUT; + output [8:0] RX_CNTVALUEOUT; + output [39:0] TX_BIT_CTRL_OUT; + output [8:0] TX_CNTVALUEOUT; + output T_OUT; + input [7:0] D; + input DATAIN; + input FIFO_RD_CLK; + input FIFO_RD_EN; + input [39:0] RX_BIT_CTRL_IN; + input RX_CE; + (* invertible_pin = "IS_RX_CLK_INVERTED" *) + input RX_CLK; + input [8:0] RX_CNTVALUEIN; + input RX_EN_VTC; + input RX_INC; + input RX_LOAD; + (* invertible_pin = "IS_RX_RST_INVERTED" *) + input RX_RST; + (* invertible_pin = "IS_RX_RST_DLY_INVERTED" *) + input RX_RST_DLY; + input T; + input TBYTE_IN; + input [39:0] TX_BIT_CTRL_IN; + input TX_CE; + (* invertible_pin = "IS_TX_CLK_INVERTED" *) + input TX_CLK; + input [8:0] TX_CNTVALUEIN; + input TX_EN_VTC; + input TX_INC; + input TX_LOAD; + (* invertible_pin = "IS_TX_RST_INVERTED" *) + input TX_RST; + (* invertible_pin = "IS_TX_RST_DLY_INVERTED" *) + input TX_RST_DLY; +endmodule + +module TX_BITSLICE (...); + parameter integer DATA_WIDTH = 8; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter ENABLE_PRE_EMPHASIS = "FALSE"; + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter NATIVE_ODELAY_BYPASS = "FALSE"; + parameter OUTPUT_PHASE_90 = "FALSE"; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter TBYTE_CTL = "TBYTE_IN"; + parameter UPDATE_MODE = "ASYNC"; + output [8:0] CNTVALUEOUT; + output O; + output [39:0] RX_BIT_CTRL_OUT; + output [39:0] TX_BIT_CTRL_OUT; + output T_OUT; + input CE; + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [8:0] CNTVALUEIN; + input [7:0] D; + input EN_VTC; + input INC; + input LOAD; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RST_DLY_INVERTED" *) + input RST_DLY; + input [39:0] RX_BIT_CTRL_IN; + input T; + input TBYTE_IN; + input [39:0] TX_BIT_CTRL_IN; +endmodule + +module TX_BITSLICE_TRI (...); + parameter integer DATA_WIDTH = 8; + parameter DELAY_FORMAT = "TIME"; + parameter DELAY_TYPE = "FIXED"; + parameter integer DELAY_VALUE = 0; + parameter [0:0] INIT = 1'b1; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter NATIVE_ODELAY_BYPASS = "FALSE"; + parameter OUTPUT_PHASE_90 = "FALSE"; + parameter real REFCLK_FREQUENCY = 300.0; + parameter SIM_DEVICE = "ULTRASCALE"; + parameter real SIM_VERSION = 2.0; + parameter UPDATE_MODE = "ASYNC"; + output [39:0] BIT_CTRL_OUT; + output [8:0] CNTVALUEOUT; + output TRI_OUT; + input [39:0] BIT_CTRL_IN; + input CE; + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input [8:0] CNTVALUEIN; + input EN_VTC; + input INC; + input LOAD; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + (* invertible_pin = "IS_RST_DLY_INVERTED" *) + input RST_DLY; +endmodule + +module IODELAY2 (...); + parameter COUNTER_WRAPAROUND = "WRAPAROUND"; + parameter DATA_RATE = "SDR"; + parameter DELAY_SRC = "IO"; + parameter integer IDELAY2_VALUE = 0; + parameter IDELAY_MODE = "NORMAL"; + parameter IDELAY_TYPE = "DEFAULT"; + parameter integer IDELAY_VALUE = 0; + parameter integer ODELAY_VALUE = 0; + parameter SERDES_MODE = "NONE"; + parameter integer SIM_TAPDELAY_VALUE = 75; + output BUSY; + output DATAOUT2; + output DATAOUT; + output DOUT; + output TOUT; + input CAL; + input CE; + (* clkbuf_sink *) + input CLK; + input IDATAIN; + input INC; + (* clkbuf_sink *) + input IOCLK0; + (* clkbuf_sink *) + input IOCLK1; + input ODATAIN; + input RST; + input T; +endmodule + +module IODRP2 (...); + parameter DATA_RATE = "SDR"; + parameter integer SIM_TAPDELAY_VALUE = 75; + output DATAOUT2; + output DATAOUT; + output DOUT; + output SDO; + output TOUT; + input ADD; + input BKST; + (* clkbuf_sink *) + input CLK; + input CS; + input IDATAIN; + (* clkbuf_sink *) + input IOCLK0; + (* clkbuf_sink *) + input IOCLK1; + input ODATAIN; + input SDI; + input T; +endmodule + +module IODRP2_MCB (...); + parameter DATA_RATE = "SDR"; + parameter integer IDELAY_VALUE = 0; + parameter integer MCB_ADDRESS = 0; + parameter integer ODELAY_VALUE = 0; + parameter SERDES_MODE = "NONE"; + parameter integer SIM_TAPDELAY_VALUE = 75; + output AUXSDO; + output DATAOUT2; + output DATAOUT; + output DOUT; + output DQSOUTN; + output DQSOUTP; + output SDO; + output TOUT; + input ADD; + input AUXSDOIN; + input BKST; + (* clkbuf_sink *) + input CLK; + input CS; + input IDATAIN; + (* clkbuf_sink *) + input IOCLK0; + (* clkbuf_sink *) + input IOCLK1; + input MEMUPDATE; + input ODATAIN; + input SDI; + input T; + input [4:0] AUXADDR; +endmodule + +module ISERDES2 (...); + parameter BITSLIP_ENABLE = "FALSE"; + parameter DATA_RATE = "SDR"; + parameter integer DATA_WIDTH = 1; + parameter INTERFACE_TYPE = "NETWORKING"; + parameter SERDES_MODE = "NONE"; + output CFB0; + output CFB1; + output DFB; + output FABRICOUT; + output INCDEC; + output Q1; + output Q2; + output Q3; + output Q4; + output SHIFTOUT; + output VALID; + input BITSLIP; + input CE0; + (* clkbuf_sink *) + input CLK0; + (* clkbuf_sink *) + input CLK1; + (* clkbuf_sink *) + input CLKDIV; + input D; + input IOCE; + input RST; + input SHIFTIN; +endmodule + +module OSERDES2 (...); + parameter BYPASS_GCLK_FF = "FALSE"; + parameter DATA_RATE_OQ = "DDR"; + parameter DATA_RATE_OT = "DDR"; + parameter integer DATA_WIDTH = 2; + parameter OUTPUT_MODE = "SINGLE_ENDED"; + parameter SERDES_MODE = "NONE"; + parameter integer TRAIN_PATTERN = 0; + output OQ; + output SHIFTOUT1; + output SHIFTOUT2; + output SHIFTOUT3; + output SHIFTOUT4; + output TQ; + (* clkbuf_sink *) + input CLK0; + (* clkbuf_sink *) + input CLK1; + (* clkbuf_sink *) + input CLKDIV; + input D1; + input D2; + input D3; + input D4; + input IOCE; + input OCE; + input RST; + input SHIFTIN1; + input SHIFTIN2; + input SHIFTIN3; + input SHIFTIN4; + input T1; + input T2; + input T3; + input T4; + input TCE; + input TRAIN; +endmodule + +module IBUF_DLY_ADJ (...); + parameter DELAY_OFFSET = "OFF"; + parameter IOSTANDARD = "DEFAULT"; + output O; + (* iopad_external_pin *) + input I; + input [2:0] S; +endmodule + +module IBUF_IBUFDISABLE (...); + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + input I; + input IBUFDISABLE; +endmodule + +module IBUF_INTERMDISABLE (...); + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + input I; + input IBUFDISABLE; + input INTERMDISABLE; +endmodule + +module IBUF_ANALOG (...); + output O; + (* iopad_external_pin *) + input I; +endmodule + +module IBUFE3 (...); + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter USE_IBUFDISABLE = "FALSE"; + parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + output O; + (* iopad_external_pin *) + input I; + input IBUFDISABLE; + input [3:0] OSC; + input OSC_EN; + input VREF; +endmodule + +module IBUFDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFDS_DLY_ADJ (...); + parameter DELAY_OFFSET = "OFF"; + parameter DIFF_TERM = "FALSE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input [2:0] S; +endmodule + +module IBUFDS_IBUFDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; +endmodule + +module IBUFDS_INTERMDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; + input INTERMDISABLE; +endmodule + +module IBUFDS_DIFF_OUT (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFDS_DIFF_OUT_IBUFDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; +endmodule + +module IBUFDS_DIFF_OUT_INTERMDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; + input INTERMDISABLE; +endmodule + +module IBUFDSE3 (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter USE_IBUFDISABLE = "FALSE"; + parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input IBUFDISABLE; + input [3:0] OSC; + input [1:0] OSC_EN; +endmodule + +module IBUFDS_DPHY (...); + parameter DIFF_TERM = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output HSRX_O; + output LPRX_O_N; + output LPRX_O_P; + input HSRX_DISABLE; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; + input LPRX_DISABLE; +endmodule + +module IBUFGDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter DIFF_TERM = "FALSE"; + parameter IBUF_DELAY_VALUE = "0"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFGDS_DIFF_OUT (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + output OB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IOBUF (...); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + output O; + (* iopad_external_pin *) + inout IO; + input I; + input T; +endmodule + +module IOBUF_DCIEN (...); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + inout IO; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input T; +endmodule + +module IOBUF_INTERMDISABLE (...); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + inout IO; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input T; +endmodule + +module IOBUFE3 (...); + parameter integer DRIVE = 12; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter USE_IBUFDISABLE = "FALSE"; + parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + output O; + (* iopad_external_pin *) + inout IO; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input [3:0] OSC; + input OSC_EN; + input T; + input VREF; +endmodule + +module IOBUFDS (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + output O; + (* iopad_external_pin *) + inout IO; + inout IOB; + input I; + input T; +endmodule + +module IOBUFDS_DCIEN (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input T; +endmodule + +module IOBUFDS_INTERMDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter SLEW = "SLOW"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input T; +endmodule + +module IOBUFDS_DIFF_OUT (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + output O; + output OB; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input I; + input TM; + input TS; +endmodule + +module IOBUFDS_DIFF_OUT_DCIEN (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + output OB; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input TM; + input TS; +endmodule + +module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SIM_DEVICE = "7SERIES"; + parameter USE_IBUFDISABLE = "TRUE"; + output O; + output OB; + (* iopad_external_pin *) + inout IO; + (* iopad_external_pin *) + inout IOB; + input I; + input IBUFDISABLE; + input INTERMDISABLE; + input TM; + input TS; +endmodule + +module IOBUFDSE3 (...); + parameter DIFF_TERM = "FALSE"; + parameter DQS_BIAS = "FALSE"; + parameter IBUF_LOW_PWR = "TRUE"; + parameter IOSTANDARD = "DEFAULT"; + parameter integer SIM_INPUT_BUFFER_OFFSET = 0; + parameter USE_IBUFDISABLE = "FALSE"; + output O; + (* iopad_external_pin *) + inout IO; + inout IOB; + input DCITERMDISABLE; + input I; + input IBUFDISABLE; + input [3:0] OSC; + input [1:0] OSC_EN; + input T; +endmodule + +module OBUFDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input I; +endmodule + +module OBUFDS_DPHY (...); + parameter IOSTANDARD = "DEFAULT"; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input HSTX_I; + input HSTX_T; + input LPTX_I_N; + input LPTX_I_P; + input LPTX_T; +endmodule + +module OBUFT (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + (* iopad_external_pin *) + output O; + input I; + input T; +endmodule + +module OBUFTDS (...); + parameter CAPACITANCE = "DONT_CARE"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input I; + input T; +endmodule + +module KEEPER (...); + inout O; +endmodule + +module PULLDOWN (...); + output O; +endmodule + +module PULLUP (...); + output O; +endmodule + +(* keep *) +module DCIRESET (...); + output LOCKED; + input RST; +endmodule + +module HPIO_VREF (...); + parameter VREF_CNTR = "OFF"; + output VREF; + input [6:0] FABRIC_VREF_TUNE; +endmodule + +module BUFGCE (...); + parameter CE_TYPE = "SYNC"; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_I_INVERTED = 1'b0; + (* clkbuf_driver *) + output O; + (* invertible_pin = "IS_CE_INVERTED" *) + input CE; + (* invertible_pin = "IS_I_INVERTED" *) + input I; +endmodule + +module BUFGCE_1 (...); + (* clkbuf_driver *) + output O; + input CE; + input I; +endmodule + +module BUFGMUX (...); + parameter CLK_SEL_TYPE = "SYNC"; + (* clkbuf_driver *) + output O; + input I0; + input I1; + input S; +endmodule + +module BUFGMUX_1 (...); + parameter CLK_SEL_TYPE = "SYNC"; + (* clkbuf_driver *) + output O; + input I0; + input I1; + input S; +endmodule + +module BUFGMUX_CTRL (...); + (* clkbuf_driver *) + output O; + input I0; + input I1; + input S; +endmodule + +module BUFGMUX_VIRTEX4 (...); + (* clkbuf_driver *) + output O; + input I0; + input I1; + input S; +endmodule + +module BUFG_GT (...); + (* clkbuf_driver *) + output O; + input CE; + input CEMASK; + input CLR; + input CLRMASK; + input [2:0] DIV; + input I; +endmodule + +module BUFG_GT_SYNC (...); + output CESYNC; + output CLRSYNC; + input CE; + input CLK; + input CLR; +endmodule + +module BUFG_PS (...); + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFGCE_DIV (...); + parameter integer BUFGCE_DIVIDE = 1; + parameter [0:0] IS_CE_INVERTED = 1'b0; + parameter [0:0] IS_CLR_INVERTED = 1'b0; + parameter [0:0] IS_I_INVERTED = 1'b0; + (* clkbuf_driver *) + output O; + (* invertible_pin = "IS_CE_INVERTED" *) + input CE; + (* invertible_pin = "IS_CLR_INVERTED" *) + input CLR; + (* invertible_pin = "IS_I_INVERTED" *) + input I; +endmodule + +module BUFH (...); + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFIO2 (...); + parameter DIVIDE_BYPASS = "TRUE"; + parameter integer DIVIDE = 1; + parameter I_INVERT = "FALSE"; + parameter USE_DOUBLER = "FALSE"; + (* clkbuf_driver *) + output DIVCLK; + (* clkbuf_driver *) + output IOCLK; + output SERDESSTROBE; + input I; +endmodule + +module BUFIO2_2CLK (...); + parameter integer DIVIDE = 2; + (* clkbuf_driver *) + output DIVCLK; + (* clkbuf_driver *) + output IOCLK; + output SERDESSTROBE; + input I; + input IB; +endmodule + +module BUFIO2FB (...); + parameter DIVIDE_BYPASS = "TRUE"; + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFPLL_MCB (...); + parameter integer DIVIDE = 2; + parameter LOCK_SRC = "LOCK_TO_0"; + (* clkbuf_driver *) + output IOCLK0; + (* clkbuf_driver *) + output IOCLK1; + output LOCK; + output SERDESSTROBE0; + output SERDESSTROBE1; + input GCLK; + input LOCKED; + input PLLIN0; + input PLLIN1; +endmodule + +module BUFIO (...); + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFIODQS (...); + parameter DQSMASK_ENABLE = "FALSE"; + (* clkbuf_driver *) + output O; + input DQSMASK; + input I; +endmodule + +module BUFR (...); + parameter BUFR_DIVIDE = "BYPASS"; + parameter SIM_DEVICE = "7SERIES"; + (* clkbuf_driver *) + output O; + input CE; + input CLR; + input I; +endmodule + +module BUFMR (...); + (* clkbuf_driver *) + output O; + input I; +endmodule + +module BUFMRCE (...); + parameter CE_TYPE = "SYNC"; + parameter integer INIT_OUT = 0; + parameter [0:0] IS_CE_INVERTED = 1'b0; + (* clkbuf_driver *) + output O; + (* invertible_pin = "IS_CE_INVERTED" *) + input CE; + input I; +endmodule + +module DCM (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DSS_MODE = "NONE"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter [15:0] FACTORY_JF = 16'hC080; + parameter integer PHASE_SHIFT = 0; + parameter SIM_MODE = "SAFE"; + parameter STARTUP_WAIT = "FALSE"; + input CLKFB; + input CLKIN; + input DSSEN; + input PSCLK; + input PSEN; + input PSINCDEC; + input RST; + output CLK0; + output CLK180; + output CLK270; + output CLK2X; + output CLK2X180; + output CLK90; + output CLKDV; + output CLKFX; + output CLKFX180; + output LOCKED; + output PSDONE; + output [7:0] STATUS; +endmodule + +module DCM_SP (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DSS_MODE = "NONE"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter FACTORY_JF = 16'hC080; + parameter integer PHASE_SHIFT = 0; + parameter STARTUP_WAIT = "FALSE"; + input CLKFB; + input CLKIN; + input DSSEN; + input PSCLK; + input PSEN; + input PSINCDEC; + input RST; + output CLK0; + output CLK180; + output CLK270; + output CLK2X; + output CLK2X180; + output CLK90; + output CLKDV; + output CLKFX; + output CLKFX180; + output LOCKED; + output PSDONE; + output [7:0] STATUS; +endmodule + +module DCM_CLKGEN (...); + parameter SPREAD_SPECTRUM = "NONE"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKFXDV_DIVIDE = 2; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter real CLKFX_MD_MAX = 0.0; + parameter real CLKIN_PERIOD = 0.0; + output CLKFX180; + output CLKFX; + output CLKFXDV; + output LOCKED; + output PROGDONE; + output [2:1] STATUS; + input CLKIN; + input FREEZEDCM; + input PROGCLK; + input PROGDATA; + input PROGEN; + input RST; +endmodule + +module DCM_ADV (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DCM_AUTOCALIBRATION = "TRUE"; + parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter FACTORY_JF = 16'hF0F0; + parameter integer PHASE_SHIFT = 0; + parameter SIM_DEVICE ="VIRTEX4"; + parameter STARTUP_WAIT = "FALSE"; + output CLK0; + output CLK180; + output CLK270; + output CLK2X180; + output CLK2X; + output CLK90; + output CLKDV; + output CLKFX180; + output CLKFX; + output DRDY; + output LOCKED; + output PSDONE; + output [15:0] DO; + input CLKFB; + input CLKIN; + input DCLK; + input DEN; + input DWE; + input PSCLK; + input PSEN; + input PSINCDEC; + input RST; + input [15:0] DI; + input [6:0] DADDR; +endmodule + +module DCM_BASE (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DCM_AUTOCALIBRATION = "TRUE"; + parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter [15:0] FACTORY_JF = 16'hF0F0; + parameter integer PHASE_SHIFT = 0; + parameter STARTUP_WAIT = "FALSE"; + output CLK0; + output CLK180; + output CLK270; + output CLK2X180; + output CLK2X; + output CLK90; + output CLKDV; + output CLKFX180; + output CLKFX; + output LOCKED; + input CLKFB; + input CLKIN; + input RST; +endmodule + +module DCM_PS (...); + parameter real CLKDV_DIVIDE = 2.0; + parameter integer CLKFX_DIVIDE = 1; + parameter integer CLKFX_MULTIPLY = 4; + parameter CLKIN_DIVIDE_BY_2 = "FALSE"; + parameter real CLKIN_PERIOD = 10.0; + parameter CLKOUT_PHASE_SHIFT = "NONE"; + parameter CLK_FEEDBACK = "1X"; + parameter DCM_AUTOCALIBRATION = "TRUE"; + parameter DCM_PERFORMANCE_MODE = "MAX_SPEED"; + parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; + parameter DFS_FREQUENCY_MODE = "LOW"; + parameter DLL_FREQUENCY_MODE = "LOW"; + parameter DUTY_CYCLE_CORRECTION = "TRUE"; + parameter [15:0] FACTORY_JF = 16'hF0F0; + parameter integer PHASE_SHIFT = 0; + parameter STARTUP_WAIT = "FALSE"; + output CLK0; + output CLK180; + output CLK270; + output CLK2X180; + output CLK2X; + output CLK90; + output CLKDV; + output CLKFX180; + output CLKFX; + output LOCKED; + output PSDONE; + output [15:0] DO; + input CLKFB; + input CLKIN; + input PSCLK; + input PSEN; + input PSINCDEC; + input RST; +endmodule + +module PMCD (...); + parameter EN_REL = "FALSE"; + parameter RST_DEASSERT_CLK = "CLKA"; + output CLKA1; + output CLKA1D2; + output CLKA1D4; + output CLKA1D8; + output CLKB1; + output CLKC1; + output CLKD1; + input CLKA; + input CLKB; + input CLKC; + input CLKD; + input REL; + input RST; +endmodule + +module PLL_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter CLK_FEEDBACK = "CLKFBOUT"; + parameter CLKFBOUT_DESKEW_ADJUST = "NONE"; + parameter CLKOUT0_DESKEW_ADJUST = "NONE"; + parameter CLKOUT1_DESKEW_ADJUST = "NONE"; + parameter CLKOUT2_DESKEW_ADJUST = "NONE"; + parameter CLKOUT3_DESKEW_ADJUST = "NONE"; + parameter CLKOUT4_DESKEW_ADJUST = "NONE"; + parameter CLKOUT5_DESKEW_ADJUST = "NONE"; + parameter integer CLKFBOUT_MULT = 1; + parameter real CLKFBOUT_PHASE = 0.0; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.5; + parameter real CLKOUT0_PHASE = 0.0; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.5; + parameter real CLKOUT1_PHASE = 0.0; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.5; + parameter real CLKOUT2_PHASE = 0.0; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.5; + parameter real CLKOUT3_PHASE = 0.0; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.5; + parameter real CLKOUT4_PHASE = 0.0; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.5; + parameter real CLKOUT5_PHASE = 0.0; + parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; + parameter integer DIVCLK_DIVIDE = 1; + parameter EN_REL = "FALSE"; + parameter PLL_PMCD_MODE = "FALSE"; + parameter real REF_JITTER = 0.100; + parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; + parameter RST_DEASSERT_CLK = "CLKIN1"; + parameter SIM_DEVICE = "VIRTEX5"; + parameter real VCOCLK_FREQ_MAX = 1440.0; + parameter real VCOCLK_FREQ_MIN = 400.0; + parameter real CLKIN_FREQ_MAX = 710.0; + parameter real CLKIN_FREQ_MIN = 19.0; + parameter real CLKPFD_FREQ_MAX = 550.0; + parameter real CLKPFD_FREQ_MIN = 19.0; + output CLKFBDCM; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output CLKOUTDCM0; + output CLKOUTDCM1; + output CLKOUTDCM2; + output CLKOUTDCM3; + output CLKOUTDCM4; + output CLKOUTDCM5; + output DRDY; + output LOCKED; + output [15:0] DO; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + input CLKINSEL; + input DCLK; + input DEN; + input DWE; + input REL; + input RST; + input [15:0] DI; + input [4:0] DADDR; +endmodule + +module PLL_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter integer CLKFBOUT_MULT = 1; + parameter real CLKFBOUT_PHASE = 0.0; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.5; + parameter real CLKOUT0_PHASE = 0.0; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.5; + parameter real CLKOUT1_PHASE = 0.0; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.5; + parameter real CLKOUT2_PHASE = 0.0; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.5; + parameter real CLKOUT3_PHASE = 0.0; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.5; + parameter real CLKOUT4_PHASE = 0.0; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.5; + parameter real CLKOUT5_PHASE = 0.0; + parameter CLK_FEEDBACK = "CLKFBOUT"; + parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER = 0.100; + parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output LOCKED; + input CLKFBIN; + input CLKIN; + input RST; +endmodule + +module MMCM_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter CLOCK_HOLD = "FALSE"; + parameter COMPENSATION = "ZHOLD"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter integer CLKOUT2_DIVIDE = 1; + parameter integer CLKOUT3_DIVIDE = 1; + parameter integer CLKOUT4_DIVIDE = 1; + parameter integer CLKOUT5_DIVIDE = 1; + parameter integer CLKOUT6_DIVIDE = 1; + parameter integer DIVCLK_DIVIDE = 1; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter real VCOCLK_FREQ_MAX = 1600.0; + parameter real VCOCLK_FREQ_MIN = 600.0; + parameter real CLKIN_FREQ_MAX = 800.0; + parameter real CLKIN_FREQ_MIN = 10.0; + parameter real CLKPFD_FREQ_MAX = 550.0; + parameter real CLKPFD_FREQ_MIN = 10.0; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output DRDY; + output LOCKED; + output PSDONE; + output [15:0] DO; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + input CLKINSEL; + input DCLK; + input DEN; + input DWE; + input PSCLK; + input PSEN; + input PSINCDEC; + input PWRDWN; + input RST; + input [15:0] DI; + input [6:0] DADDR; +endmodule + +module MMCM_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLOCK_HOLD = "FALSE"; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; +endmodule + +module MMCME2_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter COMPENSATION = "ZHOLD"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PSEN_INVERTED = 1'b0; + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter SS_EN = "FALSE"; + parameter SS_MODE = "CENTER_HIGH"; + parameter integer SS_MOD_PERIOD = 10000; + parameter STARTUP_WAIT = "FALSE"; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 600.000; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output [15:0] DO; + output DRDY; + output LOCKED; + output PSDONE; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input PSCLK; + (* invertible_pin = "IS_PSEN_INVERTED" *) + input PSEN; + (* invertible_pin = "IS_PSINCDEC_INVERTED" *) + input PSINCDEC; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME2_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; +endmodule + +module PLLE2_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter COMPENSATION = "ZHOLD"; + parameter STARTUP_WAIT = "FALSE"; + parameter integer CLKOUT0_DIVIDE = 1; + parameter integer CLKOUT1_DIVIDE = 1; + parameter integer CLKOUT2_DIVIDE = 1; + parameter integer CLKOUT3_DIVIDE = 1; + parameter integer CLKOUT4_DIVIDE = 1; + parameter integer CLKOUT5_DIVIDE = 1; + parameter integer DIVCLK_DIVIDE = 1; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter real VCOCLK_FREQ_MAX = 2133.000; + parameter real VCOCLK_FREQ_MIN = 800.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 19.000; + parameter real CLKPFD_FREQ_MAX = 550.0; + parameter real CLKPFD_FREQ_MIN = 19.0; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output DRDY; + output LOCKED; + output [15:0] DO; + input CLKFBIN; + input CLKIN1; + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input DCLK; + input DEN; + input DWE; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; + input [15:0] DI; + input [6:0] DADDR; +endmodule + +module PLLE2_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT1; + output CLKOUT2; + output CLKOUT3; + output CLKOUT4; + output CLKOUT5; + output LOCKED; + input CLKFBIN; + input CLKIN1; + input PWRDWN; + input RST; +endmodule + +module MMCME3_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter COMPENSATION = "AUTO"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN2_INVERTED = 1'b0; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PSEN_INVERTED = 1'b0; + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter SS_EN = "FALSE"; + parameter SS_MODE = "CENTER_HIGH"; + parameter integer SS_MOD_PERIOD = 10000; + parameter STARTUP_WAIT = "FALSE"; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 600.000; + parameter STARTUP_WAIT = "FALSE"; + output CDDCDONE; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output [15:0] DO; + output DRDY; + output LOCKED; + output PSDONE; + input CDDCREQ; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN1_INVERTED" *) + input CLKIN1; + (* invertible_pin = "IS_CLKIN2_INVERTED" *) + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input PSCLK; + (* invertible_pin = "IS_PSEN_INVERTED" *) + input PSEN; + (* invertible_pin = "IS_PSINCDEC_INVERTED" *) + input PSINCDEC; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME3_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN1_INVERTED" *) + input CLKIN1; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PLLE3_ADV (...); + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 70.000; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUTPHY_MODE = "VCO_2X"; + parameter real CLKPFD_FREQ_MAX = 667.500; + parameter real CLKPFD_FREQ_MIN = 70.000; + parameter COMPENSATION = "AUTO"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER = 0.010; + parameter STARTUP_WAIT = "FALSE"; + parameter real VCOCLK_FREQ_MAX = 1335.000; + parameter real VCOCLK_FREQ_MIN = 600.000; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUTPHY; + output [15:0] DO; + output DRDY; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN_INVERTED" *) + input CLKIN; + input CLKOUTPHYEN; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PLLE3_BASE (...); + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUTPHY_MODE = "VCO_2X"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUTPHY; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN_INVERTED" *) + input CLKIN; + input CLKOUTPHYEN; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME4_ADV (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter CLKFBOUT_USE_FINE_PS = "FALSE"; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKIN2_PERIOD = 0.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 10.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter CLKOUT0_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUT1_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter CLKOUT2_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT3_USE_FINE_PS = "FALSE"; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter CLKOUT4_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter CLKOUT5_USE_FINE_PS = "FALSE"; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter CLKOUT6_USE_FINE_PS = "FALSE"; + parameter real CLKPFD_FREQ_MAX = 550.000; + parameter real CLKPFD_FREQ_MIN = 10.000; + parameter COMPENSATION = "AUTO"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN2_INVERTED = 1'b0; + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; + parameter [0:0] IS_PSEN_INVERTED = 1'b0; + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter real REF_JITTER2 = 0.010; + parameter SS_EN = "FALSE"; + parameter SS_MODE = "CENTER_HIGH"; + parameter integer SS_MOD_PERIOD = 10000; + parameter STARTUP_WAIT = "FALSE"; + parameter real VCOCLK_FREQ_MAX = 1600.000; + parameter real VCOCLK_FREQ_MIN = 800.000; + parameter STARTUP_WAIT = "FALSE"; + output CDDCDONE; + output CLKFBOUT; + output CLKFBOUTB; + output CLKFBSTOPPED; + output CLKINSTOPPED; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output [15:0] DO; + output DRDY; + output LOCKED; + output PSDONE; + input CDDCREQ; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN1_INVERTED" *) + input CLKIN1; + (* invertible_pin = "IS_CLKIN2_INVERTED" *) + input CLKIN2; + (* invertible_pin = "IS_CLKINSEL_INVERTED" *) + input CLKINSEL; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input PSCLK; + (* invertible_pin = "IS_PSEN_INVERTED" *) + input PSEN; + (* invertible_pin = "IS_PSINCDEC_INVERTED" *) + input PSINCDEC; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module MMCME4_BASE (...); + parameter BANDWIDTH = "OPTIMIZED"; + parameter real CLKFBOUT_MULT_F = 5.000; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN1_PERIOD = 0.000; + parameter real CLKOUT0_DIVIDE_F = 1.000; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter integer CLKOUT2_DIVIDE = 1; + parameter real CLKOUT2_DUTY_CYCLE = 0.500; + parameter real CLKOUT2_PHASE = 0.000; + parameter integer CLKOUT3_DIVIDE = 1; + parameter real CLKOUT3_DUTY_CYCLE = 0.500; + parameter real CLKOUT3_PHASE = 0.000; + parameter CLKOUT4_CASCADE = "FALSE"; + parameter integer CLKOUT4_DIVIDE = 1; + parameter real CLKOUT4_DUTY_CYCLE = 0.500; + parameter real CLKOUT4_PHASE = 0.000; + parameter integer CLKOUT5_DIVIDE = 1; + parameter real CLKOUT5_DUTY_CYCLE = 0.500; + parameter real CLKOUT5_PHASE = 0.000; + parameter integer CLKOUT6_DIVIDE = 1; + parameter real CLKOUT6_DUTY_CYCLE = 0.500; + parameter real CLKOUT6_PHASE = 0.000; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER1 = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKFBOUTB; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUT2; + output CLKOUT2B; + output CLKOUT3; + output CLKOUT3B; + output CLKOUT4; + output CLKOUT5; + output CLKOUT6; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN1_INVERTED" *) + input CLKIN1; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PLLE4_ADV (...); + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN_FREQ_MAX = 1066.000; + parameter real CLKIN_FREQ_MIN = 70.000; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUTPHY_MODE = "VCO_2X"; + parameter real CLKPFD_FREQ_MAX = 667.500; + parameter real CLKPFD_FREQ_MIN = 70.000; + parameter COMPENSATION = "AUTO"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER = 0.010; + parameter STARTUP_WAIT = "FALSE"; + parameter real VCOCLK_FREQ_MAX = 1500.000; + parameter real VCOCLK_FREQ_MIN = 750.000; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUTPHY; + output [15:0] DO; + output DRDY; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN_INVERTED" *) + input CLKIN; + input CLKOUTPHYEN; + input [6:0] DADDR; + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module PLLE4_BASE (...); + parameter integer CLKFBOUT_MULT = 5; + parameter real CLKFBOUT_PHASE = 0.000; + parameter real CLKIN_PERIOD = 0.000; + parameter integer CLKOUT0_DIVIDE = 1; + parameter real CLKOUT0_DUTY_CYCLE = 0.500; + parameter real CLKOUT0_PHASE = 0.000; + parameter integer CLKOUT1_DIVIDE = 1; + parameter real CLKOUT1_DUTY_CYCLE = 0.500; + parameter real CLKOUT1_PHASE = 0.000; + parameter CLKOUTPHY_MODE = "VCO_2X"; + parameter integer DIVCLK_DIVIDE = 1; + parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; + parameter [0:0] IS_CLKIN_INVERTED = 1'b0; + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; + parameter [0:0] IS_RST_INVERTED = 1'b0; + parameter real REF_JITTER = 0.010; + parameter STARTUP_WAIT = "FALSE"; + output CLKFBOUT; + output CLKOUT0; + output CLKOUT0B; + output CLKOUT1; + output CLKOUT1B; + output CLKOUTPHY; + output LOCKED; + (* invertible_pin = "IS_CLKFBIN_INVERTED" *) + input CLKFBIN; + (* invertible_pin = "IS_CLKIN_INVERTED" *) + input CLKIN; + input CLKOUTPHYEN; + (* invertible_pin = "IS_PWRDWN_INVERTED" *) + input PWRDWN; + (* invertible_pin = "IS_RST_INVERTED" *) + input RST; +endmodule + +module BUFT (...); + output O; + input I; + input T; +endmodule + +module IN_FIFO (...); + parameter integer ALMOST_EMPTY_VALUE = 1; + parameter integer ALMOST_FULL_VALUE = 1; + parameter ARRAY_MODE = "ARRAY_MODE_4_X_8"; + parameter SYNCHRONOUS_MODE = "FALSE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output EMPTY; + output FULL; + output [7:0] Q0; + output [7:0] Q1; + output [7:0] Q2; + output [7:0] Q3; + output [7:0] Q4; + output [7:0] Q5; + output [7:0] Q6; + output [7:0] Q7; + output [7:0] Q8; + output [7:0] Q9; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RESET; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [3:0] D0; + input [3:0] D1; + input [3:0] D2; + input [3:0] D3; + input [3:0] D4; + input [3:0] D7; + input [3:0] D8; + input [3:0] D9; + input [7:0] D5; + input [7:0] D6; +endmodule + +module OUT_FIFO (...); + parameter integer ALMOST_EMPTY_VALUE = 1; + parameter integer ALMOST_FULL_VALUE = 1; + parameter ARRAY_MODE = "ARRAY_MODE_8_X_4"; + parameter OUTPUT_DISABLE = "FALSE"; + parameter SYNCHRONOUS_MODE = "FALSE"; + output ALMOSTEMPTY; + output ALMOSTFULL; + output EMPTY; + output FULL; + output [3:0] Q0; + output [3:0] Q1; + output [3:0] Q2; + output [3:0] Q3; + output [3:0] Q4; + output [3:0] Q7; + output [3:0] Q8; + output [3:0] Q9; + output [7:0] Q5; + output [7:0] Q6; + (* clkbuf_sink *) + input RDCLK; + input RDEN; + input RESET; + (* clkbuf_sink *) + input WRCLK; + input WREN; + input [7:0] D0; + input [7:0] D1; + input [7:0] D2; + input [7:0] D3; + input [7:0] D4; + input [7:0] D5; + input [7:0] D6; + input [7:0] D7; + input [7:0] D8; + input [7:0] D9; +endmodule + +module HARD_SYNC (...); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_CLK_INVERTED = 1'b0; + parameter integer LATENCY = 2; + output DOUT; + (* clkbuf_sink *) + (* invertible_pin = "IS_CLK_INVERTED" *) + input CLK; + input DIN; +endmodule + +(* keep *) +module STARTUP_SPARTAN3 (...); + input CLK; + input GSR; + input GTS; +endmodule + +(* keep *) +module STARTUP_SPARTAN3E (...); + input CLK; + input GSR; + input GTS; + input MBT; +endmodule + +(* keep *) +module STARTUP_SPARTAN3A (...); + input CLK; + input GSR; + input GTS; +endmodule + +(* keep *) +module STARTUP_SPARTAN6 (...); + output CFGCLK; + output CFGMCLK; + output EOS; + input CLK; + input GSR; + input GTS; + input KEYCLEARB; +endmodule + +(* keep *) +module STARTUP_VIRTEX4 (...); + output EOS; + input CLK; + input GSR; + input GTS; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module STARTUP_VIRTEX5 (...); + output CFGCLK; + output CFGMCLK; + output DINSPI; + output EOS; + output TCKSPI; + input CLK; + input GSR; + input GTS; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module STARTUP_VIRTEX6 (...); + parameter PROG_USR = "FALSE"; + output CFGCLK; + output CFGMCLK; + output DINSPI; + output EOS; + output PREQ; + output TCKSPI; + input CLK; + input GSR; + input GTS; + input KEYCLEARB; + input PACK; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module STARTUPE2 (...); + parameter PROG_USR = "FALSE"; + parameter real SIM_CCLK_FREQ = 0.0; + output CFGCLK; + output CFGMCLK; + output EOS; + output PREQ; + input CLK; + input GSR; + input GTS; + input KEYCLEARB; + input PACK; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module STARTUPE3 (...); + parameter PROG_USR = "FALSE"; + parameter real SIM_CCLK_FREQ = 0.0; + output CFGCLK; + output CFGMCLK; + output [3:0] DI; + output EOS; + output PREQ; + input [3:0] DO; + input [3:0] DTS; + input FCSBO; + input FCSBTS; + input GSR; + input GTS; + input KEYCLEARB; + input PACK; + input USRCCLKO; + input USRCCLKTS; + input USRDONEO; + input USRDONETS; +endmodule + +(* keep *) +module CAPTURE_SPARTAN3 (...); + parameter ONESHOT = "FALSE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTURE_SPARTAN3A (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTURE_VIRTEX4 (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTURE_VIRTEX5 (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTURE_VIRTEX6 (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module CAPTUREE2 (...); + parameter ONESHOT = "TRUE"; + input CAP; + input CLK; +endmodule + +(* keep *) +module ICAP_SPARTAN3A (...); + output BUSY; + output [7:0] O; + input CE; + input CLK; + input WRITE; + input [7:0] I; +endmodule + +(* keep *) +module ICAP_SPARTAN6 (...); + parameter DEVICE_ID = 32'h04000093; + parameter SIM_CFG_FILE_NAME = "NONE"; + output BUSY; + output [15:0] O; + input CLK; + input CE; + input WRITE; + input [15:0] I; +endmodule + +(* keep *) +module ICAP_VIRTEX4 (...); + parameter ICAP_WIDTH = "X8"; + output BUSY; + output [31:0] O; + input CE; + input CLK; + input WRITE; + input [31:0] I; +endmodule + +(* keep *) +module ICAP_VIRTEX5 (...); + parameter ICAP_WIDTH = "X8"; + output BUSY; + output [31:0] O; + input CE; + input CLK; + input WRITE; + input [31:0] I; +endmodule + +(* keep *) +module ICAP_VIRTEX6 (...); + parameter [31:0] DEVICE_ID = 32'h04244093; + parameter ICAP_WIDTH = "X8"; + parameter SIM_CFG_FILE_NAME = "NONE"; + output BUSY; + output [31:0] O; + input CLK; + input CSB; + input RDWRB; + input [31:0] I; +endmodule + +(* keep *) +module ICAPE2 (...); + parameter [31:0] DEVICE_ID = 32'h04244093; + parameter ICAP_WIDTH = "X32"; + parameter SIM_CFG_FILE_NAME = "NONE"; + output [31:0] O; + input CLK; + input CSIB; + input RDWRB; + input [31:0] I; +endmodule + +(* keep *) +module ICAPE3 (...); + parameter [31:0] DEVICE_ID = 32'h03628093; + parameter ICAP_AUTO_SWITCH = "DISABLE"; + parameter SIM_CFG_FILE_NAME = "NONE"; + output AVAIL; + output [31:0] O; + output PRDONE; + output PRERROR; + input CLK; + input CSIB; + input RDWRB; + input [31:0] I; +endmodule + +(* keep *) +module BSCAN_SPARTAN3 (...); + output CAPTURE; + output DRCK1; + output DRCK2; + output RESET; + output SEL1; + output SEL2; + output SHIFT; + output TDI; + output UPDATE; + input TDO1; + input TDO2; +endmodule + +(* keep *) +module BSCAN_SPARTAN3A (...); + output CAPTURE; + output DRCK1; + output DRCK2; + output RESET; + output SEL1; + output SEL2; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + input TDO1; + input TDO2; +endmodule + +(* keep *) +module BSCAN_SPARTAN6 (...); + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output RUNTEST; + output SEL; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + input TDO; +endmodule + +(* keep *) +module BSCAN_VIRTEX4 (...); + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output SEL; + output SHIFT; + output TDI; + output UPDATE; + input TDO; +endmodule + +(* keep *) +module BSCAN_VIRTEX5 (...); + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output SEL; + output SHIFT; + output TDI; + output UPDATE; + input TDO; +endmodule + +(* keep *) +module BSCAN_VIRTEX6 (...); + parameter DISABLE_JTAG = "FALSE"; + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output RUNTEST; + output SEL; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + input TDO; +endmodule + +(* keep *) +module BSCANE2 (...); + parameter DISABLE_JTAG = "FALSE"; + parameter integer JTAG_CHAIN = 1; + output CAPTURE; + output DRCK; + output RESET; + output RUNTEST; + output SEL; + output SHIFT; + output TCK; + output TDI; + output TMS; + output UPDATE; + input TDO; +endmodule + +module DNA_PORT (...); + parameter [56:0] SIM_DNA_VALUE = 57'h0; + output DOUT; + input CLK; + input DIN; + input READ; + input SHIFT; +endmodule + +module DNA_PORTE2 (...); + parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000; + output DOUT; + input CLK; + input DIN; + input READ; + input SHIFT; +endmodule + +module FRAME_ECC_VIRTEX4 (...); + output ERROR; + output [11:0] SYNDROME; + output SYNDROMEVALID; +endmodule + +module FRAME_ECC_VIRTEX5 (...); + output CRCERROR; + output ECCERROR; + output SYNDROMEVALID; + output [11:0] SYNDROME; +endmodule + +module FRAME_ECC_VIRTEX6 (...); + parameter FARSRC = "EFAR"; + parameter FRAME_RBT_IN_FILENAME = "NONE"; + output CRCERROR; + output ECCERROR; + output ECCERRORSINGLE; + output SYNDROMEVALID; + output [12:0] SYNDROME; + output [23:0] FAR; + output [4:0] SYNBIT; + output [6:0] SYNWORD; +endmodule + +module FRAME_ECCE2 (...); + parameter FARSRC = "EFAR"; + parameter FRAME_RBT_IN_FILENAME = "NONE"; + output CRCERROR; + output ECCERROR; + output ECCERRORSINGLE; + output SYNDROMEVALID; + output [12:0] SYNDROME; + output [25:0] FAR; + output [4:0] SYNBIT; + output [6:0] SYNWORD; +endmodule + +module FRAME_ECCE3 (...); + output CRCERROR; + output ECCERRORNOTSINGLE; + output ECCERRORSINGLE; + output ENDOFFRAME; + output ENDOFSCAN; + output [25:0] FAR; + input [1:0] FARSEL; + input ICAPBOTCLK; + input ICAPTOPCLK; +endmodule + +module USR_ACCESS_VIRTEX4 (...); + output [31:0] DATA; + output DATAVALID; +endmodule + +module USR_ACCESS_VIRTEX5 (...); + output CFGCLK; + output [31:0] DATA; + output DATAVALID; +endmodule + +module USR_ACCESS_VIRTEX6 (...); + output CFGCLK; + output [31:0] DATA; + output DATAVALID; +endmodule + +module USR_ACCESSE2 (...); + output CFGCLK; + output DATAVALID; + output [31:0] DATA; +endmodule + +module POST_CRC_INTERNAL (...); + output CRCERROR; +endmodule + +(* keep *) +module SUSPEND_SYNC (...); + output SREQ; + input CLK; + input SACK; +endmodule + +(* keep *) +module KEY_CLEAR (...); + input KEYCLEARB; +endmodule + +(* keep *) +module MASTER_JTAG (...); + output TDO; + input TCK; + input TDI; + input TMS; +endmodule + +(* keep *) +module SPI_ACCESS (...); + parameter SIM_DELAY_TYPE = "SCALED"; + parameter SIM_DEVICE = "3S1400AN"; + parameter SIM_FACTORY_ID = 512'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000; + parameter SIM_MEM_FILE = "NONE"; + parameter SIM_USER_ID = 512'hFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF; + output MISO; + input CLK; + input CSB; + input MOSI; +endmodule + +module EFUSE_USR (...); + parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; + output [31:0] EFUSEUSR; +endmodule + +module SYSMON (...); + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0800; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter SIM_DEVICE = "VIRTEX5"; + parameter SIM_MONITOR_FILE = "design.txt"; + output BUSY; + output DRDY; + output EOC; + output EOS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output OT; + output [15:0] DO; + output [2:0] ALM; + output [4:0] CHANNEL; + input CONVST; + input CONVSTCLK; + input DCLK; + input DEN; + input DWE; + input RESET; + input VN; + input VP; + input [15:0] DI; + input [15:0] VAUXN; + input [15:0] VAUXP; + input [6:0] DADDR; +endmodule + +module XADC (...); + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0800; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter [15:0] INIT_58 = 16'h0; + parameter [15:0] INIT_59 = 16'h0; + parameter [15:0] INIT_5A = 16'h0; + parameter [15:0] INIT_5B = 16'h0; + parameter [15:0] INIT_5C = 16'h0; + parameter [15:0] INIT_5D = 16'h0; + parameter [15:0] INIT_5E = 16'h0; + parameter [15:0] INIT_5F = 16'h0; + parameter IS_CONVSTCLK_INVERTED = 1'b0; + parameter IS_DCLK_INVERTED = 1'b0; + parameter SIM_DEVICE = "7SERIES"; + parameter SIM_MONITOR_FILE = "design.txt"; + output BUSY; + output DRDY; + output EOC; + output EOS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output OT; + output [15:0] DO; + output [7:0] ALM; + output [4:0] CHANNEL; + output [4:0] MUXADDR; + input CONVST; + (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) + input CONVSTCLK; + (* invertible_pin = "IS_DCLK_INVERTED" *) + input DCLK; + input DEN; + input DWE; + input RESET; + input VN; + input VP; + input [15:0] DI; + input [15:0] VAUXN; + input [15:0] VAUXP; + input [6:0] DADDR; +endmodule + +module SYSMONE1 (...); + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter [15:0] INIT_58 = 16'h0; + parameter [15:0] INIT_59 = 16'h0; + parameter [15:0] INIT_5A = 16'h0; + parameter [15:0] INIT_5B = 16'h0; + parameter [15:0] INIT_5C = 16'h0; + parameter [15:0] INIT_5D = 16'h0; + parameter [15:0] INIT_5E = 16'h0; + parameter [15:0] INIT_5F = 16'h0; + parameter [15:0] INIT_60 = 16'h0; + parameter [15:0] INIT_61 = 16'h0; + parameter [15:0] INIT_62 = 16'h0; + parameter [15:0] INIT_63 = 16'h0; + parameter [15:0] INIT_64 = 16'h0; + parameter [15:0] INIT_65 = 16'h0; + parameter [15:0] INIT_66 = 16'h0; + parameter [15:0] INIT_67 = 16'h0; + parameter [15:0] INIT_68 = 16'h0; + parameter [15:0] INIT_69 = 16'h0; + parameter [15:0] INIT_6A = 16'h0; + parameter [15:0] INIT_6B = 16'h0; + parameter [15:0] INIT_6C = 16'h0; + parameter [15:0] INIT_6D = 16'h0; + parameter [15:0] INIT_6E = 16'h0; + parameter [15:0] INIT_6F = 16'h0; + parameter [15:0] INIT_70 = 16'h0; + parameter [15:0] INIT_71 = 16'h0; + parameter [15:0] INIT_72 = 16'h0; + parameter [15:0] INIT_73 = 16'h0; + parameter [15:0] INIT_74 = 16'h0; + parameter [15:0] INIT_75 = 16'h0; + parameter [15:0] INIT_76 = 16'h0; + parameter [15:0] INIT_77 = 16'h0; + parameter [15:0] INIT_78 = 16'h0; + parameter [15:0] INIT_79 = 16'h0; + parameter [15:0] INIT_7A = 16'h0; + parameter [15:0] INIT_7B = 16'h0; + parameter [15:0] INIT_7C = 16'h0; + parameter [15:0] INIT_7D = 16'h0; + parameter [15:0] INIT_7E = 16'h0; + parameter [15:0] INIT_7F = 16'h0; + parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_DCLK_INVERTED = 1'b0; + parameter SIM_MONITOR_FILE = "design.txt"; + parameter integer SYSMON_VUSER0_BANK = 0; + parameter SYSMON_VUSER0_MONITOR = "NONE"; + parameter integer SYSMON_VUSER1_BANK = 0; + parameter SYSMON_VUSER1_MONITOR = "NONE"; + parameter integer SYSMON_VUSER2_BANK = 0; + parameter SYSMON_VUSER2_MONITOR = "NONE"; + parameter integer SYSMON_VUSER3_BANK = 0; + parameter SYSMON_VUSER3_MONITOR = "NONE"; + output [15:0] ALM; + output BUSY; + output [5:0] CHANNEL; + output [15:0] DO; + output DRDY; + output EOC; + output EOS; + output I2C_SCLK_TS; + output I2C_SDA_TS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output [4:0] MUXADDR; + output OT; + input CONVST; + (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) + input CONVSTCLK; + input [7:0] DADDR; + (* invertible_pin = "IS_DCLK_INVERTED" *) + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input I2C_SCLK; + input I2C_SDA; + input RESET; + input [15:0] VAUXN; + input [15:0] VAUXP; + input VN; + input VP; +endmodule + +module SYSMONE4 (...); + parameter [15:0] COMMON_N_SOURCE = 16'hFFFF; + parameter [15:0] INIT_40 = 16'h0000; + parameter [15:0] INIT_41 = 16'h0000; + parameter [15:0] INIT_42 = 16'h0000; + parameter [15:0] INIT_43 = 16'h0000; + parameter [15:0] INIT_44 = 16'h0000; + parameter [15:0] INIT_45 = 16'h0000; + parameter [15:0] INIT_46 = 16'h0000; + parameter [15:0] INIT_47 = 16'h0000; + parameter [15:0] INIT_48 = 16'h0000; + parameter [15:0] INIT_49 = 16'h0000; + parameter [15:0] INIT_4A = 16'h0000; + parameter [15:0] INIT_4B = 16'h0000; + parameter [15:0] INIT_4C = 16'h0000; + parameter [15:0] INIT_4D = 16'h0000; + parameter [15:0] INIT_4E = 16'h0000; + parameter [15:0] INIT_4F = 16'h0000; + parameter [15:0] INIT_50 = 16'h0000; + parameter [15:0] INIT_51 = 16'h0000; + parameter [15:0] INIT_52 = 16'h0000; + parameter [15:0] INIT_53 = 16'h0000; + parameter [15:0] INIT_54 = 16'h0000; + parameter [15:0] INIT_55 = 16'h0000; + parameter [15:0] INIT_56 = 16'h0000; + parameter [15:0] INIT_57 = 16'h0000; + parameter [15:0] INIT_58 = 16'h0000; + parameter [15:0] INIT_59 = 16'h0000; + parameter [15:0] INIT_5A = 16'h0000; + parameter [15:0] INIT_5B = 16'h0000; + parameter [15:0] INIT_5C = 16'h0000; + parameter [15:0] INIT_5D = 16'h0000; + parameter [15:0] INIT_5E = 16'h0000; + parameter [15:0] INIT_5F = 16'h0000; + parameter [15:0] INIT_60 = 16'h0000; + parameter [15:0] INIT_61 = 16'h0000; + parameter [15:0] INIT_62 = 16'h0000; + parameter [15:0] INIT_63 = 16'h0000; + parameter [15:0] INIT_64 = 16'h0000; + parameter [15:0] INIT_65 = 16'h0000; + parameter [15:0] INIT_66 = 16'h0000; + parameter [15:0] INIT_67 = 16'h0000; + parameter [15:0] INIT_68 = 16'h0000; + parameter [15:0] INIT_69 = 16'h0000; + parameter [15:0] INIT_6A = 16'h0000; + parameter [15:0] INIT_6B = 16'h0000; + parameter [15:0] INIT_6C = 16'h0000; + parameter [15:0] INIT_6D = 16'h0000; + parameter [15:0] INIT_6E = 16'h0000; + parameter [15:0] INIT_6F = 16'h0000; + parameter [15:0] INIT_70 = 16'h0000; + parameter [15:0] INIT_71 = 16'h0000; + parameter [15:0] INIT_72 = 16'h0000; + parameter [15:0] INIT_73 = 16'h0000; + parameter [15:0] INIT_74 = 16'h0000; + parameter [15:0] INIT_75 = 16'h0000; + parameter [15:0] INIT_76 = 16'h0000; + parameter [15:0] INIT_77 = 16'h0000; + parameter [15:0] INIT_78 = 16'h0000; + parameter [15:0] INIT_79 = 16'h0000; + parameter [15:0] INIT_7A = 16'h0000; + parameter [15:0] INIT_7B = 16'h0000; + parameter [15:0] INIT_7C = 16'h0000; + parameter [15:0] INIT_7D = 16'h0000; + parameter [15:0] INIT_7E = 16'h0000; + parameter [15:0] INIT_7F = 16'h0000; + parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_DCLK_INVERTED = 1'b0; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SIM_MONITOR_FILE = "design.txt"; + parameter integer SYSMON_VUSER0_BANK = 0; + parameter SYSMON_VUSER0_MONITOR = "NONE"; + parameter integer SYSMON_VUSER1_BANK = 0; + parameter SYSMON_VUSER1_MONITOR = "NONE"; + parameter integer SYSMON_VUSER2_BANK = 0; + parameter SYSMON_VUSER2_MONITOR = "NONE"; + parameter integer SYSMON_VUSER3_BANK = 0; + parameter SYSMON_VUSER3_MONITOR = "NONE"; + output [15:0] ADC_DATA; + output [15:0] ALM; + output BUSY; + output [5:0] CHANNEL; + output [15:0] DO; + output DRDY; + output EOC; + output EOS; + output I2C_SCLK_TS; + output I2C_SDA_TS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output [4:0] MUXADDR; + output OT; + output SMBALERT_TS; + input CONVST; + (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) + input CONVSTCLK; + input [7:0] DADDR; + (* invertible_pin = "IS_DCLK_INVERTED" *) + input DCLK; + input DEN; + input [15:0] DI; + input DWE; + input I2C_SCLK; + input I2C_SDA; + input RESET; + input [15:0] VAUXN; + input [15:0] VAUXP; + input VN; + input VP; +endmodule + +module GTPA1_DUAL (...); + parameter AC_CAP_DIS_0 = "TRUE"; + parameter AC_CAP_DIS_1 = "TRUE"; + parameter integer ALIGN_COMMA_WORD_0 = 1; + parameter integer ALIGN_COMMA_WORD_1 = 1; + parameter integer CB2_INH_CC_PERIOD_0 = 8; + parameter integer CB2_INH_CC_PERIOD_1 = 8; + parameter [4:0] CDR_PH_ADJ_TIME_0 = 5'b01010; + parameter [4:0] CDR_PH_ADJ_TIME_1 = 5'b01010; + parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7; + parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7; + parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1; + parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1; + parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; + parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; + parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE"; + parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN_0 = 1; + parameter integer CHAN_BOND_SEQ_LEN_1 = 1; + parameter integer CLK25_DIVIDER_0 = 4; + parameter integer CLK25_DIVIDER_1 = 4; + parameter CLKINDC_B_0 = "TRUE"; + parameter CLKINDC_B_1 = "TRUE"; + parameter CLKRCV_TRST_0 = "TRUE"; + parameter CLKRCV_TRST_1 = "TRUE"; + parameter CLK_CORRECT_USE_0 = "TRUE"; + parameter CLK_CORRECT_USE_1 = "TRUE"; + parameter integer CLK_COR_ADJ_LEN_0 = 1; + parameter integer CLK_COR_ADJ_LEN_1 = 1; + parameter integer CLK_COR_DET_LEN_0 = 1; + parameter integer CLK_COR_DET_LEN_1 = 1; + parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; + parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; + parameter integer CLK_COR_MAX_LAT_0 = 20; + parameter integer CLK_COR_MAX_LAT_1 = 20; + parameter integer CLK_COR_MIN_LAT_0 = 18; + parameter integer CLK_COR_MIN_LAT_1 = 18; + parameter CLK_COR_PRECEDENCE_0 = "TRUE"; + parameter CLK_COR_PRECEDENCE_1 = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT_0 = 0; + parameter integer CLK_COR_REPEAT_WAIT_1 = 0; + parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; + parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; + parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; + parameter CLK_OUT_GTP_SEL_0 = "REFCLKPLL0"; + parameter CLK_OUT_GTP_SEL_1 = "REFCLKPLL1"; + parameter [1:0] CM_TRIM_0 = 2'b00; + parameter [1:0] CM_TRIM_1 = 2'b00; + parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; + parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; + parameter [3:0] COM_BURST_VAL_0 = 4'b1111; + parameter [3:0] COM_BURST_VAL_1 = 4'b1111; + parameter DEC_MCOMMA_DETECT_0 = "TRUE"; + parameter DEC_MCOMMA_DETECT_1 = "TRUE"; + parameter DEC_PCOMMA_DETECT_0 = "TRUE"; + parameter DEC_PCOMMA_DETECT_1 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; + parameter GTP_CFG_PWRUP_0 = "TRUE"; + parameter GTP_CFG_PWRUP_1 = "TRUE"; + parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; + parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; + parameter MCOMMA_DETECT_0 = "TRUE"; + parameter MCOMMA_DETECT_1 = "TRUE"; + parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110; + parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110; + parameter integer OOB_CLK_DIVIDER_0 = 4; + parameter integer OOB_CLK_DIVIDER_1 = 4; + parameter PCI_EXPRESS_MODE_0 = "FALSE"; + parameter PCI_EXPRESS_MODE_1 = "FALSE"; + parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; + parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; + parameter PCOMMA_DETECT_0 = "TRUE"; + parameter PCOMMA_DETECT_1 = "TRUE"; + parameter [2:0] PLLLKDET_CFG_0 = 3'b101; + parameter [2:0] PLLLKDET_CFG_1 = 3'b101; + parameter [23:0] PLL_COM_CFG_0 = 24'h21680A; + parameter [23:0] PLL_COM_CFG_1 = 24'h21680A; + parameter [7:0] PLL_CP_CFG_0 = 8'h00; + parameter [7:0] PLL_CP_CFG_1 = 8'h00; + parameter integer PLL_DIVSEL_FB_0 = 5; + parameter integer PLL_DIVSEL_FB_1 = 5; + parameter integer PLL_DIVSEL_REF_0 = 2; + parameter integer PLL_DIVSEL_REF_1 = 2; + parameter integer PLL_RXDIVSEL_OUT_0 = 1; + parameter integer PLL_RXDIVSEL_OUT_1 = 1; + parameter PLL_SATA_0 = "FALSE"; + parameter PLL_SATA_1 = "FALSE"; + parameter PLL_SOURCE_0 = "PLL0"; + parameter PLL_SOURCE_1 = "PLL0"; + parameter integer PLL_TXDIVSEL_OUT_0 = 1; + parameter integer PLL_TXDIVSEL_OUT_1 = 1; + parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404040; + parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404040; + parameter [35:0] PMA_COM_CFG_EAST = 36'h000008000; + parameter [35:0] PMA_COM_CFG_WEST = 36'h00000A000; + parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h00; + parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h00; + parameter [24:0] PMA_RX_CFG_0 = 25'h05CE048; + parameter [24:0] PMA_RX_CFG_1 = 25'h05CE048; + parameter [19:0] PMA_TX_CFG_0 = 20'h00082; + parameter [19:0] PMA_TX_CFG_1 = 20'h00082; + parameter RCV_TERM_GND_0 = "FALSE"; + parameter RCV_TERM_GND_1 = "FALSE"; + parameter RCV_TERM_VTTRX_0 = "TRUE"; + parameter RCV_TERM_VTTRX_1 = "TRUE"; + parameter [7:0] RXEQ_CFG_0 = 8'b01111011; + parameter [7:0] RXEQ_CFG_1 = 8'b01111011; + parameter [0:0] RXPRBSERR_LOOPBACK_0 = 1'b0; + parameter [0:0] RXPRBSERR_LOOPBACK_1 = 1'b0; + parameter RX_BUFFER_USE_0 = "TRUE"; + parameter RX_BUFFER_USE_1 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; + parameter RX_EN_IDLE_HOLD_CDR_0 = "FALSE"; + parameter RX_EN_IDLE_HOLD_CDR_1 = "FALSE"; + parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_FR_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_FR_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_PH_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_PH_1 = "TRUE"; + parameter RX_EN_MODE_RESET_BUF_0 = "TRUE"; + parameter RX_EN_MODE_RESET_BUF_1 = "TRUE"; + parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; + parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; + parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; + parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; + parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; + parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; + parameter integer RX_LOS_INVALID_INCR_0 = 1; + parameter integer RX_LOS_INVALID_INCR_1 = 1; + parameter integer RX_LOS_THRESHOLD_0 = 4; + parameter integer RX_LOS_THRESHOLD_1 = 4; + parameter RX_SLIDE_MODE_0 = "PCS"; + parameter RX_SLIDE_MODE_1 = "PCS"; + parameter RX_STATUS_FMT_0 = "PCIE"; + parameter RX_STATUS_FMT_1 = "PCIE"; + parameter RX_XCLK_SEL_0 = "RXREC"; + parameter RX_XCLK_SEL_1 = "RXREC"; + parameter [2:0] SATA_BURST_VAL_0 = 3'b100; + parameter [2:0] SATA_BURST_VAL_1 = 3'b100; + parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; + parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; + parameter integer SATA_MAX_BURST_0 = 7; + parameter integer SATA_MAX_BURST_1 = 7; + parameter integer SATA_MAX_INIT_0 = 22; + parameter integer SATA_MAX_INIT_1 = 22; + parameter integer SATA_MAX_WAKE_0 = 7; + parameter integer SATA_MAX_WAKE_1 = 7; + parameter integer SATA_MIN_BURST_0 = 4; + parameter integer SATA_MIN_BURST_1 = 4; + parameter integer SATA_MIN_INIT_0 = 12; + parameter integer SATA_MIN_INIT_1 = 12; + parameter integer SATA_MIN_WAKE_0 = 4; + parameter integer SATA_MIN_WAKE_1 = 4; + parameter integer SIM_GTPRESET_SPEEDUP = 0; + parameter SIM_RECEIVER_DETECT_PASS = "FALSE"; + parameter [2:0] SIM_REFCLK0_SOURCE = 3'b000; + parameter [2:0] SIM_REFCLK1_SOURCE = 3'b000; + parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; + parameter SIM_VERSION = "2.0"; + parameter [4:0] TERMINATION_CTRL_0 = 5'b10100; + parameter [4:0] TERMINATION_CTRL_1 = 5'b10100; + parameter TERMINATION_OVRD_0 = "FALSE"; + parameter TERMINATION_OVRD_1 = "FALSE"; + parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03C; + parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03C; + parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; + parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; + parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; + parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; + parameter [31:0] TST_ATTR_0 = 32'h00000000; + parameter [31:0] TST_ATTR_1 = 32'h00000000; + parameter [2:0] TXRX_INVERT_0 = 3'b011; + parameter [2:0] TXRX_INVERT_1 = 3'b011; + parameter TX_BUFFER_USE_0 = "FALSE"; + parameter TX_BUFFER_USE_1 = "FALSE"; + parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; + parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; + parameter [2:0] TX_IDLE_DELAY_0 = 3'b011; + parameter [2:0] TX_IDLE_DELAY_1 = 3'b011; + parameter [1:0] TX_TDCC_CFG_0 = 2'b00; + parameter [1:0] TX_TDCC_CFG_1 = 2'b00; + parameter TX_XCLK_SEL_0 = "TXUSR"; + parameter TX_XCLK_SEL_1 = "TXUSR"; + output DRDY; + output PHYSTATUS0; + output PHYSTATUS1; + output PLLLKDET0; + output PLLLKDET1; + output REFCLKOUT0; + output REFCLKOUT1; + output REFCLKPLL0; + output REFCLKPLL1; + output RESETDONE0; + output RESETDONE1; + output RXBYTEISALIGNED0; + output RXBYTEISALIGNED1; + output RXBYTEREALIGN0; + output RXBYTEREALIGN1; + output RXCHANBONDSEQ0; + output RXCHANBONDSEQ1; + output RXCHANISALIGNED0; + output RXCHANISALIGNED1; + output RXCHANREALIGN0; + output RXCHANREALIGN1; + output RXCOMMADET0; + output RXCOMMADET1; + output RXELECIDLE0; + output RXELECIDLE1; + output RXPRBSERR0; + output RXPRBSERR1; + output RXRECCLK0; + output RXRECCLK1; + output RXVALID0; + output RXVALID1; + output TXN0; + output TXN1; + output TXOUTCLK0; + output TXOUTCLK1; + output TXP0; + output TXP1; + output [15:0] DRPDO; + output [1:0] GTPCLKFBEAST; + output [1:0] GTPCLKFBWEST; + output [1:0] GTPCLKOUT0; + output [1:0] GTPCLKOUT1; + output [1:0] RXLOSSOFSYNC0; + output [1:0] RXLOSSOFSYNC1; + output [1:0] TXBUFSTATUS0; + output [1:0] TXBUFSTATUS1; + output [2:0] RXBUFSTATUS0; + output [2:0] RXBUFSTATUS1; + output [2:0] RXCHBONDO; + output [2:0] RXCLKCORCNT0; + output [2:0] RXCLKCORCNT1; + output [2:0] RXSTATUS0; + output [2:0] RXSTATUS1; + output [31:0] RXDATA0; + output [31:0] RXDATA1; + output [3:0] RXCHARISCOMMA0; + output [3:0] RXCHARISCOMMA1; + output [3:0] RXCHARISK0; + output [3:0] RXCHARISK1; + output [3:0] RXDISPERR0; + output [3:0] RXDISPERR1; + output [3:0] RXNOTINTABLE0; + output [3:0] RXNOTINTABLE1; + output [3:0] RXRUNDISP0; + output [3:0] RXRUNDISP1; + output [3:0] TXKERR0; + output [3:0] TXKERR1; + output [3:0] TXRUNDISP0; + output [3:0] TXRUNDISP1; + output [4:0] RCALOUTEAST; + output [4:0] RCALOUTWEST; + output [4:0] TSTOUT0; + output [4:0] TSTOUT1; + input CLK00; + input CLK01; + input CLK10; + input CLK11; + input CLKINEAST0; + input CLKINEAST1; + input CLKINWEST0; + input CLKINWEST1; + input DCLK; + input DEN; + input DWE; + input GATERXELECIDLE0; + input GATERXELECIDLE1; + input GCLK00; + input GCLK01; + input GCLK10; + input GCLK11; + input GTPRESET0; + input GTPRESET1; + input IGNORESIGDET0; + input IGNORESIGDET1; + input INTDATAWIDTH0; + input INTDATAWIDTH1; + input PLLCLK00; + input PLLCLK01; + input PLLCLK10; + input PLLCLK11; + input PLLLKDETEN0; + input PLLLKDETEN1; + input PLLPOWERDOWN0; + input PLLPOWERDOWN1; + input PRBSCNTRESET0; + input PRBSCNTRESET1; + input REFCLKPWRDNB0; + input REFCLKPWRDNB1; + input RXBUFRESET0; + input RXBUFRESET1; + input RXCDRRESET0; + input RXCDRRESET1; + input RXCHBONDMASTER0; + input RXCHBONDMASTER1; + input RXCHBONDSLAVE0; + input RXCHBONDSLAVE1; + input RXCOMMADETUSE0; + input RXCOMMADETUSE1; + input RXDEC8B10BUSE0; + input RXDEC8B10BUSE1; + input RXENCHANSYNC0; + input RXENCHANSYNC1; + input RXENMCOMMAALIGN0; + input RXENMCOMMAALIGN1; + input RXENPCOMMAALIGN0; + input RXENPCOMMAALIGN1; + input RXENPMAPHASEALIGN0; + input RXENPMAPHASEALIGN1; + input RXN0; + input RXN1; + input RXP0; + input RXP1; + input RXPMASETPHASE0; + input RXPMASETPHASE1; + input RXPOLARITY0; + input RXPOLARITY1; + input RXRESET0; + input RXRESET1; + input RXSLIDE0; + input RXSLIDE1; + input RXUSRCLK0; + input RXUSRCLK1; + input RXUSRCLK20; + input RXUSRCLK21; + input TSTCLK0; + input TSTCLK1; + input TXCOMSTART0; + input TXCOMSTART1; + input TXCOMTYPE0; + input TXCOMTYPE1; + input TXDETECTRX0; + input TXDETECTRX1; + input TXELECIDLE0; + input TXELECIDLE1; + input TXENC8B10BUSE0; + input TXENC8B10BUSE1; + input TXENPMAPHASEALIGN0; + input TXENPMAPHASEALIGN1; + input TXINHIBIT0; + input TXINHIBIT1; + input TXPDOWNASYNCH0; + input TXPDOWNASYNCH1; + input TXPMASETPHASE0; + input TXPMASETPHASE1; + input TXPOLARITY0; + input TXPOLARITY1; + input TXPRBSFORCEERR0; + input TXPRBSFORCEERR1; + input TXRESET0; + input TXRESET1; + input TXUSRCLK0; + input TXUSRCLK1; + input TXUSRCLK20; + input TXUSRCLK21; + input USRCODEERR0; + input USRCODEERR1; + input [11:0] TSTIN0; + input [11:0] TSTIN1; + input [15:0] DI; + input [1:0] GTPCLKFBSEL0EAST; + input [1:0] GTPCLKFBSEL0WEST; + input [1:0] GTPCLKFBSEL1EAST; + input [1:0] GTPCLKFBSEL1WEST; + input [1:0] RXDATAWIDTH0; + input [1:0] RXDATAWIDTH1; + input [1:0] RXEQMIX0; + input [1:0] RXEQMIX1; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] TXDATAWIDTH0; + input [1:0] TXDATAWIDTH1; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [2:0] LOOPBACK0; + input [2:0] LOOPBACK1; + input [2:0] REFSELDYPLL0; + input [2:0] REFSELDYPLL1; + input [2:0] RXCHBONDI; + input [2:0] RXENPRBSTST0; + input [2:0] RXENPRBSTST1; + input [2:0] TXBUFDIFFCTRL0; + input [2:0] TXBUFDIFFCTRL1; + input [2:0] TXENPRBSTST0; + input [2:0] TXENPRBSTST1; + input [2:0] TXPREEMPHASIS0; + input [2:0] TXPREEMPHASIS1; + input [31:0] TXDATA0; + input [31:0] TXDATA1; + input [3:0] TXBYPASS8B10B0; + input [3:0] TXBYPASS8B10B1; + input [3:0] TXCHARDISPMODE0; + input [3:0] TXCHARDISPMODE1; + input [3:0] TXCHARDISPVAL0; + input [3:0] TXCHARDISPVAL1; + input [3:0] TXCHARISK0; + input [3:0] TXCHARISK1; + input [3:0] TXDIFFCTRL0; + input [3:0] TXDIFFCTRL1; + input [4:0] RCALINEAST; + input [4:0] RCALINWEST; + input [7:0] DADDR; + input [7:0] GTPTEST0; + input [7:0] GTPTEST1; +endmodule + +module GT11_CUSTOM (...); + parameter ALIGN_COMMA_WORD = 1; + parameter BANDGAPSEL = "FALSE"; + parameter BIASRESSEL = "TRUE"; + parameter CCCB_ARBITRATOR_DISABLE = "FALSE"; + parameter CHAN_BOND_LIMIT = 16; + parameter CHAN_BOND_MODE = "NONE"; + parameter CHAN_BOND_ONE_SHOT = "FALSE"; + parameter CHAN_BOND_SEQ_1_1 = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_2 = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_3 = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_4 = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_MASK = 4'b0000; + parameter CHAN_BOND_SEQ_2_1 = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_2 = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_3 = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_4 = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_MASK = 4'b0000; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_8B10B_DE = "FALSE"; + parameter CLK_COR_MAX_LAT = 36; + parameter CLK_COR_MIN_LAT = 28; + parameter CLK_COR_SEQ_1_1 = 11'b00000000000; + parameter CLK_COR_SEQ_1_2 = 11'b00000000000; + parameter CLK_COR_SEQ_1_3 = 11'b00000000000; + parameter CLK_COR_SEQ_1_4 = 11'b00000000000; + parameter CLK_COR_SEQ_1_MASK = 4'b0000; + parameter CLK_COR_SEQ_2_1 = 11'b00000000000; + parameter CLK_COR_SEQ_2_2 = 11'b00000000000; + parameter CLK_COR_SEQ_2_3 = 11'b00000000000; + parameter CLK_COR_SEQ_2_4 = 11'b00000000000; + parameter CLK_COR_SEQ_2_MASK = 4'b0000; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter CLK_COR_SEQ_DROP = "FALSE"; + parameter CLK_COR_SEQ_LEN = 1; + parameter COMMA32 = "FALSE"; + parameter COMMA_10B_MASK = 10'h3FF; + parameter CYCLE_LIMIT_SEL = 2'b00; + parameter DCDR_FILTER = 3'b010; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter DIGRX_FWDCLK = 2'b00; + parameter DIGRX_SYNC_MODE = "FALSE"; + parameter ENABLE_DCDR = "FALSE"; + parameter FDET_HYS_CAL = 3'b110; + parameter FDET_HYS_SEL = 3'b110; + parameter FDET_LCK_CAL = 3'b101; + parameter FDET_LCK_SEL = 3'b101; + parameter GT11_MODE = "SINGLE"; + parameter IREFBIASMODE = 2'b11; + parameter LOOPCAL_WAIT = 2'b00; + parameter MCOMMA_32B_VALUE = 32'h000000F6; + parameter MCOMMA_DETECT = "TRUE"; + parameter OPPOSITE_SELECT = "FALSE"; + parameter PCOMMA_32B_VALUE = 32'hF6F62828; + parameter PCOMMA_DETECT = "TRUE"; + parameter PCS_BIT_SLIP = "FALSE"; + parameter PMACLKENABLE = "TRUE"; + parameter PMACOREPWRENABLE = "TRUE"; + parameter PMAIREFTRIM = 4'b0111; + parameter PMAVBGCTRL = 5'b00000; + parameter PMAVREFTRIM = 4'b0111; + parameter PMA_BIT_SLIP = "FALSE"; + parameter REPEATER = "FALSE"; + parameter RXACTST = "FALSE"; + parameter RXAFEEQ = 9'b000000000; + parameter RXAFEPD = "FALSE"; + parameter RXAFETST = "FALSE"; + parameter RXAPD = "FALSE"; + parameter RXASYNCDIVIDE = 2'b11; + parameter RXBY_32 = "TRUE"; + parameter RXCDRLOS = 6'b000000; + parameter RXCLK0_FORCE_PMACLK = "FALSE"; + parameter RXCLKMODE = 6'b110001; + parameter RXCMADJ = 2'b10; + parameter RXCPSEL = "TRUE"; + parameter RXCPTST = "FALSE"; + parameter RXCRCCLOCKDOUBLE = "FALSE"; + parameter RXCRCENABLE = "FALSE"; + parameter RXCRCINITVAL = 32'h00000000; + parameter RXCRCINVERTGEN = "FALSE"; + parameter RXCRCSAMECLOCK = "FALSE"; + parameter RXCTRL1 = 10'h200; + parameter RXCYCLE_LIMIT_SEL = 2'b00; + parameter RXDATA_SEL = 2'b00; + parameter RXDCCOUPLE = "FALSE"; + parameter RXDIGRESET = "FALSE"; + parameter RXDIGRX = "FALSE"; + parameter RXEQ = 64'h4000000000000000; + parameter RXFDCAL_CLOCK_DIVIDE = "NONE"; + parameter RXFDET_HYS_CAL = 3'b110; + parameter RXFDET_HYS_SEL = 3'b110; + parameter RXFDET_LCK_CAL = 3'b101; + parameter RXFDET_LCK_SEL = 3'b101; + parameter RXFECONTROL1 = 2'b00; + parameter RXFECONTROL2 = 3'b000; + parameter RXFETUNE = 2'b01; + parameter RXLB = "FALSE"; + parameter RXLKADJ = 5'b00000; + parameter RXLKAPD = "FALSE"; + parameter RXLOOPCAL_WAIT = 2'b00; + parameter RXLOOPFILT = 4'b0111; + parameter RXOUTDIV2SEL = 1; + parameter RXPD = "FALSE"; + parameter RXPDDTST = "FALSE"; + parameter RXPLLNDIVSEL = 8; + parameter RXPMACLKSEL = "REFCLK1"; + parameter RXRCPADJ = 3'b011; + parameter RXRCPPD = "FALSE"; + parameter RXRECCLK1_USE_SYNC = "FALSE"; + parameter RXRIBADJ = 2'b11; + parameter RXRPDPD = "FALSE"; + parameter RXRSDPD = "FALSE"; + parameter RXSLOWDOWN_CAL = 2'b00; + parameter RXUSRDIVISOR = 1; + parameter RXVCODAC_INIT = 10'b1010000000; + parameter RXVCO_CTRL_ENABLE = "TRUE"; + parameter RX_BUFFER_USE = "TRUE"; + parameter RX_CLOCK_DIVIDER = 2'b00; + parameter RX_LOS_INVALID_INCR = 1; + parameter RX_LOS_THRESHOLD = 4; + parameter SAMPLE_8X = "FALSE"; + parameter SH_CNT_MAX = 64; + parameter SH_INVALID_CNT_MAX = 16; + parameter SLOWDOWN_CAL = 2'b00; + parameter TXABPMACLKSEL = "REFCLK1"; + parameter TXAPD = "FALSE"; + parameter TXAREFBIASSEL = "FALSE"; + parameter TXASYNCDIVIDE = 2'b11; + parameter TXCLK0_FORCE_PMACLK = "FALSE"; + parameter TXCLKMODE = 4'b1001; + parameter TXCPSEL = "TRUE"; + parameter TXCRCCLOCKDOUBLE = "FALSE"; + parameter TXCRCENABLE = "FALSE"; + parameter TXCRCINITVAL = 32'h00000000; + parameter TXCRCINVERTGEN = "FALSE"; + parameter TXCRCSAMECLOCK = "FALSE"; + parameter TXCTRL1 = 10'h200; + parameter TXDATA_SEL = 2'b00; + parameter TXDAT_PRDRV_DAC = 3'b111; + parameter TXDAT_TAP_DAC = 5'b10110; + parameter TXDIGPD = "FALSE"; + parameter TXFDCAL_CLOCK_DIVIDE = "NONE"; + parameter TXHIGHSIGNALEN = "TRUE"; + parameter TXLOOPFILT = 4'b0111; + parameter TXLVLSHFTPD = "FALSE"; + parameter TXOUTCLK1_USE_SYNC = "FALSE"; + parameter TXOUTDIV2SEL = 1; + parameter TXPD = "FALSE"; + parameter TXPHASESEL = "FALSE"; + parameter TXPLLNDIVSEL = 8; + parameter TXPOST_PRDRV_DAC = 3'b111; + parameter TXPOST_TAP_DAC = 5'b01110; + parameter TXPOST_TAP_PD = "TRUE"; + parameter TXPRE_PRDRV_DAC = 3'b111; + parameter TXPRE_TAP_DAC = 5'b00000; + parameter TXPRE_TAP_PD = "TRUE"; + parameter TXSLEWRATE = "FALSE"; + parameter TXTERMTRIM = 4'b1100; + parameter TX_BUFFER_USE = "TRUE"; + parameter TX_CLOCK_DIVIDER = 2'b00; + parameter VCODAC_INIT = 10'b1010000000; + parameter VCO_CTRL_ENABLE = "TRUE"; + parameter VREFBIASMODE = 2'b11; + output DRDY; + output RXBUFERR; + output RXCALFAIL; + output RXCOMMADET; + output RXCYCLELIMIT; + output RXLOCK; + output RXMCLK; + output RXPCSHCLKOUT; + output RXREALIGN; + output RXRECCLK1; + output RXRECCLK2; + output RXSIGDET; + output TX1N; + output TX1P; + output TXBUFERR; + output TXCALFAIL; + output TXCYCLELIMIT; + output TXLOCK; + output TXOUTCLK1; + output TXOUTCLK2; + output TXPCSHCLKOUT; + output [15:0] DO; + output [1:0] RXLOSSOFSYNC; + output [31:0] RXCRCOUT; + output [31:0] TXCRCOUT; + output [4:0] CHBONDO; + output [5:0] RXSTATUS; + output [63:0] RXDATA; + output [7:0] RXCHARISCOMMA; + output [7:0] RXCHARISK; + output [7:0] RXDISPERR; + output [7:0] RXNOTINTABLE; + output [7:0] RXRUNDISP; + output [7:0] TXKERR; + output [7:0] TXRUNDISP; + input DCLK; + input DEN; + input DWE; + input ENCHANSYNC; + input ENMCOMMAALIGN; + input ENPCOMMAALIGN; + input GREFCLK; + input POWERDOWN; + input REFCLK1; + input REFCLK2; + input RX1N; + input RX1P; + input RXBLOCKSYNC64B66BUSE; + input RXCLKSTABLE; + input RXCOMMADETUSE; + input RXCRCCLK; + input RXCRCDATAVALID; + input RXCRCINIT; + input RXCRCINTCLK; + input RXCRCPD; + input RXCRCRESET; + input RXDEC64B66BUSE; + input RXDEC8B10BUSE; + input RXDESCRAM64B66BUSE; + input RXIGNOREBTF; + input RXPMARESET; + input RXPOLARITY; + input RXRESET; + input RXSLIDE; + input RXSYNC; + input RXUSRCLK2; + input RXUSRCLK; + input TXCLKSTABLE; + input TXCRCCLK; + input TXCRCDATAVALID; + input TXCRCINIT; + input TXCRCINTCLK; + input TXCRCPD; + input TXCRCRESET; + input TXENC64B66BUSE; + input TXENC8B10BUSE; + input TXENOOB; + input TXGEARBOX64B66BUSE; + input TXINHIBIT; + input TXPMARESET; + input TXPOLARITY; + input TXRESET; + input TXSCRAM64B66BUSE; + input TXSYNC; + input TXUSRCLK2; + input TXUSRCLK; + input [15:0] DI; + input [1:0] LOOPBACK; + input [1:0] RXDATAWIDTH; + input [1:0] RXINTDATAWIDTH; + input [1:0] TXDATAWIDTH; + input [1:0] TXINTDATAWIDTH; + input [2:0] RXCRCDATAWIDTH; + input [2:0] TXCRCDATAWIDTH; + input [4:0] CHBONDI; + input [63:0] RXCRCIN; + input [63:0] TXCRCIN; + input [63:0] TXDATA; + input [7:0] DADDR; + input [7:0] TXBYPASS8B10B; + input [7:0] TXCHARDISPMODE; + input [7:0] TXCHARDISPVAL; + input [7:0] TXCHARISK; +endmodule + +module GT11_DUAL (...); + parameter ALIGN_COMMA_WORD_A = 1; + parameter ALIGN_COMMA_WORD_B = 1; + parameter BANDGAPSEL_A = "FALSE"; + parameter BANDGAPSEL_B = "FALSE"; + parameter BIASRESSEL_A = "TRUE"; + parameter BIASRESSEL_B = "TRUE"; + parameter CCCB_ARBITRATOR_DISABLE_A = "FALSE"; + parameter CCCB_ARBITRATOR_DISABLE_B = "FALSE"; + parameter CHAN_BOND_LIMIT_A = 16; + parameter CHAN_BOND_LIMIT_B = 16; + parameter CHAN_BOND_MODE_A = "NONE"; + parameter CHAN_BOND_MODE_B = "NONE"; + parameter CHAN_BOND_ONE_SHOT_A = "FALSE"; + parameter CHAN_BOND_ONE_SHOT_B = "FALSE"; + parameter CHAN_BOND_SEQ_1_1_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_1_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_2_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_2_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_3_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_3_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_4_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_4_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_1_MASK_A = 4'b0000; + parameter CHAN_BOND_SEQ_1_MASK_B = 4'b0000; + parameter CHAN_BOND_SEQ_2_1_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_1_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_2_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_2_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_3_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_3_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_4_A = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_4_B = 11'b00000000000; + parameter CHAN_BOND_SEQ_2_MASK_A = 4'b0000; + parameter CHAN_BOND_SEQ_2_MASK_B = 4'b0000; + parameter CHAN_BOND_SEQ_2_USE_A = "FALSE"; + parameter CHAN_BOND_SEQ_2_USE_B = "FALSE"; + parameter CHAN_BOND_SEQ_LEN_A = 1; + parameter CHAN_BOND_SEQ_LEN_B = 1; + parameter CLK_CORRECT_USE_A = "TRUE"; + parameter CLK_CORRECT_USE_B = "TRUE"; + parameter CLK_COR_8B10B_DE_A = "FALSE"; + parameter CLK_COR_8B10B_DE_B = "FALSE"; + parameter CLK_COR_MAX_LAT_A = 36; + parameter CLK_COR_MAX_LAT_B = 36; + parameter CLK_COR_MIN_LAT_A = 28; + parameter CLK_COR_MIN_LAT_B = 28; + parameter CLK_COR_SEQ_1_1_A = 11'b00000000000; + parameter CLK_COR_SEQ_1_1_B = 11'b00000000000; + parameter CLK_COR_SEQ_1_2_A = 11'b00000000000; + parameter CLK_COR_SEQ_1_2_B = 11'b00000000000; + parameter CLK_COR_SEQ_1_3_A = 11'b00000000000; + parameter CLK_COR_SEQ_1_3_B = 11'b00000000000; + parameter CLK_COR_SEQ_1_4_A = 11'b00000000000; + parameter CLK_COR_SEQ_1_4_B = 11'b00000000000; + parameter CLK_COR_SEQ_1_MASK_A = 4'b0000; + parameter CLK_COR_SEQ_1_MASK_B = 4'b0000; + parameter CLK_COR_SEQ_2_1_A = 11'b00000000000; + parameter CLK_COR_SEQ_2_1_B = 11'b00000000000; + parameter CLK_COR_SEQ_2_2_A = 11'b00000000000; + parameter CLK_COR_SEQ_2_2_B = 11'b00000000000; + parameter CLK_COR_SEQ_2_3_A = 11'b00000000000; + parameter CLK_COR_SEQ_2_3_B = 11'b00000000000; + parameter CLK_COR_SEQ_2_4_A = 11'b00000000000; + parameter CLK_COR_SEQ_2_4_B = 11'b00000000000; + parameter CLK_COR_SEQ_2_MASK_A = 4'b0000; + parameter CLK_COR_SEQ_2_MASK_B = 4'b0000; + parameter CLK_COR_SEQ_2_USE_A = "FALSE"; + parameter CLK_COR_SEQ_2_USE_B = "FALSE"; + parameter CLK_COR_SEQ_DROP_A = "FALSE"; + parameter CLK_COR_SEQ_DROP_B = "FALSE"; + parameter CLK_COR_SEQ_LEN_A = 1; + parameter CLK_COR_SEQ_LEN_B = 1; + parameter COMMA32_A = "FALSE"; + parameter COMMA32_B = "FALSE"; + parameter COMMA_10B_MASK_A = 10'h3FF; + parameter COMMA_10B_MASK_B = 10'h3FF; + parameter CYCLE_LIMIT_SEL_A = 2'b00; + parameter CYCLE_LIMIT_SEL_B = 2'b00; + parameter DCDR_FILTER_A = 3'b010; + parameter DCDR_FILTER_B = 3'b010; + parameter DEC_MCOMMA_DETECT_A = "TRUE"; + parameter DEC_MCOMMA_DETECT_B = "TRUE"; + parameter DEC_PCOMMA_DETECT_A = "TRUE"; + parameter DEC_PCOMMA_DETECT_B = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_A = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_B = "TRUE"; + parameter DIGRX_FWDCLK_A = 2'b00; + parameter DIGRX_FWDCLK_B = 2'b00; + parameter DIGRX_SYNC_MODE_A = "FALSE"; + parameter DIGRX_SYNC_MODE_B = "FALSE"; + parameter ENABLE_DCDR_A = "FALSE"; + parameter ENABLE_DCDR_B = "FALSE"; + parameter FDET_HYS_CAL_A = 3'b110; + parameter FDET_HYS_CAL_B = 3'b110; + parameter FDET_HYS_SEL_A = 3'b110; + parameter FDET_HYS_SEL_B = 3'b110; + parameter FDET_LCK_CAL_A = 3'b101; + parameter FDET_LCK_CAL_B = 3'b101; + parameter FDET_LCK_SEL_A = 3'b101; + parameter FDET_LCK_SEL_B = 3'b101; + parameter IREFBIASMODE_A = 2'b11; + parameter IREFBIASMODE_B = 2'b11; + parameter LOOPCAL_WAIT_A = 2'b00; + parameter LOOPCAL_WAIT_B = 2'b00; + parameter MCOMMA_32B_VALUE_A = 32'hA1A1A2A2; + parameter MCOMMA_32B_VALUE_B = 32'hA1A1A2A2; + parameter MCOMMA_DETECT_A = "TRUE"; + parameter MCOMMA_DETECT_B = "TRUE"; + parameter OPPOSITE_SELECT_A = "FALSE"; + parameter OPPOSITE_SELECT_B = "FALSE"; + parameter PCOMMA_32B_VALUE_A = 32'hA1A1A2A2; + parameter PCOMMA_32B_VALUE_B = 32'hA1A1A2A2; + parameter PCOMMA_DETECT_A = "TRUE"; + parameter PCOMMA_DETECT_B = "TRUE"; + parameter PCS_BIT_SLIP_A = "FALSE"; + parameter PCS_BIT_SLIP_B = "FALSE"; + parameter PMACLKENABLE_A = "TRUE"; + parameter PMACLKENABLE_B = "TRUE"; + parameter PMACOREPWRENABLE_A = "TRUE"; + parameter PMACOREPWRENABLE_B = "TRUE"; + parameter PMAIREFTRIM_A = 4'b0111; + parameter PMAIREFTRIM_B = 4'b0111; + parameter PMAVBGCTRL_A = 5'b00000; + parameter PMAVBGCTRL_B = 5'b00000; + parameter PMAVREFTRIM_A = 4'b0111; + parameter PMAVREFTRIM_B = 4'b0111; + parameter PMA_BIT_SLIP_A = "FALSE"; + parameter PMA_BIT_SLIP_B = "FALSE"; + parameter POWER_ENABLE_A = "TRUE"; + parameter POWER_ENABLE_B = "TRUE"; + parameter REPEATER_A = "FALSE"; + parameter REPEATER_B = "FALSE"; + parameter RXACTST_A = "FALSE"; + parameter RXACTST_B = "FALSE"; + parameter RXAFEEQ_A = 9'b000000000; + parameter RXAFEEQ_B = 9'b000000000; + parameter RXAFEPD_A = "FALSE"; + parameter RXAFEPD_B = "FALSE"; + parameter RXAFETST_A = "FALSE"; + parameter RXAFETST_B = "FALSE"; + parameter RXAPD_A = "FALSE"; + parameter RXAPD_B = "FALSE"; + parameter RXASYNCDIVIDE_A = 2'b00; + parameter RXASYNCDIVIDE_B = 2'b00; + parameter RXBY_32_A = "TRUE"; + parameter RXBY_32_B = "TRUE"; + parameter RXCDRLOS_A = 6'b000000; + parameter RXCDRLOS_B = 6'b000000; + parameter RXCLK0_FORCE_PMACLK_A = "FALSE"; + parameter RXCLK0_FORCE_PMACLK_B = "FALSE"; + parameter RXCLKMODE_A = 6'b110001; + parameter RXCLKMODE_B = 6'b110001; + parameter RXCMADJ_A = 2'b10; + parameter RXCMADJ_B = 2'b10; + parameter RXCPSEL_A = "TRUE"; + parameter RXCPSEL_B = "TRUE"; + parameter RXCPTST_A = "FALSE"; + parameter RXCPTST_B = "FALSE"; + parameter RXCRCCLOCKDOUBLE_A = "FALSE"; + parameter RXCRCCLOCKDOUBLE_B = "FALSE"; + parameter RXCRCENABLE_A = "FALSE"; + parameter RXCRCENABLE_B = "FALSE"; + parameter RXCRCINITVAL_A = 32'h00000000; + parameter RXCRCINITVAL_B = 32'h00000000; + parameter RXCRCINVERTGEN_A = "FALSE"; + parameter RXCRCINVERTGEN_B = "FALSE"; + parameter RXCRCSAMECLOCK_A = "FALSE"; + parameter RXCRCSAMECLOCK_B = "FALSE"; + parameter RXCTRL1_A = 10'h006; + parameter RXCTRL1_B = 10'h006; + parameter RXCYCLE_LIMIT_SEL_A = 2'b00; + parameter RXCYCLE_LIMIT_SEL_B = 2'b00; + parameter RXDATA_SEL_A = 2'b00; + parameter RXDATA_SEL_B = 2'b00; + parameter RXDCCOUPLE_A = "FALSE"; + parameter RXDCCOUPLE_B = "FALSE"; + parameter RXDIGRESET_A = "FALSE"; + parameter RXDIGRESET_B = "FALSE"; + parameter RXDIGRX_A = "FALSE"; + parameter RXDIGRX_B = "FALSE"; + parameter RXEQ_A = 64'h4000000000000000; + parameter RXEQ_B = 64'h4000000000000000; + parameter RXFDCAL_CLOCK_DIVIDE_A = "NONE"; + parameter RXFDCAL_CLOCK_DIVIDE_B = "NONE"; + parameter RXFDET_HYS_CAL_A = 3'b110; + parameter RXFDET_HYS_CAL_B = 3'b110; + parameter RXFDET_HYS_SEL_A = 3'b110; + parameter RXFDET_HYS_SEL_B = 3'b110; + parameter RXFDET_LCK_CAL_A = 3'b101; + parameter RXFDET_LCK_CAL_B = 3'b101; + parameter RXFDET_LCK_SEL_A = 3'b101; + parameter RXFDET_LCK_SEL_B = 3'b101; + parameter RXFECONTROL1_A = 2'b00; + parameter RXFECONTROL1_B = 2'b00; + parameter RXFECONTROL2_A = 3'b000; + parameter RXFECONTROL2_B = 3'b000; + parameter RXFETUNE_A = 2'b01; + parameter RXFETUNE_B = 2'b01; + parameter RXLB_A = "FALSE"; + parameter RXLB_B = "FALSE"; + parameter RXLKADJ_A = 5'b00000; + parameter RXLKADJ_B = 5'b00000; + parameter RXLKAPD_A = "FALSE"; + parameter RXLKAPD_B = "FALSE"; + parameter RXLOOPCAL_WAIT_A = 2'b00; + parameter RXLOOPCAL_WAIT_B = 2'b00; + parameter RXLOOPFILT_A = 4'b0111; + parameter RXLOOPFILT_B = 4'b0111; + parameter RXOUTDIV2SEL_A = 1; + parameter RXOUTDIV2SEL_B = 1; + parameter RXPDDTST_A = "FALSE"; + parameter RXPDDTST_B = "FALSE"; + parameter RXPD_A = "FALSE"; + parameter RXPD_B = "FALSE"; + parameter RXPLLNDIVSEL_A = 8; + parameter RXPLLNDIVSEL_B = 8; + parameter RXPMACLKSEL_A = "REFCLK1"; + parameter RXPMACLKSEL_B = "REFCLK1"; + parameter RXRCPADJ_A = 3'b011; + parameter RXRCPADJ_B = 3'b011; + parameter RXRCPPD_A = "FALSE"; + parameter RXRCPPD_B = "FALSE"; + parameter RXRECCLK1_USE_SYNC_A = "FALSE"; + parameter RXRECCLK1_USE_SYNC_B = "FALSE"; + parameter RXRIBADJ_A = 2'b11; + parameter RXRIBADJ_B = 2'b11; + parameter RXRPDPD_A = "FALSE"; + parameter RXRPDPD_B = "FALSE"; + parameter RXRSDPD_A = "FALSE"; + parameter RXRSDPD_B = "FALSE"; + parameter RXSLOWDOWN_CAL_A = 2'b00; + parameter RXSLOWDOWN_CAL_B = 2'b00; + parameter RXUSRDIVISOR_A = 1; + parameter RXUSRDIVISOR_B = 1; + parameter RXVCODAC_INIT_A = 10'b1010000000; + parameter RXVCODAC_INIT_B = 10'b1010000000; + parameter RXVCO_CTRL_ENABLE_A = "TRUE"; + parameter RXVCO_CTRL_ENABLE_B = "TRUE"; + parameter RX_BUFFER_USE_A = "TRUE"; + parameter RX_BUFFER_USE_B = "TRUE"; + parameter RX_CLOCK_DIVIDER_A = 2'b00; + parameter RX_CLOCK_DIVIDER_B = 2'b00; + parameter RX_LOS_INVALID_INCR_A = 1; + parameter RX_LOS_INVALID_INCR_B = 1; + parameter RX_LOS_THRESHOLD_A = 4; + parameter RX_LOS_THRESHOLD_B = 4; + parameter SAMPLE_8X_A = "FALSE"; + parameter SAMPLE_8X_B = "FALSE"; + parameter SH_CNT_MAX_A = 64; + parameter SH_CNT_MAX_B = 64; + parameter SH_INVALID_CNT_MAX_A = 16; + parameter SH_INVALID_CNT_MAX_B = 16; + parameter SLOWDOWN_CAL_A = 2'b00; + parameter SLOWDOWN_CAL_B = 2'b00; + parameter TXABPMACLKSEL_A = "REFCLK1"; + parameter TXABPMACLKSEL_B = "REFCLK1"; + parameter TXAPD_A = "FALSE"; + parameter TXAPD_B = "FALSE"; + parameter TXAREFBIASSEL_A = "FALSE"; + parameter TXAREFBIASSEL_B = "FALSE"; + parameter TXASYNCDIVIDE_A = 2'b00; + parameter TXASYNCDIVIDE_B = 2'b00; + parameter TXCLK0_FORCE_PMACLK_A = "FALSE"; + parameter TXCLK0_FORCE_PMACLK_B = "FALSE"; + parameter TXCLKMODE_A = 4'b1001; + parameter TXCLKMODE_B = 4'b1001; + parameter TXCPSEL_A = "TRUE"; + parameter TXCPSEL_B = "TRUE"; + parameter TXCRCCLOCKDOUBLE_A = "FALSE"; + parameter TXCRCCLOCKDOUBLE_B = "FALSE"; + parameter TXCRCENABLE_A = "FALSE"; + parameter TXCRCENABLE_B = "FALSE"; + parameter TXCRCINITVAL_A = 32'h00000000; + parameter TXCRCINITVAL_B = 32'h00000000; + parameter TXCRCINVERTGEN_A = "FALSE"; + parameter TXCRCINVERTGEN_B = "FALSE"; + parameter TXCRCSAMECLOCK_A = "FALSE"; + parameter TXCRCSAMECLOCK_B = "FALSE"; + parameter TXCTRL1_A = 10'h006; + parameter TXCTRL1_B = 10'h006; + parameter TXDATA_SEL_A = 2'b00; + parameter TXDATA_SEL_B = 2'b00; + parameter TXDAT_PRDRV_DAC_A = 3'b111; + parameter TXDAT_PRDRV_DAC_B = 3'b111; + parameter TXDAT_TAP_DAC_A = 5'b10110; + parameter TXDAT_TAP_DAC_B = 5'b10110; + parameter TXDIGPD_A = "FALSE"; + parameter TXDIGPD_B = "FALSE"; + parameter TXFDCAL_CLOCK_DIVIDE_A = "NONE"; + parameter TXFDCAL_CLOCK_DIVIDE_B = "NONE"; + parameter TXHIGHSIGNALEN_A = "TRUE"; + parameter TXHIGHSIGNALEN_B = "TRUE"; + parameter TXLOOPFILT_A = 4'b0111; + parameter TXLOOPFILT_B = 4'b0111; + parameter TXLVLSHFTPD_A = "FALSE"; + parameter TXLVLSHFTPD_B = "FALSE"; + parameter TXOUTCLK1_USE_SYNC_A = "FALSE"; + parameter TXOUTCLK1_USE_SYNC_B = "FALSE"; + parameter TXOUTDIV2SEL_A = 1; + parameter TXOUTDIV2SEL_B = 1; + parameter TXPD_A = "FALSE"; + parameter TXPD_B = "FALSE"; + parameter TXPHASESEL_A = "FALSE"; + parameter TXPHASESEL_B = "FALSE"; + parameter TXPLLNDIVSEL_A = 8; + parameter TXPLLNDIVSEL_B = 8; + parameter TXPOST_PRDRV_DAC_A = 3'b111; + parameter TXPOST_PRDRV_DAC_B = 3'b111; + parameter TXPOST_TAP_DAC_A = 5'b01110; + parameter TXPOST_TAP_DAC_B = 5'b01110; + parameter TXPOST_TAP_PD_A = "TRUE"; + parameter TXPOST_TAP_PD_B = "TRUE"; + parameter TXPRE_PRDRV_DAC_A = 3'b111; + parameter TXPRE_PRDRV_DAC_B = 3'b111; + parameter TXPRE_TAP_DAC_A = 5'b00000; + parameter TXPRE_TAP_DAC_B = 5'b00000; + parameter TXPRE_TAP_PD_A = "TRUE"; + parameter TXPRE_TAP_PD_B = "TRUE"; + parameter TXSLEWRATE_A = "FALSE"; + parameter TXSLEWRATE_B = "FALSE"; + parameter TXTERMTRIM_A = 4'b1100; + parameter TXTERMTRIM_B = 4'b1100; + parameter TX_BUFFER_USE_A = "TRUE"; + parameter TX_BUFFER_USE_B = "TRUE"; + parameter TX_CLOCK_DIVIDER_A = 2'b00; + parameter TX_CLOCK_DIVIDER_B = 2'b00; + parameter VCODAC_INIT_A = 10'b1010000000; + parameter VCODAC_INIT_B = 10'b1010000000; + parameter VCO_CTRL_ENABLE_A = "TRUE"; + parameter VCO_CTRL_ENABLE_B = "TRUE"; + parameter VREFBIASMODE_A = 2'b11; + parameter VREFBIASMODE_B = 2'b11; + output DRDYA; + output DRDYB; + output RXBUFERRA; + output RXBUFERRB; + output RXCALFAILA; + output RXCALFAILB; + output RXCOMMADETA; + output RXCOMMADETB; + output RXCYCLELIMITA; + output RXCYCLELIMITB; + output RXLOCKA; + output RXLOCKB; + output RXMCLKA; + output RXMCLKB; + output RXPCSHCLKOUTA; + output RXPCSHCLKOUTB; + output RXREALIGNA; + output RXREALIGNB; + output RXRECCLK1A; + output RXRECCLK1B; + output RXRECCLK2A; + output RXRECCLK2B; + output RXSIGDETA; + output RXSIGDETB; + output TX1NA; + output TX1NB; + output TX1PA; + output TX1PB; + output TXBUFERRA; + output TXBUFERRB; + output TXCALFAILA; + output TXCALFAILB; + output TXCYCLELIMITA; + output TXCYCLELIMITB; + output TXLOCKA; + output TXLOCKB; + output TXOUTCLK1A; + output TXOUTCLK1B; + output TXOUTCLK2A; + output TXOUTCLK2B; + output TXPCSHCLKOUTA; + output TXPCSHCLKOUTB; + output [15:0] DOA; + output [15:0] DOB; + output [1:0] RXLOSSOFSYNCA; + output [1:0] RXLOSSOFSYNCB; + output [31:0] RXCRCOUTA; + output [31:0] RXCRCOUTB; + output [31:0] TXCRCOUTA; + output [31:0] TXCRCOUTB; + output [4:0] CHBONDOA; + output [4:0] CHBONDOB; + output [5:0] RXSTATUSA; + output [5:0] RXSTATUSB; + output [63:0] RXDATAA; + output [63:0] RXDATAB; + output [7:0] RXCHARISCOMMAA; + output [7:0] RXCHARISCOMMAB; + output [7:0] RXCHARISKA; + output [7:0] RXCHARISKB; + output [7:0] RXDISPERRA; + output [7:0] RXDISPERRB; + output [7:0] RXNOTINTABLEA; + output [7:0] RXNOTINTABLEB; + output [7:0] RXRUNDISPA; + output [7:0] RXRUNDISPB; + output [7:0] TXKERRA; + output [7:0] TXKERRB; + output [7:0] TXRUNDISPA; + output [7:0] TXRUNDISPB; + input DCLKA; + input DCLKB; + input DENA; + input DENB; + input DWEA; + input DWEB; + input ENCHANSYNCA; + input ENCHANSYNCB; + input ENMCOMMAALIGNA; + input ENMCOMMAALIGNB; + input ENPCOMMAALIGNA; + input ENPCOMMAALIGNB; + input GREFCLKA; + input GREFCLKB; + input POWERDOWNA; + input POWERDOWNB; + input REFCLK1A; + input REFCLK1B; + input REFCLK2A; + input REFCLK2B; + input RX1NA; + input RX1NB; + input RX1PA; + input RX1PB; + input RXBLOCKSYNC64B66BUSEA; + input RXBLOCKSYNC64B66BUSEB; + input RXCLKSTABLEA; + input RXCLKSTABLEB; + input RXCOMMADETUSEA; + input RXCOMMADETUSEB; + input RXCRCCLKA; + input RXCRCCLKB; + input RXCRCDATAVALIDA; + input RXCRCDATAVALIDB; + input RXCRCINITA; + input RXCRCINITB; + input RXCRCINTCLKA; + input RXCRCINTCLKB; + input RXCRCPDA; + input RXCRCPDB; + input RXCRCRESETA; + input RXCRCRESETB; + input RXDEC64B66BUSEA; + input RXDEC64B66BUSEB; + input RXDEC8B10BUSEA; + input RXDEC8B10BUSEB; + input RXDESCRAM64B66BUSEA; + input RXDESCRAM64B66BUSEB; + input RXIGNOREBTFA; + input RXIGNOREBTFB; + input RXPMARESETA; + input RXPMARESETB; + input RXPOLARITYA; + input RXPOLARITYB; + input RXRESETA; + input RXRESETB; + input RXSLIDEA; + input RXSLIDEB; + input RXSYNCA; + input RXSYNCB; + input RXUSRCLK2A; + input RXUSRCLK2B; + input RXUSRCLKA; + input RXUSRCLKB; + input TXCLKSTABLEA; + input TXCLKSTABLEB; + input TXCRCCLKA; + input TXCRCCLKB; + input TXCRCDATAVALIDA; + input TXCRCDATAVALIDB; + input TXCRCINITA; + input TXCRCINITB; + input TXCRCINTCLKA; + input TXCRCINTCLKB; + input TXCRCPDA; + input TXCRCPDB; + input TXCRCRESETA; + input TXCRCRESETB; + input TXENC64B66BUSEA; + input TXENC64B66BUSEB; + input TXENC8B10BUSEA; + input TXENC8B10BUSEB; + input TXENOOBA; + input TXENOOBB; + input TXGEARBOX64B66BUSEA; + input TXGEARBOX64B66BUSEB; + input TXINHIBITA; + input TXINHIBITB; + input TXPMARESETA; + input TXPMARESETB; + input TXPOLARITYA; + input TXPOLARITYB; + input TXRESETA; + input TXRESETB; + input TXSCRAM64B66BUSEA; + input TXSCRAM64B66BUSEB; + input TXSYNCA; + input TXSYNCB; + input TXUSRCLK2A; + input TXUSRCLK2B; + input TXUSRCLKA; + input TXUSRCLKB; + input [15:0] DIA; + input [15:0] DIB; + input [1:0] LOOPBACKA; + input [1:0] LOOPBACKB; + input [1:0] RXDATAWIDTHA; + input [1:0] RXDATAWIDTHB; + input [1:0] RXINTDATAWIDTHA; + input [1:0] RXINTDATAWIDTHB; + input [1:0] TXDATAWIDTHA; + input [1:0] TXDATAWIDTHB; + input [1:0] TXINTDATAWIDTHA; + input [1:0] TXINTDATAWIDTHB; + input [2:0] RXCRCDATAWIDTHA; + input [2:0] RXCRCDATAWIDTHB; + input [2:0] TXCRCDATAWIDTHA; + input [2:0] TXCRCDATAWIDTHB; + input [4:0] CHBONDIA; + input [4:0] CHBONDIB; + input [63:0] RXCRCINA; + input [63:0] RXCRCINB; + input [63:0] TXCRCINA; + input [63:0] TXCRCINB; + input [63:0] TXDATAA; + input [63:0] TXDATAB; + input [7:0] DADDRA; + input [7:0] DADDRB; + input [7:0] TXBYPASS8B10BA; + input [7:0] TXBYPASS8B10BB; + input [7:0] TXCHARDISPMODEA; + input [7:0] TXCHARDISPMODEB; + input [7:0] TXCHARDISPVALA; + input [7:0] TXCHARDISPVALB; + input [7:0] TXCHARISKA; + input [7:0] TXCHARISKB; +endmodule + +module GT11CLK (...); + parameter REFCLKSEL = "MGTCLK"; + parameter SYNCLK1OUTEN = "ENABLE"; + parameter SYNCLK2OUTEN = "DISABLE"; + output SYNCLK1OUT; + output SYNCLK2OUT; + input MGTCLKN; + input MGTCLKP; + input REFCLK; + input RXBCLK; + input SYNCLK1IN; + input SYNCLK2IN; +endmodule + +module GT11CLK_MGT (...); + parameter SYNCLK1OUTEN = "ENABLE"; + parameter SYNCLK2OUTEN = "DISABLE"; + output SYNCLK1OUT; + output SYNCLK2OUT; + input MGTCLKN; + input MGTCLKP; +endmodule + +module GTP_DUAL (...); + parameter AC_CAP_DIS_0 = "TRUE"; + parameter AC_CAP_DIS_1 = "TRUE"; + parameter CHAN_BOND_MODE_0 = "OFF"; + parameter CHAN_BOND_MODE_1 = "OFF"; + parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE"; + parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE"; + parameter CLKINDC_B = "TRUE"; + parameter CLK_CORRECT_USE_0 = "TRUE"; + parameter CLK_CORRECT_USE_1 = "TRUE"; + parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; + parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; + parameter CLK_COR_PRECEDENCE_0 = "TRUE"; + parameter CLK_COR_PRECEDENCE_1 = "TRUE"; + parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; + parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; + parameter COMMA_DOUBLE_0 = "FALSE"; + parameter COMMA_DOUBLE_1 = "FALSE"; + parameter DEC_MCOMMA_DETECT_0 = "TRUE"; + parameter DEC_MCOMMA_DETECT_1 = "TRUE"; + parameter DEC_PCOMMA_DETECT_0 = "TRUE"; + parameter DEC_PCOMMA_DETECT_1 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; + parameter MCOMMA_DETECT_0 = "TRUE"; + parameter MCOMMA_DETECT_1 = "TRUE"; + parameter OVERSAMPLE_MODE = "FALSE"; + parameter PCI_EXPRESS_MODE_0 = "TRUE"; + parameter PCI_EXPRESS_MODE_1 = "TRUE"; + parameter PCOMMA_DETECT_0 = "TRUE"; + parameter PCOMMA_DETECT_1 = "TRUE"; + parameter PLL_SATA_0 = "FALSE"; + parameter PLL_SATA_1 = "FALSE"; + parameter RCV_TERM_GND_0 = "TRUE"; + parameter RCV_TERM_GND_1 = "TRUE"; + parameter RCV_TERM_MID_0 = "FALSE"; + parameter RCV_TERM_MID_1 = "FALSE"; + parameter RCV_TERM_VTTRX_0 = "FALSE"; + parameter RCV_TERM_VTTRX_1 = "FALSE"; + parameter RX_BUFFER_USE_0 = "TRUE"; + parameter RX_BUFFER_USE_1 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; + parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; + parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; + parameter RX_SLIDE_MODE_0 = "PCS"; + parameter RX_SLIDE_MODE_1 = "PCS"; + parameter RX_STATUS_FMT_0 = "PCIE"; + parameter RX_STATUS_FMT_1 = "PCIE"; + parameter RX_XCLK_SEL_0 = "RXREC"; + parameter RX_XCLK_SEL_1 = "RXREC"; + parameter SIM_PLL_PERDIV2 = 9'h190; + parameter SIM_RECEIVER_DETECT_PASS0 = "FALSE"; + parameter SIM_RECEIVER_DETECT_PASS1 = "FALSE"; + parameter TERMINATION_OVRD = "FALSE"; + parameter TX_BUFFER_USE_0 = "TRUE"; + parameter TX_BUFFER_USE_1 = "TRUE"; + parameter TX_DIFF_BOOST_0 = "TRUE"; + parameter TX_DIFF_BOOST_1 = "TRUE"; + parameter TX_XCLK_SEL_0 = "TXUSR"; + parameter TX_XCLK_SEL_1 = "TXUSR"; + parameter [15:0] TRANS_TIME_FROM_P2_0 = 16'h003c; + parameter [15:0] TRANS_TIME_FROM_P2_1 = 16'h003c; + parameter [15:0] TRANS_TIME_NON_P2_0 = 16'h0019; + parameter [15:0] TRANS_TIME_NON_P2_1 = 16'h0019; + parameter [15:0] TRANS_TIME_TO_P2_0 = 16'h0064; + parameter [15:0] TRANS_TIME_TO_P2_1 = 16'h0064; + parameter [24:0] PMA_RX_CFG_0 = 25'h09f0089; + parameter [24:0] PMA_RX_CFG_1 = 25'h09f0089; + parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c07640; + parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c07640; + parameter [27:0] PCS_COM_CFG = 28'h1680a0e; + parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b001; + parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b001; + parameter [2:0] SATA_BURST_VAL_0 = 3'b100; + parameter [2:0] SATA_BURST_VAL_1 = 3'b100; + parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; + parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; + parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1; + parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; + parameter [3:0] COM_BURST_VAL_0 = 4'b1111; + parameter [3:0] COM_BURST_VAL_1 = 4'b1111; + parameter [4:0] TERMINATION_CTRL = 5'b10100; + parameter [4:0] TXRX_INVERT_0 = 5'b00000; + parameter [4:0] TXRX_INVERT_1 = 5'b00000; + parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; + parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0; + parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; + parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; + parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; + parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; + parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; + parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; + parameter ALIGN_COMMA_WORD_0 = 1; + parameter ALIGN_COMMA_WORD_1 = 1; + parameter CHAN_BOND_1_MAX_SKEW_0 = 7; + parameter CHAN_BOND_1_MAX_SKEW_1 = 7; + parameter CHAN_BOND_2_MAX_SKEW_0 = 1; + parameter CHAN_BOND_2_MAX_SKEW_1 = 1; + parameter CHAN_BOND_LEVEL_0 = 0; + parameter CHAN_BOND_LEVEL_1 = 0; + parameter CHAN_BOND_SEQ_LEN_0 = 4; + parameter CHAN_BOND_SEQ_LEN_1 = 4; + parameter CLK25_DIVIDER = 4; + parameter CLK_COR_ADJ_LEN_0 = 1; + parameter CLK_COR_ADJ_LEN_1 = 1; + parameter CLK_COR_DET_LEN_0 = 1; + parameter CLK_COR_DET_LEN_1 = 1; + parameter CLK_COR_MAX_LAT_0 = 18; + parameter CLK_COR_MAX_LAT_1 = 18; + parameter CLK_COR_MIN_LAT_0 = 16; + parameter CLK_COR_MIN_LAT_1 = 16; + parameter CLK_COR_REPEAT_WAIT_0 = 5; + parameter CLK_COR_REPEAT_WAIT_1 = 5; + parameter OOB_CLK_DIVIDER = 4; + parameter PLL_DIVSEL_FB = 5; + parameter PLL_DIVSEL_REF = 2; + parameter PLL_RXDIVSEL_OUT_0 = 1; + parameter PLL_RXDIVSEL_OUT_1 = 1; + parameter PLL_TXDIVSEL_COMM_OUT = 1; + parameter PLL_TXDIVSEL_OUT_0 = 1; + parameter PLL_TXDIVSEL_OUT_1 = 1; + parameter RX_LOS_INVALID_INCR_0 = 8; + parameter RX_LOS_INVALID_INCR_1 = 8; + parameter RX_LOS_THRESHOLD_0 = 128; + parameter RX_LOS_THRESHOLD_1 = 128; + parameter SATA_MAX_BURST_0 = 7; + parameter SATA_MAX_BURST_1 = 7; + parameter SATA_MAX_INIT_0 = 22; + parameter SATA_MAX_INIT_1 = 22; + parameter SATA_MAX_WAKE_0 = 7; + parameter SATA_MAX_WAKE_1 = 7; + parameter SATA_MIN_BURST_0 = 4; + parameter SATA_MIN_BURST_1 = 4; + parameter SATA_MIN_INIT_0 = 12; + parameter SATA_MIN_INIT_1 = 12; + parameter SATA_MIN_WAKE_0 = 4; + parameter SATA_MIN_WAKE_1 = 4; + parameter SIM_GTPRESET_SPEEDUP = 0; + parameter TERMINATION_IMP_0 = 50; + parameter TERMINATION_IMP_1 = 50; + parameter TX_SYNC_FILTERB = 1; + output DRDY; + output PHYSTATUS0; + output PHYSTATUS1; + output PLLLKDET; + output REFCLKOUT; + output RESETDONE0; + output RESETDONE1; + output RXBYTEISALIGNED0; + output RXBYTEISALIGNED1; + output RXBYTEREALIGN0; + output RXBYTEREALIGN1; + output RXCHANBONDSEQ0; + output RXCHANBONDSEQ1; + output RXCHANISALIGNED0; + output RXCHANISALIGNED1; + output RXCHANREALIGN0; + output RXCHANREALIGN1; + output RXCOMMADET0; + output RXCOMMADET1; + output RXELECIDLE0; + output RXELECIDLE1; + output RXOVERSAMPLEERR0; + output RXOVERSAMPLEERR1; + output RXPRBSERR0; + output RXPRBSERR1; + output RXRECCLK0; + output RXRECCLK1; + output RXVALID0; + output RXVALID1; + output TXN0; + output TXN1; + output TXOUTCLK0; + output TXOUTCLK1; + output TXP0; + output TXP1; + output [15:0] DO; + output [15:0] RXDATA0; + output [15:0] RXDATA1; + output [1:0] RXCHARISCOMMA0; + output [1:0] RXCHARISCOMMA1; + output [1:0] RXCHARISK0; + output [1:0] RXCHARISK1; + output [1:0] RXDISPERR0; + output [1:0] RXDISPERR1; + output [1:0] RXLOSSOFSYNC0; + output [1:0] RXLOSSOFSYNC1; + output [1:0] RXNOTINTABLE0; + output [1:0] RXNOTINTABLE1; + output [1:0] RXRUNDISP0; + output [1:0] RXRUNDISP1; + output [1:0] TXBUFSTATUS0; + output [1:0] TXBUFSTATUS1; + output [1:0] TXKERR0; + output [1:0] TXKERR1; + output [1:0] TXRUNDISP0; + output [1:0] TXRUNDISP1; + output [2:0] RXBUFSTATUS0; + output [2:0] RXBUFSTATUS1; + output [2:0] RXCHBONDO0; + output [2:0] RXCHBONDO1; + output [2:0] RXCLKCORCNT0; + output [2:0] RXCLKCORCNT1; + output [2:0] RXSTATUS0; + output [2:0] RXSTATUS1; + input CLKIN; + input DCLK; + input DEN; + input DWE; + input GTPRESET; + input INTDATAWIDTH; + input PLLLKDETEN; + input PLLPOWERDOWN; + input PRBSCNTRESET0; + input PRBSCNTRESET1; + input REFCLKPWRDNB; + input RXBUFRESET0; + input RXBUFRESET1; + input RXCDRRESET0; + input RXCDRRESET1; + input RXCOMMADETUSE0; + input RXCOMMADETUSE1; + input RXDATAWIDTH0; + input RXDATAWIDTH1; + input RXDEC8B10BUSE0; + input RXDEC8B10BUSE1; + input RXELECIDLERESET0; + input RXELECIDLERESET1; + input RXENCHANSYNC0; + input RXENCHANSYNC1; + input RXENELECIDLERESETB; + input RXENEQB0; + input RXENEQB1; + input RXENMCOMMAALIGN0; + input RXENMCOMMAALIGN1; + input RXENPCOMMAALIGN0; + input RXENPCOMMAALIGN1; + input RXENSAMPLEALIGN0; + input RXENSAMPLEALIGN1; + input RXN0; + input RXN1; + input RXP0; + input RXP1; + input RXPMASETPHASE0; + input RXPMASETPHASE1; + input RXPOLARITY0; + input RXPOLARITY1; + input RXRESET0; + input RXRESET1; + input RXSLIDE0; + input RXSLIDE1; + input RXUSRCLK0; + input RXUSRCLK1; + input RXUSRCLK20; + input RXUSRCLK21; + input TXCOMSTART0; + input TXCOMSTART1; + input TXCOMTYPE0; + input TXCOMTYPE1; + input TXDATAWIDTH0; + input TXDATAWIDTH1; + input TXDETECTRX0; + input TXDETECTRX1; + input TXELECIDLE0; + input TXELECIDLE1; + input TXENC8B10BUSE0; + input TXENC8B10BUSE1; + input TXENPMAPHASEALIGN; + input TXINHIBIT0; + input TXINHIBIT1; + input TXPMASETPHASE; + input TXPOLARITY0; + input TXPOLARITY1; + input TXRESET0; + input TXRESET1; + input TXUSRCLK0; + input TXUSRCLK1; + input TXUSRCLK20; + input TXUSRCLK21; + input [15:0] DI; + input [15:0] TXDATA0; + input [15:0] TXDATA1; + input [1:0] RXENPRBSTST0; + input [1:0] RXENPRBSTST1; + input [1:0] RXEQMIX0; + input [1:0] RXEQMIX1; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] TXBYPASS8B10B0; + input [1:0] TXBYPASS8B10B1; + input [1:0] TXCHARDISPMODE0; + input [1:0] TXCHARDISPMODE1; + input [1:0] TXCHARDISPVAL0; + input [1:0] TXCHARDISPVAL1; + input [1:0] TXCHARISK0; + input [1:0] TXCHARISK1; + input [1:0] TXENPRBSTST0; + input [1:0] TXENPRBSTST1; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [2:0] LOOPBACK0; + input [2:0] LOOPBACK1; + input [2:0] RXCHBONDI0; + input [2:0] RXCHBONDI1; + input [2:0] TXBUFDIFFCTRL0; + input [2:0] TXBUFDIFFCTRL1; + input [2:0] TXDIFFCTRL0; + input [2:0] TXDIFFCTRL1; + input [2:0] TXPREEMPHASIS0; + input [2:0] TXPREEMPHASIS1; + input [3:0] GTPTEST; + input [3:0] RXEQPOLE0; + input [3:0] RXEQPOLE1; + input [6:0] DADDR; +endmodule + +module GTX_DUAL (...); + parameter STEPPING = "0"; + parameter AC_CAP_DIS_0 = "TRUE"; + parameter AC_CAP_DIS_1 = "TRUE"; + parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; + parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; + parameter CHAN_BOND_MODE_0 = "OFF"; + parameter CHAN_BOND_MODE_1 = "OFF"; + parameter CHAN_BOND_SEQ_2_USE_0 = "TRUE"; + parameter CHAN_BOND_SEQ_2_USE_1 = "TRUE"; + parameter CLKINDC_B = "TRUE"; + parameter CLKRCV_TRST = "FALSE"; + parameter CLK_CORRECT_USE_0 = "TRUE"; + parameter CLK_CORRECT_USE_1 = "TRUE"; + parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; + parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; + parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; + parameter CLK_COR_PRECEDENCE_0 = "TRUE"; + parameter CLK_COR_PRECEDENCE_1 = "TRUE"; + parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; + parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; + parameter COMMA_DOUBLE_0 = "FALSE"; + parameter COMMA_DOUBLE_1 = "FALSE"; + parameter DEC_MCOMMA_DETECT_0 = "TRUE"; + parameter DEC_MCOMMA_DETECT_1 = "TRUE"; + parameter DEC_PCOMMA_DETECT_0 = "TRUE"; + parameter DEC_PCOMMA_DETECT_1 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; + parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; + parameter MCOMMA_DETECT_0 = "TRUE"; + parameter MCOMMA_DETECT_1 = "TRUE"; + parameter OVERSAMPLE_MODE = "FALSE"; + parameter PCI_EXPRESS_MODE_0 = "TRUE"; + parameter PCI_EXPRESS_MODE_1 = "TRUE"; + parameter PCOMMA_DETECT_0 = "TRUE"; + parameter PCOMMA_DETECT_1 = "TRUE"; + parameter PLL_FB_DCCEN = "FALSE"; + parameter PLL_SATA_0 = "FALSE"; + parameter PLL_SATA_1 = "FALSE"; + parameter RCV_TERM_GND_0 = "TRUE"; + parameter RCV_TERM_GND_1 = "TRUE"; + parameter RCV_TERM_VTTRX_0 = "FALSE"; + parameter RCV_TERM_VTTRX_1 = "FALSE"; + parameter RXGEARBOX_USE_0 = "FALSE"; + parameter RXGEARBOX_USE_1 = "FALSE"; + parameter RX_BUFFER_USE_0 = "TRUE"; + parameter RX_BUFFER_USE_1 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; + parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; + parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; + parameter RX_EN_IDLE_HOLD_DFE_0 = "TRUE"; + parameter RX_EN_IDLE_HOLD_DFE_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; + parameter RX_EN_IDLE_RESET_FR = "TRUE"; + parameter RX_EN_IDLE_RESET_PH = "TRUE"; + parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; + parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; + parameter RX_SLIDE_MODE_0 = "PCS"; + parameter RX_SLIDE_MODE_1 = "PCS"; + parameter RX_STATUS_FMT_0 = "PCIE"; + parameter RX_STATUS_FMT_1 = "PCIE"; + parameter RX_XCLK_SEL_0 = "RXREC"; + parameter RX_XCLK_SEL_1 = "RXREC"; + parameter SIM_PLL_PERDIV2 = 9'h190; + parameter SIM_RECEIVER_DETECT_PASS_0 = "FALSE"; + parameter SIM_RECEIVER_DETECT_PASS_1 = "FALSE"; + parameter TERMINATION_OVRD = "FALSE"; + parameter TXGEARBOX_USE_0 = "FALSE"; + parameter TXGEARBOX_USE_1 = "FALSE"; + parameter TX_BUFFER_USE_0 = "TRUE"; + parameter TX_BUFFER_USE_1 = "TRUE"; + parameter TX_XCLK_SEL_0 = "TXUSR"; + parameter TX_XCLK_SEL_1 = "TXUSR"; + parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03c; + parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03c; + parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; + parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; + parameter [19:0] PMA_TX_CFG_0 = 20'h00082; + parameter [19:0] PMA_TX_CFG_1 = 20'h00082; + parameter [1:0] CM_TRIM_0 = 2'b10; + parameter [1:0] CM_TRIM_1 = 2'b10; + parameter [23:0] PLL_COM_CFG = 24'h21680a; + parameter [24:0] PMA_RX_CFG_0 = 25'h05ce109; + parameter [24:0] PMA_RX_CFG_1 = 25'h05ce109; + parameter [26:0] PMA_CDR_SCAN_0 = 27'h6c08040; + parameter [26:0] PMA_CDR_SCAN_1 = 27'h6c08040; + parameter [2:0] GEARBOX_ENDEC_0 = 3'b000; + parameter [2:0] GEARBOX_ENDEC_1 = 3'b000; + parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b111; + parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b111; + parameter [2:0] PLL_LKDET_CFG = 3'b111; + parameter [2:0] PLL_TDCC_CFG = 3'b000; + parameter [2:0] SATA_BURST_VAL_0 = 3'b100; + parameter [2:0] SATA_BURST_VAL_1 = 3'b100; + parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; + parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; + parameter [2:0] TXRX_INVERT_0 = 3'b000; + parameter [2:0] TXRX_INVERT_1 = 3'b000; + parameter [2:0] TX_IDLE_DELAY_0 = 3'b010; + parameter [2:0] TX_IDLE_DELAY_1 = 3'b010; + parameter [31:0] PRBS_ERR_THRESHOLD_0 = 32'h1; + parameter [31:0] PRBS_ERR_THRESHOLD_1 = 32'h1; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; + parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; + parameter [3:0] COM_BURST_VAL_0 = 4'b1111; + parameter [3:0] COM_BURST_VAL_1 = 4'b1111; + parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; + parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; + parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; + parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; + parameter [4:0] CDR_PH_ADJ_TIME = 5'b01010; + parameter [4:0] DFE_CAL_TIME = 5'b00110; + parameter [4:0] TERMINATION_CTRL = 5'b10100; + parameter [68:0] PMA_COM_CFG = 69'h0; + parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h0; + parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h0; + parameter [7:0] PLL_CP_CFG = 8'h00; + parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; + parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; + parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; + parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0; + parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0; + parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; + parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; + parameter [9:0] DFE_CFG_0 = 10'b0001111011; + parameter [9:0] DFE_CFG_1 = 10'b0001111011; + parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; + parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; + parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; + parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; + parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; + parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; + parameter ALIGN_COMMA_WORD_0 = 1; + parameter ALIGN_COMMA_WORD_1 = 1; + parameter CB2_INH_CC_PERIOD_0 = 8; + parameter CB2_INH_CC_PERIOD_1 = 8; + parameter CHAN_BOND_1_MAX_SKEW_0 = 7; + parameter CHAN_BOND_1_MAX_SKEW_1 = 7; + parameter CHAN_BOND_2_MAX_SKEW_0 = 1; + parameter CHAN_BOND_2_MAX_SKEW_1 = 1; + parameter CHAN_BOND_LEVEL_0 = 0; + parameter CHAN_BOND_LEVEL_1 = 0; + parameter CHAN_BOND_SEQ_LEN_0 = 4; + parameter CHAN_BOND_SEQ_LEN_1 = 4; + parameter CLK25_DIVIDER = 4; + parameter CLK_COR_ADJ_LEN_0 = 1; + parameter CLK_COR_ADJ_LEN_1 = 1; + parameter CLK_COR_DET_LEN_0 = 1; + parameter CLK_COR_DET_LEN_1 = 1; + parameter CLK_COR_MAX_LAT_0 = 18; + parameter CLK_COR_MAX_LAT_1 = 18; + parameter CLK_COR_MIN_LAT_0 = 16; + parameter CLK_COR_MIN_LAT_1 = 16; + parameter CLK_COR_REPEAT_WAIT_0 = 5; + parameter CLK_COR_REPEAT_WAIT_1 = 5; + parameter OOB_CLK_DIVIDER = 4; + parameter PLL_DIVSEL_FB = 5; + parameter PLL_DIVSEL_REF = 2; + parameter PLL_RXDIVSEL_OUT_0 = 1; + parameter PLL_RXDIVSEL_OUT_1 = 1; + parameter PLL_TXDIVSEL_OUT_0 = 1; + parameter PLL_TXDIVSEL_OUT_1 = 1; + parameter RX_LOS_INVALID_INCR_0 = 8; + parameter RX_LOS_INVALID_INCR_1 = 8; + parameter RX_LOS_THRESHOLD_0 = 128; + parameter RX_LOS_THRESHOLD_1 = 128; + parameter SATA_MAX_BURST_0 = 7; + parameter SATA_MAX_BURST_1 = 7; + parameter SATA_MAX_INIT_0 = 22; + parameter SATA_MAX_INIT_1 = 22; + parameter SATA_MAX_WAKE_0 = 7; + parameter SATA_MAX_WAKE_1 = 7; + parameter SATA_MIN_BURST_0 = 4; + parameter SATA_MIN_BURST_1 = 4; + parameter SATA_MIN_INIT_0 = 12; + parameter SATA_MIN_INIT_1 = 12; + parameter SATA_MIN_WAKE_0 = 4; + parameter SATA_MIN_WAKE_1 = 4; + parameter SIM_GTXRESET_SPEEDUP = 0; + parameter TERMINATION_IMP_0 = 50; + parameter TERMINATION_IMP_1 = 50; + output DRDY; + output PHYSTATUS0; + output PHYSTATUS1; + output PLLLKDET; + output REFCLKOUT; + output RESETDONE0; + output RESETDONE1; + output RXBYTEISALIGNED0; + output RXBYTEISALIGNED1; + output RXBYTEREALIGN0; + output RXBYTEREALIGN1; + output RXCHANBONDSEQ0; + output RXCHANBONDSEQ1; + output RXCHANISALIGNED0; + output RXCHANISALIGNED1; + output RXCHANREALIGN0; + output RXCHANREALIGN1; + output RXCOMMADET0; + output RXCOMMADET1; + output RXDATAVALID0; + output RXDATAVALID1; + output RXELECIDLE0; + output RXELECIDLE1; + output RXHEADERVALID0; + output RXHEADERVALID1; + output RXOVERSAMPLEERR0; + output RXOVERSAMPLEERR1; + output RXPRBSERR0; + output RXPRBSERR1; + output RXRECCLK0; + output RXRECCLK1; + output RXSTARTOFSEQ0; + output RXSTARTOFSEQ1; + output RXVALID0; + output RXVALID1; + output TXGEARBOXREADY0; + output TXGEARBOXREADY1; + output TXN0; + output TXN1; + output TXOUTCLK0; + output TXOUTCLK1; + output TXP0; + output TXP1; + output [15:0] DO; + output [1:0] RXLOSSOFSYNC0; + output [1:0] RXLOSSOFSYNC1; + output [1:0] TXBUFSTATUS0; + output [1:0] TXBUFSTATUS1; + output [2:0] DFESENSCAL0; + output [2:0] DFESENSCAL1; + output [2:0] RXBUFSTATUS0; + output [2:0] RXBUFSTATUS1; + output [2:0] RXCLKCORCNT0; + output [2:0] RXCLKCORCNT1; + output [2:0] RXHEADER0; + output [2:0] RXHEADER1; + output [2:0] RXSTATUS0; + output [2:0] RXSTATUS1; + output [31:0] RXDATA0; + output [31:0] RXDATA1; + output [3:0] DFETAP3MONITOR0; + output [3:0] DFETAP3MONITOR1; + output [3:0] DFETAP4MONITOR0; + output [3:0] DFETAP4MONITOR1; + output [3:0] RXCHARISCOMMA0; + output [3:0] RXCHARISCOMMA1; + output [3:0] RXCHARISK0; + output [3:0] RXCHARISK1; + output [3:0] RXCHBONDO0; + output [3:0] RXCHBONDO1; + output [3:0] RXDISPERR0; + output [3:0] RXDISPERR1; + output [3:0] RXNOTINTABLE0; + output [3:0] RXNOTINTABLE1; + output [3:0] RXRUNDISP0; + output [3:0] RXRUNDISP1; + output [3:0] TXKERR0; + output [3:0] TXKERR1; + output [3:0] TXRUNDISP0; + output [3:0] TXRUNDISP1; + output [4:0] DFEEYEDACMONITOR0; + output [4:0] DFEEYEDACMONITOR1; + output [4:0] DFETAP1MONITOR0; + output [4:0] DFETAP1MONITOR1; + output [4:0] DFETAP2MONITOR0; + output [4:0] DFETAP2MONITOR1; + output [5:0] DFECLKDLYADJMONITOR0; + output [5:0] DFECLKDLYADJMONITOR1; + input CLKIN; + input DCLK; + input DEN; + input DWE; + input GTXRESET; + input INTDATAWIDTH; + input PLLLKDETEN; + input PLLPOWERDOWN; + input PRBSCNTRESET0; + input PRBSCNTRESET1; + input REFCLKPWRDNB; + input RXBUFRESET0; + input RXBUFRESET1; + input RXCDRRESET0; + input RXCDRRESET1; + input RXCOMMADETUSE0; + input RXCOMMADETUSE1; + input RXDEC8B10BUSE0; + input RXDEC8B10BUSE1; + input RXENCHANSYNC0; + input RXENCHANSYNC1; + input RXENEQB0; + input RXENEQB1; + input RXENMCOMMAALIGN0; + input RXENMCOMMAALIGN1; + input RXENPCOMMAALIGN0; + input RXENPCOMMAALIGN1; + input RXENPMAPHASEALIGN0; + input RXENPMAPHASEALIGN1; + input RXENSAMPLEALIGN0; + input RXENSAMPLEALIGN1; + input RXGEARBOXSLIP0; + input RXGEARBOXSLIP1; + input RXN0; + input RXN1; + input RXP0; + input RXP1; + input RXPMASETPHASE0; + input RXPMASETPHASE1; + input RXPOLARITY0; + input RXPOLARITY1; + input RXRESET0; + input RXRESET1; + input RXSLIDE0; + input RXSLIDE1; + input RXUSRCLK0; + input RXUSRCLK1; + input RXUSRCLK20; + input RXUSRCLK21; + input TXCOMSTART0; + input TXCOMSTART1; + input TXCOMTYPE0; + input TXCOMTYPE1; + input TXDETECTRX0; + input TXDETECTRX1; + input TXELECIDLE0; + input TXELECIDLE1; + input TXENC8B10BUSE0; + input TXENC8B10BUSE1; + input TXENPMAPHASEALIGN0; + input TXENPMAPHASEALIGN1; + input TXINHIBIT0; + input TXINHIBIT1; + input TXPMASETPHASE0; + input TXPMASETPHASE1; + input TXPOLARITY0; + input TXPOLARITY1; + input TXRESET0; + input TXRESET1; + input TXSTARTSEQ0; + input TXSTARTSEQ1; + input TXUSRCLK0; + input TXUSRCLK1; + input TXUSRCLK20; + input TXUSRCLK21; + input [13:0] GTXTEST; + input [15:0] DI; + input [1:0] RXDATAWIDTH0; + input [1:0] RXDATAWIDTH1; + input [1:0] RXENPRBSTST0; + input [1:0] RXENPRBSTST1; + input [1:0] RXEQMIX0; + input [1:0] RXEQMIX1; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] TXDATAWIDTH0; + input [1:0] TXDATAWIDTH1; + input [1:0] TXENPRBSTST0; + input [1:0] TXENPRBSTST1; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [2:0] LOOPBACK0; + input [2:0] LOOPBACK1; + input [2:0] TXBUFDIFFCTRL0; + input [2:0] TXBUFDIFFCTRL1; + input [2:0] TXDIFFCTRL0; + input [2:0] TXDIFFCTRL1; + input [2:0] TXHEADER0; + input [2:0] TXHEADER1; + input [31:0] TXDATA0; + input [31:0] TXDATA1; + input [3:0] DFETAP30; + input [3:0] DFETAP31; + input [3:0] DFETAP40; + input [3:0] DFETAP41; + input [3:0] RXCHBONDI0; + input [3:0] RXCHBONDI1; + input [3:0] RXEQPOLE0; + input [3:0] RXEQPOLE1; + input [3:0] TXBYPASS8B10B0; + input [3:0] TXBYPASS8B10B1; + input [3:0] TXCHARDISPMODE0; + input [3:0] TXCHARDISPMODE1; + input [3:0] TXCHARDISPVAL0; + input [3:0] TXCHARDISPVAL1; + input [3:0] TXCHARISK0; + input [3:0] TXCHARISK1; + input [3:0] TXPREEMPHASIS0; + input [3:0] TXPREEMPHASIS1; + input [4:0] DFETAP10; + input [4:0] DFETAP11; + input [4:0] DFETAP20; + input [4:0] DFETAP21; + input [5:0] DFECLKDLYADJ0; + input [5:0] DFECLKDLYADJ1; + input [6:0] DADDR; + input [6:0] TXSEQUENCE0; + input [6:0] TXSEQUENCE1; +endmodule + +module CRC32 (...); + parameter CRC_INIT = 32'hFFFFFFFF; + output [31:0] CRCOUT; + (* clkbuf_sink *) + input CRCCLK; + input CRCDATAVALID; + input [2:0] CRCDATAWIDTH; + input [31:0] CRCIN; + input CRCRESET; +endmodule + +module CRC64 (...); + parameter CRC_INIT = 32'hFFFFFFFF; + output [31:0] CRCOUT; + (* clkbuf_sink *) + input CRCCLK; + input CRCDATAVALID; + input [2:0] CRCDATAWIDTH; + input [63:0] CRCIN; + input CRCRESET; +endmodule + +module GTHE1_QUAD (...); + parameter [15:0] BER_CONST_PTRN0 = 16'h0000; + parameter [15:0] BER_CONST_PTRN1 = 16'h0000; + parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE1 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE2 = 16'h4004; + parameter [15:0] BUFFER_CONFIG_LANE3 = 16'h4004; + parameter [15:0] DFE_TRAIN_CTRL_LANE0 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE1 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE2 = 16'h0000; + parameter [15:0] DFE_TRAIN_CTRL_LANE3 = 16'h0000; + parameter [15:0] DLL_CFG0 = 16'h8202; + parameter [15:0] DLL_CFG1 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE3 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE3 = 16'h0000; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE0 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE1 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE2 = 16'h0002; + parameter [15:0] E10GBASEKR_PMA_CTRL_LANE3 = 16'h0002; + parameter [15:0] E10GBASEKX_CTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASEKX_CTRL_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_CFG_LANE0 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE1 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE2 = 16'h070C; + parameter [15:0] E10GBASER_PCS_CFG_LANE3 = 16'h070C; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE0 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE1 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE2 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA0_LANE3 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA1_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA2_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDA3_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE0 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE1 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE2 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB0_LANE3 = 16'h0001; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB1_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB2_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_SEEDB3_LANE3 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE3 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE0 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE1 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE2 = 16'h0000; + parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE3 = 16'h0000; + parameter [15:0] GLBL0_NOISE_CTRL = 16'hF0B8; + parameter [15:0] GLBL_AMON_SEL = 16'h0000; + parameter [15:0] GLBL_DMON_SEL = 16'h0200; + parameter [15:0] GLBL_PWR_CTRL = 16'h0000; + parameter [0:0] GTH_CFG_PWRUP_LANE0 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE1 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE2 = 1'b1; + parameter [0:0] GTH_CFG_PWRUP_LANE3 = 1'b1; + parameter [15:0] LANE_AMON_SEL = 16'h00F0; + parameter [15:0] LANE_DMON_SEL = 16'h0000; + parameter [15:0] LANE_LNK_CFGOVRD = 16'h0000; + parameter [15:0] LANE_PWR_CTRL_LANE0 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE1 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE2 = 16'h0400; + parameter [15:0] LANE_PWR_CTRL_LANE3 = 16'h0400; + parameter [15:0] LNK_TRN_CFG_LANE0 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE1 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE2 = 16'h0000; + parameter [15:0] LNK_TRN_CFG_LANE3 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE0 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE1 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE2 = 16'h0000; + parameter [15:0] LNK_TRN_COEFF_REQ_LANE3 = 16'h0000; + parameter [15:0] MISC_CFG = 16'h0008; + parameter [15:0] MODE_CFG1 = 16'h0000; + parameter [15:0] MODE_CFG2 = 16'h0000; + parameter [15:0] MODE_CFG3 = 16'h0000; + parameter [15:0] MODE_CFG4 = 16'h0000; + parameter [15:0] MODE_CFG5 = 16'h0000; + parameter [15:0] MODE_CFG6 = 16'h0000; + parameter [15:0] MODE_CFG7 = 16'h0000; + parameter [15:0] PCS_ABILITY_LANE0 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE1 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE2 = 16'h0010; + parameter [15:0] PCS_ABILITY_LANE3 = 16'h0010; + parameter [15:0] PCS_CTRL1_LANE0 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE1 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE2 = 16'h2040; + parameter [15:0] PCS_CTRL1_LANE3 = 16'h2040; + parameter [15:0] PCS_CTRL2_LANE0 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE1 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE2 = 16'h0000; + parameter [15:0] PCS_CTRL2_LANE3 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_0_LANE0 = 16'h1116; + parameter [15:0] PCS_MISC_CFG_0_LANE1 = 16'h1116; + parameter [15:0] PCS_MISC_CFG_0_LANE2 = 16'h1116; + parameter [15:0] PCS_MISC_CFG_0_LANE3 = 16'h1116; + parameter [15:0] PCS_MISC_CFG_1_LANE0 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE1 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE2 = 16'h0000; + parameter [15:0] PCS_MISC_CFG_1_LANE3 = 16'h0000; + parameter [15:0] PCS_MODE_LANE0 = 16'h0000; + parameter [15:0] PCS_MODE_LANE1 = 16'h0000; + parameter [15:0] PCS_MODE_LANE2 = 16'h0000; + parameter [15:0] PCS_MODE_LANE3 = 16'h0000; + parameter [15:0] PCS_RESET_1_LANE0 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE1 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE2 = 16'h0002; + parameter [15:0] PCS_RESET_1_LANE3 = 16'h0002; + parameter [15:0] PCS_RESET_LANE0 = 16'h0000; + parameter [15:0] PCS_RESET_LANE1 = 16'h0000; + parameter [15:0] PCS_RESET_LANE2 = 16'h0000; + parameter [15:0] PCS_RESET_LANE3 = 16'h0000; + parameter [15:0] PCS_TYPE_LANE0 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE1 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE2 = 16'h002C; + parameter [15:0] PCS_TYPE_LANE3 = 16'h002C; + parameter [15:0] PLL_CFG0 = 16'h95DF; + parameter [15:0] PLL_CFG1 = 16'h81C0; + parameter [15:0] PLL_CFG2 = 16'h0424; + parameter [15:0] PMA_CTRL1_LANE0 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE1 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE2 = 16'h0000; + parameter [15:0] PMA_CTRL1_LANE3 = 16'h0000; + parameter [15:0] PMA_CTRL2_LANE0 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE1 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE2 = 16'h000B; + parameter [15:0] PMA_CTRL2_LANE3 = 16'h000B; + parameter [15:0] PMA_LPBK_CTRL_LANE0 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE1 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE2 = 16'h0004; + parameter [15:0] PMA_LPBK_CTRL_LANE3 = 16'h0004; + parameter [15:0] PRBS_BER_CFG0_LANE0 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE1 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE2 = 16'h0000; + parameter [15:0] PRBS_BER_CFG0_LANE3 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE0 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE1 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE2 = 16'h0000; + parameter [15:0] PRBS_BER_CFG1_LANE3 = 16'h0000; + parameter [15:0] PRBS_CFG_LANE0 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE1 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE2 = 16'h000A; + parameter [15:0] PRBS_CFG_LANE3 = 16'h000A; + parameter [15:0] PTRN_CFG0_LSB = 16'h5555; + parameter [15:0] PTRN_CFG0_MSB = 16'h5555; + parameter [15:0] PTRN_LEN_CFG = 16'h001F; + parameter [15:0] PWRUP_DLY = 16'h0000; + parameter [15:0] RX_AEQ_VAL0_LANE0 = 16'h03C0; + parameter [15:0] RX_AEQ_VAL0_LANE1 = 16'h03C0; + parameter [15:0] RX_AEQ_VAL0_LANE2 = 16'h03C0; + parameter [15:0] RX_AEQ_VAL0_LANE3 = 16'h03C0; + parameter [15:0] RX_AEQ_VAL1_LANE0 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE1 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE2 = 16'h0000; + parameter [15:0] RX_AEQ_VAL1_LANE3 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE0 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE1 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE2 = 16'h0000; + parameter [15:0] RX_AGC_CTRL_LANE3 = 16'h0000; + parameter [15:0] RX_CDR_CTRL0_LANE0 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE1 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE2 = 16'h0005; + parameter [15:0] RX_CDR_CTRL0_LANE3 = 16'h0005; + parameter [15:0] RX_CDR_CTRL1_LANE0 = 16'h4200; + parameter [15:0] RX_CDR_CTRL1_LANE1 = 16'h4200; + parameter [15:0] RX_CDR_CTRL1_LANE2 = 16'h4200; + parameter [15:0] RX_CDR_CTRL1_LANE3 = 16'h4200; + parameter [15:0] RX_CDR_CTRL2_LANE0 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE1 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE2 = 16'h2000; + parameter [15:0] RX_CDR_CTRL2_LANE3 = 16'h2000; + parameter [15:0] RX_CFG0_LANE0 = 16'h0500; + parameter [15:0] RX_CFG0_LANE1 = 16'h0500; + parameter [15:0] RX_CFG0_LANE2 = 16'h0500; + parameter [15:0] RX_CFG0_LANE3 = 16'h0500; + parameter [15:0] RX_CFG1_LANE0 = 16'h821F; + parameter [15:0] RX_CFG1_LANE1 = 16'h821F; + parameter [15:0] RX_CFG1_LANE2 = 16'h821F; + parameter [15:0] RX_CFG1_LANE3 = 16'h821F; + parameter [15:0] RX_CFG2_LANE0 = 16'h1001; + parameter [15:0] RX_CFG2_LANE1 = 16'h1001; + parameter [15:0] RX_CFG2_LANE2 = 16'h1001; + parameter [15:0] RX_CFG2_LANE3 = 16'h1001; + parameter [15:0] RX_CTLE_CTRL_LANE0 = 16'h008F; + parameter [15:0] RX_CTLE_CTRL_LANE1 = 16'h008F; + parameter [15:0] RX_CTLE_CTRL_LANE2 = 16'h008F; + parameter [15:0] RX_CTLE_CTRL_LANE3 = 16'h008F; + parameter [15:0] RX_CTRL_OVRD_LANE0 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE1 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE2 = 16'h000C; + parameter [15:0] RX_CTRL_OVRD_LANE3 = 16'h000C; + parameter integer RX_FABRIC_WIDTH0 = 6466; + parameter integer RX_FABRIC_WIDTH1 = 6466; + parameter integer RX_FABRIC_WIDTH2 = 6466; + parameter integer RX_FABRIC_WIDTH3 = 6466; + parameter [15:0] RX_LOOP_CTRL_LANE0 = 16'h007F; + parameter [15:0] RX_LOOP_CTRL_LANE1 = 16'h007F; + parameter [15:0] RX_LOOP_CTRL_LANE2 = 16'h007F; + parameter [15:0] RX_LOOP_CTRL_LANE3 = 16'h007F; + parameter [15:0] RX_MVAL0_LANE0 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE1 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE2 = 16'h0000; + parameter [15:0] RX_MVAL0_LANE3 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE0 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE1 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE2 = 16'h0000; + parameter [15:0] RX_MVAL1_LANE3 = 16'h0000; + parameter [15:0] RX_P0S_CTRL = 16'h1206; + parameter [15:0] RX_P0_CTRL = 16'h11F0; + parameter [15:0] RX_P1_CTRL = 16'h120F; + parameter [15:0] RX_P2_CTRL = 16'h0E0F; + parameter [15:0] RX_PI_CTRL0 = 16'hD2F0; + parameter [15:0] RX_PI_CTRL1 = 16'h0080; + parameter integer SIM_GTHRESET_SPEEDUP = 1; + parameter SIM_VERSION = "1.0"; + parameter [15:0] SLICE_CFG = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_0_LANE01 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_0_LANE23 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_1_LANE01 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_1_LANE23 = 16'h0000; + parameter [15:0] SLICE_NOISE_CTRL_2_LANE01 = 16'h7FFF; + parameter [15:0] SLICE_NOISE_CTRL_2_LANE23 = 16'h7FFF; + parameter [15:0] SLICE_TX_RESET_LANE01 = 16'h0000; + parameter [15:0] SLICE_TX_RESET_LANE23 = 16'h0000; + parameter [15:0] TERM_CTRL_LANE0 = 16'h5007; + parameter [15:0] TERM_CTRL_LANE1 = 16'h5007; + parameter [15:0] TERM_CTRL_LANE2 = 16'h5007; + parameter [15:0] TERM_CTRL_LANE3 = 16'h5007; + parameter [15:0] TX_CFG0_LANE0 = 16'h203D; + parameter [15:0] TX_CFG0_LANE1 = 16'h203D; + parameter [15:0] TX_CFG0_LANE2 = 16'h203D; + parameter [15:0] TX_CFG0_LANE3 = 16'h203D; + parameter [15:0] TX_CFG1_LANE0 = 16'h0F00; + parameter [15:0] TX_CFG1_LANE1 = 16'h0F00; + parameter [15:0] TX_CFG1_LANE2 = 16'h0F00; + parameter [15:0] TX_CFG1_LANE3 = 16'h0F00; + parameter [15:0] TX_CFG2_LANE0 = 16'h0081; + parameter [15:0] TX_CFG2_LANE1 = 16'h0081; + parameter [15:0] TX_CFG2_LANE2 = 16'h0081; + parameter [15:0] TX_CFG2_LANE3 = 16'h0081; + parameter [15:0] TX_CLK_SEL0_LANE0 = 16'h2121; + parameter [15:0] TX_CLK_SEL0_LANE1 = 16'h2121; + parameter [15:0] TX_CLK_SEL0_LANE2 = 16'h2121; + parameter [15:0] TX_CLK_SEL0_LANE3 = 16'h2121; + parameter [15:0] TX_CLK_SEL1_LANE0 = 16'h2121; + parameter [15:0] TX_CLK_SEL1_LANE1 = 16'h2121; + parameter [15:0] TX_CLK_SEL1_LANE2 = 16'h2121; + parameter [15:0] TX_CLK_SEL1_LANE3 = 16'h2121; + parameter [15:0] TX_DISABLE_LANE0 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE1 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE2 = 16'h0000; + parameter [15:0] TX_DISABLE_LANE3 = 16'h0000; + parameter integer TX_FABRIC_WIDTH0 = 6466; + parameter integer TX_FABRIC_WIDTH1 = 6466; + parameter integer TX_FABRIC_WIDTH2 = 6466; + parameter integer TX_FABRIC_WIDTH3 = 6466; + parameter [15:0] TX_P0P0S_CTRL = 16'h060C; + parameter [15:0] TX_P1P2_CTRL = 16'h0C39; + parameter [15:0] TX_PREEMPH_LANE0 = 16'h00A1; + parameter [15:0] TX_PREEMPH_LANE1 = 16'h00A1; + parameter [15:0] TX_PREEMPH_LANE2 = 16'h00A1; + parameter [15:0] TX_PREEMPH_LANE3 = 16'h00A1; + parameter [15:0] TX_PWR_RATE_OVRD_LANE0 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE1 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE2 = 16'h0060; + parameter [15:0] TX_PWR_RATE_OVRD_LANE3 = 16'h0060; + output DRDY; + output GTHINITDONE; + output MGMTPCSRDACK; + output RXCTRLACK0; + output RXCTRLACK1; + output RXCTRLACK2; + output RXCTRLACK3; + output RXDATATAP0; + output RXDATATAP1; + output RXDATATAP2; + output RXDATATAP3; + output RXPCSCLKSMPL0; + output RXPCSCLKSMPL1; + output RXPCSCLKSMPL2; + output RXPCSCLKSMPL3; + output RXUSERCLKOUT0; + output RXUSERCLKOUT1; + output RXUSERCLKOUT2; + output RXUSERCLKOUT3; + output TSTPATH; + output TSTREFCLKFAB; + output TSTREFCLKOUT; + output TXCTRLACK0; + output TXCTRLACK1; + output TXCTRLACK2; + output TXCTRLACK3; + output TXDATATAP10; + output TXDATATAP11; + output TXDATATAP12; + output TXDATATAP13; + output TXDATATAP20; + output TXDATATAP21; + output TXDATATAP22; + output TXDATATAP23; + output TXN0; + output TXN1; + output TXN2; + output TXN3; + output TXP0; + output TXP1; + output TXP2; + output TXP3; + output TXPCSCLKSMPL0; + output TXPCSCLKSMPL1; + output TXPCSCLKSMPL2; + output TXPCSCLKSMPL3; + output TXUSERCLKOUT0; + output TXUSERCLKOUT1; + output TXUSERCLKOUT2; + output TXUSERCLKOUT3; + output [15:0] DRPDO; + output [15:0] MGMTPCSRDDATA; + output [63:0] RXDATA0; + output [63:0] RXDATA1; + output [63:0] RXDATA2; + output [63:0] RXDATA3; + output [7:0] RXCODEERR0; + output [7:0] RXCODEERR1; + output [7:0] RXCODEERR2; + output [7:0] RXCODEERR3; + output [7:0] RXCTRL0; + output [7:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [7:0] RXDISPERR0; + output [7:0] RXDISPERR1; + output [7:0] RXDISPERR2; + output [7:0] RXDISPERR3; + output [7:0] RXVALID0; + output [7:0] RXVALID1; + output [7:0] RXVALID2; + output [7:0] RXVALID3; + input DCLK; + input DEN; + input DFETRAINCTRL0; + input DFETRAINCTRL1; + input DFETRAINCTRL2; + input DFETRAINCTRL3; + input DISABLEDRP; + input DWE; + input GTHINIT; + input GTHRESET; + input GTHX2LANE01; + input GTHX2LANE23; + input GTHX4LANE; + input MGMTPCSREGRD; + input MGMTPCSREGWR; + input POWERDOWN0; + input POWERDOWN1; + input POWERDOWN2; + input POWERDOWN3; + input REFCLK; + input RXBUFRESET0; + input RXBUFRESET1; + input RXBUFRESET2; + input RXBUFRESET3; + input RXENCOMMADET0; + input RXENCOMMADET1; + input RXENCOMMADET2; + input RXENCOMMADET3; + input RXN0; + input RXN1; + input RXN2; + input RXN3; + input RXP0; + input RXP1; + input RXP2; + input RXP3; + input RXPOLARITY0; + input RXPOLARITY1; + input RXPOLARITY2; + input RXPOLARITY3; + input RXSLIP0; + input RXSLIP1; + input RXSLIP2; + input RXSLIP3; + input RXUSERCLKIN0; + input RXUSERCLKIN1; + input RXUSERCLKIN2; + input RXUSERCLKIN3; + input TXBUFRESET0; + input TXBUFRESET1; + input TXBUFRESET2; + input TXBUFRESET3; + input TXDEEMPH0; + input TXDEEMPH1; + input TXDEEMPH2; + input TXDEEMPH3; + input TXUSERCLKIN0; + input TXUSERCLKIN1; + input TXUSERCLKIN2; + input TXUSERCLKIN3; + input [15:0] DADDR; + input [15:0] DI; + input [15:0] MGMTPCSREGADDR; + input [15:0] MGMTPCSWRDATA; + input [1:0] RXPOWERDOWN0; + input [1:0] RXPOWERDOWN1; + input [1:0] RXPOWERDOWN2; + input [1:0] RXPOWERDOWN3; + input [1:0] RXRATE0; + input [1:0] RXRATE1; + input [1:0] RXRATE2; + input [1:0] RXRATE3; + input [1:0] TXPOWERDOWN0; + input [1:0] TXPOWERDOWN1; + input [1:0] TXPOWERDOWN2; + input [1:0] TXPOWERDOWN3; + input [1:0] TXRATE0; + input [1:0] TXRATE1; + input [1:0] TXRATE2; + input [1:0] TXRATE3; + input [2:0] PLLREFCLKSEL; + input [2:0] SAMPLERATE0; + input [2:0] SAMPLERATE1; + input [2:0] SAMPLERATE2; + input [2:0] SAMPLERATE3; + input [2:0] TXMARGIN0; + input [2:0] TXMARGIN1; + input [2:0] TXMARGIN2; + input [2:0] TXMARGIN3; + input [3:0] MGMTPCSLANESEL; + input [4:0] MGMTPCSMMDADDR; + input [5:0] PLLPCSCLKDIV; + input [63:0] TXDATA0; + input [63:0] TXDATA1; + input [63:0] TXDATA2; + input [63:0] TXDATA3; + input [7:0] TXCTRL0; + input [7:0] TXCTRL1; + input [7:0] TXCTRL2; + input [7:0] TXCTRL3; + input [7:0] TXDATAMSB0; + input [7:0] TXDATAMSB1; + input [7:0] TXDATAMSB2; + input [7:0] TXDATAMSB3; +endmodule + +module GTXE1 (...); + parameter AC_CAP_DIS = "TRUE"; + parameter integer ALIGN_COMMA_WORD = 1; + parameter [1:0] BGTEST_CFG = 2'b00; + parameter [16:0] BIAS_CFG = 17'h00000; + parameter [4:0] CDR_PH_ADJ_TIME = 5'b10100; + parameter integer CHAN_BOND_1_MAX_SKEW = 7; + parameter integer CHAN_BOND_2_MAX_SKEW = 1; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0001001010; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0110111100; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100111100; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0110111100; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100111100; + parameter [4:0] CHAN_BOND_SEQ_2_CFG = 5'b00000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter integer CLK_COR_ADJ_LEN = 1; + parameter integer CLK_COR_DET_LEN = 1; + parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter [1:0] CM_TRIM = 2'b01; + parameter [9:0] COMMA_10B_ENABLE = 10'b1111111111; + parameter COMMA_DOUBLE = "FALSE"; + parameter [3:0] COM_BURST_VAL = 4'b1111; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [4:0] DFE_CAL_TIME = 5'b01100; + parameter [7:0] DFE_CFG = 8'b00011011; + parameter [2:0] GEARBOX_ENDEC = 3'b000; + parameter GEN_RXUSRCLK = "TRUE"; + parameter GEN_TXUSRCLK = "TRUE"; + parameter GTX_CFG_PWRUP = "TRUE"; + parameter [9:0] MCOMMA_10B_VALUE = 10'b1010000011; + parameter MCOMMA_DETECT = "TRUE"; + parameter [2:0] OOBDETECT_THRESHOLD = 3'b011; + parameter PCI_EXPRESS_MODE = "FALSE"; + parameter [9:0] PCOMMA_10B_VALUE = 10'b0101111100; + parameter PCOMMA_DETECT = "TRUE"; + parameter PMA_CAS_CLK_EN = "FALSE"; + parameter [26:0] PMA_CDR_SCAN = 27'h640404C; + parameter [75:0] PMA_CFG = 76'h0040000040000000003; + parameter [6:0] PMA_RXSYNC_CFG = 7'h00; + parameter [24:0] PMA_RX_CFG = 25'h05CE048; + parameter [19:0] PMA_TX_CFG = 20'h00082; + parameter [9:0] POWER_SAVE = 10'b0000110100; + parameter RCV_TERM_GND = "FALSE"; + parameter RCV_TERM_VTTRX = "TRUE"; + parameter RXGEARBOX_USE = "FALSE"; + parameter [23:0] RXPLL_COM_CFG = 24'h21680A; + parameter [7:0] RXPLL_CP_CFG = 8'h00; + parameter integer RXPLL_DIVSEL45_FB = 5; + parameter integer RXPLL_DIVSEL_FB = 2; + parameter integer RXPLL_DIVSEL_OUT = 1; + parameter integer RXPLL_DIVSEL_REF = 1; + parameter [2:0] RXPLL_LKDET_CFG = 3'b111; + parameter [0:0] RXPRBSERR_LOOPBACK = 1'b0; + parameter RXRECCLK_CTRL = "RXRECCLKPCS"; + parameter [9:0] RXRECCLK_DLY = 10'b0000000000; + parameter [15:0] RXUSRCLK_DLY = 16'h0000; + parameter RX_BUFFER_USE = "TRUE"; + parameter integer RX_CLK25_DIVIDER = 6; + parameter integer RX_DATA_WIDTH = 20; + parameter RX_DECODE_SEQ_MATCH = "TRUE"; + parameter [3:0] RX_DLYALIGN_CTRINC = 4'b0100; + parameter [4:0] RX_DLYALIGN_EDGESET = 5'b00110; + parameter [3:0] RX_DLYALIGN_LPFINC = 4'b0111; + parameter [2:0] RX_DLYALIGN_MONSEL = 3'b000; + parameter [7:0] RX_DLYALIGN_OVRDSETTING = 8'b00000000; + parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; + parameter RX_EN_IDLE_HOLD_DFE = "TRUE"; + parameter RX_EN_IDLE_RESET_BUF = "TRUE"; + parameter RX_EN_IDLE_RESET_FR = "TRUE"; + parameter RX_EN_IDLE_RESET_PH = "TRUE"; + parameter RX_EN_MODE_RESET_BUF = "TRUE"; + parameter RX_EN_RATE_RESET_BUF = "TRUE"; + parameter RX_EN_REALIGN_RESET_BUF = "FALSE"; + parameter RX_EN_REALIGN_RESET_BUF2 = "FALSE"; + parameter [7:0] RX_EYE_OFFSET = 8'h4C; + parameter [1:0] RX_EYE_SCANMODE = 2'b00; + parameter RX_FIFO_ADDR_MODE = "FULL"; + parameter [3:0] RX_IDLE_HI_CNT = 4'b1000; + parameter [3:0] RX_IDLE_LO_CNT = 4'b0000; + parameter RX_LOSS_OF_SYNC_FSM = "FALSE"; + parameter integer RX_LOS_INVALID_INCR = 1; + parameter integer RX_LOS_THRESHOLD = 4; + parameter RX_OVERSAMPLE_MODE = "FALSE"; + parameter integer RX_SLIDE_AUTO_WAIT = 5; + parameter RX_SLIDE_MODE = "OFF"; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COMSAS = 52; + parameter integer SAS_MIN_COMSAS = 40; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter [2:0] SATA_IDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 7; + parameter integer SATA_MAX_INIT = 22; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter integer SIM_GTXRESET_SPEEDUP = 1; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter [2:0] SIM_RXREFCLK_SOURCE = 3'b000; + parameter [2:0] SIM_TXREFCLK_SOURCE = 3'b000; + parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; + parameter SIM_VERSION = "2.0"; + parameter [4:0] TERMINATION_CTRL = 5'b10100; + parameter TERMINATION_OVRD = "FALSE"; + parameter [11:0] TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] TRANS_TIME_NON_P2 = 8'h19; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [9:0] TRANS_TIME_TO_P2 = 10'h064; + parameter [31:0] TST_ATTR = 32'h00000000; + parameter TXDRIVE_LOOPBACK_HIZ = "FALSE"; + parameter TXDRIVE_LOOPBACK_PD = "FALSE"; + parameter TXGEARBOX_USE = "FALSE"; + parameter TXOUTCLK_CTRL = "TXOUTCLKPCS"; + parameter [9:0] TXOUTCLK_DLY = 10'b0000000000; + parameter [23:0] TXPLL_COM_CFG = 24'h21680A; + parameter [7:0] TXPLL_CP_CFG = 8'h00; + parameter integer TXPLL_DIVSEL45_FB = 5; + parameter integer TXPLL_DIVSEL_FB = 2; + parameter integer TXPLL_DIVSEL_OUT = 1; + parameter integer TXPLL_DIVSEL_REF = 1; + parameter [2:0] TXPLL_LKDET_CFG = 3'b111; + parameter [1:0] TXPLL_SATA = 2'b00; + parameter TX_BUFFER_USE = "TRUE"; + parameter [5:0] TX_BYTECLK_CFG = 6'h00; + parameter integer TX_CLK25_DIVIDER = 6; + parameter TX_CLK_SOURCE = "RXPLL"; + parameter integer TX_DATA_WIDTH = 20; + parameter [4:0] TX_DEEMPH_0 = 5'b11010; + parameter [4:0] TX_DEEMPH_1 = 5'b10000; + parameter [13:0] TX_DETECT_RX_CFG = 14'h1832; + parameter [3:0] TX_DLYALIGN_CTRINC = 4'b0100; + parameter [3:0] TX_DLYALIGN_LPFINC = 4'b0110; + parameter [2:0] TX_DLYALIGN_MONSEL = 3'b000; + parameter [7:0] TX_DLYALIGN_OVRDSETTING = 8'b10000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter TX_EN_RATE_RESET_BUF = "TRUE"; + parameter [2:0] TX_IDLE_ASSERT_DELAY = 3'b100; + parameter [2:0] TX_IDLE_DEASSERT_DELAY = 3'b010; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter TX_OVERSAMPLE_MODE = "FALSE"; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [1:0] TX_TDCC_CFG = 2'b11; + parameter [5:0] TX_USRCLK_CFG = 6'h00; + parameter TX_XCLK_SEL = "TXUSR"; + output COMFINISH; + output COMINITDET; + output COMSASDET; + output COMWAKEDET; + output DRDY; + output PHYSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMMADET; + output RXDATAVALID; + output RXELECIDLE; + output RXHEADERVALID; + output RXOVERSAMPLEERR; + output RXPLLLKDET; + output RXPRBSERR; + output RXRATEDONE; + output RXRECCLK; + output RXRECCLKPCS; + output RXRESETDONE; + output RXSTARTOFSEQ; + output RXVALID; + output TXGEARBOXREADY; + output TXN; + output TXOUTCLK; + output TXOUTCLKPCS; + output TXP; + output TXPLLLKDET; + output TXRATEDONE; + output TXRESETDONE; + output [15:0] DRPDO; + output [1:0] MGTREFCLKFAB; + output [1:0] RXLOSSOFSYNC; + output [1:0] TXBUFSTATUS; + output [2:0] DFESENSCAL; + output [2:0] RXBUFSTATUS; + output [2:0] RXCLKCORCNT; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [31:0] RXDATA; + output [3:0] DFETAP3MONITOR; + output [3:0] DFETAP4MONITOR; + output [3:0] RXCHARISCOMMA; + output [3:0] RXCHARISK; + output [3:0] RXCHBONDO; + output [3:0] RXDISPERR; + output [3:0] RXNOTINTABLE; + output [3:0] RXRUNDISP; + output [3:0] TXKERR; + output [3:0] TXRUNDISP; + output [4:0] DFEEYEDACMON; + output [4:0] DFETAP1MONITOR; + output [4:0] DFETAP2MONITOR; + output [5:0] DFECLKDLYADJMON; + output [7:0] RXDLYALIGNMONITOR; + output [7:0] TXDLYALIGNMONITOR; + output [9:0] TSTOUT; + input DCLK; + input DEN; + input DFEDLYOVRD; + input DFETAPOVRD; + input DWE; + input GATERXELECIDLE; + input GREFCLKRX; + input GREFCLKTX; + input GTXRXRESET; + input GTXTXRESET; + input IGNORESIGDET; + input PERFCLKRX; + input PERFCLKTX; + input PLLRXRESET; + input PLLTXRESET; + input PRBSCNTRESET; + input RXBUFRESET; + input RXCDRRESET; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETUSE; + input RXDEC8B10BUSE; + input RXDLYALIGNDISABLE; + input RXDLYALIGNMONENB; + input RXDLYALIGNOVERRIDE; + input RXDLYALIGNRESET; + input RXDLYALIGNSWPPRECURB; + input RXDLYALIGNUPDSW; + input RXENCHANSYNC; + input RXENMCOMMAALIGN; + input RXENPCOMMAALIGN; + input RXENPMAPHASEALIGN; + input RXENSAMPLEALIGN; + input RXGEARBOXSLIP; + input RXN; + input RXP; + input RXPLLLKDETEN; + input RXPLLPOWERDOWN; + input RXPMASETPHASE; + input RXPOLARITY; + input RXRESET; + input RXSLIDE; + input RXUSRCLK2; + input RXUSRCLK; + input TSTCLK0; + input TSTCLK1; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDLYALIGNDISABLE; + input TXDLYALIGNMONENB; + input TXDLYALIGNOVERRIDE; + input TXDLYALIGNRESET; + input TXDLYALIGNUPDSW; + input TXELECIDLE; + input TXENC8B10BUSE; + input TXENPMAPHASEALIGN; + input TXINHIBIT; + input TXPDOWNASYNCH; + input TXPLLLKDETEN; + input TXPLLPOWERDOWN; + input TXPMASETPHASE; + input TXPOLARITY; + input TXPRBSFORCEERR; + input TXRESET; + input TXSTARTSEQ; + input TXSWING; + input TXUSRCLK2; + input TXUSRCLK; + input USRCODEERR; + input [12:0] GTXTEST; + input [15:0] DI; + input [19:0] TSTIN; + input [1:0] MGTREFCLKRX; + input [1:0] MGTREFCLKTX; + input [1:0] NORTHREFCLKRX; + input [1:0] NORTHREFCLKTX; + input [1:0] RXPOWERDOWN; + input [1:0] RXRATE; + input [1:0] SOUTHREFCLKRX; + input [1:0] SOUTHREFCLKTX; + input [1:0] TXPOWERDOWN; + input [1:0] TXRATE; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXENPRBSTST; + input [2:0] RXPLLREFSELDY; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXENPRBSTST; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXPLLREFSELDY; + input [31:0] TXDATA; + input [3:0] DFETAP3; + input [3:0] DFETAP4; + input [3:0] RXCHBONDI; + input [3:0] TXBYPASS8B10B; + input [3:0] TXCHARDISPMODE; + input [3:0] TXCHARDISPVAL; + input [3:0] TXCHARISK; + input [3:0] TXDIFFCTRL; + input [3:0] TXPREEMPHASIS; + input [4:0] DFETAP1; + input [4:0] DFETAP2; + input [4:0] TXPOSTEMPHASIS; + input [5:0] DFECLKDLYADJ; + input [6:0] TXSEQUENCE; + input [7:0] DADDR; + input [9:0] RXEQMIX; +endmodule + +module IBUFDS_GTXE1 (...); + parameter CLKCM_CFG = "TRUE"; + parameter CLKRCV_TRST = "TRUE"; + parameter [9:0] REFCLKOUT_DLY = 10'b0000000000; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFDS_GTHE1 (...); + output O; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module GTHE2_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [19:0] ADAPT_CFG0 = 20'h00C10; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [41:0] CFOK_CFG = 42'h24800040E80; + parameter [5:0] CFOK_CFG2 = 6'b100000; + parameter [5:0] CFOK_CFG3 = 6'b100000; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter [28:0] CPLL_CFG = 29'h00BC07DC; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 5; + parameter [23:0] CPLL_INIT_CFG = 24'h00001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "TRUE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; + parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; + parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [0:0] LOOPBACK_CFG = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [31:0] PMA_RSV = 32'b00000000000000000000000010000000; + parameter [31:0] PMA_RSV2 = 32'b00011100000000000000000000001010; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [14:0] PMA_RSV4 = 15'b000000000001000; + parameter [3:0] PMA_RSV5 = 4'b0000; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [82:0] RXCDR_CFG = 83'h0002007FE2000C208001A; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [8:0] RXDLY_LCFG = 9'h030; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [13:0] RXLPM_HF_CFG = 14'b00001000000000; + parameter [17:0] RXLPM_LF_CFG = 18'b001001000000000000; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084020; + parameter [23:0] RXPH_CFG = 24'hC00002; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] RXPI_CFG0 = 2'b00; + parameter [1:0] RXPI_CFG1 = 2'b00; + parameter [1:0] RXPI_CFG2 = 2'b00; + parameter [1:0] RXPI_CFG3 = 2'b00; + parameter [0:0] RXPI_CFG4 = 1'b0; + parameter [0:0] RXPI_CFG5 = 1'b0; + parameter [2:0] RXPI_CFG6 = 3'b100; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [23:0] RX_BIAS_CFG = 24'b000011000000000000010000; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_PD = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [3:0] RX_CM_TRIM = 4'b0100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; + parameter [0:0] RX_DFELPM_CFG1 = 1'b0; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010; + parameter [3:0] RX_DFE_AGC_CFG2 = 4'b0000; + parameter [0:0] RX_DFE_AGC_OVRDEN = 1'b1; + parameter [22:0] RX_DFE_GAIN_CFG = 23'h0020C0; + parameter [11:0] RX_DFE_H2_CFG = 12'b000000000000; + parameter [11:0] RX_DFE_H3_CFG = 12'b000001000000; + parameter [10:0] RX_DFE_H4_CFG = 11'b00011100000; + parameter [10:0] RX_DFE_H5_CFG = 11'b00011100000; + parameter [10:0] RX_DFE_H6_CFG = 11'b00000100000; + parameter [10:0] RX_DFE_H7_CFG = 11'b00000100000; + parameter [32:0] RX_DFE_KL_CFG = 33'b000000000000000000000001100010000; + parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; + parameter [3:0] RX_DFE_KL_LPM_KH_CFG2 = 4'b0010; + parameter [0:0] RX_DFE_KL_LPM_KH_OVRDEN = 1'b1; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b10; + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; + parameter [3:0] RX_DFE_KL_LPM_KL_CFG2 = 4'b0010; + parameter [0:0] RX_DFE_KL_LPM_KL_OVRDEN = 1'b1; + parameter [15:0] RX_DFE_LPM_CFG = 16'h0080; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter [53:0] RX_DFE_ST_CFG = 54'h00E100000C003F; + parameter [16:0] RX_DFE_UT_CFG = 17'b00011100000000000; + parameter [16:0] RX_DFE_VP_CFG = 17'b00011101010100011; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter integer RX_INT_DATAWIDTH = 0; + parameter [12:0] RX_OS_CFG = 13'b0000010000000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "1.1"; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [8:0] TXDLY_LCFG = 9'h030; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter [0:0] TXOOB_CFG = 1'b0; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084020; + parameter [15:0] TXPH_CFG = 16'h0780; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b0; + parameter [2:0] TXPI_CFG5 = 3'b100; + parameter [0:0] TXPI_GREY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_PD = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter integer TX_INT_DATAWIDTH = 0; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [16:0] TX_RXDETECT_PRECHARGE_TIME = 17'h00000; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output DRPRDY; + output EYESCANDATAERROR; + output GTHTXN; + output GTHTXP; + output GTREFCLKMONITOR; + output PHYSTATUS; + output RSOSINTDONE; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDFESLIDETAPSTARTED; + output RXDFESLIDETAPSTROBEDONE; + output RXDFESLIDETAPSTROBESTARTED; + output RXDFESTADAPTDONE; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPMARESETDONE; + output RXPRBSERR; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRESETDONE; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + output [14:0] DMONITOROUT; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] RXDATAVALID; + output [1:0] RXHEADERVALID; + output [1:0] RXSTARTOFSEQ; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXSTATUS; + output [4:0] RXCHBONDO; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + output [5:0] RXHEADER; + output [63:0] RXDATA; + output [6:0] RXMONITOROUT; + output [7:0] RXCHARISCOMMA; + output [7:0] RXCHARISK; + output [7:0] RXDISPERR; + output [7:0] RXNOTINTABLE; + input CFGRESET; + (* invertible_pin = "IS_CLKRSVD0_INVERTED" *) + input CLKRSVD0; + (* invertible_pin = "IS_CLKRSVD1_INVERTED" *) + input CLKRSVD1; + (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *) + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input CPLLRESET; + input DMONFIFORESET; + (* invertible_pin = "IS_DMONITORCLK_INVERTED" *) + input DMONITORCLK; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) + input GTGREFCLK; + input GTHRXN; + input GTHRXP; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input QPLLCLK; + input QPLLREFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFECM1EN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFESLIDETAPADAPTEN; + input RXDFESLIDETAPHOLD; + input RXDFESLIDETAPINITOVRDEN; + input RXDFESLIDETAPONLYADAPTEN; + input RXDFESLIDETAPOVRDEN; + input RXDFESLIDETAPSTROBE; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTNTRLEN; + input RXOSINTOVRDEN; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXQPIEN; + input RXRATEMODE; + input RXSLIDE; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input RXUSERRDY; + (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) + input RXUSRCLK2; + (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) + input RXUSRCLK; + input SETERRSTATUS; + (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *) + input SIGVALIDCLK; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXQPIBIASEN; + input TXQPISTRONGPDOWN; + input TXQPIWEAKPUP; + input TXRATEMODE; + input TXSTARTSEQ; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input TXUSERRDY; + (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) + input TXUSRCLK2; + (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) + input TXUSRCLK; + input [13:0] RXADAPTSELTEST; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXMONITORSEL; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] CPLLREFCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [3:0] RXOSINTCFG; + input [3:0] RXOSINTID0; + input [3:0] TXDIFFCTRL; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN; + input [4:0] RXCHBONDI; + input [4:0] RXDFEAGCTRL; + input [4:0] RXDFESLIDETAP; + input [4:0] TXPIPPMSTEPSIZE; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [5:0] RXDFESLIDETAPID; + input [63:0] TXDATA; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [7:0] TX8B10BBYPASS; + input [7:0] TXCHARDISPMODE; + input [7:0] TXCHARDISPVAL; + input [7:0] TXCHARISK; + input [8:0] DRPADDR; +endmodule + +module GTHE2_COMMON (...); + parameter [63:0] BIAS_CFG = 64'h0000040000001000; + parameter [31:0] COMMON_CFG = 32'h0000001C; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] QPLL_CFG = 27'h0480181; + parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; + parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; + parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; + parameter [9:0] QPLL_CP = 10'b0000011111; + parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; + parameter [9:0] QPLL_FBDIV = 10'b0000000000; + parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; + parameter [23:0] QPLL_INIT_CFG = 24'h000006; + parameter [15:0] QPLL_LOCK_CFG = 16'h01E8; + parameter [3:0] QPLL_LPF = 4'b1111; + parameter integer QPLL_REFCLK_DIV = 2; + parameter [0:0] QPLL_RP_COMP = 1'b0; + parameter [1:0] QPLL_VTRL_RESET = 2'b00; + parameter [1:0] RCAL_CFG = 2'b00; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "1.1"; + output DRPRDY; + output QPLLFBCLKLOST; + output QPLLLOCK; + output QPLLOUTCLK; + output QPLLOUTREFCLK; + output QPLLREFCLKLOST; + output REFCLKOUTMONITOR; + output [15:0] DRPDO; + output [15:0] PMARSVDOUT; + output [7:0] QPLLDMONITOR; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input BGRCALOVRDENB; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *) + input QPLLLOCKDETCLK; + input QPLLLOCKEN; + input QPLLOUTRESET; + input QPLLPD; + input QPLLRESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] QPLLRSVD1; + input [2:0] QPLLREFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] QPLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; +endmodule + +module GTPE2_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000; + parameter [6:0] CFOK_CFG2 = 7'b0100000; + parameter [6:0] CFOK_CFG3 = 7'b0100000; + parameter [0:0] CFOK_CFG4 = 1'b0; + parameter [1:0] CFOK_CFG5 = 2'b00; + parameter [3:0] CFOK_CFG6 = 4'b0000; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter [0:0] CLK_COMMON_SWING = 1'b0; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h010; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; + parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; + parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [0:0] LOOPBACK_CFG = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [0:0] PMA_LOOPBACK_CFG = 1'b0; + parameter [31:0] PMA_RSV = 32'h00000333; + parameter [31:0] PMA_RSV2 = 32'h00002050; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [3:0] PMA_RSV4 = 4'b0000; + parameter [0:0] PMA_RSV5 = 1'b0; + parameter [0:0] PMA_RSV6 = 1'b0; + parameter [0:0] PMA_RSV7 = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXDLY_CFG = 16'h0010; + parameter [8:0] RXDLY_LCFG = 9'h020; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [6:0] RXLPMRESET_TIME = 7'b0001111; + parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0; + parameter [3:0] RXLPM_CFG = 4'b0110; + parameter [0:0] RXLPM_CFG1 = 1'b0; + parameter [0:0] RXLPM_CM_CFG = 1'b0; + parameter [8:0] RXLPM_GC_CFG = 9'b111100010; + parameter [2:0] RXLPM_GC_CFG2 = 3'b001; + parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000; + parameter [4:0] RXLPM_HF_CFG2 = 5'b01010; + parameter [3:0] RXLPM_HF_CFG3 = 4'b0000; + parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0; + parameter [0:0] RXLPM_INCM_CFG = 1'b0; + parameter [0:0] RXLPM_IPCM_CFG = 1'b0; + parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000; + parameter [4:0] RXLPM_LF_CFG2 = 5'b01010; + parameter [2:0] RXLPM_OSINT_CFG = 3'b100; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084000; + parameter [23:0] RXPH_CFG = 24'hC00002; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [2:0] RXPI_CFG0 = 3'b000; + parameter [0:0] RXPI_CFG1 = 1'b0; + parameter [0:0] RXPI_CFG2 = 1'b0; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [3:0] RX_CM_TRIM = 4'b0100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [12:0] RX_OS_CFG = 13'b0001111110000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SATA_PLL_CFG = "VCO_3000MHZ"; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "1.0"; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h0010; + parameter [8:0] TXDLY_LCFG = 9'h020; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter [0:0] TXOOB_CFG = 1'b0; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084000; + parameter [15:0] TXPH_CFG = 16'h0400; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b0; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GREY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_PREDRIVER_MODE = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + output DRPRDY; + output EYESCANDATAERROR; + output GTPTXN; + output GTPTXP; + output PHYSTATUS; + output PMARSVDOUT0; + output PMARSVDOUT1; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXHEADERVALID; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPMARESETDONE; + output RXPRBSERR; + output RXRATEDONE; + output RXRESETDONE; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + output [14:0] DMONITOROUT; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] RXDATAVALID; + output [1:0] RXSTARTOFSEQ; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [31:0] RXDATA; + output [3:0] RXCHARISCOMMA; + output [3:0] RXCHARISK; + output [3:0] RXCHBONDO; + output [3:0] RXDISPERR; + output [3:0] RXNOTINTABLE; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + input CFGRESET; + (* invertible_pin = "IS_CLKRSVD0_INVERTED" *) + input CLKRSVD0; + (* invertible_pin = "IS_CLKRSVD1_INVERTED" *) + input CLKRSVD1; + input DMONFIFORESET; + (* invertible_pin = "IS_DMONITORCLK_INVERTED" *) + input DMONITORCLK; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTPRXN; + input GTPRXP; + input GTRESETSEL; + input GTRXRESET; + input GTTXRESET; + input PLL0CLK; + input PLL0REFCLK; + input PLL1CLK; + input PLL1REFCLK; + input PMARSVDIN0; + input PMARSVDIN1; + input PMARSVDIN2; + input PMARSVDIN3; + input PMARSVDIN4; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFOVRDEN; + input RXLPMOSINTNTRLEN; + input RXLPMRESET; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTNTRLEN; + input RXOSINTOVRDEN; + input RXOSINTPD; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXRATEMODE; + input RXSLIDE; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input RXUSERRDY; + (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) + input RXUSRCLK2; + (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) + input RXUSRCLK; + input SETERRSTATUS; + (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *) + input SIGVALIDCLK; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXRATEMODE; + input TXSTARTSEQ; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input TXUSERRDY; + (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) + input TXUSRCLK2; + (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) + input TXUSRCLK; + input [13:0] RXADAPTSELTEST; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [31:0] TXDATA; + input [3:0] RXCHBONDI; + input [3:0] RXOSINTCFG; + input [3:0] RXOSINTID0; + input [3:0] TX8B10BBYPASS; + input [3:0] TXCHARDISPMODE; + input [3:0] TXCHARDISPVAL; + input [3:0] TXCHARISK; + input [3:0] TXDIFFCTRL; + input [4:0] TXPIPPMSTEPSIZE; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [8:0] DRPADDR; +endmodule + +module GTPE2_COMMON (...); + parameter [63:0] BIAS_CFG = 64'h0000000000000000; + parameter [31:0] COMMON_CFG = 32'h00000000; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0; + parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] PLL0_CFG = 27'h01F03DC; + parameter [0:0] PLL0_DMON_CFG = 1'b0; + parameter integer PLL0_FBDIV = 4; + parameter integer PLL0_FBDIV_45 = 5; + parameter [23:0] PLL0_INIT_CFG = 24'h00001E; + parameter [8:0] PLL0_LOCK_CFG = 9'h1E8; + parameter integer PLL0_REFCLK_DIV = 1; + parameter [26:0] PLL1_CFG = 27'h01F03DC; + parameter [0:0] PLL1_DMON_CFG = 1'b0; + parameter integer PLL1_FBDIV = 4; + parameter integer PLL1_FBDIV_45 = 5; + parameter [23:0] PLL1_INIT_CFG = 24'h00001E; + parameter [8:0] PLL1_LOCK_CFG = 9'h1E8; + parameter integer PLL1_REFCLK_DIV = 1; + parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [2:0] SIM_PLL0REFCLK_SEL = 3'b001; + parameter [2:0] SIM_PLL1REFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "1.0"; + output DRPRDY; + output PLL0FBCLKLOST; + output PLL0LOCK; + output PLL0OUTCLK; + output PLL0OUTREFCLK; + output PLL0REFCLKLOST; + output PLL1FBCLKLOST; + output PLL1LOCK; + output PLL1OUTCLK; + output PLL1OUTREFCLK; + output PLL1REFCLKLOST; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [15:0] DRPDO; + output [15:0] PMARSVDOUT; + output [7:0] DMONITOROUT; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input BGRCALOVRDENB; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + input GTEASTREFCLK0; + input GTEASTREFCLK1; + (* invertible_pin = "IS_GTGREFCLK0_INVERTED" *) + input GTGREFCLK0; + (* invertible_pin = "IS_GTGREFCLK1_INVERTED" *) + input GTGREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTWESTREFCLK0; + input GTWESTREFCLK1; + (* invertible_pin = "IS_PLL0LOCKDETCLK_INVERTED" *) + input PLL0LOCKDETCLK; + input PLL0LOCKEN; + input PLL0PD; + input PLL0RESET; + (* invertible_pin = "IS_PLL1LOCKDETCLK_INVERTED" *) + input PLL1LOCKDETCLK; + input PLL1LOCKEN; + input PLL1PD; + input PLL1RESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] PLLRSVD1; + input [2:0] PLL0REFCLKSEL; + input [2:0] PLL1REFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] PLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; +endmodule + +module GTXE2_CHANNEL (...); + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 1; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 1; + parameter [23:0] CPLL_CFG = 24'hB007D8; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 5; + parameter [23:0] CPLL_INIT_CFG = 24'h00001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [23:0] DMONITOR_CFG = 24'h000A00; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; + parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; + parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; + parameter [8:0] ES_VERT_OFFSET = 9'b000000000; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [2:0] GEARBOX_MODE = 3'b000; + parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; + parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; + parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; + parameter PCS_PCIE_EN = "FALSE"; + parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [31:0] PMA_RSV = 32'h00000000; + parameter [15:0] PMA_RSV2 = 16'h2050; + parameter [1:0] PMA_RSV3 = 2'b00; + parameter [31:0] PMA_RSV4 = 32'h00000000; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 61; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [71:0] RXCDR_CFG = 72'h0B000023FF20400020; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [5:0] RXCDR_LOCK_CFG = 6'b010101; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [8:0] RXDLY_LCFG = 9'h030; + parameter [15:0] RXDLY_TAP_CFG = 16'h0000; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [13:0] RXLPM_HF_CFG = 14'b00000011110000; + parameter [13:0] RXLPM_LF_CFG = 14'b00000011110000; + parameter [6:0] RXOOB_CFG = 7'b0000110; + parameter integer RXOUT_DIV = 2; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [23:0] RXPHDLY_CFG = 24'h084020; + parameter [23:0] RXPH_CFG = 24'h000000; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [4:0] RXPMARESET_TIME = 5'b00011; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [11:0] RX_BIAS_CFG = 12'b000000000000; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter integer RX_CLK25_DIV = 7; + parameter [0:0] RX_CLKMUX_PD = 1'b1; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [2:0] RX_CM_TRIM = 3'b100; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter [11:0] RX_DEBUG_CFG = 12'b000000000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [22:0] RX_DFE_GAIN_CFG = 23'h180E0F; + parameter [11:0] RX_DFE_H2_CFG = 12'b000111100000; + parameter [11:0] RX_DFE_H3_CFG = 12'b000111100000; + parameter [10:0] RX_DFE_H4_CFG = 11'b00011110000; + parameter [10:0] RX_DFE_H5_CFG = 11'b00011110000; + parameter [12:0] RX_DFE_KL_CFG = 13'b0001111110000; + parameter [31:0] RX_DFE_KL_CFG2 = 32'h3008E56A; + parameter [15:0] RX_DFE_LPM_CFG = 16'h0904; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter [16:0] RX_DFE_UT_CFG = 17'b00111111000000000; + parameter [16:0] RX_DFE_VP_CFG = 17'b00011111100000000; + parameter [12:0] RX_DFE_XYD_CFG = 13'b0000000010000; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter integer RX_INT_DATAWIDTH = 0; + parameter [12:0] RX_OS_CFG = 13'b0001111110000; + parameter integer RX_SIG_VALID_DLY = 10; + parameter RX_XCLK_SEL = "RXREC"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; + parameter SIM_VERSION = "4.0"; + parameter [4:0] TERM_RCAL_CFG = 5'b10000; + parameter [0:0] TERM_RCAL_OVRD = 1'b0; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [31:0] TST_RSV = 32'h00000000; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [8:0] TXDLY_LCFG = 9'h030; + parameter [15:0] TXDLY_TAP_CFG = 16'h0000; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 2; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [23:0] TXPHDLY_CFG = 24'h084020; + parameter [15:0] TXPH_CFG = 16'h0780; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter integer TX_CLK25_DIV = 7; + parameter [0:0] TX_CLKMUX_PD = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [4:0] TX_DEEMPH0 = 5'b00000; + parameter [4:0] TX_DEEMPH1 = 5'b00000; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter integer TX_INT_DATAWIDTH = 0; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [0:0] TX_PREDRIVER_MODE = 1'b0; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h1832; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter TX_XCLK_SEL = "TXUSR"; + parameter [0:0] UCODEER_CLR = 1'b0; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output DRPRDY; + output EYESCANDATAERROR; + output GTREFCLKMONITOR; + output GTXTXN; + output GTXTXP; + output PHYSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output RXHEADERVALID; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPRBSERR; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRESETDONE; + output RXSTARTOFSEQ; + output RXVALID; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXGEARBOXREADY; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output [15:0] DRPDO; + output [15:0] PCSRSVDOUT; + output [1:0] RXCLKCORCNT; + output [1:0] TXBUFSTATUS; + output [2:0] RXBUFSTATUS; + output [2:0] RXHEADER; + output [2:0] RXSTATUS; + output [4:0] RXCHBONDO; + output [4:0] RXPHMONITOR; + output [4:0] RXPHSLIPMONITOR; + output [63:0] RXDATA; + output [6:0] RXMONITOROUT; + output [7:0] DMONITOROUT; + output [7:0] RXCHARISCOMMA; + output [7:0] RXCHARISK; + output [7:0] RXDISPERR; + output [7:0] RXNOTINTABLE; + output [9:0] TSTOUT; + input CFGRESET; + (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *) + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input CPLLRESET; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTXRXN; + input GTXRXP; + input QPLLCLK; + input QPLLREFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input RXDDIEN; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFECM1EN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDFEXYDHOLD; + input RXDFEXYDOVRDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input RXGEARBOXSLIP; + input RXLPMEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXMCOMMAALIGNEN; + input RXOOBRESET; + input RXOSHOLD; + input RXOSOVRDEN; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input RXQPIEN; + input RXSLIDE; + input RXUSERRDY; + (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) + input RXUSRCLK2; + (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) + input RXUSRCLK; + input SETERRSTATUS; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input TXDEEMPH; + input TXDETECTRX; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXINHIBIT; + input TXPCSRESET; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPISOPD; + input TXPMARESET; + input TXPOLARITY; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input TXPRECURSORINV; + input TXQPIBIASEN; + input TXQPISTRONGPDOWN; + input TXQPIWEAKPUP; + input TXSTARTSEQ; + input TXSWING; + input TXUSERRDY; + (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) + input TXUSRCLK2; + (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) + input TXUSRCLK; + input [15:0] DRPDI; + input [15:0] GTRSVD; + input [15:0] PCSRSVDIN; + input [19:0] TSTIN; + input [1:0] RXELECIDLEMODE; + input [1:0] RXMONITORSEL; + input [1:0] RXPD; + input [1:0] RXSYSCLKSEL; + input [1:0] TXPD; + input [1:0] TXSYSCLKSEL; + input [2:0] CPLLREFCLKSEL; + input [2:0] LOOPBACK; + input [2:0] RXCHBONDLEVEL; + input [2:0] RXOUTCLKSEL; + input [2:0] RXPRBSSEL; + input [2:0] RXRATE; + input [2:0] TXBUFDIFFCTRL; + input [2:0] TXHEADER; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input [2:0] TXPRBSSEL; + input [2:0] TXRATE; + input [3:0] CLKRSVD; + input [3:0] TXDIFFCTRL; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN2; + input [4:0] PMARSVDIN; + input [4:0] RXCHBONDI; + input [4:0] TXPOSTCURSOR; + input [4:0] TXPRECURSOR; + input [63:0] TXDATA; + input [6:0] TXMAINCURSOR; + input [6:0] TXSEQUENCE; + input [7:0] TX8B10BBYPASS; + input [7:0] TXCHARDISPMODE; + input [7:0] TXCHARDISPVAL; + input [7:0] TXCHARISK; + input [8:0] DRPADDR; +endmodule + +module GTXE2_COMMON (...); + parameter [63:0] BIAS_CFG = 64'h0000040000001000; + parameter [31:0] COMMON_CFG = 32'h00000000; + parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; + parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; + parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; + parameter [26:0] QPLL_CFG = 27'h0680181; + parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; + parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; + parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; + parameter [9:0] QPLL_CP = 10'b0000011111; + parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; + parameter [9:0] QPLL_FBDIV = 10'b0000000000; + parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; + parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; + parameter [23:0] QPLL_INIT_CFG = 24'h000006; + parameter [15:0] QPLL_LOCK_CFG = 16'h21E8; + parameter [3:0] QPLL_LPF = 4'b1111; + parameter integer QPLL_REFCLK_DIV = 2; + parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_VERSION = "4.0"; + output DRPRDY; + output QPLLFBCLKLOST; + output QPLLLOCK; + output QPLLOUTCLK; + output QPLLOUTREFCLK; + output QPLLREFCLKLOST; + output REFCLKOUTMONITOR; + output [15:0] DRPDO; + output [7:0] QPLLDMONITOR; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + (* invertible_pin = "IS_DRPCLK_INVERTED" *) + input DRPCLK; + input DRPEN; + input DRPWE; + (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *) + input QPLLLOCKDETCLK; + input QPLLLOCKEN; + input QPLLOUTRESET; + input QPLLPD; + input QPLLRESET; + input RCALENB; + input [15:0] DRPDI; + input [15:0] QPLLRSVD1; + input [2:0] QPLLREFCLKSEL; + input [4:0] BGRCALOVRD; + input [4:0] QPLLRSVD2; + input [7:0] DRPADDR; + input [7:0] PMARSVD; +endmodule + +module IBUFDS_GTE2 (...); + parameter CLKCM_CFG = "TRUE"; + parameter CLKRCV_TRST = "TRUE"; + parameter CLKSWING_CFG = "TRUE"; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module GTHE3_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [15:0] ADAPT_CFG0 = 16'hF800; + parameter [15:0] ADAPT_CFG1 = 16'h0000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [0:0] A_TXPROGDIVRESET = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 2; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 2; + parameter [15:0] CPLL_CFG0 = 16'h20F8; + parameter [15:0] CPLL_CFG1 = 16'hA494; + parameter [15:0] CPLL_CFG2 = 16'hF001; + parameter [5:0] CPLL_CFG3 = 6'h00; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 4; + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [7:0] CPLL_INIT_CFG1 = 8'h00; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter [1:0] DDI_CTRL = 2'b00; + parameter integer DDI_REALIGN_WAIT = 15; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [0:0] DFE_D_X_REL_POS = 1'b0; + parameter [0:0] DFE_VCM_COMP_EN = 1'b0; + parameter [9:0] DMONITOR_CFG0 = 10'h000; + parameter [7:0] DMONITOR_CFG1 = 8'h00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [15:0] ES_QUALIFIER0 = 16'h0000; + parameter [15:0] ES_QUALIFIER1 = 16'h0000; + parameter [15:0] ES_QUALIFIER2 = 16'h0000; + parameter [15:0] ES_QUALIFIER3 = 16'h0000; + parameter [15:0] ES_QUALIFIER4 = 16'h0000; + parameter [15:0] ES_QUAL_MASK0 = 16'h0000; + parameter [15:0] ES_QUAL_MASK1 = 16'h0000; + parameter [15:0] ES_QUAL_MASK2 = 16'h0000; + parameter [15:0] ES_QUAL_MASK3 = 16'h0000; + parameter [15:0] ES_QUAL_MASK4 = 16'h0000; + parameter [15:0] ES_SDATA_MASK0 = 16'h0000; + parameter [15:0] ES_SDATA_MASK1 = 16'h0000; + parameter [15:0] ES_SDATA_MASK2 = 16'h0000; + parameter [15:0] ES_SDATA_MASK3 = 16'h0000; + parameter [15:0] ES_SDATA_MASK4 = 16'h0000; + parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] GM_BIAS_SELECT = 1'b0; + parameter [0:0] LOCAL_MASTER = 1'b0; + parameter [1:0] OOBDIVCTL = 2'b00; + parameter [0:0] OOB_PWRUP = 1'b0; + parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; + parameter PCS_PCIE_EN = "FALSE"; + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; + parameter [2:0] PCS_RSVD1 = 3'b000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; + parameter [15:0] PMA_RSV1 = 16'h0000; + parameter [2:0] PROCESS_PAR = 3'b010; + parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 0; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [15:0] RXCDR_CFG0 = 16'h0000; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG1 = 16'h0080; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG2 = 16'h07E6; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG3 = 16'h0000; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG4 = 16'h0000; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG5 = 16'h0000; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0; + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXCFOK_CFG0 = 16'h4000; + parameter [15:0] RXCFOK_CFG1 = 16'h0060; + parameter [15:0] RXCFOK_CFG2 = 16'h000E; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032; + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000; + parameter [15:0] RXDFE_CFG0 = 16'h0A00; + parameter [15:0] RXDFE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG1 = 16'h7840; + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H3_CFG0 = 16'h4000; + parameter [15:0] RXDFE_H3_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H4_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H5_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H5_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H6_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H6_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H7_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H7_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H8_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H8_CFG1 = 16'h0000; + parameter [15:0] RXDFE_H9_CFG0 = 16'h2000; + parameter [15:0] RXDFE_H9_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HA_CFG0 = 16'h2000; + parameter [15:0] RXDFE_HA_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HB_CFG0 = 16'h2000; + parameter [15:0] RXDFE_HB_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG1 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG0 = 16'h8000; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG0 = 16'h8000; + parameter [15:0] RXDFE_UT_CFG1 = 16'h0003; + parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00; + parameter [15:0] RXDFE_VP_CFG1 = 16'h0033; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [15:0] RXDLY_LCFG = 16'h0030; + parameter RXELECIDLE_CFG = "Sigcfg_4"; + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [15:0] RXLPM_CFG = 16'h0000; + parameter [15:0] RXLPM_GC_CFG = 16'h0000; + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; + parameter [15:0] RXLPM_OS_CFG0 = 16'h8000; + parameter [15:0] RXLPM_OS_CFG1 = 16'h0002; + parameter [8:0] RXOOB_CFG = 9'b000000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter integer RXOUT_DIV = 4; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [15:0] RXPHBEACON_CFG = 16'h0000; + parameter [15:0] RXPHDLY_CFG = 16'h2020; + parameter [15:0] RXPHSAMP_CFG = 16'h2100; + parameter [15:0] RXPHSLIP_CFG = 16'h6622; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] RXPI_CFG0 = 2'b00; + parameter [1:0] RXPI_CFG1 = 2'b00; + parameter [1:0] RXPI_CFG2 = 2'b00; + parameter [1:0] RXPI_CFG3 = 2'b00; + parameter [0:0] RXPI_CFG4 = 1'b0; + parameter [0:0] RXPI_CFG5 = 1'b1; + parameter [2:0] RXPI_CFG6 = 3'b000; + parameter [0:0] RXPI_LPM = 1'b0; + parameter [0:0] RXPI_VREFSEL = 1'b0; + parameter RXPMACLK_SEL = "DATA"; + parameter [4:0] RXPMARESET_TIME = 5'b00001; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [0:0] RX_AFE_CM_EN = 1'b0; + parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; + parameter integer RX_CLK25_DIV = 8; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; + parameter [3:0] RX_CM_BUF_CFG = 4'b1010; + parameter [0:0] RX_CM_BUF_PD = 1'b0; + parameter [1:0] RX_CM_SEL = 2'b11; + parameter [3:0] RX_CM_TRIM = 4'b0100; + parameter [7:0] RX_CTLE3_LPF = 8'b00000000; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; + parameter [0:0] RX_DFELPM_CFG1 = 1'b0; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100; + parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [4:0] RX_DIVRESET_TIME = 5'b00001; + parameter [0:0] RX_EN_HI_LR = 1'b0; + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; + parameter integer RX_INT_DATAWIDTH = 1; + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter real RX_PROGDIV_CFG = 4.0; + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; + parameter integer RX_SIG_VALID_DLY = 11; + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; + parameter [1:0] RX_SUM_RES_CTRL = 2'b00; + parameter [3:0] RX_SUM_VCMTUNE = 4'b0000; + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; + parameter [2:0] RX_SUM_VREF_TUNE = 3'b000; + parameter [1:0] RX_TUNE_AFE_OS = 2'b00; + parameter [0:0] RX_WIDEMODE_CDR = 1'b0; + parameter RX_XCLK_SEL = "RXDES"; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_MODE = "FAST"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; + parameter integer SIM_VERSION = 2; + parameter [1:0] TAPDLY_SET_TX = 2'h0; + parameter [3:0] TEMPERATUR_PAR = 4'b0010; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [7:0] TST_RSV0 = 8'h00; + parameter [7:0] TST_RSV1 = 8'h00; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter [3:0] TXDRVBIAS_N = 4'b1010; + parameter [3:0] TXDRVBIAS_P = 4'b1100; + parameter TXFIFO_ADDR_CFG = "LOW"; + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 4; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [15:0] TXPHDLY_CFG0 = 16'h2020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0001; + parameter [15:0] TXPH_CFG = 16'h0980; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b1; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GRAY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter [0:0] TXPI_LPM = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [0:0] TXPI_VREFSEL = 1'b0; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 8; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DCD_CFG = 6'b000010; + parameter [0:0] TX_DCD_EN = 1'b0; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [4:0] TX_DIVRESET_TIME = 5'b00001; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_EML_PHI_TUNE = 1'b0; + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; + parameter integer TX_INT_DATAWIDTH = 1; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [2:0] TX_MODE_SEL = 3'b000; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter TX_PROGCLK_SEL = "POSTPI"; + parameter real TX_PROGDIV_CFG = 4.0; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h0032; + parameter [2:0] TX_RXDETECT_REF = 3'b100; + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; + parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + parameter [1:0] WB_MODE = 2'b00; + output [2:0] BUFGTCE; + output [2:0] BUFGTCEMASK; + output [8:0] BUFGTDIV; + output [2:0] BUFGTRESET; + output [2:0] BUFGTRSTMASK; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output [16:0] DMONITOROUT; + output [15:0] DRPDO; + output DRPRDY; + output EYESCANDATAERROR; + output GTHTXN; + output GTHTXP; + output GTPOWERGOOD; + output GTREFCLKMONITOR; + output PCIERATEGEN3; + output PCIERATEIDLE; + output [1:0] PCIERATEQPLLPD; + output [1:0] PCIERATEQPLLRESET; + output PCIESYNCTXSYNCDONE; + output PCIEUSERGEN3RDY; + output PCIEUSERPHYSTATUSRST; + output PCIEUSERRATESTART; + output [11:0] PCSRSVDOUT; + output PHYSTATUS; + output [7:0] PINRSRVDAS; + output RESETEXCEPTION; + output [2:0] RXBUFSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCDRPHDONE; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output [4:0] RXCHBONDO; + output [1:0] RXCLKCORCNT; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output [15:0] RXCTRL0; + output [15:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [127:0] RXDATA; + output [7:0] RXDATAEXTENDRSVD; + output [1:0] RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output [5:0] RXHEADER; + output [1:0] RXHEADERVALID; + output [6:0] RXMONITOROUT; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPHALIGNERR; + output RXPMARESETDONE; + output RXPRBSERR; + output RXPRBSLOCKED; + output RXPRGDIVRESETDONE; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRECCLKOUT; + output RXRESETDONE; + output RXSLIDERDY; + output RXSLIPDONE; + output RXSLIPOUTCLKRDY; + output RXSLIPPMARDY; + output [1:0] RXSTARTOFSEQ; + output [2:0] RXSTATUS; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output [1:0] TXBUFSTATUS; + output TXCOMFINISH; + output TXDLYSRESETDONE; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXPRGDIVRESETDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input [2:0] CPLLREFCLKSEL; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input [8:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input EVODDPHICALDONE; + input EVODDPHICALSTART; + input EVODDPHIDRDEN; + input EVODDPHIDWREN; + input EVODDPHIXRDEN; + input EVODDPHIXWREN; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTGREFCLK; + input GTHRXN; + input GTHRXP; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input [15:0] GTRSVD; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input [2:0] LOOPBACK; + input LPBKRXTXSEREN; + input LPBKTXRXSEREN; + input PCIEEQRXEQADAPTDONE; + input PCIERSTIDLE; + input PCIERSTTXSYNCSTART; + input PCIEUSERRATEDONE; + input [15:0] PCSRSVDIN; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN; + input QPLL0CLK; + input QPLL0REFCLK; + input QPLL1CLK; + input QPLL1REFCLK; + input RESETOVRD; + input RSTCLKENTX; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input [4:0] RXCHBONDI; + input [2:0] RXCHBONDLEVEL; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCOMMADETEN; + input [1:0] RXDFEAGCCTRL; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP10HOLD; + input RXDFETAP10OVRDEN; + input RXDFETAP11HOLD; + input RXDFETAP11OVRDEN; + input RXDFETAP12HOLD; + input RXDFETAP12OVRDEN; + input RXDFETAP13HOLD; + input RXDFETAP13OVRDEN; + input RXDFETAP14HOLD; + input RXDFETAP14OVRDEN; + input RXDFETAP15HOLD; + input RXDFETAP15OVRDEN; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFETAP8HOLD; + input RXDFETAP8OVRDEN; + input RXDFETAP9HOLD; + input RXDFETAP9OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input [1:0] RXELECIDLEMODE; + input RXGEARBOXSLIP; + input RXLATCLK; + input RXLPMEN; + input RXLPMGCHOLD; + input RXLPMGCOVRDEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXLPMOSHOLD; + input RXLPMOSOVRDEN; + input RXMCOMMAALIGNEN; + input [1:0] RXMONITORSEL; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input [3:0] RXOSINTCFG; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTOVRDEN; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input [2:0] RXOUTCLKSEL; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input [1:0] RXPD; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input [1:0] RXPLLCLKSEL; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input [3:0] RXPRBSSEL; + input RXPROGDIVRESET; + input RXQPIEN; + input [2:0] RXRATE; + input RXRATEMODE; + input RXSLIDE; + input RXSLIPOUTCLK; + input RXSLIPPMA; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input [1:0] RXSYSCLKSEL; + input RXUSERRDY; + input RXUSRCLK; + input RXUSRCLK2; + input SIGVALIDCLK; + input [19:0] TSTIN; + input [7:0] TX8B10BBYPASS; + input TX8B10BEN; + input [2:0] TXBUFDIFFCTRL; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input [15:0] TXCTRL0; + input [15:0] TXCTRL1; + input [7:0] TXCTRL2; + input [127:0] TXDATA; + input [7:0] TXDATAEXTENDRSVD; + input TXDEEMPH; + input TXDETECTRX; + input [3:0] TXDIFFCTRL; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input [5:0] TXHEADER; + input TXINHIBIT; + input TXLATCLK; + input [6:0] TXMAINCURSOR; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input TXPCSRESET; + input [1:0] TXPD; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input [4:0] TXPIPPMSTEPSIZE; + input TXPISOPD; + input [1:0] TXPLLCLKSEL; + input TXPMARESET; + input TXPOLARITY; + input [4:0] TXPOSTCURSOR; + input TXPOSTCURSORINV; + input TXPRBSFORCEERR; + input [3:0] TXPRBSSEL; + input [4:0] TXPRECURSOR; + input TXPRECURSORINV; + input TXPROGDIVRESET; + input TXQPIBIASEN; + input TXQPISTRONGPDOWN; + input TXQPIWEAKPUP; + input [2:0] TXRATE; + input TXRATEMODE; + input [6:0] TXSEQUENCE; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input [1:0] TXSYSCLKSEL; + input TXUSERRDY; + input TXUSRCLK; + input TXUSRCLK2; +endmodule + +module GTHE3_COMMON (...); + parameter [15:0] BIAS_CFG0 = 16'h0000; + parameter [15:0] BIAS_CFG1 = 16'h0000; + parameter [15:0] BIAS_CFG2 = 16'h0000; + parameter [15:0] BIAS_CFG3 = 16'h0000; + parameter [15:0] BIAS_CFG4 = 16'h0000; + parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; + parameter [15:0] COMMON_CFG0 = 16'h0000; + parameter [15:0] COMMON_CFG1 = 16'h0000; + parameter [15:0] POR_CFG = 16'h0004; + parameter [15:0] QPLL0_CFG0 = 16'h3018; + parameter [15:0] QPLL0_CFG1 = 16'h0000; + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL0_CFG2 = 16'h0000; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0000; + parameter [15:0] QPLL0_CFG3 = 16'h0120; + parameter [15:0] QPLL0_CFG4 = 16'h0009; + parameter [9:0] QPLL0_CP = 10'b0000011111; + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; + parameter integer QPLL0_FBDIV = 66; + parameter integer QPLL0_FBDIV_G3 = 80; + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h01E8; + parameter [9:0] QPLL0_LPF = 10'b1111111111; + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; + parameter integer QPLL0_REFCLK_DIV = 2; + parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000000000000; + parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000; + parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000; + parameter [15:0] QPLL1_CFG0 = 16'h3018; + parameter [15:0] QPLL1_CFG1 = 16'h0000; + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL1_CFG2 = 16'h0000; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0000; + parameter [15:0] QPLL1_CFG3 = 16'h0120; + parameter [15:0] QPLL1_CFG4 = 16'h0009; + parameter [9:0] QPLL1_CP = 10'b0000011111; + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; + parameter integer QPLL1_FBDIV = 66; + parameter integer QPLL1_FBDIV_G3 = 80; + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL1_LPF = 10'b1111111111; + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; + parameter integer QPLL1_REFCLK_DIV = 2; + parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000000000000; + parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000; + parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [15:0] RSVD_ATTR2 = 16'h0000; + parameter [15:0] RSVD_ATTR3 = 16'h0000; + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; + parameter [0:0] SARC_EN = 1'b1; + parameter [0:0] SARC_SEL = 1'b0; + parameter [15:0] SDM0DATA1_0 = 16'b0000000000000000; + parameter [8:0] SDM0DATA1_1 = 9'b000000000; + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; + parameter [0:0] SDM0_DATA_PIN_SEL = 1'b0; + parameter [0:0] SDM0_WIDTH_PIN_SEL = 1'b0; + parameter [15:0] SDM1DATA1_0 = 16'b0000000000000000; + parameter [8:0] SDM1DATA1_1 = 9'b000000000; + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter [0:0] SDM1_DATA_PIN_SEL = 1'b0; + parameter [0:0] SDM1_WIDTH_PIN_SEL = 1'b0; + parameter SIM_MODE = "FAST"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter integer SIM_VERSION = 2; + output [15:0] DRPDO; + output DRPRDY; + output [7:0] PMARSVDOUT0; + output [7:0] PMARSVDOUT1; + output QPLL0FBCLKLOST; + output QPLL0LOCK; + output QPLL0OUTCLK; + output QPLL0OUTREFCLK; + output QPLL0REFCLKLOST; + output QPLL1FBCLKLOST; + output QPLL1LOCK; + output QPLL1OUTCLK; + output QPLL1OUTREFCLK; + output QPLL1REFCLKLOST; + output [7:0] QPLLDMONITOR0; + output [7:0] QPLLDMONITOR1; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [1:0] RXRECCLK0_SEL; + output [1:0] RXRECCLK1_SEL; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input [8:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input GTGREFCLK0; + input GTGREFCLK1; + input GTNORTHREFCLK00; + input GTNORTHREFCLK01; + input GTNORTHREFCLK10; + input GTNORTHREFCLK11; + input GTREFCLK00; + input GTREFCLK01; + input GTREFCLK10; + input GTREFCLK11; + input GTSOUTHREFCLK00; + input GTSOUTHREFCLK01; + input GTSOUTHREFCLK10; + input GTSOUTHREFCLK11; + input [7:0] PMARSVD0; + input [7:0] PMARSVD1; + input QPLL0CLKRSVD0; + input QPLL0CLKRSVD1; + input QPLL0LOCKDETCLK; + input QPLL0LOCKEN; + input QPLL0PD; + input [2:0] QPLL0REFCLKSEL; + input QPLL0RESET; + input QPLL1CLKRSVD0; + input QPLL1CLKRSVD1; + input QPLL1LOCKDETCLK; + input QPLL1LOCKEN; + input QPLL1PD; + input [2:0] QPLL1REFCLKSEL; + input QPLL1RESET; + input [7:0] QPLLRSVD1; + input [4:0] QPLLRSVD2; + input [4:0] QPLLRSVD3; + input [7:0] QPLLRSVD4; + input RCALENB; +endmodule + +module GTHE4_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [15:0] ADAPT_CFG0 = 16'h9200; + parameter [15:0] ADAPT_CFG1 = 16'h801C; + parameter [15:0] ADAPT_CFG2 = 16'h0000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [0:0] A_RXTERMINATION = 1'b1; + parameter [4:0] A_TXDIFFCTRL = 5'b01100; + parameter [0:0] A_TXPROGDIVRESET = 1'b0; + parameter [0:0] CAPBYPASS_FORCE = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter [0:0] CFOK_PWRSVE_EN = 1'b1; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 2; + parameter [15:0] CH_HSPMUX = 16'h2424; + parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; + parameter [15:0] CKCAL_RSVD0 = 16'h4000; + parameter [15:0] CKCAL_RSVD1 = 16'h0000; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 2; + parameter [15:0] CPLL_CFG0 = 16'h01FA; + parameter [15:0] CPLL_CFG1 = 16'h24A9; + parameter [15:0] CPLL_CFG2 = 16'h6807; + parameter [15:0] CPLL_CFG3 = 16'h0000; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 4; + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; + parameter [1:0] DDI_CTRL = 2'b00; + parameter integer DDI_REALIGN_WAIT = 15; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [0:0] DELAY_ELEC = 1'b0; + parameter [9:0] DMONITOR_CFG0 = 10'h000; + parameter [7:0] DMONITOR_CFG1 = 8'h00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h800; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [15:0] ES_QUALIFIER0 = 16'h0000; + parameter [15:0] ES_QUALIFIER1 = 16'h0000; + parameter [15:0] ES_QUALIFIER2 = 16'h0000; + parameter [15:0] ES_QUALIFIER3 = 16'h0000; + parameter [15:0] ES_QUALIFIER4 = 16'h0000; + parameter [15:0] ES_QUALIFIER5 = 16'h0000; + parameter [15:0] ES_QUALIFIER6 = 16'h0000; + parameter [15:0] ES_QUALIFIER7 = 16'h0000; + parameter [15:0] ES_QUALIFIER8 = 16'h0000; + parameter [15:0] ES_QUALIFIER9 = 16'h0000; + parameter [15:0] ES_QUAL_MASK0 = 16'h0000; + parameter [15:0] ES_QUAL_MASK1 = 16'h0000; + parameter [15:0] ES_QUAL_MASK2 = 16'h0000; + parameter [15:0] ES_QUAL_MASK3 = 16'h0000; + parameter [15:0] ES_QUAL_MASK4 = 16'h0000; + parameter [15:0] ES_QUAL_MASK5 = 16'h0000; + parameter [15:0] ES_QUAL_MASK6 = 16'h0000; + parameter [15:0] ES_QUAL_MASK7 = 16'h0000; + parameter [15:0] ES_QUAL_MASK8 = 16'h0000; + parameter [15:0] ES_QUAL_MASK9 = 16'h0000; + parameter [15:0] ES_SDATA_MASK0 = 16'h0000; + parameter [15:0] ES_SDATA_MASK1 = 16'h0000; + parameter [15:0] ES_SDATA_MASK2 = 16'h0000; + parameter [15:0] ES_SDATA_MASK3 = 16'h0000; + parameter [15:0] ES_SDATA_MASK4 = 16'h0000; + parameter [15:0] ES_SDATA_MASK5 = 16'h0000; + parameter [15:0] ES_SDATA_MASK6 = 16'h0000; + parameter [15:0] ES_SDATA_MASK7 = 16'h0000; + parameter [15:0] ES_SDATA_MASK8 = 16'h0000; + parameter [15:0] ES_SDATA_MASK9 = 16'h0000; + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; + parameter [0:0] LOCAL_MASTER = 1'b0; + parameter [2:0] LPBK_BIAS_CTRL = 3'b000; + parameter [0:0] LPBK_EN_RCAL_B = 1'b0; + parameter [3:0] LPBK_EXT_RCAL = 4'b0000; + parameter [2:0] LPBK_IND_CTRL0 = 3'b000; + parameter [2:0] LPBK_IND_CTRL1 = 3'b000; + parameter [2:0] LPBK_IND_CTRL2 = 3'b000; + parameter [3:0] LPBK_RG_CTRL = 4'b0000; + parameter [1:0] OOBDIVCTL = 2'b00; + parameter [0:0] OOB_PWRUP = 1'b0; + parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; + parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; + parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; + parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; + parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; + parameter PCS_PCIE_EN = "FALSE"; + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter integer PREIQ_FREQ_BST = 0; + parameter [2:0] PROCESS_PAR = 3'b010; + parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; + parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; + parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 0; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [15:0] RXCDR_CFG0 = 16'h0003; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; + parameter [15:0] RXCDR_CFG1 = 16'h0000; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG2 = 16'h0164; + parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; + parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; + parameter [15:0] RXCDR_CFG3 = 16'h0024; + parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; + parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; + parameter [15:0] RXCDR_CFG4 = 16'h5CF6; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; + parameter [15:0] RXCDR_CFG5 = 16'hB46B; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXCFOK_CFG0 = 16'h0000; + parameter [15:0] RXCFOK_CFG1 = 16'h0002; + parameter [15:0] RXCFOK_CFG2 = 16'h002D; + parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; + parameter [15:0] RXDFE_CFG0 = 16'h4000; + parameter [15:0] RXDFE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; + parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0002; + parameter [0:0] RXDFE_PWR_SAVING = 1'b0; + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; + parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; + parameter [15:0] RXDLY_CFG = 16'h0010; + parameter [15:0] RXDLY_LCFG = 16'h0030; + parameter RXELECIDLE_CFG = "SIGCFG_4"; + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [15:0] RXLPM_CFG = 16'h0000; + parameter [15:0] RXLPM_GC_CFG = 16'h1000; + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; + parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; + parameter [8:0] RXOOB_CFG = 9'b000110000; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter integer RXOUT_DIV = 4; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [15:0] RXPHBEACON_CFG = 16'h0000; + parameter [15:0] RXPHDLY_CFG = 16'h2020; + parameter [15:0] RXPHSAMP_CFG = 16'h2100; + parameter [15:0] RXPHSLIP_CFG = 16'h9933; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; + parameter [15:0] RXPI_CFG0 = 16'h0002; + parameter [15:0] RXPI_CFG1 = 16'b0000000000000000; + parameter [0:0] RXPI_LPM = 1'b0; + parameter [1:0] RXPI_SEL_LC = 2'b00; + parameter [1:0] RXPI_STARTCODE = 2'b00; + parameter [0:0] RXPI_VREFSEL = 1'b0; + parameter RXPMACLK_SEL = "DATA"; + parameter [4:0] RXPMARESET_TIME = 5'b00001; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [0:0] RX_AFE_CM_EN = 1'b0; + parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; + parameter integer RX_CLK25_DIV = 8; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; + parameter [3:0] RX_CM_BUF_CFG = 4'b1010; + parameter [0:0] RX_CM_BUF_PD = 1'b0; + parameter integer RX_CM_SEL = 3; + parameter integer RX_CM_TRIM = 12; + parameter [7:0] RX_CTLE3_LPF = 8'b00000000; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [2:0] RX_DEGEN_CTRL = 3'b011; + parameter integer RX_DFELPM_CFG0 = 0; + parameter [0:0] RX_DFELPM_CFG1 = 1'b1; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter integer RX_DFE_AGC_CFG1 = 4; + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; + parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [0:0] RX_DIV2_MODE_B = 1'b0; + parameter [4:0] RX_DIVRESET_TIME = 5'b00001; + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; + parameter [0:0] RX_EN_HI_LR = 1'b1; + parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; + parameter integer RX_INT_DATAWIDTH = 1; + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] RX_PMA_RSV0 = 16'h0000; + parameter real RX_PROGDIV_CFG = 0.0; + parameter [15:0] RX_PROGDIV_RATE = 16'h0001; + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; + parameter [0:0] RX_RESLOAD_OVRD = 1'b0; + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; + parameter integer RX_SIG_VALID_DLY = 11; + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001; + parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000; + parameter [3:0] RX_SUM_VCMTUNE = 4'b1010; + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; + parameter [1:0] RX_TUNE_AFE_OS = 2'b00; + parameter [2:0] RX_VREG_CTRL = 3'b101; + parameter [0:0] RX_VREG_PDB = 1'b1; + parameter [1:0] RX_WIDEMODE_CDR = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; + parameter RX_XCLK_SEL = "RXDES"; + parameter [0:0] RX_XMODE_SEL = 1'b0; + parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; + parameter [0:0] SAS_12G_MODE = 1'b0; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SIM_MODE = "FAST"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; + parameter [0:0] SRSTMODE = 1'b0; + parameter [1:0] TAPDLY_SET_TX = 2'h0; + parameter [3:0] TEMPERATURE_PAR = 4'b0010; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [7:0] TST_RSV0 = 8'h00; + parameter [7:0] TST_RSV1 = 8'h00; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h0010; + parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter [3:0] TXDRVBIAS_N = 4'b1010; + parameter TXFIFO_ADDR_CFG = "LOW"; + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 4; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [15:0] TXPHDLY_CFG0 = 16'h6020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0002; + parameter [15:0] TXPH_CFG = 16'h0123; + parameter [15:0] TXPH_CFG2 = 16'h0000; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [15:0] TXPI_CFG = 16'h0000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b1; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GRAY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter [0:0] TXPI_LPM = 1'b0; + parameter [0:0] TXPI_PPM = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [0:0] TXPI_VREFSEL = 1'b0; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 8; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [5:0] TX_DEEMPH2 = 6'b000000; + parameter [5:0] TX_DEEMPH3 = 6'b000000; + parameter [4:0] TX_DIVRESET_TIME = 5'b00001; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter integer TX_DRVMUX_CTRL = 2; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] TX_FIFO_BYP_EN = 1'b0; + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; + parameter integer TX_INT_DATAWIDTH = 1; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; + parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; + parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; + parameter integer TX_PI_BIASSET = 0; + parameter [1:0] TX_PI_IBIAS_MID = 2'b00; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] TX_PMA_RSV0 = 16'h0008; + parameter integer TX_PREDRV_CTRL = 2; + parameter TX_PROGCLK_SEL = "POSTPI"; + parameter real TX_PROGDIV_CFG = 0.0; + parameter [15:0] TX_PROGDIV_RATE = 16'h0001; + parameter [0:0] TX_QPI_STATUS_EN = 1'b0; + parameter [13:0] TX_RXDETECT_CFG = 14'h0032; + parameter integer TX_RXDETECT_REF = 3; + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; + parameter [1:0] TX_SW_MEAS = 2'b00; + parameter [2:0] TX_VREG_CTRL = 3'b000; + parameter [0:0] TX_VREG_PDB = 1'b0; + parameter [1:0] TX_VREG_VREFSEL = 2'b00; + parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; + parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; + parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; + parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; + parameter [0:0] USB_EXT_CNTL = 1'b1; + parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; + parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; + parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; + parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; + parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; + parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; + parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; + parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; + parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; + parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; + parameter [0:0] USB_MODE = 1'b0; + parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; + parameter integer USB_PING_SATA_MAX_INIT = 21; + parameter integer USB_PING_SATA_MIN_INIT = 12; + parameter integer USB_POLL_SATA_MAX_BURST = 8; + parameter integer USB_POLL_SATA_MIN_BURST = 4; + parameter [0:0] USB_RAW_ELEC = 1'b0; + parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; + parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; + parameter integer USB_U1_SATA_MAX_WAKE = 7; + parameter integer USB_U1_SATA_MIN_WAKE = 4; + parameter integer USB_U2_SAS_MAX_COM = 64; + parameter integer USB_U2_SAS_MIN_COM = 36; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + parameter [0:0] Y_ALL_MODE = 1'b0; + output BUFGTCE; + output [2:0] BUFGTCEMASK; + output [8:0] BUFGTDIV; + output BUFGTRESET; + output [2:0] BUFGTRSTMASK; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output [15:0] DMONITOROUT; + output DMONITOROUTCLK; + output [15:0] DRPDO; + output DRPRDY; + output EYESCANDATAERROR; + output GTHTXN; + output GTHTXP; + output GTPOWERGOOD; + output GTREFCLKMONITOR; + output PCIERATEGEN3; + output PCIERATEIDLE; + output [1:0] PCIERATEQPLLPD; + output [1:0] PCIERATEQPLLRESET; + output PCIESYNCTXSYNCDONE; + output PCIEUSERGEN3RDY; + output PCIEUSERPHYSTATUSRST; + output PCIEUSERRATESTART; + output [15:0] PCSRSVDOUT; + output PHYSTATUS; + output [15:0] PINRSRVDAS; + output POWERPRESENT; + output RESETEXCEPTION; + output [2:0] RXBUFSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCDRPHDONE; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output [4:0] RXCHBONDO; + output RXCKCALDONE; + output [1:0] RXCLKCORCNT; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output [15:0] RXCTRL0; + output [15:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [127:0] RXDATA; + output [7:0] RXDATAEXTENDRSVD; + output [1:0] RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output [5:0] RXHEADER; + output [1:0] RXHEADERVALID; + output RXLFPSTRESETDET; + output RXLFPSU2LPEXITDET; + output RXLFPSU3WAKEDET; + output [7:0] RXMONITOROUT; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPHALIGNERR; + output RXPMARESETDONE; + output RXPRBSERR; + output RXPRBSLOCKED; + output RXPRGDIVRESETDONE; + output RXQPISENN; + output RXQPISENP; + output RXRATEDONE; + output RXRECCLKOUT; + output RXRESETDONE; + output RXSLIDERDY; + output RXSLIPDONE; + output RXSLIPOUTCLKRDY; + output RXSLIPPMARDY; + output [1:0] RXSTARTOFSEQ; + output [2:0] RXSTATUS; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output [1:0] TXBUFSTATUS; + output TXCOMFINISH; + output TXDCCDONE; + output TXDLYSRESETDONE; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXPRGDIVRESETDONE; + output TXQPISENN; + output TXQPISENP; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + input CDRSTEPDIR; + input CDRSTEPSQ; + input CDRSTEPSX; + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLFREQLOCK; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input [2:0] CPLLREFCLKSEL; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPRST; + input DRPWE; + input EYESCANRESET; + input EYESCANTRIGGER; + input FREQOS; + input GTGREFCLK; + input GTHRXN; + input GTHRXP; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input [15:0] GTRSVD; + input GTRXRESET; + input GTRXRESETSEL; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTTXRESETSEL; + input INCPCTRL; + input [2:0] LOOPBACK; + input PCIEEQRXEQADAPTDONE; + input PCIERSTIDLE; + input PCIERSTTXSYNCSTART; + input PCIEUSERRATEDONE; + input [15:0] PCSRSVDIN; + input QPLL0CLK; + input QPLL0FREQLOCK; + input QPLL0REFCLK; + input QPLL1CLK; + input QPLL1FREQLOCK; + input QPLL1REFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXAFECFOKEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCHBONDEN; + input [4:0] RXCHBONDI; + input [2:0] RXCHBONDLEVEL; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCKCALRESET; + input [6:0] RXCKCALSTART; + input RXCOMMADETEN; + input [1:0] RXDFEAGCCTRL; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input [3:0] RXDFECFOKFCNUM; + input RXDFECFOKFEN; + input RXDFECFOKFPULSE; + input RXDFECFOKHOLD; + input RXDFECFOKOVREN; + input RXDFEKHHOLD; + input RXDFEKHOVRDEN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP10HOLD; + input RXDFETAP10OVRDEN; + input RXDFETAP11HOLD; + input RXDFETAP11OVRDEN; + input RXDFETAP12HOLD; + input RXDFETAP12OVRDEN; + input RXDFETAP13HOLD; + input RXDFETAP13OVRDEN; + input RXDFETAP14HOLD; + input RXDFETAP14OVRDEN; + input RXDFETAP15HOLD; + input RXDFETAP15OVRDEN; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFETAP8HOLD; + input RXDFETAP8OVRDEN; + input RXDFETAP9HOLD; + input RXDFETAP9OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input [1:0] RXELECIDLEMODE; + input RXEQTRAINING; + input RXGEARBOXSLIP; + input RXLATCLK; + input RXLPMEN; + input RXLPMGCHOLD; + input RXLPMGCOVRDEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXLPMOSHOLD; + input RXLPMOSOVRDEN; + input RXMCOMMAALIGNEN; + input [1:0] RXMONITORSEL; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSOVRDEN; + input [2:0] RXOUTCLKSEL; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input [1:0] RXPD; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input [1:0] RXPLLCLKSEL; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input [3:0] RXPRBSSEL; + input RXPROGDIVRESET; + input RXQPIEN; + input [2:0] RXRATE; + input RXRATEMODE; + input RXSLIDE; + input RXSLIPOUTCLK; + input RXSLIPPMA; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input [1:0] RXSYSCLKSEL; + input RXTERMINATION; + input RXUSERRDY; + input RXUSRCLK; + input RXUSRCLK2; + input SIGVALIDCLK; + input [19:0] TSTIN; + input [7:0] TX8B10BBYPASS; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input [15:0] TXCTRL0; + input [15:0] TXCTRL1; + input [7:0] TXCTRL2; + input [127:0] TXDATA; + input [7:0] TXDATAEXTENDRSVD; + input TXDCCFORCESTART; + input TXDCCRESET; + input [1:0] TXDEEMPH; + input TXDETECTRX; + input [4:0] TXDIFFCTRL; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input [5:0] TXHEADER; + input TXINHIBIT; + input TXLATCLK; + input TXLFPSTRESET; + input TXLFPSU2LPEXIT; + input TXLFPSU3WAKE; + input [6:0] TXMAINCURSOR; + input [2:0] TXMARGIN; + input TXMUXDCDEXHOLD; + input TXMUXDCDORWREN; + input TXONESZEROS; + input [2:0] TXOUTCLKSEL; + input TXPCSRESET; + input [1:0] TXPD; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input [4:0] TXPIPPMSTEPSIZE; + input TXPISOPD; + input [1:0] TXPLLCLKSEL; + input TXPMARESET; + input TXPOLARITY; + input [4:0] TXPOSTCURSOR; + input TXPRBSFORCEERR; + input [3:0] TXPRBSSEL; + input [4:0] TXPRECURSOR; + input TXPROGDIVRESET; + input TXQPIBIASEN; + input TXQPIWEAKPUP; + input [2:0] TXRATE; + input TXRATEMODE; + input [6:0] TXSEQUENCE; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input [1:0] TXSYSCLKSEL; + input TXUSERRDY; + input TXUSRCLK; + input TXUSRCLK2; +endmodule + +module GTHE4_COMMON (...); + parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; + parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; + parameter [0:0] AEN_SDM0TOGGLE = 1'b0; + parameter [0:0] AEN_SDM1TOGGLE = 1'b0; + parameter [0:0] A_SDM0TOGGLE = 1'b0; + parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; + parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; + parameter [0:0] A_SDM1TOGGLE = 1'b0; + parameter [15:0] BIAS_CFG0 = 16'h0000; + parameter [15:0] BIAS_CFG1 = 16'h0000; + parameter [15:0] BIAS_CFG2 = 16'h0000; + parameter [15:0] BIAS_CFG3 = 16'h0000; + parameter [15:0] BIAS_CFG4 = 16'h0000; + parameter [15:0] BIAS_CFG_RSVD = 16'h0000; + parameter [15:0] COMMON_CFG0 = 16'h0000; + parameter [15:0] COMMON_CFG1 = 16'h0000; + parameter [15:0] POR_CFG = 16'h0000; + parameter [15:0] PPF0_CFG = 16'h0F00; + parameter [15:0] PPF1_CFG = 16'h0F00; + parameter QPLL0CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL0_CFG0 = 16'h391C; + parameter [15:0] QPLL0_CFG1 = 16'h0000; + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL0_CFG2 = 16'h0F80; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL0_CFG3 = 16'h0120; + parameter [15:0] QPLL0_CFG4 = 16'h0002; + parameter [9:0] QPLL0_CP = 10'b0000011111; + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; + parameter integer QPLL0_FBDIV = 66; + parameter integer QPLL0_FBDIV_G3 = 80; + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL0_LPF = 10'b1011111111; + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; + parameter [0:0] QPLL0_PCI_EN = 1'b0; + parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL0_REFCLK_DIV = 1; + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; + parameter QPLL1CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL1_CFG0 = 16'h691C; + parameter [15:0] QPLL1_CFG1 = 16'h0020; + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL1_CFG2 = 16'h0F80; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL1_CFG3 = 16'h0120; + parameter [15:0] QPLL1_CFG4 = 16'h0002; + parameter [9:0] QPLL1_CP = 10'b0000011111; + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; + parameter integer QPLL1_FBDIV = 66; + parameter integer QPLL1_FBDIV_G3 = 80; + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL1_LPF = 10'b1011111111; + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; + parameter [0:0] QPLL1_PCI_EN = 1'b0; + parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL1_REFCLK_DIV = 1; + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [15:0] RSVD_ATTR2 = 16'h0000; + parameter [15:0] RSVD_ATTR3 = 16'h0000; + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; + parameter [0:0] SARC_ENB = 1'b0; + parameter [0:0] SARC_SEL = 1'b0; + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter SIM_MODE = "FAST"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + output [15:0] DRPDO; + output DRPRDY; + output [7:0] PMARSVDOUT0; + output [7:0] PMARSVDOUT1; + output QPLL0FBCLKLOST; + output QPLL0LOCK; + output QPLL0OUTCLK; + output QPLL0OUTREFCLK; + output QPLL0REFCLKLOST; + output QPLL1FBCLKLOST; + output QPLL1LOCK; + output QPLL1OUTCLK; + output QPLL1OUTREFCLK; + output QPLL1REFCLKLOST; + output [7:0] QPLLDMONITOR0; + output [7:0] QPLLDMONITOR1; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [1:0] RXRECCLK0SEL; + output [1:0] RXRECCLK1SEL; + output [3:0] SDM0FINALOUT; + output [14:0] SDM0TESTDATA; + output [3:0] SDM1FINALOUT; + output [14:0] SDM1TESTDATA; + output [9:0] TCONGPO; + output TCONRSVDOUT0; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input [15:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input GTGREFCLK0; + input GTGREFCLK1; + input GTNORTHREFCLK00; + input GTNORTHREFCLK01; + input GTNORTHREFCLK10; + input GTNORTHREFCLK11; + input GTREFCLK00; + input GTREFCLK01; + input GTREFCLK10; + input GTREFCLK11; + input GTSOUTHREFCLK00; + input GTSOUTHREFCLK01; + input GTSOUTHREFCLK10; + input GTSOUTHREFCLK11; + input [2:0] PCIERATEQPLL0; + input [2:0] PCIERATEQPLL1; + input [7:0] PMARSVD0; + input [7:0] PMARSVD1; + input QPLL0CLKRSVD0; + input QPLL0CLKRSVD1; + input [7:0] QPLL0FBDIV; + input QPLL0LOCKDETCLK; + input QPLL0LOCKEN; + input QPLL0PD; + input [2:0] QPLL0REFCLKSEL; + input QPLL0RESET; + input QPLL1CLKRSVD0; + input QPLL1CLKRSVD1; + input [7:0] QPLL1FBDIV; + input QPLL1LOCKDETCLK; + input QPLL1LOCKEN; + input QPLL1PD; + input [2:0] QPLL1REFCLKSEL; + input QPLL1RESET; + input [7:0] QPLLRSVD1; + input [4:0] QPLLRSVD2; + input [4:0] QPLLRSVD3; + input [7:0] QPLLRSVD4; + input RCALENB; + input [24:0] SDM0DATA; + input SDM0RESET; + input SDM0TOGGLE; + input [1:0] SDM0WIDTH; + input [24:0] SDM1DATA; + input SDM1RESET; + input SDM1TOGGLE; + input [1:0] SDM1WIDTH; + input [9:0] TCONGPI; + input TCONPOWERUP; + input [1:0] TCONRESET; + input [1:0] TCONRSVDIN1; +endmodule + +module GTYE3_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [15:0] ADAPT_CFG0 = 16'h9200; + parameter [15:0] ADAPT_CFG1 = 16'h801C; + parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [4:0] A_TXDIFFCTRL = 5'b01100; + parameter [0:0] A_TXPROGDIVRESET = 1'b0; + parameter [0:0] CAPBYPASS_FORCE = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 2; + parameter [15:0] CH_HSPMUX = 16'h0000; + parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; + parameter [15:0] CKCAL_RSVD0 = 16'h0000; + parameter [15:0] CKCAL_RSVD1 = 16'h0000; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 2; + parameter [15:0] CPLL_CFG0 = 16'h20F8; + parameter [15:0] CPLL_CFG1 = 16'hA494; + parameter [15:0] CPLL_CFG2 = 16'hF001; + parameter [5:0] CPLL_CFG3 = 6'h00; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 4; + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [7:0] CPLL_INIT_CFG1 = 8'h00; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; + parameter [1:0] DDI_CTRL = 2'b00; + parameter integer DDI_REALIGN_WAIT = 15; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [0:0] DFE_D_X_REL_POS = 1'b0; + parameter [0:0] DFE_VCM_COMP_EN = 1'b0; + parameter [9:0] DMONITOR_CFG0 = 10'h000; + parameter [7:0] DMONITOR_CFG1 = 8'h00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h000; + parameter [9:0] ES_PMA_CFG = 10'b0000000000; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [15:0] ES_QUALIFIER0 = 16'h0000; + parameter [15:0] ES_QUALIFIER1 = 16'h0000; + parameter [15:0] ES_QUALIFIER2 = 16'h0000; + parameter [15:0] ES_QUALIFIER3 = 16'h0000; + parameter [15:0] ES_QUALIFIER4 = 16'h0000; + parameter [15:0] ES_QUALIFIER5 = 16'h0000; + parameter [15:0] ES_QUALIFIER6 = 16'h0000; + parameter [15:0] ES_QUALIFIER7 = 16'h0000; + parameter [15:0] ES_QUALIFIER8 = 16'h0000; + parameter [15:0] ES_QUALIFIER9 = 16'h0000; + parameter [15:0] ES_QUAL_MASK0 = 16'h0000; + parameter [15:0] ES_QUAL_MASK1 = 16'h0000; + parameter [15:0] ES_QUAL_MASK2 = 16'h0000; + parameter [15:0] ES_QUAL_MASK3 = 16'h0000; + parameter [15:0] ES_QUAL_MASK4 = 16'h0000; + parameter [15:0] ES_QUAL_MASK5 = 16'h0000; + parameter [15:0] ES_QUAL_MASK6 = 16'h0000; + parameter [15:0] ES_QUAL_MASK7 = 16'h0000; + parameter [15:0] ES_QUAL_MASK8 = 16'h0000; + parameter [15:0] ES_QUAL_MASK9 = 16'h0000; + parameter [15:0] ES_SDATA_MASK0 = 16'h0000; + parameter [15:0] ES_SDATA_MASK1 = 16'h0000; + parameter [15:0] ES_SDATA_MASK2 = 16'h0000; + parameter [15:0] ES_SDATA_MASK3 = 16'h0000; + parameter [15:0] ES_SDATA_MASK4 = 16'h0000; + parameter [15:0] ES_SDATA_MASK5 = 16'h0000; + parameter [15:0] ES_SDATA_MASK6 = 16'h0000; + parameter [15:0] ES_SDATA_MASK7 = 16'h0000; + parameter [15:0] ES_SDATA_MASK8 = 16'h0000; + parameter [15:0] ES_SDATA_MASK9 = 16'h0000; + parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] GM_BIAS_SELECT = 1'b0; + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; + parameter [0:0] LOCAL_MASTER = 1'b0; + parameter [15:0] LOOP0_CFG = 16'h0000; + parameter [15:0] LOOP10_CFG = 16'h0000; + parameter [15:0] LOOP11_CFG = 16'h0000; + parameter [15:0] LOOP12_CFG = 16'h0000; + parameter [15:0] LOOP13_CFG = 16'h0000; + parameter [15:0] LOOP1_CFG = 16'h0000; + parameter [15:0] LOOP2_CFG = 16'h0000; + parameter [15:0] LOOP3_CFG = 16'h0000; + parameter [15:0] LOOP4_CFG = 16'h0000; + parameter [15:0] LOOP5_CFG = 16'h0000; + parameter [15:0] LOOP6_CFG = 16'h0000; + parameter [15:0] LOOP7_CFG = 16'h0000; + parameter [15:0] LOOP8_CFG = 16'h0000; + parameter [15:0] LOOP9_CFG = 16'h0000; + parameter [2:0] LPBK_BIAS_CTRL = 3'b000; + parameter [0:0] LPBK_EN_RCAL_B = 1'b0; + parameter [3:0] LPBK_EXT_RCAL = 4'b0000; + parameter [3:0] LPBK_RG_CTRL = 4'b0000; + parameter [1:0] OOBDIVCTL = 2'b00; + parameter [0:0] OOB_PWRUP = 1'b0; + parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; + parameter PCS_PCIE_EN = "FALSE"; + parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; + parameter [2:0] PCS_RSVD1 = 3'b000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; + parameter [15:0] PMA_RSV0 = 16'h0000; + parameter [15:0] PMA_RSV1 = 16'h0000; + parameter integer PREIQ_FREQ_BST = 0; + parameter [2:0] PROCESS_PAR = 3'b010; + parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 0; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [15:0] RXCDR_CFG0 = 16'h0000; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG1 = 16'h0300; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300; + parameter [15:0] RXCDR_CFG2 = 16'h0060; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060; + parameter [15:0] RXCDR_CFG3 = 16'h0000; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG4 = 16'h0002; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002; + parameter [15:0] RXCDR_CFG5 = 16'h0000; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [1:0] RXCFOKDONE_SRC = 2'b00; + parameter [15:0] RXCFOK_CFG0 = 16'h3E00; + parameter [15:0] RXCFOK_CFG1 = 16'h0042; + parameter [15:0] RXCFOK_CFG2 = 16'h002D; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; + parameter [15:0] RXDFE_CFG0 = 16'h4C00; + parameter [15:0] RXDFE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00; + parameter [15:0] RXDFE_GC_CFG1 = 16'h1900; + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0200; + parameter [0:0] RXDFE_PWR_SAVING = 1'b0; + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; + parameter [15:0] RXDLY_CFG = 16'h001F; + parameter [15:0] RXDLY_LCFG = 16'h0030; + parameter RXELECIDLE_CFG = "SIGCFG_4"; + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [15:0] RXLPM_CFG = 16'h0000; + parameter [15:0] RXLPM_GC_CFG = 16'h0200; + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; + parameter [15:0] RXLPM_OS_CFG0 = 16'h0400; + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; + parameter [8:0] RXOOB_CFG = 9'b000000110; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter integer RXOUT_DIV = 4; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [15:0] RXPHBEACON_CFG = 16'h0000; + parameter [15:0] RXPHDLY_CFG = 16'h2020; + parameter [15:0] RXPHSAMP_CFG = 16'h2100; + parameter [15:0] RXPHSLIP_CFG = 16'h9933; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; + parameter [15:0] RXPI_CFG = 16'h0100; + parameter [0:0] RXPI_LPM = 1'b0; + parameter [15:0] RXPI_RSV0 = 16'h0000; + parameter [1:0] RXPI_SEL_LC = 2'b00; + parameter [1:0] RXPI_STARTCODE = 2'b00; + parameter [0:0] RXPI_VREFSEL = 1'b0; + parameter RXPMACLK_SEL = "DATA"; + parameter [4:0] RXPMARESET_TIME = 5'b00001; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [0:0] RX_AFE_CM_EN = 1'b0; + parameter [15:0] RX_BIAS_CFG0 = 16'h1534; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; + parameter integer RX_CLK25_DIV = 8; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; + parameter [3:0] RX_CM_BUF_CFG = 4'b1010; + parameter [0:0] RX_CM_BUF_PD = 1'b0; + parameter integer RX_CM_SEL = 3; + parameter integer RX_CM_TRIM = 10; + parameter [0:0] RX_CTLE1_KHKL = 1'b0; + parameter [0:0] RX_CTLE2_KHKL = 1'b0; + parameter [0:0] RX_CTLE3_AGC = 1'b0; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [2:0] RX_DEGEN_CTRL = 3'b010; + parameter integer RX_DFELPM_CFG0 = 6; + parameter [0:0] RX_DFELPM_CFG1 = 1'b0; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; + parameter integer RX_DFE_AGC_CFG1 = 4; + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; + parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [0:0] RX_DIV2_MODE_B = 1'b0; + parameter [4:0] RX_DIVRESET_TIME = 5'b00001; + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; + parameter [0:0] RX_EN_HI_LR = 1'b0; + parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; + parameter integer RX_INT_DATAWIDTH = 1; + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter real RX_PROGDIV_CFG = 0.0; + parameter [15:0] RX_PROGDIV_RATE = 16'h0001; + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; + parameter [0:0] RX_RESLOAD_OVRD = 1'b0; + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; + parameter integer RX_SIG_VALID_DLY = 11; + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; + parameter [3:0] RX_SUM_VCMTUNE = 4'b1000; + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; + parameter [1:0] RX_TUNE_AFE_OS = 2'b00; + parameter [2:0] RX_VREG_CTRL = 3'b101; + parameter [0:0] RX_VREG_PDB = 1'b1; + parameter [1:0] RX_WIDEMODE_CDR = 2'b01; + parameter RX_XCLK_SEL = "RXDES"; + parameter [0:0] RX_XMODE_SEL = 1'b0; + parameter integer SAS_MAX_COM = 64; + parameter integer SAS_MIN_COM = 36; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter integer SATA_MAX_BURST = 8; + parameter integer SATA_MAX_INIT = 21; + parameter integer SATA_MAX_WAKE = 7; + parameter integer SATA_MIN_BURST = 4; + parameter integer SATA_MIN_INIT = 12; + parameter integer SATA_MIN_WAKE = 4; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_MODE = "FAST"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; + parameter integer SIM_VERSION = 2; + parameter [1:0] TAPDLY_SET_TX = 2'h0; + parameter [3:0] TEMPERATURE_PAR = 4'b0010; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [7:0] TST_RSV0 = 8'h00; + parameter [7:0] TST_RSV1 = 8'h00; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h001F; + parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter TXFIFO_ADDR_CFG = "LOW"; + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 4; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [15:0] TXPHDLY_CFG0 = 16'h2020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0001; + parameter [15:0] TXPH_CFG = 16'h0123; + parameter [15:0] TXPH_CFG2 = 16'h0000; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [1:0] TXPI_CFG0 = 2'b00; + parameter [1:0] TXPI_CFG1 = 2'b00; + parameter [1:0] TXPI_CFG2 = 2'b00; + parameter [0:0] TXPI_CFG3 = 1'b0; + parameter [0:0] TXPI_CFG4 = 1'b1; + parameter [2:0] TXPI_CFG5 = 3'b000; + parameter [0:0] TXPI_GRAY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter [0:0] TXPI_LPM = 1'b0; + parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [15:0] TXPI_RSV0 = 16'h0000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [0:0] TXPI_VREFSEL = 1'b0; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 8; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter [0:0] TX_CLKREG_PDB = 1'b0; + parameter [2:0] TX_CLKREG_SET = 3'b000; + parameter integer TX_DATA_WIDTH = 20; + parameter [5:0] TX_DCD_CFG = 6'b000010; + parameter [0:0] TX_DCD_EN = 1'b0; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [4:0] TX_DIVRESET_TIME = 5'b00001; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter integer TX_DRVMUX_CTRL = 2; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_EML_PHI_TUNE = 1'b0; + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] TX_FIFO_BYP_EN = 1'b0; + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; + parameter integer TX_INT_DATAWIDTH = 1; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [2:0] TX_MODE_SEL = 3'b000; + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; + parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00; + parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; + parameter integer TX_PI_BIASSET = 0; + parameter [15:0] TX_PI_CFG0 = 16'h0000; + parameter [15:0] TX_PI_CFG1 = 16'h0000; + parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0; + parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0; + parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter integer TX_PREDRV_CTRL = 2; + parameter TX_PROGCLK_SEL = "POSTPI"; + parameter real TX_PROGDIV_CFG = 0.0; + parameter [15:0] TX_PROGDIV_RATE = 16'h0001; + parameter [13:0] TX_RXDETECT_CFG = 14'h0032; + parameter integer TX_RXDETECT_REF = 4; + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; + parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; + parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + output [2:0] BUFGTCE; + output [2:0] BUFGTCEMASK; + output [8:0] BUFGTDIV; + output [2:0] BUFGTRESET; + output [2:0] BUFGTRSTMASK; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output [16:0] DMONITOROUT; + output [15:0] DRPDO; + output DRPRDY; + output EYESCANDATAERROR; + output GTPOWERGOOD; + output GTREFCLKMONITOR; + output GTYTXN; + output GTYTXP; + output PCIERATEGEN3; + output PCIERATEIDLE; + output [1:0] PCIERATEQPLLPD; + output [1:0] PCIERATEQPLLRESET; + output PCIESYNCTXSYNCDONE; + output PCIEUSERGEN3RDY; + output PCIEUSERPHYSTATUSRST; + output PCIEUSERRATESTART; + output [15:0] PCSRSVDOUT; + output PHYSTATUS; + output [7:0] PINRSRVDAS; + output RESETEXCEPTION; + output [2:0] RXBUFSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCDRPHDONE; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output [4:0] RXCHBONDO; + output RXCKCALDONE; + output [1:0] RXCLKCORCNT; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output [15:0] RXCTRL0; + output [15:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [127:0] RXDATA; + output [7:0] RXDATAEXTENDRSVD; + output [1:0] RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output [5:0] RXHEADER; + output [1:0] RXHEADERVALID; + output [6:0] RXMONITOROUT; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPHALIGNERR; + output RXPMARESETDONE; + output RXPRBSERR; + output RXPRBSLOCKED; + output RXPRGDIVRESETDONE; + output RXRATEDONE; + output RXRECCLKOUT; + output RXRESETDONE; + output RXSLIDERDY; + output RXSLIPDONE; + output RXSLIPOUTCLKRDY; + output RXSLIPPMARDY; + output [1:0] RXSTARTOFSEQ; + output [2:0] RXSTATUS; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output [1:0] TXBUFSTATUS; + output TXCOMFINISH; + output TXDCCDONE; + output TXDLYSRESETDONE; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXPRGDIVRESETDONE; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + input CDRSTEPDIR; + input CDRSTEPSQ; + input CDRSTEPSX; + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input [2:0] CPLLREFCLKSEL; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input ELPCALDVORWREN; + input ELPCALPAORWREN; + input EVODDPHICALDONE; + input EVODDPHICALSTART; + input EVODDPHIDRDEN; + input EVODDPHIDWREN; + input EVODDPHIXRDEN; + input EVODDPHIXWREN; + input EYESCANMODE; + input EYESCANRESET; + input EYESCANTRIGGER; + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input GTRESETSEL; + input [15:0] GTRSVD; + input GTRXRESET; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTYRXN; + input GTYRXP; + input [2:0] LOOPBACK; + input [15:0] LOOPRSVD; + input LPBKRXTXSEREN; + input LPBKTXRXSEREN; + input PCIEEQRXEQADAPTDONE; + input PCIERSTIDLE; + input PCIERSTTXSYNCSTART; + input PCIEUSERRATEDONE; + input [15:0] PCSRSVDIN; + input [4:0] PCSRSVDIN2; + input [4:0] PMARSVDIN; + input QPLL0CLK; + input QPLL0REFCLK; + input QPLL1CLK; + input QPLL1REFCLK; + input RESETOVRD; + input RSTCLKENTX; + input RX8B10BEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCDRRESETRSV; + input RXCHBONDEN; + input [4:0] RXCHBONDI; + input [2:0] RXCHBONDLEVEL; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCKCALRESET; + input RXCOMMADETEN; + input RXDCCFORCESTART; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP10HOLD; + input RXDFETAP10OVRDEN; + input RXDFETAP11HOLD; + input RXDFETAP11OVRDEN; + input RXDFETAP12HOLD; + input RXDFETAP12OVRDEN; + input RXDFETAP13HOLD; + input RXDFETAP13OVRDEN; + input RXDFETAP14HOLD; + input RXDFETAP14OVRDEN; + input RXDFETAP15HOLD; + input RXDFETAP15OVRDEN; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFETAP8HOLD; + input RXDFETAP8OVRDEN; + input RXDFETAP9HOLD; + input RXDFETAP9OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEVSEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input [1:0] RXELECIDLEMODE; + input RXGEARBOXSLIP; + input RXLATCLK; + input RXLPMEN; + input RXLPMGCHOLD; + input RXLPMGCOVRDEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXLPMOSHOLD; + input RXLPMOSOVRDEN; + input RXMCOMMAALIGNEN; + input [1:0] RXMONITORSEL; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input [3:0] RXOSINTCFG; + input RXOSINTEN; + input RXOSINTHOLD; + input RXOSINTOVRDEN; + input RXOSINTSTROBE; + input RXOSINTTESTOVRDEN; + input RXOSOVRDEN; + input [2:0] RXOUTCLKSEL; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input [1:0] RXPD; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input RXPHOVRDEN; + input [1:0] RXPLLCLKSEL; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input [3:0] RXPRBSSEL; + input RXPROGDIVRESET; + input [2:0] RXRATE; + input RXRATEMODE; + input RXSLIDE; + input RXSLIPOUTCLK; + input RXSLIPPMA; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input [1:0] RXSYSCLKSEL; + input RXUSERRDY; + input RXUSRCLK; + input RXUSRCLK2; + input SIGVALIDCLK; + input [19:0] TSTIN; + input [7:0] TX8B10BBYPASS; + input TX8B10BEN; + input [2:0] TXBUFDIFFCTRL; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input [15:0] TXCTRL0; + input [15:0] TXCTRL1; + input [7:0] TXCTRL2; + input [127:0] TXDATA; + input [7:0] TXDATAEXTENDRSVD; + input TXDCCFORCESTART; + input TXDCCRESET; + input TXDEEMPH; + input TXDETECTRX; + input [4:0] TXDIFFCTRL; + input TXDIFFPD; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input TXELFORCESTART; + input [5:0] TXHEADER; + input TXINHIBIT; + input TXLATCLK; + input [6:0] TXMAINCURSOR; + input [2:0] TXMARGIN; + input [2:0] TXOUTCLKSEL; + input TXPCSRESET; + input [1:0] TXPD; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input [4:0] TXPIPPMSTEPSIZE; + input TXPISOPD; + input [1:0] TXPLLCLKSEL; + input TXPMARESET; + input TXPOLARITY; + input [4:0] TXPOSTCURSOR; + input TXPRBSFORCEERR; + input [3:0] TXPRBSSEL; + input [4:0] TXPRECURSOR; + input TXPROGDIVRESET; + input [2:0] TXRATE; + input TXRATEMODE; + input [6:0] TXSEQUENCE; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input [1:0] TXSYSCLKSEL; + input TXUSERRDY; + input TXUSRCLK; + input TXUSRCLK2; +endmodule + +module GTYE3_COMMON (...); + parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000; + parameter [8:0] A_SDM1DATA1_1 = 9'b000000000; + parameter [15:0] BIAS_CFG0 = 16'h0000; + parameter [15:0] BIAS_CFG1 = 16'h0000; + parameter [15:0] BIAS_CFG2 = 16'h0000; + parameter [15:0] BIAS_CFG3 = 16'h0000; + parameter [15:0] BIAS_CFG4 = 16'h0000; + parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; + parameter [15:0] COMMON_CFG0 = 16'h0000; + parameter [15:0] COMMON_CFG1 = 16'h0000; + parameter [15:0] POR_CFG = 16'h0004; + parameter [15:0] PPF0_CFG = 16'h0FFF; + parameter [15:0] PPF1_CFG = 16'h0FFF; + parameter QPLL0CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL0_CFG0 = 16'h301C; + parameter [15:0] QPLL0_CFG1 = 16'h0000; + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL0_CFG2 = 16'h0780; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0780; + parameter [15:0] QPLL0_CFG3 = 16'h0120; + parameter [15:0] QPLL0_CFG4 = 16'h0021; + parameter [9:0] QPLL0_CP = 10'b0000011111; + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; + parameter integer QPLL0_FBDIV = 66; + parameter integer QPLL0_FBDIV_G3 = 80; + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL0_LPF = 10'b1111111111; + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; + parameter integer QPLL0_REFCLK_DIV = 2; + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; + parameter QPLL1CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL1_CFG0 = 16'h301C; + parameter [15:0] QPLL1_CFG1 = 16'h0000; + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL1_CFG2 = 16'h0780; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0780; + parameter [15:0] QPLL1_CFG3 = 16'h0120; + parameter [15:0] QPLL1_CFG4 = 16'h0021; + parameter [9:0] QPLL1_CP = 10'b0000011111; + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; + parameter integer QPLL1_FBDIV = 66; + parameter integer QPLL1_FBDIV_G3 = 80; + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL1_LPF = 10'b1111111111; + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; + parameter integer QPLL1_REFCLK_DIV = 2; + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040; + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [15:0] RSVD_ATTR2 = 16'h0000; + parameter [15:0] RSVD_ATTR3 = 16'h0000; + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; + parameter [0:0] SARC_EN = 1'b1; + parameter [0:0] SARC_SEL = 1'b0; + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter SIM_MODE = "FAST"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter integer SIM_VERSION = 2; + output [15:0] DRPDO; + output DRPRDY; + output [7:0] PMARSVDOUT0; + output [7:0] PMARSVDOUT1; + output QPLL0FBCLKLOST; + output QPLL0LOCK; + output QPLL0OUTCLK; + output QPLL0OUTREFCLK; + output QPLL0REFCLKLOST; + output QPLL1FBCLKLOST; + output QPLL1LOCK; + output QPLL1OUTCLK; + output QPLL1OUTREFCLK; + output QPLL1REFCLKLOST; + output [7:0] QPLLDMONITOR0; + output [7:0] QPLLDMONITOR1; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [1:0] RXRECCLK0_SEL; + output [1:0] RXRECCLK1_SEL; + output [3:0] SDM0FINALOUT; + output [14:0] SDM0TESTDATA; + output [3:0] SDM1FINALOUT; + output [14:0] SDM1TESTDATA; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input GTGREFCLK0; + input GTGREFCLK1; + input GTNORTHREFCLK00; + input GTNORTHREFCLK01; + input GTNORTHREFCLK10; + input GTNORTHREFCLK11; + input GTREFCLK00; + input GTREFCLK01; + input GTREFCLK10; + input GTREFCLK11; + input GTSOUTHREFCLK00; + input GTSOUTHREFCLK01; + input GTSOUTHREFCLK10; + input GTSOUTHREFCLK11; + input [7:0] PMARSVD0; + input [7:0] PMARSVD1; + input QPLL0CLKRSVD0; + input QPLL0LOCKDETCLK; + input QPLL0LOCKEN; + input QPLL0PD; + input [2:0] QPLL0REFCLKSEL; + input QPLL0RESET; + input QPLL1CLKRSVD0; + input QPLL1LOCKDETCLK; + input QPLL1LOCKEN; + input QPLL1PD; + input [2:0] QPLL1REFCLKSEL; + input QPLL1RESET; + input [7:0] QPLLRSVD1; + input [4:0] QPLLRSVD2; + input [4:0] QPLLRSVD3; + input [7:0] QPLLRSVD4; + input RCALENB; + input [24:0] SDM0DATA; + input SDM0RESET; + input [1:0] SDM0WIDTH; + input [24:0] SDM1DATA; + input SDM1RESET; + input [1:0] SDM1WIDTH; +endmodule + +module GTYE4_CHANNEL (...); + parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; + parameter [0:0] ACJTAG_MODE = 1'b0; + parameter [0:0] ACJTAG_RESET = 1'b0; + parameter [15:0] ADAPT_CFG0 = 16'h9200; + parameter [15:0] ADAPT_CFG1 = 16'h801C; + parameter [15:0] ADAPT_CFG2 = 16'h0000; + parameter ALIGN_COMMA_DOUBLE = "FALSE"; + parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; + parameter integer ALIGN_COMMA_WORD = 1; + parameter ALIGN_MCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; + parameter ALIGN_PCOMMA_DET = "TRUE"; + parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; + parameter [0:0] A_RXOSCALRESET = 1'b0; + parameter [0:0] A_RXPROGDIVRESET = 1'b0; + parameter [0:0] A_RXTERMINATION = 1'b1; + parameter [4:0] A_TXDIFFCTRL = 5'b01100; + parameter [0:0] A_TXPROGDIVRESET = 1'b0; + parameter CBCC_DATA_SOURCE_SEL = "DECODED"; + parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; + parameter [0:0] CFOK_PWRSVE_EN = 1'b1; + parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; + parameter integer CHAN_BOND_MAX_SKEW = 7; + parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; + parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; + parameter CHAN_BOND_SEQ_2_USE = "FALSE"; + parameter integer CHAN_BOND_SEQ_LEN = 2; + parameter [15:0] CH_HSPMUX = 16'h2424; + parameter [15:0] CKCAL1_CFG_0 = 16'b1100000011000000; + parameter [15:0] CKCAL1_CFG_1 = 16'b0101000011000000; + parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_0 = 16'b1100000011000000; + parameter [15:0] CKCAL2_CFG_1 = 16'b1000000011000000; + parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; + parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; + parameter CLK_CORRECT_USE = "TRUE"; + parameter CLK_COR_KEEP_IDLE = "FALSE"; + parameter integer CLK_COR_MAX_LAT = 20; + parameter integer CLK_COR_MIN_LAT = 18; + parameter CLK_COR_PRECEDENCE = "TRUE"; + parameter integer CLK_COR_REPEAT_WAIT = 0; + parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; + parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; + parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; + parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; + parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; + parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; + parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; + parameter CLK_COR_SEQ_2_USE = "FALSE"; + parameter integer CLK_COR_SEQ_LEN = 2; + parameter [15:0] CPLL_CFG0 = 16'h01FA; + parameter [15:0] CPLL_CFG1 = 16'h24A9; + parameter [15:0] CPLL_CFG2 = 16'h6807; + parameter [15:0] CPLL_CFG3 = 16'h0000; + parameter integer CPLL_FBDIV = 4; + parameter integer CPLL_FBDIV_45 = 4; + parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; + parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; + parameter integer CPLL_REFCLK_DIV = 1; + parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; + parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; + parameter [1:0] DDI_CTRL = 2'b00; + parameter integer DDI_REALIGN_WAIT = 15; + parameter DEC_MCOMMA_DETECT = "TRUE"; + parameter DEC_PCOMMA_DETECT = "TRUE"; + parameter DEC_VALID_COMMA_ONLY = "TRUE"; + parameter [0:0] DELAY_ELEC = 1'b0; + parameter [9:0] DMONITOR_CFG0 = 10'h000; + parameter [7:0] DMONITOR_CFG1 = 8'h00; + parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; + parameter [5:0] ES_CONTROL = 6'b000000; + parameter ES_ERRDET_EN = "FALSE"; + parameter ES_EYE_SCAN_EN = "FALSE"; + parameter [11:0] ES_HORZ_OFFSET = 12'h800; + parameter [4:0] ES_PRESCALE = 5'b00000; + parameter [15:0] ES_QUALIFIER0 = 16'h0000; + parameter [15:0] ES_QUALIFIER1 = 16'h0000; + parameter [15:0] ES_QUALIFIER2 = 16'h0000; + parameter [15:0] ES_QUALIFIER3 = 16'h0000; + parameter [15:0] ES_QUALIFIER4 = 16'h0000; + parameter [15:0] ES_QUALIFIER5 = 16'h0000; + parameter [15:0] ES_QUALIFIER6 = 16'h0000; + parameter [15:0] ES_QUALIFIER7 = 16'h0000; + parameter [15:0] ES_QUALIFIER8 = 16'h0000; + parameter [15:0] ES_QUALIFIER9 = 16'h0000; + parameter [15:0] ES_QUAL_MASK0 = 16'h0000; + parameter [15:0] ES_QUAL_MASK1 = 16'h0000; + parameter [15:0] ES_QUAL_MASK2 = 16'h0000; + parameter [15:0] ES_QUAL_MASK3 = 16'h0000; + parameter [15:0] ES_QUAL_MASK4 = 16'h0000; + parameter [15:0] ES_QUAL_MASK5 = 16'h0000; + parameter [15:0] ES_QUAL_MASK6 = 16'h0000; + parameter [15:0] ES_QUAL_MASK7 = 16'h0000; + parameter [15:0] ES_QUAL_MASK8 = 16'h0000; + parameter [15:0] ES_QUAL_MASK9 = 16'h0000; + parameter [15:0] ES_SDATA_MASK0 = 16'h0000; + parameter [15:0] ES_SDATA_MASK1 = 16'h0000; + parameter [15:0] ES_SDATA_MASK2 = 16'h0000; + parameter [15:0] ES_SDATA_MASK3 = 16'h0000; + parameter [15:0] ES_SDATA_MASK4 = 16'h0000; + parameter [15:0] ES_SDATA_MASK5 = 16'h0000; + parameter [15:0] ES_SDATA_MASK6 = 16'h0000; + parameter [15:0] ES_SDATA_MASK7 = 16'h0000; + parameter [15:0] ES_SDATA_MASK8 = 16'h0000; + parameter [15:0] ES_SDATA_MASK9 = 16'h0000; + parameter integer EYESCAN_VP_RANGE = 0; + parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; + parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; + parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; + parameter FTS_LANE_DESKEW_EN = "FALSE"; + parameter [4:0] GEARBOX_MODE = 5'b00000; + parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; + parameter [0:0] LOCAL_MASTER = 1'b0; + parameter integer LPBK_BIAS_CTRL = 4; + parameter [0:0] LPBK_EN_RCAL_B = 1'b0; + parameter [3:0] LPBK_EXT_RCAL = 4'b0000; + parameter integer LPBK_IND_CTRL0 = 5; + parameter integer LPBK_IND_CTRL1 = 5; + parameter integer LPBK_IND_CTRL2 = 5; + parameter integer LPBK_RG_CTRL = 2; + parameter [1:0] OOBDIVCTL = 2'b00; + parameter [0:0] OOB_PWRUP = 1'b0; + parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; + parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; + parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; + parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; + parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; + parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; + parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; + parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; + parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; + parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; + parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; + parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; + parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; + parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; + parameter PCIE_64B_DYN_CLKSW_DIS = "FALSE"; + parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; + parameter PCIE_GEN4_64BIT_INT_EN = "FALSE"; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; + parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; + parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; + parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; + parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; + parameter PCS_PCIE_EN = "FALSE"; + parameter [15:0] PCS_RSVD0 = 16'h0000; + parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; + parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; + parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; + parameter integer PREIQ_FREQ_BST = 0; + parameter [0:0] RATE_SW_USE_DRP = 1'b0; + parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; + parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; + parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; + parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; + parameter [4:0] RXBUFRESET_TIME = 5'b00001; + parameter RXBUF_ADDR_MODE = "FULL"; + parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; + parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; + parameter RXBUF_EN = "TRUE"; + parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; + parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; + parameter RXBUF_RESET_ON_EIDLE = "FALSE"; + parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; + parameter integer RXBUF_THRESH_OVFLW = 0; + parameter RXBUF_THRESH_OVRD = "FALSE"; + parameter integer RXBUF_THRESH_UNDFLW = 4; + parameter [4:0] RXCDRFREQRESET_TIME = 5'b10000; + parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; + parameter [15:0] RXCDR_CFG0 = 16'h0003; + parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; + parameter [15:0] RXCDR_CFG1 = 16'h0000; + parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; + parameter [15:0] RXCDR_CFG2 = 16'h0164; + parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; + parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; + parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; + parameter [15:0] RXCDR_CFG3 = 16'h0024; + parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; + parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; + parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; + parameter [15:0] RXCDR_CFG4 = 16'h5CF6; + parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; + parameter [15:0] RXCDR_CFG5 = 16'hB46B; + parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; + parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; + parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; + parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; + parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; + parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; + parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; + parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; + parameter [15:0] RXCFOK_CFG0 = 16'h0000; + parameter [15:0] RXCFOK_CFG1 = 16'h0002; + parameter [15:0] RXCFOK_CFG2 = 16'h002D; + parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; + parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; + parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; + parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; + parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; + parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; + parameter [15:0] RXDFE_CFG0 = 16'h4000; + parameter [15:0] RXDFE_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; + parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; + parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; + parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; + parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; + parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; + parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; + parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; + parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; + parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; + parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; + parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; + parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; + parameter [15:0] RXDLY_CFG = 16'h0010; + parameter [15:0] RXDLY_LCFG = 16'h0030; + parameter RXELECIDLE_CFG = "SIGCFG_4"; + parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter RXGEARBOX_EN = "FALSE"; + parameter [4:0] RXISCANRESET_TIME = 5'b00001; + parameter [15:0] RXLPM_CFG = 16'h0000; + parameter [15:0] RXLPM_GC_CFG = 16'h1000; + parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; + parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; + parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; + parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; + parameter [8:0] RXOOB_CFG = 9'b000110000; + parameter RXOOB_CLK_CFG = "PMA"; + parameter [4:0] RXOSCALRESET_TIME = 5'b00011; + parameter integer RXOUT_DIV = 4; + parameter [4:0] RXPCSRESET_TIME = 5'b00001; + parameter [15:0] RXPHBEACON_CFG = 16'h0000; + parameter [15:0] RXPHDLY_CFG = 16'h2020; + parameter [15:0] RXPHSAMP_CFG = 16'h2100; + parameter [15:0] RXPHSLIP_CFG = 16'h9933; + parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; + parameter [15:0] RXPI_CFG0 = 16'h0102; + parameter [15:0] RXPI_CFG1 = 16'b0000000001010100; + parameter RXPMACLK_SEL = "DATA"; + parameter [4:0] RXPMARESET_TIME = 5'b00001; + parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; + parameter integer RXPRBS_LINKACQ_CNT = 15; + parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; + parameter integer RXSLIDE_AUTO_WAIT = 7; + parameter RXSLIDE_MODE = "OFF"; + parameter [0:0] RXSYNC_MULTILANE = 1'b0; + parameter [0:0] RXSYNC_OVRD = 1'b0; + parameter [0:0] RXSYNC_SKIP_DA = 1'b0; + parameter [0:0] RX_AFE_CM_EN = 1'b0; + parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; + parameter [5:0] RX_BUFFER_CFG = 6'b000000; + parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; + parameter integer RX_CLK25_DIV = 8; + parameter [0:0] RX_CLKMUX_EN = 1'b1; + parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; + parameter [3:0] RX_CM_BUF_CFG = 4'b1010; + parameter [0:0] RX_CM_BUF_PD = 1'b0; + parameter integer RX_CM_SEL = 3; + parameter integer RX_CM_TRIM = 12; + parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0; + parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000; + parameter integer RX_DATA_WIDTH = 20; + parameter [5:0] RX_DDI_SEL = 6'b000000; + parameter RX_DEFER_RESET_BUF_EN = "TRUE"; + parameter [2:0] RX_DEGEN_CTRL = 3'b100; + parameter integer RX_DFELPM_CFG0 = 0; + parameter [0:0] RX_DFELPM_CFG1 = 1'b1; + parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; + parameter integer RX_DFE_AGC_CFG1 = 4; + parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; + parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; + parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; + parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; + parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; + parameter RX_DISPERR_SEQ_MATCH = "TRUE"; + parameter [4:0] RX_DIVRESET_TIME = 5'b00001; + parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; + parameter integer RX_EN_SUM_RCAL_B = 0; + parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; + parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; + parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b10; + parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; + parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] RX_I2V_FILTER_EN = 1'b1; + parameter integer RX_INT_DATAWIDTH = 1; + parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] RX_PMA_RSV0 = 16'h000F; + parameter real RX_PROGDIV_CFG = 0.0; + parameter [15:0] RX_PROGDIV_RATE = 16'h0001; + parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; + parameter [0:0] RX_RESLOAD_OVRD = 1'b0; + parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; + parameter integer RX_SIG_VALID_DLY = 11; + parameter integer RX_SUM_DEGEN_AVTT_OVERITE = 0; + parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; + parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; + parameter integer RX_SUM_PWR_SAVING = 0; + parameter [3:0] RX_SUM_RES_CTRL = 4'b0000; + parameter [3:0] RX_SUM_VCMTUNE = 4'b0011; + parameter [0:0] RX_SUM_VCM_BIAS_TUNE_EN = 1'b1; + parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; + parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; + parameter [1:0] RX_TUNE_AFE_OS = 2'b00; + parameter [2:0] RX_VREG_CTRL = 3'b010; + parameter [0:0] RX_VREG_PDB = 1'b1; + parameter [1:0] RX_WIDEMODE_CDR = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; + parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; + parameter RX_XCLK_SEL = "RXDES"; + parameter [0:0] RX_XMODE_SEL = 1'b0; + parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; + parameter [0:0] SAS_12G_MODE = 1'b0; + parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; + parameter [2:0] SATA_BURST_VAL = 3'b100; + parameter SATA_CPLL_CFG = "VCO_3000MHZ"; + parameter [2:0] SATA_EIDLE_VAL = 3'b100; + parameter SHOW_REALIGN_COMMA = "TRUE"; + parameter SIM_MODE = "FAST"; + parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter [0:0] SRSTMODE = 1'b0; + parameter [1:0] TAPDLY_SET_TX = 2'h0; + parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; + parameter [2:0] TERM_RCAL_OVRD = 3'b000; + parameter [7:0] TRANS_TIME_RATE = 8'h0E; + parameter [7:0] TST_RSV0 = 8'h00; + parameter [7:0] TST_RSV1 = 8'h00; + parameter TXBUF_EN = "TRUE"; + parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; + parameter [15:0] TXDLY_CFG = 16'h0010; + parameter [15:0] TXDLY_LCFG = 16'h0030; + parameter integer TXDRV_FREQBAND = 0; + parameter [15:0] TXFE_CFG0 = 16'b0000000000000000; + parameter [15:0] TXFE_CFG1 = 16'b0000000000000000; + parameter [15:0] TXFE_CFG2 = 16'b0000000000000000; + parameter [15:0] TXFE_CFG3 = 16'b0000000000000000; + parameter TXFIFO_ADDR_CFG = "LOW"; + parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; + parameter TXGEARBOX_EN = "FALSE"; + parameter integer TXOUT_DIV = 4; + parameter [4:0] TXPCSRESET_TIME = 5'b00001; + parameter [15:0] TXPHDLY_CFG0 = 16'h6020; + parameter [15:0] TXPHDLY_CFG1 = 16'h0002; + parameter [15:0] TXPH_CFG = 16'h0123; + parameter [15:0] TXPH_CFG2 = 16'h0000; + parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; + parameter [15:0] TXPI_CFG0 = 16'b0000000100000000; + parameter [15:0] TXPI_CFG1 = 16'b0000000000000000; + parameter [0:0] TXPI_GRAY_SEL = 1'b0; + parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; + parameter [0:0] TXPI_PPM = 1'b0; + parameter [7:0] TXPI_PPM_CFG = 8'b00000000; + parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; + parameter [4:0] TXPMARESET_TIME = 5'b00001; + parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; + parameter integer TXSWBST_BST = 1; + parameter integer TXSWBST_EN = 0; + parameter integer TXSWBST_MAG = 6; + parameter [0:0] TXSYNC_MULTILANE = 1'b0; + parameter [0:0] TXSYNC_OVRD = 1'b0; + parameter [0:0] TXSYNC_SKIP_DA = 1'b0; + parameter integer TX_CLK25_DIV = 8; + parameter [0:0] TX_CLKMUX_EN = 1'b1; + parameter integer TX_DATA_WIDTH = 20; + parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; + parameter [5:0] TX_DEEMPH0 = 6'b000000; + parameter [5:0] TX_DEEMPH1 = 6'b000000; + parameter [5:0] TX_DEEMPH2 = 6'b000000; + parameter [5:0] TX_DEEMPH3 = 6'b000000; + parameter [4:0] TX_DIVRESET_TIME = 5'b00001; + parameter TX_DRIVE_MODE = "DIRECT"; + parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; + parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; + parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; + parameter [0:0] TX_FIFO_BYP_EN = 1'b0; + parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; + parameter integer TX_INT_DATAWIDTH = 1; + parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; + parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; + parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; + parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; + parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; + parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; + parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; + parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; + parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; + parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; + parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; + parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; + parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; + parameter integer TX_PI_BIASSET = 0; + parameter [0:0] TX_PMADATA_OPT = 1'b0; + parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; + parameter [15:0] TX_PMA_RSV0 = 16'h0000; + parameter [15:0] TX_PMA_RSV1 = 16'h0000; + parameter TX_PROGCLK_SEL = "POSTPI"; + parameter real TX_PROGDIV_CFG = 0.0; + parameter [15:0] TX_PROGDIV_RATE = 16'h0001; + parameter [13:0] TX_RXDETECT_CFG = 14'h0032; + parameter integer TX_RXDETECT_REF = 3; + parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; + parameter [1:0] TX_SW_MEAS = 2'b00; + parameter [2:0] TX_VREG_CTRL = 3'b000; + parameter [0:0] TX_VREG_PDB = 1'b0; + parameter [1:0] TX_VREG_VREFSEL = 2'b00; + parameter TX_XCLK_SEL = "TXOUT"; + parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; + parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; + parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; + parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; + parameter [0:0] USB_EXT_CNTL = 1'b1; + parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; + parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; + parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; + parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; + parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; + parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; + parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; + parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; + parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; + parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; + parameter [0:0] USB_MODE = 1'b0; + parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; + parameter integer USB_PING_SATA_MAX_INIT = 21; + parameter integer USB_PING_SATA_MIN_INIT = 12; + parameter integer USB_POLL_SATA_MAX_BURST = 8; + parameter integer USB_POLL_SATA_MIN_BURST = 4; + parameter [0:0] USB_RAW_ELEC = 1'b0; + parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; + parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; + parameter integer USB_U1_SATA_MAX_WAKE = 7; + parameter integer USB_U1_SATA_MIN_WAKE = 4; + parameter integer USB_U2_SAS_MAX_COM = 64; + parameter integer USB_U2_SAS_MIN_COM = 36; + parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; + parameter [0:0] Y_ALL_MODE = 1'b0; + output BUFGTCE; + output [2:0] BUFGTCEMASK; + output [8:0] BUFGTDIV; + output BUFGTRESET; + output [2:0] BUFGTRSTMASK; + output CPLLFBCLKLOST; + output CPLLLOCK; + output CPLLREFCLKLOST; + output [15:0] DMONITOROUT; + output DMONITOROUTCLK; + output [15:0] DRPDO; + output DRPRDY; + output EYESCANDATAERROR; + output GTPOWERGOOD; + output GTREFCLKMONITOR; + output GTYTXN; + output GTYTXP; + output PCIERATEGEN3; + output PCIERATEIDLE; + output [1:0] PCIERATEQPLLPD; + output [1:0] PCIERATEQPLLRESET; + output PCIESYNCTXSYNCDONE; + output PCIEUSERGEN3RDY; + output PCIEUSERPHYSTATUSRST; + output PCIEUSERRATESTART; + output [15:0] PCSRSVDOUT; + output PHYSTATUS; + output [15:0] PINRSRVDAS; + output POWERPRESENT; + output RESETEXCEPTION; + output [2:0] RXBUFSTATUS; + output RXBYTEISALIGNED; + output RXBYTEREALIGN; + output RXCDRLOCK; + output RXCDRPHDONE; + output RXCHANBONDSEQ; + output RXCHANISALIGNED; + output RXCHANREALIGN; + output [4:0] RXCHBONDO; + output RXCKCALDONE; + output [1:0] RXCLKCORCNT; + output RXCOMINITDET; + output RXCOMMADET; + output RXCOMSASDET; + output RXCOMWAKEDET; + output [15:0] RXCTRL0; + output [15:0] RXCTRL1; + output [7:0] RXCTRL2; + output [7:0] RXCTRL3; + output [127:0] RXDATA; + output [7:0] RXDATAEXTENDRSVD; + output [1:0] RXDATAVALID; + output RXDLYSRESETDONE; + output RXELECIDLE; + output [5:0] RXHEADER; + output [1:0] RXHEADERVALID; + output RXLFPSTRESETDET; + output RXLFPSU2LPEXITDET; + output RXLFPSU3WAKEDET; + output [7:0] RXMONITOROUT; + output RXOSINTDONE; + output RXOSINTSTARTED; + output RXOSINTSTROBEDONE; + output RXOSINTSTROBESTARTED; + output RXOUTCLK; + output RXOUTCLKFABRIC; + output RXOUTCLKPCS; + output RXPHALIGNDONE; + output RXPHALIGNERR; + output RXPMARESETDONE; + output RXPRBSERR; + output RXPRBSLOCKED; + output RXPRGDIVRESETDONE; + output RXRATEDONE; + output RXRECCLKOUT; + output RXRESETDONE; + output RXSLIDERDY; + output RXSLIPDONE; + output RXSLIPOUTCLKRDY; + output RXSLIPPMARDY; + output [1:0] RXSTARTOFSEQ; + output [2:0] RXSTATUS; + output RXSYNCDONE; + output RXSYNCOUT; + output RXVALID; + output [1:0] TXBUFSTATUS; + output TXCOMFINISH; + output TXDCCDONE; + output TXDLYSRESETDONE; + output TXOUTCLK; + output TXOUTCLKFABRIC; + output TXOUTCLKPCS; + output TXPHALIGNDONE; + output TXPHINITDONE; + output TXPMARESETDONE; + output TXPRGDIVRESETDONE; + output TXRATEDONE; + output TXRESETDONE; + output TXSYNCDONE; + output TXSYNCOUT; + input CDRSTEPDIR; + input CDRSTEPSQ; + input CDRSTEPSX; + input CFGRESET; + input CLKRSVD0; + input CLKRSVD1; + input CPLLFREQLOCK; + input CPLLLOCKDETCLK; + input CPLLLOCKEN; + input CPLLPD; + input [2:0] CPLLREFCLKSEL; + input CPLLRESET; + input DMONFIFORESET; + input DMONITORCLK; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPRST; + input DRPWE; + input EYESCANRESET; + input EYESCANTRIGGER; + input FREQOS; + input GTGREFCLK; + input GTNORTHREFCLK0; + input GTNORTHREFCLK1; + input GTREFCLK0; + input GTREFCLK1; + input [15:0] GTRSVD; + input GTRXRESET; + input GTRXRESETSEL; + input GTSOUTHREFCLK0; + input GTSOUTHREFCLK1; + input GTTXRESET; + input GTTXRESETSEL; + input GTYRXN; + input GTYRXP; + input INCPCTRL; + input [2:0] LOOPBACK; + input PCIEEQRXEQADAPTDONE; + input PCIERSTIDLE; + input PCIERSTTXSYNCSTART; + input PCIEUSERRATEDONE; + input [15:0] PCSRSVDIN; + input QPLL0CLK; + input QPLL0FREQLOCK; + input QPLL0REFCLK; + input QPLL1CLK; + input QPLL1FREQLOCK; + input QPLL1REFCLK; + input RESETOVRD; + input RX8B10BEN; + input RXAFECFOKEN; + input RXBUFRESET; + input RXCDRFREQRESET; + input RXCDRHOLD; + input RXCDROVRDEN; + input RXCDRRESET; + input RXCHBONDEN; + input [4:0] RXCHBONDI; + input [2:0] RXCHBONDLEVEL; + input RXCHBONDMASTER; + input RXCHBONDSLAVE; + input RXCKCALRESET; + input [6:0] RXCKCALSTART; + input RXCOMMADETEN; + input RXDFEAGCHOLD; + input RXDFEAGCOVRDEN; + input [3:0] RXDFECFOKFCNUM; + input RXDFECFOKFEN; + input RXDFECFOKFPULSE; + input RXDFECFOKHOLD; + input RXDFECFOKOVREN; + input RXDFEKHHOLD; + input RXDFEKHOVRDEN; + input RXDFELFHOLD; + input RXDFELFOVRDEN; + input RXDFELPMRESET; + input RXDFETAP10HOLD; + input RXDFETAP10OVRDEN; + input RXDFETAP11HOLD; + input RXDFETAP11OVRDEN; + input RXDFETAP12HOLD; + input RXDFETAP12OVRDEN; + input RXDFETAP13HOLD; + input RXDFETAP13OVRDEN; + input RXDFETAP14HOLD; + input RXDFETAP14OVRDEN; + input RXDFETAP15HOLD; + input RXDFETAP15OVRDEN; + input RXDFETAP2HOLD; + input RXDFETAP2OVRDEN; + input RXDFETAP3HOLD; + input RXDFETAP3OVRDEN; + input RXDFETAP4HOLD; + input RXDFETAP4OVRDEN; + input RXDFETAP5HOLD; + input RXDFETAP5OVRDEN; + input RXDFETAP6HOLD; + input RXDFETAP6OVRDEN; + input RXDFETAP7HOLD; + input RXDFETAP7OVRDEN; + input RXDFETAP8HOLD; + input RXDFETAP8OVRDEN; + input RXDFETAP9HOLD; + input RXDFETAP9OVRDEN; + input RXDFEUTHOLD; + input RXDFEUTOVRDEN; + input RXDFEVPHOLD; + input RXDFEVPOVRDEN; + input RXDFEXYDEN; + input RXDLYBYPASS; + input RXDLYEN; + input RXDLYOVRDEN; + input RXDLYSRESET; + input [1:0] RXELECIDLEMODE; + input RXEQTRAINING; + input RXGEARBOXSLIP; + input RXLATCLK; + input RXLPMEN; + input RXLPMGCHOLD; + input RXLPMGCOVRDEN; + input RXLPMHFHOLD; + input RXLPMHFOVRDEN; + input RXLPMLFHOLD; + input RXLPMLFKLOVRDEN; + input RXLPMOSHOLD; + input RXLPMOSOVRDEN; + input RXMCOMMAALIGNEN; + input [1:0] RXMONITORSEL; + input RXOOBRESET; + input RXOSCALRESET; + input RXOSHOLD; + input RXOSOVRDEN; + input [2:0] RXOUTCLKSEL; + input RXPCOMMAALIGNEN; + input RXPCSRESET; + input [1:0] RXPD; + input RXPHALIGN; + input RXPHALIGNEN; + input RXPHDLYPD; + input RXPHDLYRESET; + input [1:0] RXPLLCLKSEL; + input RXPMARESET; + input RXPOLARITY; + input RXPRBSCNTRESET; + input [3:0] RXPRBSSEL; + input RXPROGDIVRESET; + input [2:0] RXRATE; + input RXRATEMODE; + input RXSLIDE; + input RXSLIPOUTCLK; + input RXSLIPPMA; + input RXSYNCALLIN; + input RXSYNCIN; + input RXSYNCMODE; + input [1:0] RXSYSCLKSEL; + input RXTERMINATION; + input RXUSERRDY; + input RXUSRCLK; + input RXUSRCLK2; + input SIGVALIDCLK; + input [19:0] TSTIN; + input [7:0] TX8B10BBYPASS; + input TX8B10BEN; + input TXCOMINIT; + input TXCOMSAS; + input TXCOMWAKE; + input [15:0] TXCTRL0; + input [15:0] TXCTRL1; + input [7:0] TXCTRL2; + input [127:0] TXDATA; + input [7:0] TXDATAEXTENDRSVD; + input TXDCCFORCESTART; + input TXDCCRESET; + input [1:0] TXDEEMPH; + input TXDETECTRX; + input [4:0] TXDIFFCTRL; + input TXDLYBYPASS; + input TXDLYEN; + input TXDLYHOLD; + input TXDLYOVRDEN; + input TXDLYSRESET; + input TXDLYUPDOWN; + input TXELECIDLE; + input [5:0] TXHEADER; + input TXINHIBIT; + input TXLATCLK; + input TXLFPSTRESET; + input TXLFPSU2LPEXIT; + input TXLFPSU3WAKE; + input [6:0] TXMAINCURSOR; + input [2:0] TXMARGIN; + input TXMUXDCDEXHOLD; + input TXMUXDCDORWREN; + input TXONESZEROS; + input [2:0] TXOUTCLKSEL; + input TXPCSRESET; + input [1:0] TXPD; + input TXPDELECIDLEMODE; + input TXPHALIGN; + input TXPHALIGNEN; + input TXPHDLYPD; + input TXPHDLYRESET; + input TXPHDLYTSTCLK; + input TXPHINIT; + input TXPHOVRDEN; + input TXPIPPMEN; + input TXPIPPMOVRDEN; + input TXPIPPMPD; + input TXPIPPMSEL; + input [4:0] TXPIPPMSTEPSIZE; + input TXPISOPD; + input [1:0] TXPLLCLKSEL; + input TXPMARESET; + input TXPOLARITY; + input [4:0] TXPOSTCURSOR; + input TXPRBSFORCEERR; + input [3:0] TXPRBSSEL; + input [4:0] TXPRECURSOR; + input TXPROGDIVRESET; + input [2:0] TXRATE; + input TXRATEMODE; + input [6:0] TXSEQUENCE; + input TXSWING; + input TXSYNCALLIN; + input TXSYNCIN; + input TXSYNCMODE; + input [1:0] TXSYSCLKSEL; + input TXUSERRDY; + input TXUSRCLK; + input TXUSRCLK2; +endmodule + +module GTYE4_COMMON (...); + parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; + parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; + parameter [0:0] AEN_SDM0TOGGLE = 1'b0; + parameter [0:0] AEN_SDM1TOGGLE = 1'b0; + parameter [0:0] A_SDM0TOGGLE = 1'b0; + parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; + parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; + parameter [0:0] A_SDM1TOGGLE = 1'b0; + parameter [15:0] BIAS_CFG0 = 16'h0000; + parameter [15:0] BIAS_CFG1 = 16'h0000; + parameter [15:0] BIAS_CFG2 = 16'h0000; + parameter [15:0] BIAS_CFG3 = 16'h0000; + parameter [15:0] BIAS_CFG4 = 16'h0000; + parameter [15:0] BIAS_CFG_RSVD = 16'h0000; + parameter [15:0] COMMON_CFG0 = 16'h0000; + parameter [15:0] COMMON_CFG1 = 16'h0000; + parameter [15:0] POR_CFG = 16'h0000; + parameter [15:0] PPF0_CFG = 16'h0F00; + parameter [15:0] PPF1_CFG = 16'h0F00; + parameter QPLL0CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL0_CFG0 = 16'h391C; + parameter [15:0] QPLL0_CFG1 = 16'h0000; + parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL0_CFG2 = 16'h0F80; + parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL0_CFG3 = 16'h0120; + parameter [15:0] QPLL0_CFG4 = 16'h0002; + parameter [9:0] QPLL0_CP = 10'b0000011111; + parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; + parameter integer QPLL0_FBDIV = 66; + parameter integer QPLL0_FBDIV_G3 = 80; + parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL0_LPF = 10'b1011111111; + parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; + parameter [0:0] QPLL0_PCI_EN = 1'b0; + parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL0_REFCLK_DIV = 1; + parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; + parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; + parameter QPLL1CLKOUT_RATE = "FULL"; + parameter [15:0] QPLL1_CFG0 = 16'h691C; + parameter [15:0] QPLL1_CFG1 = 16'h0020; + parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; + parameter [15:0] QPLL1_CFG2 = 16'h0F80; + parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; + parameter [15:0] QPLL1_CFG3 = 16'h0120; + parameter [15:0] QPLL1_CFG4 = 16'h0002; + parameter [9:0] QPLL1_CP = 10'b0000011111; + parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; + parameter integer QPLL1_FBDIV = 66; + parameter integer QPLL1_FBDIV_G3 = 80; + parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; + parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; + parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; + parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; + parameter [9:0] QPLL1_LPF = 10'b1011111111; + parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; + parameter [0:0] QPLL1_PCI_EN = 1'b0; + parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; + parameter integer QPLL1_REFCLK_DIV = 1; + parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; + parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; + parameter [15:0] RSVD_ATTR0 = 16'h0000; + parameter [15:0] RSVD_ATTR1 = 16'h0000; + parameter [15:0] RSVD_ATTR2 = 16'h0000; + parameter [15:0] RSVD_ATTR3 = 16'h0000; + parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; + parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; + parameter [0:0] SARC_ENB = 1'b0; + parameter [0:0] SARC_SEL = 1'b0; + parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; + parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; + parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; + parameter SIM_MODE = "FAST"; + parameter SIM_RESET_SPEEDUP = "TRUE"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter [15:0] UB_CFG0 = 16'h0000; + parameter [15:0] UB_CFG1 = 16'h0000; + parameter [15:0] UB_CFG2 = 16'h0000; + parameter [15:0] UB_CFG3 = 16'h0000; + parameter [15:0] UB_CFG4 = 16'h0000; + parameter [15:0] UB_CFG5 = 16'h0400; + parameter [15:0] UB_CFG6 = 16'h0000; + output [15:0] DRPDO; + output DRPRDY; + output [7:0] PMARSVDOUT0; + output [7:0] PMARSVDOUT1; + output QPLL0FBCLKLOST; + output QPLL0LOCK; + output QPLL0OUTCLK; + output QPLL0OUTREFCLK; + output QPLL0REFCLKLOST; + output QPLL1FBCLKLOST; + output QPLL1LOCK; + output QPLL1OUTCLK; + output QPLL1OUTREFCLK; + output QPLL1REFCLKLOST; + output [7:0] QPLLDMONITOR0; + output [7:0] QPLLDMONITOR1; + output REFCLKOUTMONITOR0; + output REFCLKOUTMONITOR1; + output [1:0] RXRECCLK0SEL; + output [1:0] RXRECCLK1SEL; + output [3:0] SDM0FINALOUT; + output [14:0] SDM0TESTDATA; + output [3:0] SDM1FINALOUT; + output [14:0] SDM1TESTDATA; + output [15:0] UBDADDR; + output UBDEN; + output [15:0] UBDI; + output UBDWE; + output UBMDMTDO; + output UBRSVDOUT; + output UBTXUART; + input BGBYPASSB; + input BGMONITORENB; + input BGPDB; + input [4:0] BGRCALOVRD; + input BGRCALOVRDENB; + input [15:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input GTGREFCLK0; + input GTGREFCLK1; + input GTNORTHREFCLK00; + input GTNORTHREFCLK01; + input GTNORTHREFCLK10; + input GTNORTHREFCLK11; + input GTREFCLK00; + input GTREFCLK01; + input GTREFCLK10; + input GTREFCLK11; + input GTSOUTHREFCLK00; + input GTSOUTHREFCLK01; + input GTSOUTHREFCLK10; + input GTSOUTHREFCLK11; + input [2:0] PCIERATEQPLL0; + input [2:0] PCIERATEQPLL1; + input [7:0] PMARSVD0; + input [7:0] PMARSVD1; + input QPLL0CLKRSVD0; + input QPLL0CLKRSVD1; + input [7:0] QPLL0FBDIV; + input QPLL0LOCKDETCLK; + input QPLL0LOCKEN; + input QPLL0PD; + input [2:0] QPLL0REFCLKSEL; + input QPLL0RESET; + input QPLL1CLKRSVD0; + input QPLL1CLKRSVD1; + input [7:0] QPLL1FBDIV; + input QPLL1LOCKDETCLK; + input QPLL1LOCKEN; + input QPLL1PD; + input [2:0] QPLL1REFCLKSEL; + input QPLL1RESET; + input [7:0] QPLLRSVD1; + input [4:0] QPLLRSVD2; + input [4:0] QPLLRSVD3; + input [7:0] QPLLRSVD4; + input RCALENB; + input [24:0] SDM0DATA; + input SDM0RESET; + input SDM0TOGGLE; + input [1:0] SDM0WIDTH; + input [24:0] SDM1DATA; + input SDM1RESET; + input SDM1TOGGLE; + input [1:0] SDM1WIDTH; + input UBCFGSTREAMEN; + input [15:0] UBDO; + input UBDRDY; + input UBENABLE; + input [1:0] UBGPI; + input [1:0] UBINTR; + input UBIOLMBRST; + input UBMBRST; + input UBMDMCAPTURE; + input UBMDMDBGRST; + input UBMDMDBGUPDATE; + input [3:0] UBMDMREGEN; + input UBMDMSHIFT; + input UBMDMSYSRST; + input UBMDMTCK; + input UBMDMTDI; +endmodule + +module IBUFDS_GTE3 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; + parameter [1:0] REFCLK_ICNTL_RX = 2'b00; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module IBUFDS_GTE4 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; + parameter [1:0] REFCLK_ICNTL_RX = 2'b00; + output O; + output ODIV2; + input CEB; + (* iopad_external_pin *) + input I; + (* iopad_external_pin *) + input IB; +endmodule + +module OBUFDS_GTE3 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input I; +endmodule + +module OBUFDS_GTE3_ADV (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input [3:0] I; + input [1:0] RXRECCLK_SEL; +endmodule + +module OBUFDS_GTE4 (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input I; +endmodule + +module OBUFDS_GTE4_ADV (...); + parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; + parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; + (* iopad_external_pin *) + output O; + (* iopad_external_pin *) + output OB; + input CEB; + input [3:0] I; + input [1:0] RXRECCLK_SEL; +endmodule + +module PCIE_A1 (...); + parameter [31:0] BAR0 = 32'h00000000; + parameter [31:0] BAR1 = 32'h00000000; + parameter [31:0] BAR2 = 32'h00000000; + parameter [31:0] BAR3 = 32'h00000000; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 7; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter [21:0] EXPANSION_ROM = 22'h000000; + parameter FAST_TRAIN = "FALSE"; + parameter integer GTP_SEL = 0; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter integer LINK_CAP_L0S_EXIT_LATENCY = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY = 7; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0204; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h060D; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h1; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'b00000; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter [11:0] PCIE_GENERIC = 12'h000; + parameter PLM_AUTO_CONFIG = "FALSE"; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'b01111; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_VERSION = 3; + parameter [7:0] PM_DATA0 = 8'h1E; + parameter [7:0] PM_DATA1 = 8'h1E; + parameter [7:0] PM_DATA2 = 8'h1E; + parameter [7:0] PM_DATA3 = 8'h1E; + parameter [7:0] PM_DATA4 = 8'h1E; + parameter [7:0] PM_DATA5 = 8'h1E; + parameter [7:0] PM_DATA6 = 8'h1E; + parameter [7:0] PM_DATA7 = 8'h1E; + parameter [1:0] PM_DATA_SCALE0 = 2'b01; + parameter [1:0] PM_DATA_SCALE1 = 2'b01; + parameter [1:0] PM_DATA_SCALE2 = 2'b01; + parameter [1:0] PM_DATA_SCALE3 = 2'b01; + parameter [1:0] PM_DATA_SCALE4 = 2'b01; + parameter [1:0] PM_DATA_SCALE5 = 2'b01; + parameter [1:0] PM_DATA_SCALE6 = 2'b01; + parameter [1:0] PM_DATA_SCALE7 = 2'b01; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 1; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter USR_CFG = "FALSE"; + parameter USR_EXT_CFG = "FALSE"; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [11:0] VC0_RX_RAM_LIMIT = 12'h01E; + parameter integer VC0_TOTAL_CREDITS_CD = 104; + parameter integer VC0_TOTAL_CREDITS_CH = 36; + parameter integer VC0_TOTAL_CREDITS_NPH = 8; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTRDYN; + output CFGLINKCONTOLRCB; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGRDWRDONEN; + output CFGTOTURNOFFN; + output DBGBADDLLPSTATUS; + output DBGBADTLPLCRC; + output DBGBADTLPSEQNUM; + output DBGBADTLPSTATUS; + output DBGDLPROTOCOLSTATUS; + output DBGFCPROTOCOLERRSTATUS; + output DBGMLFRMDLENGTH; + output DBGMLFRMDMPS; + output DBGMLFRMDTCVC; + output DBGMLFRMDTLPSTATUS; + output DBGMLFRMDUNRECTYPE; + output DBGPOISTLPSTATUS; + output DBGRCVROVERFLOWSTATUS; + output DBGREGDETECTEDCORRECTABLE; + output DBGREGDETECTEDFATAL; + output DBGREGDETECTEDNONFATAL; + output DBGREGDETECTEDUNSUPPORTED; + output DBGRPLYROLLOVERSTATUS; + output DBGRPLYTIMEOUTSTATUS; + output DBGURNOBARHIT; + output DBGURPOISCFGWR; + output DBGURSTATUS; + output DBGURUNSUPMSG; + output MIMRXREN; + output MIMRXWEN; + output MIMTXREN; + output MIMTXWEN; + output PIPEGTTXELECIDLEA; + output PIPEGTTXELECIDLEB; + output PIPERXPOLARITYA; + output PIPERXPOLARITYB; + output PIPERXRESETA; + output PIPERXRESETB; + output PIPETXRCVRDETA; + output PIPETXRCVRDETB; + output RECEIVEDHOTRESET; + output TRNLNKUPN; + output TRNREOFN; + output TRNRERRFWDN; + output TRNRSOFN; + output TRNRSRCDSCN; + output TRNRSRCRDYN; + output TRNTCFGREQN; + output TRNTDSTRDYN; + output TRNTERRDROPN; + output USERRSTN; + output [11:0] MIMRXRADDR; + output [11:0] MIMRXWADDR; + output [11:0] MIMTXRADDR; + output [11:0] MIMTXWADDR; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [15:0] PIPETXDATAA; + output [15:0] PIPETXDATAB; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] PIPEGTPOWERDOWNA; + output [1:0] PIPEGTPOWERDOWNB; + output [1:0] PIPETXCHARDISPMODEA; + output [1:0] PIPETXCHARDISPMODEB; + output [1:0] PIPETXCHARDISPVALA; + output [1:0] PIPETXCHARDISPVALB; + output [1:0] PIPETXCHARISKA; + output [1:0] PIPETXCHARISKB; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGFUNCTIONNUMBER; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATEN; + output [31:0] CFGDO; + output [31:0] TRNRD; + output [34:0] MIMRXWDATA; + output [35:0] MIMTXWDATA; + output [4:0] CFGDEVICENUMBER; + output [4:0] CFGLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [6:0] TRNRBARHITN; + output [7:0] CFGBUSNUMBER; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRECRCN; + input CFGERRLOCKEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGPMWAKEN; + input CFGRDENN; + input CFGTRNPENDINGN; + input CFGTURNOFFOKN; + input CLOCKLOCKED; + input MGTCLK; + input PIPEGTRESETDONEA; + input PIPEGTRESETDONEB; + input PIPEPHYSTATUSA; + input PIPEPHYSTATUSB; + input PIPERXENTERELECIDLEA; + input PIPERXENTERELECIDLEB; + input SYSRESETN; + input TRNRDSTRDYN; + input TRNRNPOKN; + input TRNTCFGGNTN; + input TRNTEOFN; + input TRNTERRFWDN; + input TRNTSOFN; + input TRNTSRCDSCN; + input TRNTSRCRDYN; + input TRNTSTRN; + input USERCLK; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENID; + input [15:0] CFGVENID; + input [15:0] PIPERXDATAA; + input [15:0] PIPERXDATAB; + input [1:0] PIPERXCHARISKA; + input [1:0] PIPERXCHARISKB; + input [2:0] PIPERXSTATUSA; + input [2:0] PIPERXSTATUSB; + input [2:0] TRNFCSEL; + input [31:0] TRNTD; + input [34:0] MIMRXRDATA; + input [35:0] MIMTXRDATA; + input [47:0] CFGERRTLPCPLHEADER; + input [63:0] CFGDSN; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGREVID; + input [9:0] CFGDWADDR; +endmodule + +module PCIE_EP (...); + parameter BAR0EXIST = "TRUE"; + parameter BAR0PREFETCHABLE = "TRUE"; + parameter BAR1EXIST = "FALSE"; + parameter BAR1PREFETCHABLE = "FALSE"; + parameter BAR2EXIST = "FALSE"; + parameter BAR2PREFETCHABLE = "FALSE"; + parameter BAR3EXIST = "FALSE"; + parameter BAR3PREFETCHABLE = "FALSE"; + parameter BAR4EXIST = "FALSE"; + parameter BAR4PREFETCHABLE = "FALSE"; + parameter BAR5EXIST = "FALSE"; + parameter BAR5PREFETCHABLE = "FALSE"; + parameter CLKDIVIDED = "FALSE"; + parameter INFINITECOMPLETIONS = "TRUE"; + parameter LINKSTATUSSLOTCLOCKCONFIG = "FALSE"; + parameter PBCAPABILITYSYSTEMALLOCATED = "FALSE"; + parameter PMCAPABILITYD1SUPPORT = "FALSE"; + parameter PMCAPABILITYD2SUPPORT = "FALSE"; + parameter PMCAPABILITYDSI = "TRUE"; + parameter RESETMODE = "FALSE"; + parameter [10:0] VC0TOTALCREDITSCD = 11'h0; + parameter [10:0] VC0TOTALCREDITSPD = 11'h34; + parameter [10:0] VC1TOTALCREDITSCD = 11'h0; + parameter [10:0] VC1TOTALCREDITSPD = 11'h0; + parameter [11:0] AERBASEPTR = 12'h110; + parameter [11:0] AERCAPABILITYNEXTPTR = 12'h138; + parameter [11:0] DSNBASEPTR = 12'h148; + parameter [11:0] DSNCAPABILITYNEXTPTR = 12'h154; + parameter [11:0] MSIBASEPTR = 12'h48; + parameter [11:0] PBBASEPTR = 12'h138; + parameter [11:0] PBCAPABILITYNEXTPTR = 12'h148; + parameter [11:0] PMBASEPTR = 12'h40; + parameter [11:0] RETRYRAMSIZE = 12'h9; + parameter [11:0] VCBASEPTR = 12'h154; + parameter [11:0] VCCAPABILITYNEXTPTR = 12'h0; + parameter [12:0] VC0RXFIFOBASEC = 13'h98; + parameter [12:0] VC0RXFIFOBASENP = 13'h80; + parameter [12:0] VC0RXFIFOBASEP = 13'h0; + parameter [12:0] VC0RXFIFOLIMITC = 13'h117; + parameter [12:0] VC0RXFIFOLIMITNP = 13'h97; + parameter [12:0] VC0RXFIFOLIMITP = 13'h7f; + parameter [12:0] VC0TXFIFOBASEC = 13'h98; + parameter [12:0] VC0TXFIFOBASENP = 13'h80; + parameter [12:0] VC0TXFIFOBASEP = 13'h0; + parameter [12:0] VC0TXFIFOLIMITC = 13'h117; + parameter [12:0] VC0TXFIFOLIMITNP = 13'h97; + parameter [12:0] VC0TXFIFOLIMITP = 13'h7f; + parameter [12:0] VC1RXFIFOBASEC = 13'h118; + parameter [12:0] VC1RXFIFOBASENP = 13'h118; + parameter [12:0] VC1RXFIFOBASEP = 13'h118; + parameter [12:0] VC1RXFIFOLIMITC = 13'h118; + parameter [12:0] VC1RXFIFOLIMITNP = 13'h118; + parameter [12:0] VC1RXFIFOLIMITP = 13'h118; + parameter [12:0] VC1TXFIFOBASEC = 13'h118; + parameter [12:0] VC1TXFIFOBASENP = 13'h118; + parameter [12:0] VC1TXFIFOBASEP = 13'h118; + parameter [12:0] VC1TXFIFOLIMITC = 13'h118; + parameter [12:0] VC1TXFIFOLIMITNP = 13'h118; + parameter [12:0] VC1TXFIFOLIMITP = 13'h118; + parameter [15:0] DEVICEID = 16'h5050; + parameter [15:0] SUBSYSTEMID = 16'h5050; + parameter [15:0] SUBSYSTEMVENDORID = 16'h10EE; + parameter [15:0] VENDORID = 16'h10EE; + parameter [1:0] LINKCAPABILITYASPMSUPPORT = 2'h1; + parameter [1:0] PBCAPABILITYDW0DATASCALE = 2'h0; + parameter [1:0] PBCAPABILITYDW0PMSTATE = 2'h0; + parameter [1:0] PBCAPABILITYDW1DATASCALE = 2'h0; + parameter [1:0] PBCAPABILITYDW1PMSTATE = 2'h0; + parameter [1:0] PBCAPABILITYDW2DATASCALE = 2'h0; + parameter [1:0] PBCAPABILITYDW2PMSTATE = 2'h0; + parameter [1:0] PBCAPABILITYDW3DATASCALE = 2'h0; + parameter [1:0] PBCAPABILITYDW3PMSTATE = 2'h0; + parameter [23:0] CLASSCODE = 24'h058000; + parameter [2:0] DEVICECAPABILITYENDPOINTL0SLATENCY = 3'h0; + parameter [2:0] DEVICECAPABILITYENDPOINTL1LATENCY = 3'h0; + parameter [2:0] MSICAPABILITYMULTIMSGCAP = 3'h0; + parameter [2:0] PBCAPABILITYDW0PMSUBSTATE = 3'h0; + parameter [2:0] PBCAPABILITYDW0POWERRAIL = 3'h0; + parameter [2:0] PBCAPABILITYDW0TYPE = 3'h0; + parameter [2:0] PBCAPABILITYDW1PMSUBSTATE = 3'h0; + parameter [2:0] PBCAPABILITYDW1POWERRAIL = 3'h0; + parameter [2:0] PBCAPABILITYDW1TYPE = 3'h0; + parameter [2:0] PBCAPABILITYDW2PMSUBSTATE = 3'h0; + parameter [2:0] PBCAPABILITYDW2POWERRAIL = 3'h0; + parameter [2:0] PBCAPABILITYDW2TYPE = 3'h0; + parameter [2:0] PBCAPABILITYDW3PMSUBSTATE = 3'h0; + parameter [2:0] PBCAPABILITYDW3POWERRAIL = 3'h0; + parameter [2:0] PBCAPABILITYDW3TYPE = 3'h0; + parameter [2:0] PMCAPABILITYAUXCURRENT = 3'h0; + parameter [2:0] PORTVCCAPABILITYEXTENDEDVCCOUNT = 3'h0; + parameter [31:0] CARDBUSCISPOINTER = 32'h0; + parameter [3:0] XPDEVICEPORTTYPE = 4'h0; + parameter [4:0] PMCAPABILITYPMESUPPORT = 5'h0; + parameter [5:0] BAR0MASKWIDTH = 6'h14; + parameter [5:0] BAR1MASKWIDTH = 6'h0; + parameter [5:0] BAR2MASKWIDTH = 6'h0; + parameter [5:0] BAR3MASKWIDTH = 6'h0; + parameter [5:0] BAR4MASKWIDTH = 6'h0; + parameter [5:0] BAR5MASKWIDTH = 6'h0; + parameter [5:0] LINKCAPABILITYMAXLINKWIDTH = 6'h01; + parameter [63:0] DEVICESERIALNUMBER = 64'hE000000001000A35; + parameter [6:0] VC0TOTALCREDITSCH = 7'h0; + parameter [6:0] VC0TOTALCREDITSNPH = 7'h08; + parameter [6:0] VC0TOTALCREDITSPH = 7'h08; + parameter [6:0] VC1TOTALCREDITSCH = 7'h0; + parameter [6:0] VC1TOTALCREDITSNPH = 7'h0; + parameter [6:0] VC1TOTALCREDITSPH = 7'h0; + parameter [7:0] ACTIVELANESIN = 8'h1; + parameter [7:0] CAPABILITIESPOINTER = 8'h40; + parameter [7:0] INTERRUPTPIN = 8'h0; + parameter [7:0] MSICAPABILITYNEXTPTR = 8'h60; + parameter [7:0] PBCAPABILITYDW0BASEPOWER = 8'h0; + parameter [7:0] PBCAPABILITYDW1BASEPOWER = 8'h0; + parameter [7:0] PBCAPABILITYDW2BASEPOWER = 8'h0; + parameter [7:0] PBCAPABILITYDW3BASEPOWER = 8'h0; + parameter [7:0] PCIECAPABILITYNEXTPTR = 8'h0; + parameter [7:0] PMCAPABILITYNEXTPTR = 8'h60; + parameter [7:0] PMDATA0 = 8'h0; + parameter [7:0] PMDATA1 = 8'h0; + parameter [7:0] PMDATA2 = 8'h0; + parameter [7:0] PMDATA3 = 8'h0; + parameter [7:0] PMDATA4 = 8'h0; + parameter [7:0] PMDATA5 = 8'h0; + parameter [7:0] PMDATA6 = 8'h0; + parameter [7:0] PMDATA7 = 8'h0; + parameter [7:0] PORTVCCAPABILITYVCARBCAP = 8'h0; + parameter [7:0] PORTVCCAPABILITYVCARBTABLEOFFSET = 8'h0; + parameter [7:0] REVISIONID = 8'h0; + parameter [7:0] XPBASEPTR = 8'h60; + parameter BAR0ADDRWIDTH = 0; + parameter BAR0IOMEMN = 0; + parameter BAR1ADDRWIDTH = 0; + parameter BAR1IOMEMN = 0; + parameter BAR2ADDRWIDTH = 0; + parameter BAR2IOMEMN = 0; + parameter BAR3ADDRWIDTH = 0; + parameter BAR3IOMEMN = 0; + parameter BAR4ADDRWIDTH = 0; + parameter BAR4IOMEMN = 0; + parameter BAR5IOMEMN = 0; + parameter L0SEXITLATENCY = 7; + parameter L0SEXITLATENCYCOMCLK = 7; + parameter L1EXITLATENCY = 7; + parameter L1EXITLATENCYCOMCLK = 7; + parameter LOWPRIORITYVCCOUNT = 0; + parameter PMDATASCALE0 = 0; + parameter PMDATASCALE1 = 0; + parameter PMDATASCALE2 = 0; + parameter PMDATASCALE3 = 0; + parameter PMDATASCALE4 = 0; + parameter PMDATASCALE5 = 0; + parameter PMDATASCALE6 = 0; + parameter PMDATASCALE7 = 0; + parameter RETRYRAMREADLATENCY = 3; + parameter RETRYRAMWRITELATENCY = 1; + parameter TLRAMREADLATENCY = 3; + parameter TLRAMWRITELATENCY = 1; + parameter TXTSNFTS = 255; + parameter TXTSNFTSCOMCLK = 255; + parameter XPMAXPAYLOAD = 0; + output BUSMASTERENABLE; + output CRMDOHOTRESETN; + output CRMPWRSOFTRESETN; + output DLLTXPMDLLPOUTSTANDING; + output INTERRUPTDISABLE; + output IOSPACEENABLE; + output L0CFGLOOPBACKACK; + output L0DLLRXACKOUTSTANDING; + output L0DLLTXNONFCOUTSTANDING; + output L0DLLTXOUTSTANDING; + output L0FIRSTCFGWRITEOCCURRED; + output L0MACENTEREDL0; + output L0MACLINKTRAINING; + output L0MACLINKUP; + output L0MACNEWSTATEACK; + output L0MACRXL0SSTATE; + output L0MSIENABLE0; + output L0PMEACK; + output L0PMEEN; + output L0PMEREQOUT; + output L0PWRL1STATE; + output L0PWRL23READYSTATE; + output L0PWRTURNOFFREQ; + output L0PWRTXL0SSTATE; + output L0RXDLLPM; + output L0STATSCFGOTHERRECEIVED; + output L0STATSCFGOTHERTRANSMITTED; + output L0STATSCFGRECEIVED; + output L0STATSCFGTRANSMITTED; + output L0STATSDLLPRECEIVED; + output L0STATSDLLPTRANSMITTED; + output L0STATSOSRECEIVED; + output L0STATSOSTRANSMITTED; + output L0STATSTLPRECEIVED; + output L0STATSTLPTRANSMITTED; + output L0UNLOCKRECEIVED; + output LLKRXEOFN; + output LLKRXEOPN; + output LLKRXSOFN; + output LLKRXSOPN; + output LLKRXSRCLASTREQN; + output LLKRXSRCRDYN; + output LLKTXCONFIGREADYN; + output LLKTXDSTRDYN; + output MEMSPACEENABLE; + output MIMDLLBREN; + output MIMDLLBWEN; + output MIMRXBREN; + output MIMRXBWEN; + output MIMTXBREN; + output MIMTXBWEN; + output PARITYERRORRESPONSE; + output PIPEDESKEWLANESL0; + output PIPEDESKEWLANESL1; + output PIPEDESKEWLANESL2; + output PIPEDESKEWLANESL3; + output PIPEDESKEWLANESL4; + output PIPEDESKEWLANESL5; + output PIPEDESKEWLANESL6; + output PIPEDESKEWLANESL7; + output PIPERESETL0; + output PIPERESETL1; + output PIPERESETL2; + output PIPERESETL3; + output PIPERESETL4; + output PIPERESETL5; + output PIPERESETL6; + output PIPERESETL7; + output PIPERXPOLARITYL0; + output PIPERXPOLARITYL1; + output PIPERXPOLARITYL2; + output PIPERXPOLARITYL3; + output PIPERXPOLARITYL4; + output PIPERXPOLARITYL5; + output PIPERXPOLARITYL6; + output PIPERXPOLARITYL7; + output PIPETXCOMPLIANCEL0; + output PIPETXCOMPLIANCEL1; + output PIPETXCOMPLIANCEL2; + output PIPETXCOMPLIANCEL3; + output PIPETXCOMPLIANCEL4; + output PIPETXCOMPLIANCEL5; + output PIPETXCOMPLIANCEL6; + output PIPETXCOMPLIANCEL7; + output PIPETXDATAKL0; + output PIPETXDATAKL1; + output PIPETXDATAKL2; + output PIPETXDATAKL3; + output PIPETXDATAKL4; + output PIPETXDATAKL5; + output PIPETXDATAKL6; + output PIPETXDATAKL7; + output PIPETXDETECTRXLOOPBACKL0; + output PIPETXDETECTRXLOOPBACKL1; + output PIPETXDETECTRXLOOPBACKL2; + output PIPETXDETECTRXLOOPBACKL3; + output PIPETXDETECTRXLOOPBACKL4; + output PIPETXDETECTRXLOOPBACKL5; + output PIPETXDETECTRXLOOPBACKL6; + output PIPETXDETECTRXLOOPBACKL7; + output PIPETXELECIDLEL0; + output PIPETXELECIDLEL1; + output PIPETXELECIDLEL2; + output PIPETXELECIDLEL3; + output PIPETXELECIDLEL4; + output PIPETXELECIDLEL5; + output PIPETXELECIDLEL6; + output PIPETXELECIDLEL7; + output SERRENABLE; + output URREPORTINGENABLE; + output [11:0] MGMTSTATSCREDIT; + output [11:0] MIMDLLBRADD; + output [11:0] MIMDLLBWADD; + output [12:0] L0COMPLETERID; + output [12:0] MIMRXBRADD; + output [12:0] MIMRXBWADD; + output [12:0] MIMTXBRADD; + output [12:0] MIMTXBWADD; + output [15:0] LLKRXPREFERREDTYPE; + output [16:0] MGMTPSO; + output [1:0] L0PWRSTATE0; + output [1:0] L0RXMACLINKERROR; + output [1:0] LLKRXVALIDN; + output [1:0] PIPEPOWERDOWNL0; + output [1:0] PIPEPOWERDOWNL1; + output [1:0] PIPEPOWERDOWNL2; + output [1:0] PIPEPOWERDOWNL3; + output [1:0] PIPEPOWERDOWNL4; + output [1:0] PIPEPOWERDOWNL5; + output [1:0] PIPEPOWERDOWNL6; + output [1:0] PIPEPOWERDOWNL7; + output [2:0] L0MULTIMSGEN0; + output [2:0] L0RXDLLPMTYPE; + output [2:0] MAXPAYLOADSIZE; + output [2:0] MAXREADREQUESTSIZE; + output [31:0] MGMTRDATA; + output [3:0] L0LTSSMSTATE; + output [3:0] L0MACNEGOTIATEDLINKWIDTH; + output [63:0] LLKRXDATA; + output [63:0] MIMDLLBWDATA; + output [63:0] MIMRXBWDATA; + output [63:0] MIMTXBWDATA; + output [6:0] L0DLLERRORVECTOR; + output [7:0] L0DLLVCSTATUS; + output [7:0] L0DLUPDOWN; + output [7:0] LLKRXCHCOMPLETIONAVAILABLEN; + output [7:0] LLKRXCHNONPOSTEDAVAILABLEN; + output [7:0] LLKRXCHPOSTEDAVAILABLEN; + output [7:0] LLKTCSTATUS; + output [7:0] LLKTXCHCOMPLETIONREADYN; + output [7:0] LLKTXCHNONPOSTEDREADYN; + output [7:0] LLKTXCHPOSTEDREADYN; + output [7:0] PIPETXDATAL0; + output [7:0] PIPETXDATAL1; + output [7:0] PIPETXDATAL2; + output [7:0] PIPETXDATAL3; + output [7:0] PIPETXDATAL4; + output [7:0] PIPETXDATAL5; + output [7:0] PIPETXDATAL6; + output [7:0] PIPETXDATAL7; + output [9:0] LLKTXCHANSPACE; + input AUXPOWER; + input COMPLIANCEAVOID; + input CRMCORECLK; + input CRMCORECLKDLO; + input CRMCORECLKRXO; + input CRMCORECLKTXO; + input CRMLINKRSTN; + input CRMMACRSTN; + input CRMMGMTRSTN; + input CRMNVRSTN; + input CRMURSTN; + input CRMUSERCFGRSTN; + input CRMUSERCLK; + input CRMUSERCLKRXO; + input CRMUSERCLKTXO; + input L0CFGDISABLESCRAMBLE; + input L0CFGLOOPBACKMASTER; + input L0LEGACYINTFUNCT0; + input L0PMEREQIN; + input L0SETCOMPLETERABORTERROR; + input L0SETCOMPLETIONTIMEOUTCORRERROR; + input L0SETCOMPLETIONTIMEOUTUNCORRERROR; + input L0SETDETECTEDCORRERROR; + input L0SETDETECTEDFATALERROR; + input L0SETDETECTEDNONFATALERROR; + input L0SETUNEXPECTEDCOMPLETIONCORRERROR; + input L0SETUNEXPECTEDCOMPLETIONUNCORRERROR; + input L0SETUNSUPPORTEDREQUESTNONPOSTEDERROR; + input L0SETUNSUPPORTEDREQUESTOTHERERROR; + input L0SETUSERDETECTEDPARITYERROR; + input L0SETUSERMASTERDATAPARITY; + input L0SETUSERRECEIVEDMASTERABORT; + input L0SETUSERRECEIVEDTARGETABORT; + input L0SETUSERSIGNALLEDTARGETABORT; + input L0SETUSERSYSTEMERROR; + input L0TRANSACTIONSPENDING; + input LLKRXDSTCONTREQN; + input LLKRXDSTREQN; + input LLKTXEOFN; + input LLKTXEOPN; + input LLKTXSOFN; + input LLKTXSOPN; + input LLKTXSRCDSCN; + input LLKTXSRCRDYN; + input MGMTRDEN; + input MGMTWREN; + input PIPEPHYSTATUSL0; + input PIPEPHYSTATUSL1; + input PIPEPHYSTATUSL2; + input PIPEPHYSTATUSL3; + input PIPEPHYSTATUSL4; + input PIPEPHYSTATUSL5; + input PIPEPHYSTATUSL6; + input PIPEPHYSTATUSL7; + input PIPERXCHANISALIGNEDL0; + input PIPERXCHANISALIGNEDL1; + input PIPERXCHANISALIGNEDL2; + input PIPERXCHANISALIGNEDL3; + input PIPERXCHANISALIGNEDL4; + input PIPERXCHANISALIGNEDL5; + input PIPERXCHANISALIGNEDL6; + input PIPERXCHANISALIGNEDL7; + input PIPERXDATAKL0; + input PIPERXDATAKL1; + input PIPERXDATAKL2; + input PIPERXDATAKL3; + input PIPERXDATAKL4; + input PIPERXDATAKL5; + input PIPERXDATAKL6; + input PIPERXDATAKL7; + input PIPERXELECIDLEL0; + input PIPERXELECIDLEL1; + input PIPERXELECIDLEL2; + input PIPERXELECIDLEL3; + input PIPERXELECIDLEL4; + input PIPERXELECIDLEL5; + input PIPERXELECIDLEL6; + input PIPERXELECIDLEL7; + input PIPERXVALIDL0; + input PIPERXVALIDL1; + input PIPERXVALIDL2; + input PIPERXVALIDL3; + input PIPERXVALIDL4; + input PIPERXVALIDL5; + input PIPERXVALIDL6; + input PIPERXVALIDL7; + input [10:0] MGMTADDR; + input [127:0] L0PACKETHEADERFROMUSER; + input [1:0] LLKRXCHFIFO; + input [1:0] LLKTXCHFIFO; + input [1:0] LLKTXENABLEN; + input [2:0] LLKRXCHTC; + input [2:0] LLKTXCHTC; + input [2:0] PIPERXSTATUSL0; + input [2:0] PIPERXSTATUSL1; + input [2:0] PIPERXSTATUSL2; + input [2:0] PIPERXSTATUSL3; + input [2:0] PIPERXSTATUSL4; + input [2:0] PIPERXSTATUSL5; + input [2:0] PIPERXSTATUSL6; + input [2:0] PIPERXSTATUSL7; + input [31:0] MGMTWDATA; + input [3:0] L0MSIREQUEST0; + input [3:0] MGMTBWREN; + input [63:0] LLKTXDATA; + input [63:0] MIMDLLBRDATA; + input [63:0] MIMRXBRDATA; + input [63:0] MIMTXBRDATA; + input [6:0] MGMTSTATSCREDITSEL; + input [7:0] PIPERXDATAL0; + input [7:0] PIPERXDATAL1; + input [7:0] PIPERXDATAL2; + input [7:0] PIPERXDATAL3; + input [7:0] PIPERXDATAL4; + input [7:0] PIPERXDATAL5; + input [7:0] PIPERXDATAL6; + input [7:0] PIPERXDATAL7; +endmodule + +module PCIE_2_0 (...); + parameter [11:0] AER_BASE_PTR = 12'h128; + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [15:0] AER_CAP_ID = 16'h0001; + parameter [4:0] AER_CAP_INT_MSG_NUM_MSI = 5'h0A; + parameter [4:0] AER_CAP_INT_MSG_NUM_MSIX = 5'h15; + parameter [11:0] AER_CAP_NEXTPTR = 12'h160; + parameter AER_CAP_ON = "FALSE"; + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; + parameter [3:0] AER_CAP_VERSION = 4'h1; + parameter ALLOW_X8_GEN2 = "FALSE"; + parameter [31:0] BAR0 = 32'hFFFFFF00; + parameter [31:0] BAR1 = 32'hFFFF0000; + parameter [31:0] BAR2 = 32'hFFFF000C; + parameter [31:0] BAR3 = 32'hFFFFFFFF; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [7:0] CAPABILITIES_PTR = 8'h40; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter CMD_INTX_IMPLEMENTED = "TRUE"; + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; + parameter [6:0] CRM_MODULE_RSTS = 7'h00; + parameter [15:0] DEVICE_ID = 16'h0007; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter integer DEV_CAP_RSVD_14_12 = 0; + parameter integer DEV_CAP_RSVD_17_16 = 0; + parameter integer DEV_CAP_RSVD_31_29 = 0; + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; + parameter DISABLE_ASPM_L1_TIMER = "FALSE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_LANE_REVERSAL = "FALSE"; + parameter DISABLE_RX_TC_FILTER = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [11:0] DSN_BASE_PTR = 12'h100; + parameter [15:0] DSN_CAP_ID = 16'h0003; + parameter [11:0] DSN_CAP_NEXTPTR = 12'h000; + parameter DSN_CAP_ON = "TRUE"; + parameter [3:0] DSN_CAP_VERSION = 4'h1; + parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter ENTER_RVRY_EI_L0 = "TRUE"; + parameter EXIT_LOOPBACK_ON_EI = "TRUE"; + parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; + parameter [7:0] HEADER_TYPE = 8'h00; + parameter [4:0] INFER_EI = 5'h00; + parameter [7:0] INTERRUPT_PIN = 8'h01; + parameter IS_SWITCH = "FALSE"; + parameter [9:0] LAST_CONFIG_DWORD = 10'h042; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; + parameter integer LINK_CAP_RSVD_23_22 = 0; + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; + parameter integer LINK_CONTROL_RCB = 0; + parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; + parameter [7:0] MSIX_BASE_PTR = 8'h9C; + parameter [7:0] MSIX_CAP_ID = 8'h11; + parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; + parameter MSIX_CAP_ON = "FALSE"; + parameter integer MSIX_CAP_PBA_BIR = 0; + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] MSI_BASE_PTR = 8'h48; + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; + parameter [7:0] MSI_CAP_ID = 8'h05; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; + parameter MSI_CAP_ON = "FALSE"; + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; + parameter integer N_FTS_COMCLK_GEN1 = 255; + parameter integer N_FTS_COMCLK_GEN2 = 255; + parameter integer N_FTS_GEN1 = 255; + parameter integer N_FTS_GEN2 = 255; + parameter [7:0] PCIE_BASE_PTR = 8'h60; + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'h00; + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00; + parameter PCIE_CAP_ON = "TRUE"; + parameter integer PCIE_CAP_RSVD_15_14 = 0; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter integer PCIE_REVISION = 2; + parameter integer PGL0_LANE = 0; + parameter integer PGL1_LANE = 1; + parameter integer PGL2_LANE = 2; + parameter integer PGL3_LANE = 3; + parameter integer PGL4_LANE = 4; + parameter integer PGL5_LANE = 5; + parameter integer PGL6_LANE = 6; + parameter integer PGL7_LANE = 7; + parameter integer PL_AUTO_CONFIG = 0; + parameter PL_FAST_TRAIN = "FALSE"; + parameter [7:0] PM_BASE_PTR = 8'h40; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [7:0] PM_CAP_ID = 8'h01; + parameter [7:0] PM_CAP_NEXTPTR = 8'h48; + parameter PM_CAP_ON = "TRUE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_RSVD_04 = 0; + parameter integer PM_CAP_VERSION = 3; + parameter PM_CSR_B2B3 = "FALSE"; + parameter PM_CSR_BPCCEN = "FALSE"; + parameter PM_CSR_NOSOFTRST = "TRUE"; + parameter [7:0] PM_DATA0 = 8'h01; + parameter [7:0] PM_DATA1 = 8'h01; + parameter [7:0] PM_DATA2 = 8'h01; + parameter [7:0] PM_DATA3 = 8'h01; + parameter [7:0] PM_DATA4 = 8'h01; + parameter [7:0] PM_DATA5 = 8'h01; + parameter [7:0] PM_DATA6 = 8'h01; + parameter [7:0] PM_DATA7 = 8'h01; + parameter [1:0] PM_DATA_SCALE0 = 2'h1; + parameter [1:0] PM_DATA_SCALE1 = 2'h1; + parameter [1:0] PM_DATA_SCALE2 = 2'h1; + parameter [1:0] PM_DATA_SCALE3 = 2'h1; + parameter [1:0] PM_DATA_SCALE4 = 2'h1; + parameter [1:0] PM_DATA_SCALE5 = 2'h1; + parameter [1:0] PM_DATA_SCALE6 = 2'h1; + parameter [1:0] PM_DATA_SCALE7 = 2'h1; + parameter integer RECRC_CHK = 0; + parameter RECRC_CHK_TRIM = "FALSE"; + parameter [7:0] REVISION_ID = 8'h00; + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; + parameter SELECT_DLL_IF = "FALSE"; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter [15:0] SUBSYSTEM_ID = 16'h0007; + parameter [15:0] SUBSYSTEM_VENDOR_ID = 16'h10EE; + parameter TL_RBYPASS = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 0; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter integer TL_TX_RAM_WRITE_LATENCY = 0; + parameter UPCONFIG_CAPABLE = "TRUE"; + parameter UPSTREAM_FACING = "TRUE"; + parameter UR_INV_REQ = "TRUE"; + parameter integer USER_CLK_FREQ = 3; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; + parameter integer VC0_TOTAL_CREDITS_CD = 127; + parameter integer VC0_TOTAL_CREDITS_CH = 31; + parameter integer VC0_TOTAL_CREDITS_NPH = 12; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + parameter [11:0] VC_BASE_PTR = 12'h10C; + parameter [15:0] VC_CAP_ID = 16'h0002; + parameter [11:0] VC_CAP_NEXTPTR = 12'h000; + parameter VC_CAP_ON = "FALSE"; + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; + parameter [3:0] VC_CAP_VERSION = 4'h1; + parameter [15:0] VENDOR_ID = 16'h10EE; + parameter [11:0] VSEC_BASE_PTR = 12'h160; + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; + parameter [15:0] VSEC_CAP_ID = 16'h000B; + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000; + parameter VSEC_CAP_ON = "FALSE"; + parameter [3:0] VSEC_CAP_VERSION = 4'h1; + output CFGAERECRCCHECKEN; + output CFGAERECRCGENEN; + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROL2CPLTIMEOUTDIS; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRAERHEADERLOGSETN; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIXENABLE; + output CFGINTERRUPTMSIXFM; + output CFGINTERRUPTRDYN; + output CFGLINKCONTROLAUTOBANDWIDTHINTEN; + output CFGLINKCONTROLBANDWIDTHINTEN; + output CFGLINKCONTROLCLOCKPMEN; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGLINKCONTROLHWAUTOWIDTHDIS; + output CFGLINKCONTROLLINKDISABLE; + output CFGLINKCONTROLRCB; + output CFGLINKCONTROLRETRAINLINK; + output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + output CFGLINKSTATUSBANDWITHSTATUS; + output CFGLINKSTATUSDLLACTIVE; + output CFGLINKSTATUSLINKTRAINING; + output CFGMSGRECEIVED; + output CFGMSGRECEIVEDASSERTINTA; + output CFGMSGRECEIVEDASSERTINTB; + output CFGMSGRECEIVEDASSERTINTC; + output CFGMSGRECEIVEDASSERTINTD; + output CFGMSGRECEIVEDDEASSERTINTA; + output CFGMSGRECEIVEDDEASSERTINTB; + output CFGMSGRECEIVEDDEASSERTINTC; + output CFGMSGRECEIVEDDEASSERTINTD; + output CFGMSGRECEIVEDERRCOR; + output CFGMSGRECEIVEDERRFATAL; + output CFGMSGRECEIVEDERRNONFATAL; + output CFGMSGRECEIVEDPMASNAK; + output CFGMSGRECEIVEDPMETO; + output CFGMSGRECEIVEDPMETOACK; + output CFGMSGRECEIVEDPMPME; + output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + output CFGMSGRECEIVEDUNLOCK; + output CFGPMCSRPMEEN; + output CFGPMCSRPMESTATUS; + output CFGPMRCVASREQL1N; + output CFGPMRCVENTERL1N; + output CFGPMRCVENTERL23N; + output CFGPMRCVREQACKN; + output CFGRDWRDONEN; + output CFGSLOTCONTROLELECTROMECHILCTLPULSE; + output CFGTRANSACTION; + output CFGTRANSACTIONTYPE; + output DBGSCLRA; + output DBGSCLRB; + output DBGSCLRC; + output DBGSCLRD; + output DBGSCLRE; + output DBGSCLRF; + output DBGSCLRG; + output DBGSCLRH; + output DBGSCLRI; + output DBGSCLRJ; + output DBGSCLRK; + output DRPDRDY; + output LL2BADDLLPERRN; + output LL2BADTLPERRN; + output LL2PROTOCOLERRN; + output LL2REPLAYROERRN; + output LL2REPLAYTOERRN; + output LL2SUSPENDOKN; + output LL2TFCINIT1SEQN; + output LL2TFCINIT2SEQN; + output LNKCLKEN; + output MIMRXRCE; + output MIMRXREN; + output MIMRXWEN; + output MIMTXRCE; + output MIMTXREN; + output MIMTXWEN; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0ELECIDLE; + output PIPETX1COMPLIANCE; + output PIPETX1ELECIDLE; + output PIPETX2COMPLIANCE; + output PIPETX2ELECIDLE; + output PIPETX3COMPLIANCE; + output PIPETX3ELECIDLE; + output PIPETX4COMPLIANCE; + output PIPETX4ELECIDLE; + output PIPETX5COMPLIANCE; + output PIPETX5ELECIDLE; + output PIPETX6COMPLIANCE; + output PIPETX6ELECIDLE; + output PIPETX7COMPLIANCE; + output PIPETX7ELECIDLE; + output PIPETXDEEMPH; + output PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PL2LINKUPN; + output PL2RECEIVERERRN; + output PL2RECOVERYN; + output PL2RXELECIDLE; + output PL2SUSPENDOK; + output PLLINKGEN2CAP; + output PLLINKPARTNERGEN2SUPPORTED; + output PLLINKUPCFGCAP; + output PLPHYLNKUPN; + output PLRECEIVEDHOTRST; + output PLSELLNKRATE; + output RECEIVEDFUNCLVLRSTN; + output TL2ASPMSUSPENDCREDITCHECKOKN; + output TL2ASPMSUSPENDREQN; + output TL2PPMSUSPENDOKN; + output TRNLNKUPN; + output TRNRDLLPSRCRDYN; + output TRNRECRCERRN; + output TRNREOFN; + output TRNRERRFWDN; + output TRNRREMN; + output TRNRSOFN; + output TRNRSRCDSCN; + output TRNRSRCRDYN; + output TRNTCFGREQN; + output TRNTDLLPDSTRDYN; + output TRNTDSTRDYN; + output TRNTERRDROPN; + output USERRSTN; + output [11:0] DBGVECC; + output [11:0] PLDBGVEC; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [12:0] MIMRXRADDR; + output [12:0] MIMRXWADDR; + output [12:0] MIMTXRADDR; + output [12:0] MIMTXWADDR; + output [15:0] CFGMSGDATA; + output [15:0] DRPDO; + output [15:0] PIPETX0DATA; + output [15:0] PIPETX1DATA; + output [15:0] PIPETX2DATA; + output [15:0] PIPETX3DATA; + output [15:0] PIPETX4DATA; + output [15:0] PIPETX5DATA; + output [15:0] PIPETX6DATA; + output [15:0] PIPETX7DATA; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] CFGLINKSTATUSCURRENTSPEED; + output [1:0] CFGPMCSRPOWERSTATE; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PLLANEREVERSALMODE; + output [1:0] PLRXPMSTATE; + output [1:0] PLSELLNKWIDTH; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATE; + output [2:0] PIPETXMARGIN; + output [2:0] PLINITIALLINKWIDTH; + output [2:0] PLTXPMSTATE; + output [31:0] CFGDO; + output [31:0] TRNRDLLPDATA; + output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; + output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; + output [5:0] PLLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [63:0] DBGVECA; + output [63:0] DBGVECB; + output [63:0] TRNRD; + output [67:0] MIMRXWDATA; + output [68:0] MIMTXWDATA; + output [6:0] CFGTRANSACTIONADDR; + output [6:0] CFGVCTCVCMAP; + output [6:0] TRNRBARHITN; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + input CFGERRACSN; + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRCPLUNEXPECTN; + input CFGERRECRCN; + input CFGERRLOCKEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGPMDIRECTASPML1N; + input CFGPMSENDPMACKN; + input CFGPMSENDPMETON; + input CFGPMSENDPMNAKN; + input CFGPMTURNOFFOKN; + input CFGPMWAKEN; + input CFGRDENN; + input CFGTRNPENDINGN; + input CFGWRENN; + input CFGWRREADONLYN; + input CFGWRRW1CASRWN; + input CMRSTN; + input CMSTICKYRSTN; + input DBGSUBMODE; + input DLRSTN; + input DRPCLK; + input DRPDEN; + input DRPDWE; + input FUNCLVLRSTN; + input LL2SENDASREQL1N; + input LL2SENDENTERL1N; + input LL2SENDENTERL23N; + input LL2SUSPENDNOWN; + input LL2TLPRCVN; + input PIPECLK; + input PIPERX0CHANISALIGNED; + input PIPERX0ELECIDLE; + input PIPERX0PHYSTATUS; + input PIPERX0VALID; + input PIPERX1CHANISALIGNED; + input PIPERX1ELECIDLE; + input PIPERX1PHYSTATUS; + input PIPERX1VALID; + input PIPERX2CHANISALIGNED; + input PIPERX2ELECIDLE; + input PIPERX2PHYSTATUS; + input PIPERX2VALID; + input PIPERX3CHANISALIGNED; + input PIPERX3ELECIDLE; + input PIPERX3PHYSTATUS; + input PIPERX3VALID; + input PIPERX4CHANISALIGNED; + input PIPERX4ELECIDLE; + input PIPERX4PHYSTATUS; + input PIPERX4VALID; + input PIPERX5CHANISALIGNED; + input PIPERX5ELECIDLE; + input PIPERX5PHYSTATUS; + input PIPERX5VALID; + input PIPERX6CHANISALIGNED; + input PIPERX6ELECIDLE; + input PIPERX6PHYSTATUS; + input PIPERX6VALID; + input PIPERX7CHANISALIGNED; + input PIPERX7ELECIDLE; + input PIPERX7PHYSTATUS; + input PIPERX7VALID; + input PLDIRECTEDLINKAUTON; + input PLDIRECTEDLINKSPEED; + input PLDOWNSTREAMDEEMPHSOURCE; + input PLRSTN; + input PLTRANSMITHOTRST; + input PLUPSTREAMPREFERDEEMPH; + input SYSRSTN; + input TL2ASPMSUSPENDCREDITCHECKN; + input TL2PPMSUSPENDREQN; + input TLRSTN; + input TRNRDSTRDYN; + input TRNRNPOKN; + input TRNTCFGGNTN; + input TRNTDLLPSRCRDYN; + input TRNTECRCGENN; + input TRNTEOFN; + input TRNTERRFWDN; + input TRNTREMN; + input TRNTSOFN; + input TRNTSRCDSCN; + input TRNTSRCRDYN; + input TRNTSTRN; + input USERCLK; + input [127:0] CFGERRAERHEADERLOG; + input [15:0] DRPDI; + input [15:0] PIPERX0DATA; + input [15:0] PIPERX1DATA; + input [15:0] PIPERX2DATA; + input [15:0] PIPERX3DATA; + input [15:0] PIPERX4DATA; + input [15:0] PIPERX5DATA; + input [15:0] PIPERX6DATA; + input [15:0] PIPERX7DATA; + input [1:0] DBGMODE; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX7CHARISK; + input [1:0] PLDIRECTEDLINKCHANGE; + input [1:0] PLDIRECTEDLINKWIDTH; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [2:0] PLDBGMODE; + input [2:0] TRNFCSEL; + input [31:0] CFGDI; + input [31:0] TRNTDLLPDATA; + input [3:0] CFGBYTEENN; + input [47:0] CFGERRTLPCPLHEADER; + input [4:0] CFGDSDEVICENUMBER; + input [4:0] PL2DIRECTEDLSTATE; + input [63:0] CFGDSN; + input [63:0] TRNTD; + input [67:0] MIMRXRDATA; + input [68:0] MIMTXRDATA; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGPORTNUMBER; + input [8:0] DRPDADDR; + input [9:0] CFGDWADDR; +endmodule + +module PCIE_2_1 (...); + parameter [11:0] AER_BASE_PTR = 12'h140; + parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [15:0] AER_CAP_ID = 16'h0001; + parameter AER_CAP_MULTIHEADER = "FALSE"; + parameter [11:0] AER_CAP_NEXTPTR = 12'h178; + parameter AER_CAP_ON = "FALSE"; + parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000; + parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; + parameter [3:0] AER_CAP_VERSION = 4'h2; + parameter ALLOW_X8_GEN2 = "FALSE"; + parameter [31:0] BAR0 = 32'hFFFFFF00; + parameter [31:0] BAR1 = 32'hFFFF0000; + parameter [31:0] BAR2 = 32'hFFFF000C; + parameter [31:0] BAR3 = 32'hFFFFFFFF; + parameter [31:0] BAR4 = 32'h00000000; + parameter [31:0] BAR5 = 32'h00000000; + parameter [7:0] CAPABILITIES_PTR = 8'h40; + parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; + parameter integer CFG_ECRC_ERR_CPLSTAT = 0; + parameter [23:0] CLASS_CODE = 24'h000000; + parameter CMD_INTX_IMPLEMENTED = "TRUE"; + parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; + parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; + parameter [6:0] CRM_MODULE_RSTS = 7'h00; + parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE"; + parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE"; + parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE"; + parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE"; + parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE"; + parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0; + parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE"; + parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; + parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; + parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; + parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; + parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; + parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; + parameter integer DEV_CAP_RSVD_14_12 = 0; + parameter integer DEV_CAP_RSVD_17_16 = 0; + parameter integer DEV_CAP_RSVD_31_29 = 0; + parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; + parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE"; + parameter DISABLE_ASPM_L1_TIMER = "FALSE"; + parameter DISABLE_BAR_FILTERING = "FALSE"; + parameter DISABLE_ERR_MSG = "FALSE"; + parameter DISABLE_ID_CHECK = "FALSE"; + parameter DISABLE_LANE_REVERSAL = "FALSE"; + parameter DISABLE_LOCKED_FILTER = "FALSE"; + parameter DISABLE_PPM_FILTER = "FALSE"; + parameter DISABLE_RX_POISONED_RESP = "FALSE"; + parameter DISABLE_RX_TC_FILTER = "FALSE"; + parameter DISABLE_SCRAMBLING = "FALSE"; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [11:0] DSN_BASE_PTR = 12'h100; + parameter [15:0] DSN_CAP_ID = 16'h0003; + parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C; + parameter DSN_CAP_ON = "TRUE"; + parameter [3:0] DSN_CAP_VERSION = 4'h1; + parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; + parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; + parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE"; + parameter ENTER_RVRY_EI_L0 = "TRUE"; + parameter EXIT_LOOPBACK_ON_EI = "TRUE"; + parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; + parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; + parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; + parameter [7:0] HEADER_TYPE = 8'h00; + parameter [4:0] INFER_EI = 5'h00; + parameter [7:0] INTERRUPT_PIN = 8'h01; + parameter INTERRUPT_STAT_AUTO = "TRUE"; + parameter IS_SWITCH = "FALSE"; + parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF; + parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE"; + parameter integer LINK_CAP_ASPM_SUPPORT = 1; + parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; + parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; + parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; + parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; + parameter integer LINK_CAP_RSVD_23 = 0; + parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; + parameter integer LINK_CONTROL_RCB = 0; + parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; + parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; + parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; + parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; + parameter MPS_FORCE = "FALSE"; + parameter [7:0] MSIX_BASE_PTR = 8'h9C; + parameter [7:0] MSIX_CAP_ID = 8'h11; + parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; + parameter MSIX_CAP_ON = "FALSE"; + parameter integer MSIX_CAP_PBA_BIR = 0; + parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] MSI_BASE_PTR = 8'h48; + parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; + parameter [7:0] MSI_CAP_ID = 8'h05; + parameter integer MSI_CAP_MULTIMSGCAP = 0; + parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; + parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; + parameter MSI_CAP_ON = "FALSE"; + parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; + parameter integer N_FTS_COMCLK_GEN1 = 255; + parameter integer N_FTS_COMCLK_GEN2 = 255; + parameter integer N_FTS_GEN1 = 255; + parameter integer N_FTS_GEN2 = 255; + parameter [7:0] PCIE_BASE_PTR = 8'h60; + parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; + parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; + parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; + parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C; + parameter PCIE_CAP_ON = "TRUE"; + parameter integer PCIE_CAP_RSVD_15_14 = 0; + parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; + parameter integer PCIE_REVISION = 2; + parameter integer PL_AUTO_CONFIG = 0; + parameter PL_FAST_TRAIN = "FALSE"; + parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000; + parameter PM_ASPML0S_TIMEOUT_EN = "FALSE"; + parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0; + parameter PM_ASPM_FASTEXIT = "FALSE"; + parameter [7:0] PM_BASE_PTR = 8'h40; + parameter integer PM_CAP_AUXCURRENT = 0; + parameter PM_CAP_D1SUPPORT = "TRUE"; + parameter PM_CAP_D2SUPPORT = "TRUE"; + parameter PM_CAP_DSI = "FALSE"; + parameter [7:0] PM_CAP_ID = 8'h01; + parameter [7:0] PM_CAP_NEXTPTR = 8'h48; + parameter PM_CAP_ON = "TRUE"; + parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; + parameter PM_CAP_PME_CLOCK = "FALSE"; + parameter integer PM_CAP_RSVD_04 = 0; + parameter integer PM_CAP_VERSION = 3; + parameter PM_CSR_B2B3 = "FALSE"; + parameter PM_CSR_BPCCEN = "FALSE"; + parameter PM_CSR_NOSOFTRST = "TRUE"; + parameter [7:0] PM_DATA0 = 8'h01; + parameter [7:0] PM_DATA1 = 8'h01; + parameter [7:0] PM_DATA2 = 8'h01; + parameter [7:0] PM_DATA3 = 8'h01; + parameter [7:0] PM_DATA4 = 8'h01; + parameter [7:0] PM_DATA5 = 8'h01; + parameter [7:0] PM_DATA6 = 8'h01; + parameter [7:0] PM_DATA7 = 8'h01; + parameter [1:0] PM_DATA_SCALE0 = 2'h1; + parameter [1:0] PM_DATA_SCALE1 = 2'h1; + parameter [1:0] PM_DATA_SCALE2 = 2'h1; + parameter [1:0] PM_DATA_SCALE3 = 2'h1; + parameter [1:0] PM_DATA_SCALE4 = 2'h1; + parameter [1:0] PM_DATA_SCALE5 = 2'h1; + parameter [1:0] PM_DATA_SCALE6 = 2'h1; + parameter [1:0] PM_DATA_SCALE7 = 2'h1; + parameter PM_MF = "FALSE"; + parameter [11:0] RBAR_BASE_PTR = 12'h178; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00; + parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00; + parameter [15:0] RBAR_CAP_ID = 16'h0015; + parameter [2:0] RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX2 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX3 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX4 = 3'h0; + parameter [2:0] RBAR_CAP_INDEX5 = 3'h0; + parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000; + parameter RBAR_CAP_ON = "FALSE"; + parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000; + parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000; + parameter [3:0] RBAR_CAP_VERSION = 4'h1; + parameter [2:0] RBAR_NUM = 3'h1; + parameter integer RECRC_CHK = 0; + parameter RECRC_CHK_TRIM = "FALSE"; + parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; + parameter [1:0] RP_AUTO_SPD = 2'h1; + parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F; + parameter SELECT_DLL_IF = "FALSE"; + parameter SIM_VERSION = "1.0"; + parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; + parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; + parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; + parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; + parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; + parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; + parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; + parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; + parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; + parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; + parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; + parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter SSL_MESSAGE_AUTO = "FALSE"; + parameter TECRC_EP_INV = "FALSE"; + parameter TL_RBYPASS = "FALSE"; + parameter integer TL_RX_RAM_RADDR_LATENCY = 0; + parameter integer TL_RX_RAM_RDATA_LATENCY = 2; + parameter integer TL_RX_RAM_WRITE_LATENCY = 0; + parameter TL_TFC_DISABLE = "FALSE"; + parameter TL_TX_CHECKS_DISABLE = "FALSE"; + parameter integer TL_TX_RAM_RADDR_LATENCY = 0; + parameter integer TL_TX_RAM_RDATA_LATENCY = 2; + parameter integer TL_TX_RAM_WRITE_LATENCY = 0; + parameter TRN_DW = "FALSE"; + parameter TRN_NP_FC = "FALSE"; + parameter UPCONFIG_CAPABLE = "TRUE"; + parameter UPSTREAM_FACING = "TRUE"; + parameter UR_ATOMIC = "TRUE"; + parameter UR_CFG1 = "TRUE"; + parameter UR_INV_REQ = "TRUE"; + parameter UR_PRS_RESPONSE = "TRUE"; + parameter USER_CLK2_DIV2 = "FALSE"; + parameter integer USER_CLK_FREQ = 3; + parameter USE_RID_PINS = "FALSE"; + parameter VC0_CPL_INFINITE = "TRUE"; + parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; + parameter integer VC0_TOTAL_CREDITS_CD = 127; + parameter integer VC0_TOTAL_CREDITS_CH = 31; + parameter integer VC0_TOTAL_CREDITS_NPD = 24; + parameter integer VC0_TOTAL_CREDITS_NPH = 12; + parameter integer VC0_TOTAL_CREDITS_PD = 288; + parameter integer VC0_TOTAL_CREDITS_PH = 32; + parameter integer VC0_TX_LASTPACKET = 31; + parameter [11:0] VC_BASE_PTR = 12'h10C; + parameter [15:0] VC_CAP_ID = 16'h0002; + parameter [11:0] VC_CAP_NEXTPTR = 12'h000; + parameter VC_CAP_ON = "FALSE"; + parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; + parameter [3:0] VC_CAP_VERSION = 4'h1; + parameter [11:0] VSEC_BASE_PTR = 12'h128; + parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; + parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; + parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; + parameter [15:0] VSEC_CAP_ID = 16'h000B; + parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; + parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140; + parameter VSEC_CAP_ON = "FALSE"; + parameter [3:0] VSEC_CAP_VERSION = 4'h1; + output CFGAERECRCCHECKEN; + output CFGAERECRCGENEN; + output CFGAERROOTERRCORRERRRECEIVED; + output CFGAERROOTERRCORRERRREPORTINGEN; + output CFGAERROOTERRFATALERRRECEIVED; + output CFGAERROOTERRFATALERRREPORTINGEN; + output CFGAERROOTERRNONFATALERRRECEIVED; + output CFGAERROOTERRNONFATALERRREPORTINGEN; + output CFGBRIDGESERREN; + output CFGCOMMANDBUSMASTERENABLE; + output CFGCOMMANDINTERRUPTDISABLE; + output CFGCOMMANDIOENABLE; + output CFGCOMMANDMEMENABLE; + output CFGCOMMANDSERREN; + output CFGDEVCONTROL2ARIFORWARDEN; + output CFGDEVCONTROL2ATOMICEGRESSBLOCK; + output CFGDEVCONTROL2ATOMICREQUESTEREN; + output CFGDEVCONTROL2CPLTIMEOUTDIS; + output CFGDEVCONTROL2IDOCPLEN; + output CFGDEVCONTROL2IDOREQEN; + output CFGDEVCONTROL2LTREN; + output CFGDEVCONTROL2TLPPREFIXBLOCK; + output CFGDEVCONTROLAUXPOWEREN; + output CFGDEVCONTROLCORRERRREPORTINGEN; + output CFGDEVCONTROLENABLERO; + output CFGDEVCONTROLEXTTAGEN; + output CFGDEVCONTROLFATALERRREPORTINGEN; + output CFGDEVCONTROLNONFATALREPORTINGEN; + output CFGDEVCONTROLNOSNOOPEN; + output CFGDEVCONTROLPHANTOMEN; + output CFGDEVCONTROLURERRREPORTINGEN; + output CFGDEVSTATUSCORRERRDETECTED; + output CFGDEVSTATUSFATALERRDETECTED; + output CFGDEVSTATUSNONFATALERRDETECTED; + output CFGDEVSTATUSURDETECTED; + output CFGERRAERHEADERLOGSETN; + output CFGERRCPLRDYN; + output CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIXENABLE; + output CFGINTERRUPTMSIXFM; + output CFGINTERRUPTRDYN; + output CFGLINKCONTROLAUTOBANDWIDTHINTEN; + output CFGLINKCONTROLBANDWIDTHINTEN; + output CFGLINKCONTROLCLOCKPMEN; + output CFGLINKCONTROLCOMMONCLOCK; + output CFGLINKCONTROLEXTENDEDSYNC; + output CFGLINKCONTROLHWAUTOWIDTHDIS; + output CFGLINKCONTROLLINKDISABLE; + output CFGLINKCONTROLRCB; + output CFGLINKCONTROLRETRAINLINK; + output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; + output CFGLINKSTATUSBANDWIDTHSTATUS; + output CFGLINKSTATUSDLLACTIVE; + output CFGLINKSTATUSLINKTRAINING; + output CFGMGMTRDWRDONEN; + output CFGMSGRECEIVED; + output CFGMSGRECEIVEDASSERTINTA; + output CFGMSGRECEIVEDASSERTINTB; + output CFGMSGRECEIVEDASSERTINTC; + output CFGMSGRECEIVEDASSERTINTD; + output CFGMSGRECEIVEDDEASSERTINTA; + output CFGMSGRECEIVEDDEASSERTINTB; + output CFGMSGRECEIVEDDEASSERTINTC; + output CFGMSGRECEIVEDDEASSERTINTD; + output CFGMSGRECEIVEDERRCOR; + output CFGMSGRECEIVEDERRFATAL; + output CFGMSGRECEIVEDERRNONFATAL; + output CFGMSGRECEIVEDPMASNAK; + output CFGMSGRECEIVEDPMETO; + output CFGMSGRECEIVEDPMETOACK; + output CFGMSGRECEIVEDPMPME; + output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; + output CFGMSGRECEIVEDUNLOCK; + output CFGPMCSRPMEEN; + output CFGPMCSRPMESTATUS; + output CFGPMRCVASREQL1N; + output CFGPMRCVENTERL1N; + output CFGPMRCVENTERL23N; + output CFGPMRCVREQACKN; + output CFGROOTCONTROLPMEINTEN; + output CFGROOTCONTROLSYSERRCORRERREN; + output CFGROOTCONTROLSYSERRFATALERREN; + output CFGROOTCONTROLSYSERRNONFATALERREN; + output CFGSLOTCONTROLELECTROMECHILCTLPULSE; + output CFGTRANSACTION; + output CFGTRANSACTIONTYPE; + output DBGSCLRA; + output DBGSCLRB; + output DBGSCLRC; + output DBGSCLRD; + output DBGSCLRE; + output DBGSCLRF; + output DBGSCLRG; + output DBGSCLRH; + output DBGSCLRI; + output DBGSCLRJ; + output DBGSCLRK; + output DRPRDY; + output LL2BADDLLPERR; + output LL2BADTLPERR; + output LL2PROTOCOLERR; + output LL2RECEIVERERR; + output LL2REPLAYROERR; + output LL2REPLAYTOERR; + output LL2SUSPENDOK; + output LL2TFCINIT1SEQ; + output LL2TFCINIT2SEQ; + output LL2TXIDLE; + output LNKCLKEN; + output MIMRXREN; + output MIMRXWEN; + output MIMTXREN; + output MIMTXWEN; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0ELECIDLE; + output PIPETX1COMPLIANCE; + output PIPETX1ELECIDLE; + output PIPETX2COMPLIANCE; + output PIPETX2ELECIDLE; + output PIPETX3COMPLIANCE; + output PIPETX3ELECIDLE; + output PIPETX4COMPLIANCE; + output PIPETX4ELECIDLE; + output PIPETX5COMPLIANCE; + output PIPETX5ELECIDLE; + output PIPETX6COMPLIANCE; + output PIPETX6ELECIDLE; + output PIPETX7COMPLIANCE; + output PIPETX7ELECIDLE; + output PIPETXDEEMPH; + output PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PL2L0REQ; + output PL2LINKUP; + output PL2RECEIVERERR; + output PL2RECOVERY; + output PL2RXELECIDLE; + output PL2SUSPENDOK; + output PLDIRECTEDCHANGEDONE; + output PLLINKGEN2CAP; + output PLLINKPARTNERGEN2SUPPORTED; + output PLLINKUPCFGCAP; + output PLPHYLNKUPN; + output PLRECEIVEDHOTRST; + output PLSELLNKRATE; + output RECEIVEDFUNCLVLRSTN; + output TL2ASPMSUSPENDCREDITCHECKOK; + output TL2ASPMSUSPENDREQ; + output TL2ERRFCPE; + output TL2ERRMALFORMED; + output TL2ERRRXOVERFLOW; + output TL2PPMSUSPENDOK; + output TRNLNKUP; + output TRNRECRCERR; + output TRNREOF; + output TRNRERRFWD; + output TRNRSOF; + output TRNRSRCDSC; + output TRNRSRCRDY; + output TRNTCFGREQ; + output TRNTDLLPDSTRDY; + output TRNTERRDROP; + output USERRSTN; + output [11:0] DBGVECC; + output [11:0] PLDBGVEC; + output [11:0] TRNFCCPLD; + output [11:0] TRNFCNPD; + output [11:0] TRNFCPD; + output [127:0] TRNRD; + output [12:0] MIMRXRADDR; + output [12:0] MIMRXWADDR; + output [12:0] MIMTXRADDR; + output [12:0] MIMTXWADDR; + output [15:0] CFGMSGDATA; + output [15:0] DRPDO; + output [15:0] PIPETX0DATA; + output [15:0] PIPETX1DATA; + output [15:0] PIPETX2DATA; + output [15:0] PIPETX3DATA; + output [15:0] PIPETX4DATA; + output [15:0] PIPETX5DATA; + output [15:0] PIPETX6DATA; + output [15:0] PIPETX7DATA; + output [1:0] CFGLINKCONTROLASPMCONTROL; + output [1:0] CFGLINKSTATUSCURRENTSPEED; + output [1:0] CFGPMCSRPOWERSTATE; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PL2RXPMSTATE; + output [1:0] PLLANEREVERSALMODE; + output [1:0] PLRXPMSTATE; + output [1:0] PLSELLNKWIDTH; + output [1:0] TRNRDLLPSRCRDY; + output [1:0] TRNRREM; + output [2:0] CFGDEVCONTROLMAXPAYLOAD; + output [2:0] CFGDEVCONTROLMAXREADREQ; + output [2:0] CFGINTERRUPTMMENABLE; + output [2:0] CFGPCIELINKSTATE; + output [2:0] PIPETXMARGIN; + output [2:0] PLINITIALLINKWIDTH; + output [2:0] PLTXPMSTATE; + output [31:0] CFGMGMTDO; + output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; + output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; + output [3:0] TRNTDSTRDY; + output [4:0] LL2LINKSTATUS; + output [5:0] PLLTSSMSTATE; + output [5:0] TRNTBUFAV; + output [63:0] DBGVECA; + output [63:0] DBGVECB; + output [63:0] TL2ERRHDR; + output [63:0] TRNRDLLPDATA; + output [67:0] MIMRXWDATA; + output [68:0] MIMTXWDATA; + output [6:0] CFGTRANSACTIONADDR; + output [6:0] CFGVCTCVCMAP; + output [7:0] CFGINTERRUPTDO; + output [7:0] TRNFCCPLH; + output [7:0] TRNFCNPH; + output [7:0] TRNFCPH; + output [7:0] TRNRBARHIT; + input CFGERRACSN; + input CFGERRATOMICEGRESSBLOCKEDN; + input CFGERRCORN; + input CFGERRCPLABORTN; + input CFGERRCPLTIMEOUTN; + input CFGERRCPLUNEXPECTN; + input CFGERRECRCN; + input CFGERRINTERNALCORN; + input CFGERRINTERNALUNCORN; + input CFGERRLOCKEDN; + input CFGERRMALFORMEDN; + input CFGERRMCBLOCKEDN; + input CFGERRNORECOVERYN; + input CFGERRPOISONEDN; + input CFGERRPOSTEDN; + input CFGERRURN; + input CFGFORCECOMMONCLOCKOFF; + input CFGFORCEEXTENDEDSYNCON; + input CFGINTERRUPTASSERTN; + input CFGINTERRUPTN; + input CFGINTERRUPTSTATN; + input CFGMGMTRDENN; + input CFGMGMTWRENN; + input CFGMGMTWRREADONLYN; + input CFGMGMTWRRW1CASRWN; + input CFGPMFORCESTATEENN; + input CFGPMHALTASPML0SN; + input CFGPMHALTASPML1N; + input CFGPMSENDPMETON; + input CFGPMTURNOFFOKN; + input CFGPMWAKEN; + input CFGTRNPENDINGN; + input CMRSTN; + input CMSTICKYRSTN; + input DBGSUBMODE; + input DLRSTN; + input DRPCLK; + input DRPEN; + input DRPWE; + input FUNCLVLRSTN; + input LL2SENDASREQL1; + input LL2SENDENTERL1; + input LL2SENDENTERL23; + input LL2SENDPMACK; + input LL2SUSPENDNOW; + input LL2TLPRCV; + input PIPECLK; + input PIPERX0CHANISALIGNED; + input PIPERX0ELECIDLE; + input PIPERX0PHYSTATUS; + input PIPERX0VALID; + input PIPERX1CHANISALIGNED; + input PIPERX1ELECIDLE; + input PIPERX1PHYSTATUS; + input PIPERX1VALID; + input PIPERX2CHANISALIGNED; + input PIPERX2ELECIDLE; + input PIPERX2PHYSTATUS; + input PIPERX2VALID; + input PIPERX3CHANISALIGNED; + input PIPERX3ELECIDLE; + input PIPERX3PHYSTATUS; + input PIPERX3VALID; + input PIPERX4CHANISALIGNED; + input PIPERX4ELECIDLE; + input PIPERX4PHYSTATUS; + input PIPERX4VALID; + input PIPERX5CHANISALIGNED; + input PIPERX5ELECIDLE; + input PIPERX5PHYSTATUS; + input PIPERX5VALID; + input PIPERX6CHANISALIGNED; + input PIPERX6ELECIDLE; + input PIPERX6PHYSTATUS; + input PIPERX6VALID; + input PIPERX7CHANISALIGNED; + input PIPERX7ELECIDLE; + input PIPERX7PHYSTATUS; + input PIPERX7VALID; + input PLDIRECTEDLINKAUTON; + input PLDIRECTEDLINKSPEED; + input PLDIRECTEDLTSSMNEWVLD; + input PLDIRECTEDLTSSMSTALL; + input PLDOWNSTREAMDEEMPHSOURCE; + input PLRSTN; + input PLTRANSMITHOTRST; + input PLUPSTREAMPREFERDEEMPH; + input SYSRSTN; + input TL2ASPMSUSPENDCREDITCHECK; + input TL2PPMSUSPENDREQ; + input TLRSTN; + input TRNRDSTRDY; + input TRNRFCPRET; + input TRNRNPOK; + input TRNRNPREQ; + input TRNTCFGGNT; + input TRNTDLLPSRCRDY; + input TRNTECRCGEN; + input TRNTEOF; + input TRNTERRFWD; + input TRNTSOF; + input TRNTSRCDSC; + input TRNTSRCRDY; + input TRNTSTR; + input USERCLK2; + input USERCLK; + input [127:0] CFGERRAERHEADERLOG; + input [127:0] TRNTD; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENDID; + input [15:0] CFGVENDID; + input [15:0] DRPDI; + input [15:0] PIPERX0DATA; + input [15:0] PIPERX1DATA; + input [15:0] PIPERX2DATA; + input [15:0] PIPERX3DATA; + input [15:0] PIPERX4DATA; + input [15:0] PIPERX5DATA; + input [15:0] PIPERX6DATA; + input [15:0] PIPERX7DATA; + input [1:0] CFGPMFORCESTATE; + input [1:0] DBGMODE; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX7CHARISK; + input [1:0] PLDIRECTEDLINKCHANGE; + input [1:0] PLDIRECTEDLINKWIDTH; + input [1:0] TRNTREM; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] CFGFORCEMPS; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [2:0] PLDBGMODE; + input [2:0] TRNFCSEL; + input [31:0] CFGMGMTDI; + input [31:0] TRNTDLLPDATA; + input [3:0] CFGMGMTBYTEENN; + input [47:0] CFGERRTLPCPLHEADER; + input [4:0] CFGAERINTERRUPTMSGNUM; + input [4:0] CFGDSDEVICENUMBER; + input [4:0] CFGPCIECAPINTERRUPTMSGNUM; + input [4:0] PL2DIRECTEDLSTATE; + input [5:0] PLDIRECTEDLTSSMNEW; + input [63:0] CFGDSN; + input [67:0] MIMRXRDATA; + input [68:0] MIMTXRDATA; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGINTERRUPTDI; + input [7:0] CFGPORTNUMBER; + input [7:0] CFGREVID; + input [8:0] DRPADDR; + input [9:0] CFGMGMTDWADDR; +endmodule + +module PCIE_3_0 (...); + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; + parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1; + parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE"; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; + parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; + parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_BIST_REGISTER = 8'h00; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter [15:0] PF0_DEVICE_ID = 16'h0000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF0_DPA_CAP_VER = 4'h1; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; + parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF0_PB_CAP_VER = 4'h1; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter PF0_RBAR_CAP_ENABLE = "FALSE"; + parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0; + parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF0_RBAR_NUM = 3'h1; + parameter [7:0] PF0_REVISION_ID = 8'h00; + parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_BIST_REGISTER = 8'h00; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [15:0] PF1_DEVICE_ID = 16'h0000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF1_DPA_CAP_VER = 4'h1; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; + parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF1_PB_CAP_VER = 4'h1; + parameter [7:0] PF1_PM_CAP_ID = 8'h01; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; + parameter PF1_RBAR_CAP_ENABLE = "FALSE"; + parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0; + parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0; + parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0; + parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF1_RBAR_NUM = 3'h1; + parameter [7:0] PF1_REVISION_ID = 8'h00; + parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; + parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF1_TPHR_CAP_ENABLE = "FALSE"; + parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_SCRAMBLING = "FALSE"; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; + parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; + parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; + parameter integer PL_N_FTS_COMCLK_GEN1 = 255; + parameter integer PL_N_FTS_COMCLK_GEN2 = 255; + parameter integer PL_N_FTS_COMCLK_GEN3 = 255; + parameter integer PL_N_FTS_GEN1 = 255; + parameter integer PL_N_FTS_GEN2 = 255; + parameter integer PL_N_FTS_GEN3 = 255; + parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; + parameter SIM_VERSION = "1.0"; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter SRIOV_CAP_ENABLE = "FALSE"; + parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000; + parameter [11:0] TL_CREDITS_CD = 12'h3E0; + parameter [7:0] TL_CREDITS_CH = 8'h20; + parameter [11:0] TL_CREDITS_NPD = 12'h028; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [11:0] TL_CREDITS_PD = 12'h198; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; + parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_MODE_ENABLE = "FALSE"; + parameter TL_PF_ENABLE_REG = "FALSE"; + parameter TL_TAG_MGMT_ENABLE = "TRUE"; + parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; + parameter integer VF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF0_PM_CAP_ID = 8'h01; + parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; + parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF0_TPHR_CAP_ENABLE = "FALSE"; + parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF1_PM_CAP_ID = 8'h01; + parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; + parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF1_TPHR_CAP_ENABLE = "FALSE"; + parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF2_PM_CAP_ID = 8'h01; + parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; + parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF2_TPHR_CAP_ENABLE = "FALSE"; + parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF3_PM_CAP_ID = 8'h01; + parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; + parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF3_TPHR_CAP_ENABLE = "FALSE"; + parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF4_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF4_PM_CAP_ID = 8'h01; + parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; + parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF4_TPHR_CAP_ENABLE = "FALSE"; + parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF5_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF5_PM_CAP_ID = 8'h01; + parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; + parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF5_TPHR_CAP_ENABLE = "FALSE"; + parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output CFGEXTREADRECEIVED; + output CFGEXTWRITERECEIVED; + output CFGHOTRESETOUT; + output CFGINPUTUPDATEDONE; + output CFGINTERRUPTAOUTPUT; + output CFGINTERRUPTBOUTPUT; + output CFGINTERRUPTCOUTPUT; + output CFGINTERRUPTDOUTPUT; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output CFGINTERRUPTMSISENT; + output CFGINTERRUPTMSIXFAIL; + output CFGINTERRUPTMSIXSENT; + output CFGINTERRUPTSENT; + output CFGLOCALERROR; + output CFGLTRENABLE; + output CFGMCUPDATEDONE; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output CFGMSGTRANSMITDONE; + output CFGPERFUNCTIONUPDATEDONE; + output CFGPHYLINKDOWN; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output CFGTPHSTTREADENABLE; + output CFGTPHSTTWRITEENABLE; + output DRPRDY; + output MAXISCQTLAST; + output MAXISCQTVALID; + output MAXISRCTLAST; + output MAXISRCTVALID; + output PCIERQSEQNUMVLD; + output PCIERQTAGVLD; + output PIPERX0POLARITY; + output PIPERX1POLARITY; + output PIPERX2POLARITY; + output PIPERX3POLARITY; + output PIPERX4POLARITY; + output PIPERX5POLARITY; + output PIPERX6POLARITY; + output PIPERX7POLARITY; + output PIPETX0COMPLIANCE; + output PIPETX0DATAVALID; + output PIPETX0ELECIDLE; + output PIPETX0STARTBLOCK; + output PIPETX1COMPLIANCE; + output PIPETX1DATAVALID; + output PIPETX1ELECIDLE; + output PIPETX1STARTBLOCK; + output PIPETX2COMPLIANCE; + output PIPETX2DATAVALID; + output PIPETX2ELECIDLE; + output PIPETX2STARTBLOCK; + output PIPETX3COMPLIANCE; + output PIPETX3DATAVALID; + output PIPETX3ELECIDLE; + output PIPETX3STARTBLOCK; + output PIPETX4COMPLIANCE; + output PIPETX4DATAVALID; + output PIPETX4ELECIDLE; + output PIPETX4STARTBLOCK; + output PIPETX5COMPLIANCE; + output PIPETX5DATAVALID; + output PIPETX5ELECIDLE; + output PIPETX5STARTBLOCK; + output PIPETX6COMPLIANCE; + output PIPETX6DATAVALID; + output PIPETX6ELECIDLE; + output PIPETX6STARTBLOCK; + output PIPETX7COMPLIANCE; + output PIPETX7DATAVALID; + output PIPETX7ELECIDLE; + output PIPETX7STARTBLOCK; + output PIPETXDEEMPH; + output PIPETXRCVRDET; + output PIPETXRESET; + output PIPETXSWING; + output PLEQINPROGRESS; + output [11:0] CFGFCCPLD; + output [11:0] CFGFCNPD; + output [11:0] CFGFCPD; + output [11:0] CFGVFSTATUS; + output [143:0] MIREPLAYRAMWRITEDATA; + output [143:0] MIREQUESTRAMWRITEDATA; + output [15:0] CFGPERFUNCSTATUSDATA; + output [15:0] DBGDATAOUT; + output [15:0] DRPDO; + output [17:0] CFGVFPOWERSTATE; + output [17:0] CFGVFTPHSTMODE; + output [1:0] CFGDPASUBSTATECHANGE; + output [1:0] CFGFLRINPROCESS; + output [1:0] CFGINTERRUPTMSIENABLE; + output [1:0] CFGINTERRUPTMSIXENABLE; + output [1:0] CFGINTERRUPTMSIXMASK; + output [1:0] CFGLINKPOWERSTATE; + output [1:0] CFGOBFFENABLE; + output [1:0] CFGPHYLINKSTATUS; + output [1:0] CFGRCBSTATUS; + output [1:0] CFGTPHREQUESTERENABLE; + output [1:0] MIREPLAYRAMREADENABLE; + output [1:0] MIREPLAYRAMWRITEENABLE; + output [1:0] PCIERQTAGAV; + output [1:0] PCIETFCNPDAV; + output [1:0] PCIETFCNPHAV; + output [1:0] PIPERX0EQCONTROL; + output [1:0] PIPERX1EQCONTROL; + output [1:0] PIPERX2EQCONTROL; + output [1:0] PIPERX3EQCONTROL; + output [1:0] PIPERX4EQCONTROL; + output [1:0] PIPERX5EQCONTROL; + output [1:0] PIPERX6EQCONTROL; + output [1:0] PIPERX7EQCONTROL; + output [1:0] PIPETX0CHARISK; + output [1:0] PIPETX0EQCONTROL; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX0SYNCHEADER; + output [1:0] PIPETX1CHARISK; + output [1:0] PIPETX1EQCONTROL; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX1SYNCHEADER; + output [1:0] PIPETX2CHARISK; + output [1:0] PIPETX2EQCONTROL; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX2SYNCHEADER; + output [1:0] PIPETX3CHARISK; + output [1:0] PIPETX3EQCONTROL; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX3SYNCHEADER; + output [1:0] PIPETX4CHARISK; + output [1:0] PIPETX4EQCONTROL; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX4SYNCHEADER; + output [1:0] PIPETX5CHARISK; + output [1:0] PIPETX5EQCONTROL; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX5SYNCHEADER; + output [1:0] PIPETX6CHARISK; + output [1:0] PIPETX6EQCONTROL; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX6SYNCHEADER; + output [1:0] PIPETX7CHARISK; + output [1:0] PIPETX7EQCONTROL; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PIPETX7SYNCHEADER; + output [1:0] PIPETXRATE; + output [1:0] PLEQPHASE; + output [255:0] MAXISCQTDATA; + output [255:0] MAXISRCTDATA; + output [2:0] CFGCURRENTSPEED; + output [2:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [2:0] CFGTPHFUNCTIONNUM; + output [2:0] PIPERX0EQPRESET; + output [2:0] PIPERX1EQPRESET; + output [2:0] PIPERX2EQPRESET; + output [2:0] PIPERX3EQPRESET; + output [2:0] PIPERX4EQPRESET; + output [2:0] PIPERX5EQPRESET; + output [2:0] PIPERX6EQPRESET; + output [2:0] PIPERX7EQPRESET; + output [2:0] PIPETXMARGIN; + output [31:0] CFGEXTWRITEDATA; + output [31:0] CFGINTERRUPTMSIDATA; + output [31:0] CFGMGMTREADDATA; + output [31:0] CFGTPHSTTWRITEDATA; + output [31:0] PIPETX0DATA; + output [31:0] PIPETX1DATA; + output [31:0] PIPETX2DATA; + output [31:0] PIPETX3DATA; + output [31:0] PIPETX4DATA; + output [31:0] PIPETX5DATA; + output [31:0] PIPETX6DATA; + output [31:0] PIPETX7DATA; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [3:0] CFGNEGOTIATEDWIDTH; + output [3:0] CFGTPHSTTWRITEBYTEVALID; + output [3:0] MICOMPLETIONRAMREADENABLEL; + output [3:0] MICOMPLETIONRAMREADENABLEU; + output [3:0] MICOMPLETIONRAMWRITEENABLEL; + output [3:0] MICOMPLETIONRAMWRITEENABLEU; + output [3:0] MIREQUESTRAMREADENABLE; + output [3:0] MIREQUESTRAMWRITEENABLE; + output [3:0] PCIERQSEQNUM; + output [3:0] PIPERX0EQLPTXPRESET; + output [3:0] PIPERX1EQLPTXPRESET; + output [3:0] PIPERX2EQLPTXPRESET; + output [3:0] PIPERX3EQLPTXPRESET; + output [3:0] PIPERX4EQLPTXPRESET; + output [3:0] PIPERX5EQLPTXPRESET; + output [3:0] PIPERX6EQLPTXPRESET; + output [3:0] PIPERX7EQLPTXPRESET; + output [3:0] PIPETX0EQPRESET; + output [3:0] PIPETX1EQPRESET; + output [3:0] PIPETX2EQPRESET; + output [3:0] PIPETX3EQPRESET; + output [3:0] PIPETX4EQPRESET; + output [3:0] PIPETX5EQPRESET; + output [3:0] PIPETX6EQPRESET; + output [3:0] PIPETX7EQPRESET; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [4:0] CFGMSGRECEIVEDTYPE; + output [4:0] CFGTPHSTTADDRESS; + output [5:0] CFGFUNCTIONPOWERSTATE; + output [5:0] CFGINTERRUPTMSIMMENABLE; + output [5:0] CFGINTERRUPTMSIVFENABLE; + output [5:0] CFGINTERRUPTMSIXVFENABLE; + output [5:0] CFGINTERRUPTMSIXVFMASK; + output [5:0] CFGLTSSMSTATE; + output [5:0] CFGTPHSTMODE; + output [5:0] CFGVFFLRINPROCESS; + output [5:0] CFGVFTPHREQUESTERENABLE; + output [5:0] PCIECQNPREQCOUNT; + output [5:0] PCIERQTAG; + output [5:0] PIPERX0EQLPLFFS; + output [5:0] PIPERX1EQLPLFFS; + output [5:0] PIPERX2EQLPLFFS; + output [5:0] PIPERX3EQLPLFFS; + output [5:0] PIPERX4EQLPLFFS; + output [5:0] PIPERX5EQLPLFFS; + output [5:0] PIPERX6EQLPLFFS; + output [5:0] PIPERX7EQLPLFFS; + output [5:0] PIPETX0EQDEEMPH; + output [5:0] PIPETX1EQDEEMPH; + output [5:0] PIPETX2EQDEEMPH; + output [5:0] PIPETX3EQDEEMPH; + output [5:0] PIPETX4EQDEEMPH; + output [5:0] PIPETX5EQDEEMPH; + output [5:0] PIPETX6EQDEEMPH; + output [5:0] PIPETX7EQDEEMPH; + output [71:0] MICOMPLETIONRAMWRITEDATAL; + output [71:0] MICOMPLETIONRAMWRITEDATAU; + output [74:0] MAXISRCTUSER; + output [7:0] CFGEXTFUNCTIONNUMBER; + output [7:0] CFGFCCPLH; + output [7:0] CFGFCNPH; + output [7:0] CFGFCPH; + output [7:0] CFGFUNCTIONSTATUS; + output [7:0] CFGMSGRECEIVEDDATA; + output [7:0] MAXISCQTKEEP; + output [7:0] MAXISRCTKEEP; + output [7:0] PLGEN3PCSRXSLIDE; + output [84:0] MAXISCQTUSER; + output [8:0] MIREPLAYRAMADDRESS; + output [8:0] MIREQUESTRAMREADADDRESSA; + output [8:0] MIREQUESTRAMREADADDRESSB; + output [8:0] MIREQUESTRAMWRITEADDRESSA; + output [8:0] MIREQUESTRAMWRITEADDRESSB; + output [9:0] CFGEXTREGISTERNUMBER; + output [9:0] MICOMPLETIONRAMREADADDRESSAL; + output [9:0] MICOMPLETIONRAMREADADDRESSAU; + output [9:0] MICOMPLETIONRAMREADADDRESSBL; + output [9:0] MICOMPLETIONRAMREADADDRESSBU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; + input CFGCONFIGSPACEENABLE; + input CFGERRCORIN; + input CFGERRUNCORIN; + input CFGEXTREADDATAVALID; + input CFGHOTRESETIN; + input CFGINPUTUPDATEREQUEST; + input CFGINTERRUPTMSITPHPRESENT; + input CFGINTERRUPTMSIXINT; + input CFGLINKTRAININGENABLE; + input CFGMCUPDATEREQUEST; + input CFGMGMTREAD; + input CFGMGMTTYPE1CFGREGACCESS; + input CFGMGMTWRITE; + input CFGMSGTRANSMIT; + input CFGPERFUNCTIONOUTPUTREQUEST; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input CFGTPHSTTREADDATAVALID; + input CORECLK; + input CORECLKMICOMPLETIONRAML; + input CORECLKMICOMPLETIONRAMU; + input CORECLKMIREPLAYRAM; + input CORECLKMIREQUESTRAM; + input DRPCLK; + input DRPEN; + input DRPWE; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input PCIECQNPREQ; + input PIPECLK; + input PIPERESETN; + input PIPERX0DATAVALID; + input PIPERX0ELECIDLE; + input PIPERX0EQDONE; + input PIPERX0EQLPADAPTDONE; + input PIPERX0EQLPLFFSSEL; + input PIPERX0PHYSTATUS; + input PIPERX0STARTBLOCK; + input PIPERX0VALID; + input PIPERX1DATAVALID; + input PIPERX1ELECIDLE; + input PIPERX1EQDONE; + input PIPERX1EQLPADAPTDONE; + input PIPERX1EQLPLFFSSEL; + input PIPERX1PHYSTATUS; + input PIPERX1STARTBLOCK; + input PIPERX1VALID; + input PIPERX2DATAVALID; + input PIPERX2ELECIDLE; + input PIPERX2EQDONE; + input PIPERX2EQLPADAPTDONE; + input PIPERX2EQLPLFFSSEL; + input PIPERX2PHYSTATUS; + input PIPERX2STARTBLOCK; + input PIPERX2VALID; + input PIPERX3DATAVALID; + input PIPERX3ELECIDLE; + input PIPERX3EQDONE; + input PIPERX3EQLPADAPTDONE; + input PIPERX3EQLPLFFSSEL; + input PIPERX3PHYSTATUS; + input PIPERX3STARTBLOCK; + input PIPERX3VALID; + input PIPERX4DATAVALID; + input PIPERX4ELECIDLE; + input PIPERX4EQDONE; + input PIPERX4EQLPADAPTDONE; + input PIPERX4EQLPLFFSSEL; + input PIPERX4PHYSTATUS; + input PIPERX4STARTBLOCK; + input PIPERX4VALID; + input PIPERX5DATAVALID; + input PIPERX5ELECIDLE; + input PIPERX5EQDONE; + input PIPERX5EQLPADAPTDONE; + input PIPERX5EQLPLFFSSEL; + input PIPERX5PHYSTATUS; + input PIPERX5STARTBLOCK; + input PIPERX5VALID; + input PIPERX6DATAVALID; + input PIPERX6ELECIDLE; + input PIPERX6EQDONE; + input PIPERX6EQLPADAPTDONE; + input PIPERX6EQLPLFFSSEL; + input PIPERX6PHYSTATUS; + input PIPERX6STARTBLOCK; + input PIPERX6VALID; + input PIPERX7DATAVALID; + input PIPERX7ELECIDLE; + input PIPERX7EQDONE; + input PIPERX7EQLPADAPTDONE; + input PIPERX7EQLPLFFSSEL; + input PIPERX7PHYSTATUS; + input PIPERX7STARTBLOCK; + input PIPERX7VALID; + input PIPETX0EQDONE; + input PIPETX1EQDONE; + input PIPETX2EQDONE; + input PIPETX3EQDONE; + input PIPETX4EQDONE; + input PIPETX5EQDONE; + input PIPETX6EQDONE; + input PIPETX7EQDONE; + input PLDISABLESCRAMBLER; + input PLEQRESETEIEOSCOUNT; + input PLGEN3PCSDISABLE; + input RECCLK; + input RESETN; + input SAXISCCTLAST; + input SAXISCCTVALID; + input SAXISRQTLAST; + input SAXISRQTVALID; + input USERCLK; + input [10:0] DRPADDR; + input [143:0] MICOMPLETIONRAMREADDATA; + input [143:0] MIREPLAYRAMREADDATA; + input [143:0] MIREQUESTRAMREADDATA; + input [15:0] CFGDEVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENDID; + input [15:0] CFGVENDID; + input [15:0] DRPDI; + input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; + input [17:0] PIPETX0EQCOEFF; + input [17:0] PIPETX1EQCOEFF; + input [17:0] PIPETX2EQCOEFF; + input [17:0] PIPETX3EQCOEFF; + input [17:0] PIPETX4EQCOEFF; + input [17:0] PIPETX5EQCOEFF; + input [17:0] PIPETX6EQCOEFF; + input [17:0] PIPETX7EQCOEFF; + input [18:0] CFGMGMTADDR; + input [1:0] CFGFLRDONE; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [1:0] CFGINTERRUPTPENDING; + input [1:0] PIPERX0CHARISK; + input [1:0] PIPERX0SYNCHEADER; + input [1:0] PIPERX1CHARISK; + input [1:0] PIPERX1SYNCHEADER; + input [1:0] PIPERX2CHARISK; + input [1:0] PIPERX2SYNCHEADER; + input [1:0] PIPERX3CHARISK; + input [1:0] PIPERX3SYNCHEADER; + input [1:0] PIPERX4CHARISK; + input [1:0] PIPERX4SYNCHEADER; + input [1:0] PIPERX5CHARISK; + input [1:0] PIPERX5SYNCHEADER; + input [1:0] PIPERX6CHARISK; + input [1:0] PIPERX6SYNCHEADER; + input [1:0] PIPERX7CHARISK; + input [1:0] PIPERX7SYNCHEADER; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input [255:0] SAXISCCTDATA; + input [255:0] SAXISRQTDATA; + input [2:0] CFGDSFUNCTIONNUMBER; + input [2:0] CFGFCSEL; + input [2:0] CFGINTERRUPTMSIATTR; + input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [2:0] CFGMSGTRANSMITTYPE; + input [2:0] CFGPERFUNCSTATUSCONTROL; + input [2:0] CFGPERFUNCTIONNUMBER; + input [2:0] PIPERX0STATUS; + input [2:0] PIPERX1STATUS; + input [2:0] PIPERX2STATUS; + input [2:0] PIPERX3STATUS; + input [2:0] PIPERX4STATUS; + input [2:0] PIPERX5STATUS; + input [2:0] PIPERX6STATUS; + input [2:0] PIPERX7STATUS; + input [31:0] CFGEXTREADDATA; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIXDATA; + input [31:0] CFGMGMTWRITEDATA; + input [31:0] CFGMSGTRANSMITDATA; + input [31:0] CFGTPHSTTREADDATA; + input [31:0] PIPERX0DATA; + input [31:0] PIPERX1DATA; + input [31:0] PIPERX2DATA; + input [31:0] PIPERX3DATA; + input [31:0] PIPERX4DATA; + input [31:0] PIPERX5DATA; + input [31:0] PIPERX6DATA; + input [31:0] PIPERX7DATA; + input [32:0] SAXISCCTUSER; + input [3:0] CFGINTERRUPTINT; + input [3:0] CFGINTERRUPTMSISELECT; + input [3:0] CFGMGMTBYTEENABLE; + input [4:0] CFGDSDEVICENUMBER; + input [59:0] SAXISRQTUSER; + input [5:0] CFGVFFLRDONE; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input [63:0] CFGDSN; + input [63:0] CFGINTERRUPTMSIPENDINGSTATUS; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [7:0] CFGDSBUSNUMBER; + input [7:0] CFGDSPORTNUMBER; + input [7:0] CFGREVID; + input [7:0] PLGEN3PCSRXSYNCDONE; + input [7:0] SAXISCCTKEEP; + input [7:0] SAXISRQTKEEP; + input [8:0] CFGINTERRUPTMSITPHSTTAG; +endmodule + +module PCIE_3_1 (...); + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; + parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; + parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE"; + parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; + parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; + parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; + parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; + parameter MCAP_ENABLE = "FALSE"; + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; + parameter [15:0] MCAP_VSEC_ID = 16'h0000; + parameter [11:0] MCAP_VSEC_LEN = 12'h02C; + parameter [3:0] MCAP_VSEC_REV = 4'h0; + parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_BIST_REGISTER = 8'h00; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter [15:0] PF0_DEVICE_ID = 16'h0000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF0_DPA_CAP_VER = 4'h1; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000; + parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; + parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000; + parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000; + parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; + parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF0_PB_CAP_VER = 4'h1; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter PF0_RBAR_CAP_ENABLE = "FALSE"; + parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0; + parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0; + parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0; + parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00; + parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00; + parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00; + parameter [2:0] PF0_RBAR_NUM = 3'h1; + parameter [7:0] PF0_REVISION_ID = 8'h00; + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter PF0_VC_CAP_ENABLE = "FALSE"; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_BIST_REGISTER = 8'h00; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [15:0] PF1_DEVICE_ID = 16'h0000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF1_DPA_CAP_VER = 4'h1; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000; + parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; + parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000; + parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000; + parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; + parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF1_PB_CAP_VER = 4'h1; + parameter [7:0] PF1_PM_CAP_ID = 8'h01; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; + parameter PF1_RBAR_CAP_ENABLE = "FALSE"; + parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0; + parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0; + parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0; + parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00; + parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00; + parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00; + parameter [2:0] PF1_RBAR_NUM = 3'h1; + parameter [7:0] PF1_REVISION_ID = 8'h00; + parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; + parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF1_TPHR_CAP_ENABLE = "FALSE"; + parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; + parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR0_CONTROL = 3'h4; + parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00; + parameter [2:0] PF2_BAR1_CONTROL = 3'h0; + parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR3_CONTROL = 3'h0; + parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR5_CONTROL = 3'h0; + parameter [7:0] PF2_BIST_REGISTER = 8'h00; + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF2_CLASS_CODE = 24'h000000; + parameter [15:0] PF2_DEVICE_ID = 16'h0000; + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF2_DPA_CAP_VER = 4'h1; + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF2_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000; + parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; + parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000; + parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000; + parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000; + parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF2_PB_CAP_VER = 4'h1; + parameter [7:0] PF2_PM_CAP_ID = 8'h01; + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3; + parameter PF2_RBAR_CAP_ENABLE = "FALSE"; + parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF2_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0; + parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0; + parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0; + parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00; + parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00; + parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00; + parameter [2:0] PF2_RBAR_NUM = 3'h1; + parameter [7:0] PF2_REVISION_ID = 8'h00; + parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000; + parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF2_TPHR_CAP_ENABLE = "FALSE"; + parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF2_TPHR_CAP_VER = 4'h1; + parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; + parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR0_CONTROL = 3'h4; + parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00; + parameter [2:0] PF3_BAR1_CONTROL = 3'h0; + parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR3_CONTROL = 3'h0; + parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR5_CONTROL = 3'h0; + parameter [7:0] PF3_BIST_REGISTER = 8'h00; + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50; + parameter [23:0] PF3_CLASS_CODE = 24'h000000; + parameter [15:0] PF3_DEVICE_ID = 16'h0000; + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000; + parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00; + parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; + parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; + parameter [3:0] PF3_DPA_CAP_VER = 4'h1; + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [7:0] PF3_INTERRUPT_LINE = 8'h00; + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000; + parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; + parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000; + parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000; + parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000; + parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; + parameter [3:0] PF3_PB_CAP_VER = 4'h1; + parameter [7:0] PF3_PM_CAP_ID = 8'h01; + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3; + parameter PF3_RBAR_CAP_ENABLE = "FALSE"; + parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000; + parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000; + parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000; + parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000; + parameter [3:0] PF3_RBAR_CAP_VER = 4'h1; + parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0; + parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0; + parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0; + parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00; + parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00; + parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00; + parameter [2:0] PF3_RBAR_NUM = 3'h1; + parameter [7:0] PF3_REVISION_ID = 8'h00; + parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; + parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; + parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000; + parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF3_TPHR_CAP_ENABLE = "FALSE"; + parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF3_TPHR_CAP_VER = 4'h1; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "TRUE"; + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; + parameter PL_DISABLE_SCRAMBLING = "FALSE"; + parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE"; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; + parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; + parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3; + parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4; + parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE"; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; + parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; + parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; + parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; + parameter integer PL_N_FTS_COMCLK_GEN1 = 255; + parameter integer PL_N_FTS_COMCLK_GEN2 = 255; + parameter integer PL_N_FTS_COMCLK_GEN3 = 255; + parameter integer PL_N_FTS_GEN1 = 255; + parameter integer PL_N_FTS_GEN2 = 255; + parameter integer PL_N_FTS_GEN3 = 255; + parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE"; + parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; + parameter PM_ENABLE_L23_ENTRY = "FALSE"; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; + parameter SIM_VERSION = "1.0"; + parameter integer SPARE_BIT0 = 0; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter integer SPARE_BIT3 = 0; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter SRIOV_CAP_ENABLE = "FALSE"; + parameter TL_COMPLETION_RAM_SIZE_16K = "TRUE"; + parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2FAF080; + parameter [11:0] TL_CREDITS_CD = 12'h3E0; + parameter [7:0] TL_CREDITS_CH = 8'h20; + parameter [11:0] TL_CREDITS_NPD = 12'h028; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [11:0] TL_CREDITS_PD = 12'h198; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; + parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter TL_LEGACY_MODE_ENABLE = "FALSE"; + parameter [1:0] TL_PF_ENABLE_REG = 2'h0; + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; + parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE"; + parameter TWO_LAYER_MODE_ENABLE = "FALSE"; + parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE"; + parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; + parameter integer VF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF0_PM_CAP_ID = 8'h01; + parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; + parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF0_TPHR_CAP_ENABLE = "FALSE"; + parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF1_PM_CAP_ID = 8'h01; + parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; + parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF1_TPHR_CAP_ENABLE = "FALSE"; + parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF2_PM_CAP_ID = 8'h01; + parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; + parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF2_TPHR_CAP_ENABLE = "FALSE"; + parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF3_PM_CAP_ID = 8'h01; + parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; + parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF3_TPHR_CAP_ENABLE = "FALSE"; + parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF4_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF4_PM_CAP_ID = 8'h01; + parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; + parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF4_TPHR_CAP_ENABLE = "FALSE"; + parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF5_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF5_PM_CAP_ID = 8'h01; + parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; + parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF5_TPHR_CAP_ENABLE = "FALSE"; + parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF6_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF6_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF6_PM_CAP_ID = 8'h01; + parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3; + parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF6_TPHR_CAP_ENABLE = "FALSE"; + parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF6_TPHR_CAP_VER = 4'h1; + parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000; + parameter integer VF7_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VF7_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] VF7_PM_CAP_ID = 8'h01; + parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00; + parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3; + parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter VF7_TPHR_CAP_ENABLE = "FALSE"; + parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] VF7_TPHR_CAP_VER = 4'h1; + output [2:0] CFGCURRENTSPEED; + output [3:0] CFGDPASUBSTATECHANGE; + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output [7:0] CFGEXTFUNCTIONNUMBER; + output CFGEXTREADRECEIVED; + output [9:0] CFGEXTREGISTERNUMBER; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [31:0] CFGEXTWRITEDATA; + output CFGEXTWRITERECEIVED; + output [11:0] CFGFCCPLD; + output [7:0] CFGFCCPLH; + output [11:0] CFGFCNPD; + output [7:0] CFGFCNPH; + output [11:0] CFGFCPD; + output [7:0] CFGFCPH; + output [3:0] CFGFLRINPROCESS; + output [11:0] CFGFUNCTIONPOWERSTATE; + output [15:0] CFGFUNCTIONSTATUS; + output CFGHOTRESETOUT; + output [31:0] CFGINTERRUPTMSIDATA; + output [3:0] CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output [11:0] CFGINTERRUPTMSIMMENABLE; + output CFGINTERRUPTMSISENT; + output [7:0] CFGINTERRUPTMSIVFENABLE; + output [3:0] CFGINTERRUPTMSIXENABLE; + output CFGINTERRUPTMSIXFAIL; + output [3:0] CFGINTERRUPTMSIXMASK; + output CFGINTERRUPTMSIXSENT; + output [7:0] CFGINTERRUPTMSIXVFENABLE; + output [7:0] CFGINTERRUPTMSIXVFMASK; + output CFGINTERRUPTSENT; + output [1:0] CFGLINKPOWERSTATE; + output CFGLOCALERROR; + output CFGLTRENABLE; + output [5:0] CFGLTSSMSTATE; + output [2:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [31:0] CFGMGMTREADDATA; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output [7:0] CFGMSGRECEIVEDDATA; + output [4:0] CFGMSGRECEIVEDTYPE; + output CFGMSGTRANSMITDONE; + output [3:0] CFGNEGOTIATEDWIDTH; + output [1:0] CFGOBFFENABLE; + output [15:0] CFGPERFUNCSTATUSDATA; + output CFGPERFUNCTIONUPDATEDONE; + output CFGPHYLINKDOWN; + output [1:0] CFGPHYLINKSTATUS; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output [3:0] CFGRCBSTATUS; + output [3:0] CFGTPHFUNCTIONNUM; + output [3:0] CFGTPHREQUESTERENABLE; + output [11:0] CFGTPHSTMODE; + output [4:0] CFGTPHSTTADDRESS; + output CFGTPHSTTREADENABLE; + output [3:0] CFGTPHSTTWRITEBYTEVALID; + output [31:0] CFGTPHSTTWRITEDATA; + output CFGTPHSTTWRITEENABLE; + output [7:0] CFGVFFLRINPROCESS; + output [23:0] CFGVFPOWERSTATE; + output [15:0] CFGVFSTATUS; + output [7:0] CFGVFTPHREQUESTERENABLE; + output [23:0] CFGVFTPHSTMODE; + output CONFMCAPDESIGNSWITCH; + output CONFMCAPEOS; + output CONFMCAPINUSEBYPCIE; + output CONFREQREADY; + output [31:0] CONFRESPRDATA; + output CONFRESPVALID; + output [15:0] DBGDATAOUT; + output DBGMCAPCSB; + output [31:0] DBGMCAPDATA; + output DBGMCAPEOS; + output DBGMCAPERROR; + output DBGMCAPMODE; + output DBGMCAPRDATAVALID; + output DBGMCAPRDWRB; + output DBGMCAPRESET; + output DBGPLDATABLOCKRECEIVEDAFTEREDS; + output DBGPLGEN3FRAMINGERRORDETECTED; + output DBGPLGEN3SYNCHEADERERRORDETECTED; + output [7:0] DBGPLINFERREDRXELECTRICALIDLE; + output [15:0] DRPDO; + output DRPRDY; + output LL2LMMASTERTLPSENT0; + output LL2LMMASTERTLPSENT1; + output [3:0] LL2LMMASTERTLPSENTTLPID0; + output [3:0] LL2LMMASTERTLPSENTTLPID1; + output [255:0] LL2LMMAXISRXTDATA; + output [17:0] LL2LMMAXISRXTUSER; + output [7:0] LL2LMMAXISRXTVALID; + output [7:0] LL2LMSAXISTXTREADY; + output [255:0] MAXISCQTDATA; + output [7:0] MAXISCQTKEEP; + output MAXISCQTLAST; + output [84:0] MAXISCQTUSER; + output MAXISCQTVALID; + output [255:0] MAXISRCTDATA; + output [7:0] MAXISRCTKEEP; + output MAXISRCTLAST; + output [74:0] MAXISRCTUSER; + output MAXISRCTVALID; + output [9:0] MICOMPLETIONRAMREADADDRESSAL; + output [9:0] MICOMPLETIONRAMREADADDRESSAU; + output [9:0] MICOMPLETIONRAMREADADDRESSBL; + output [9:0] MICOMPLETIONRAMREADADDRESSBU; + output [3:0] MICOMPLETIONRAMREADENABLEL; + output [3:0] MICOMPLETIONRAMREADENABLEU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; + output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; + output [71:0] MICOMPLETIONRAMWRITEDATAL; + output [71:0] MICOMPLETIONRAMWRITEDATAU; + output [3:0] MICOMPLETIONRAMWRITEENABLEL; + output [3:0] MICOMPLETIONRAMWRITEENABLEU; + output [8:0] MIREPLAYRAMADDRESS; + output [1:0] MIREPLAYRAMREADENABLE; + output [143:0] MIREPLAYRAMWRITEDATA; + output [1:0] MIREPLAYRAMWRITEENABLE; + output [8:0] MIREQUESTRAMREADADDRESSA; + output [8:0] MIREQUESTRAMREADADDRESSB; + output [3:0] MIREQUESTRAMREADENABLE; + output [8:0] MIREQUESTRAMWRITEADDRESSA; + output [8:0] MIREQUESTRAMWRITEADDRESSB; + output [143:0] MIREQUESTRAMWRITEDATA; + output [3:0] MIREQUESTRAMWRITEENABLE; + output [5:0] PCIECQNPREQCOUNT; + output PCIEPERST0B; + output PCIEPERST1B; + output [3:0] PCIERQSEQNUM; + output PCIERQSEQNUMVLD; + output [5:0] PCIERQTAG; + output [1:0] PCIERQTAGAV; + output PCIERQTAGVLD; + output [1:0] PCIETFCNPDAV; + output [1:0] PCIETFCNPHAV; + output [1:0] PIPERX0EQCONTROL; + output [5:0] PIPERX0EQLPLFFS; + output [3:0] PIPERX0EQLPTXPRESET; + output [2:0] PIPERX0EQPRESET; + output PIPERX0POLARITY; + output [1:0] PIPERX1EQCONTROL; + output [5:0] PIPERX1EQLPLFFS; + output [3:0] PIPERX1EQLPTXPRESET; + output [2:0] PIPERX1EQPRESET; + output PIPERX1POLARITY; + output [1:0] PIPERX2EQCONTROL; + output [5:0] PIPERX2EQLPLFFS; + output [3:0] PIPERX2EQLPTXPRESET; + output [2:0] PIPERX2EQPRESET; + output PIPERX2POLARITY; + output [1:0] PIPERX3EQCONTROL; + output [5:0] PIPERX3EQLPLFFS; + output [3:0] PIPERX3EQLPTXPRESET; + output [2:0] PIPERX3EQPRESET; + output PIPERX3POLARITY; + output [1:0] PIPERX4EQCONTROL; + output [5:0] PIPERX4EQLPLFFS; + output [3:0] PIPERX4EQLPTXPRESET; + output [2:0] PIPERX4EQPRESET; + output PIPERX4POLARITY; + output [1:0] PIPERX5EQCONTROL; + output [5:0] PIPERX5EQLPLFFS; + output [3:0] PIPERX5EQLPTXPRESET; + output [2:0] PIPERX5EQPRESET; + output PIPERX5POLARITY; + output [1:0] PIPERX6EQCONTROL; + output [5:0] PIPERX6EQLPLFFS; + output [3:0] PIPERX6EQLPTXPRESET; + output [2:0] PIPERX6EQPRESET; + output PIPERX6POLARITY; + output [1:0] PIPERX7EQCONTROL; + output [5:0] PIPERX7EQLPLFFS; + output [3:0] PIPERX7EQLPTXPRESET; + output [2:0] PIPERX7EQPRESET; + output PIPERX7POLARITY; + output [1:0] PIPETX0CHARISK; + output PIPETX0COMPLIANCE; + output [31:0] PIPETX0DATA; + output PIPETX0DATAVALID; + output PIPETX0DEEMPH; + output PIPETX0ELECIDLE; + output [1:0] PIPETX0EQCONTROL; + output [5:0] PIPETX0EQDEEMPH; + output [3:0] PIPETX0EQPRESET; + output [2:0] PIPETX0MARGIN; + output [1:0] PIPETX0POWERDOWN; + output [1:0] PIPETX0RATE; + output PIPETX0RCVRDET; + output PIPETX0RESET; + output PIPETX0STARTBLOCK; + output PIPETX0SWING; + output [1:0] PIPETX0SYNCHEADER; + output [1:0] PIPETX1CHARISK; + output PIPETX1COMPLIANCE; + output [31:0] PIPETX1DATA; + output PIPETX1DATAVALID; + output PIPETX1DEEMPH; + output PIPETX1ELECIDLE; + output [1:0] PIPETX1EQCONTROL; + output [5:0] PIPETX1EQDEEMPH; + output [3:0] PIPETX1EQPRESET; + output [2:0] PIPETX1MARGIN; + output [1:0] PIPETX1POWERDOWN; + output [1:0] PIPETX1RATE; + output PIPETX1RCVRDET; + output PIPETX1RESET; + output PIPETX1STARTBLOCK; + output PIPETX1SWING; + output [1:0] PIPETX1SYNCHEADER; + output [1:0] PIPETX2CHARISK; + output PIPETX2COMPLIANCE; + output [31:0] PIPETX2DATA; + output PIPETX2DATAVALID; + output PIPETX2DEEMPH; + output PIPETX2ELECIDLE; + output [1:0] PIPETX2EQCONTROL; + output [5:0] PIPETX2EQDEEMPH; + output [3:0] PIPETX2EQPRESET; + output [2:0] PIPETX2MARGIN; + output [1:0] PIPETX2POWERDOWN; + output [1:0] PIPETX2RATE; + output PIPETX2RCVRDET; + output PIPETX2RESET; + output PIPETX2STARTBLOCK; + output PIPETX2SWING; + output [1:0] PIPETX2SYNCHEADER; + output [1:0] PIPETX3CHARISK; + output PIPETX3COMPLIANCE; + output [31:0] PIPETX3DATA; + output PIPETX3DATAVALID; + output PIPETX3DEEMPH; + output PIPETX3ELECIDLE; + output [1:0] PIPETX3EQCONTROL; + output [5:0] PIPETX3EQDEEMPH; + output [3:0] PIPETX3EQPRESET; + output [2:0] PIPETX3MARGIN; + output [1:0] PIPETX3POWERDOWN; + output [1:0] PIPETX3RATE; + output PIPETX3RCVRDET; + output PIPETX3RESET; + output PIPETX3STARTBLOCK; + output PIPETX3SWING; + output [1:0] PIPETX3SYNCHEADER; + output [1:0] PIPETX4CHARISK; + output PIPETX4COMPLIANCE; + output [31:0] PIPETX4DATA; + output PIPETX4DATAVALID; + output PIPETX4DEEMPH; + output PIPETX4ELECIDLE; + output [1:0] PIPETX4EQCONTROL; + output [5:0] PIPETX4EQDEEMPH; + output [3:0] PIPETX4EQPRESET; + output [2:0] PIPETX4MARGIN; + output [1:0] PIPETX4POWERDOWN; + output [1:0] PIPETX4RATE; + output PIPETX4RCVRDET; + output PIPETX4RESET; + output PIPETX4STARTBLOCK; + output PIPETX4SWING; + output [1:0] PIPETX4SYNCHEADER; + output [1:0] PIPETX5CHARISK; + output PIPETX5COMPLIANCE; + output [31:0] PIPETX5DATA; + output PIPETX5DATAVALID; + output PIPETX5DEEMPH; + output PIPETX5ELECIDLE; + output [1:0] PIPETX5EQCONTROL; + output [5:0] PIPETX5EQDEEMPH; + output [3:0] PIPETX5EQPRESET; + output [2:0] PIPETX5MARGIN; + output [1:0] PIPETX5POWERDOWN; + output [1:0] PIPETX5RATE; + output PIPETX5RCVRDET; + output PIPETX5RESET; + output PIPETX5STARTBLOCK; + output PIPETX5SWING; + output [1:0] PIPETX5SYNCHEADER; + output [1:0] PIPETX6CHARISK; + output PIPETX6COMPLIANCE; + output [31:0] PIPETX6DATA; + output PIPETX6DATAVALID; + output PIPETX6DEEMPH; + output PIPETX6ELECIDLE; + output [1:0] PIPETX6EQCONTROL; + output [5:0] PIPETX6EQDEEMPH; + output [3:0] PIPETX6EQPRESET; + output [2:0] PIPETX6MARGIN; + output [1:0] PIPETX6POWERDOWN; + output [1:0] PIPETX6RATE; + output PIPETX6RCVRDET; + output PIPETX6RESET; + output PIPETX6STARTBLOCK; + output PIPETX6SWING; + output [1:0] PIPETX6SYNCHEADER; + output [1:0] PIPETX7CHARISK; + output PIPETX7COMPLIANCE; + output [31:0] PIPETX7DATA; + output PIPETX7DATAVALID; + output PIPETX7DEEMPH; + output PIPETX7ELECIDLE; + output [1:0] PIPETX7EQCONTROL; + output [5:0] PIPETX7EQDEEMPH; + output [3:0] PIPETX7EQPRESET; + output [2:0] PIPETX7MARGIN; + output [1:0] PIPETX7POWERDOWN; + output [1:0] PIPETX7RATE; + output PIPETX7RCVRDET; + output PIPETX7RESET; + output PIPETX7STARTBLOCK; + output PIPETX7SWING; + output [1:0] PIPETX7SYNCHEADER; + output PLEQINPROGRESS; + output [1:0] PLEQPHASE; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [31:0] SPAREOUT; + input CFGCONFIGSPACEENABLE; + input [15:0] CFGDEVID; + input [7:0] CFGDSBUSNUMBER; + input [4:0] CFGDSDEVICENUMBER; + input [2:0] CFGDSFUNCTIONNUMBER; + input [63:0] CFGDSN; + input [7:0] CFGDSPORTNUMBER; + input CFGERRCORIN; + input CFGERRUNCORIN; + input [31:0] CFGEXTREADDATA; + input CFGEXTREADDATAVALID; + input [2:0] CFGFCSEL; + input [3:0] CFGFLRDONE; + input CFGHOTRESETIN; + input [3:0] CFGINTERRUPTINT; + input [2:0] CFGINTERRUPTMSIATTR; + input [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; + input [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; + input [3:0] CFGINTERRUPTMSISELECT; + input CFGINTERRUPTMSITPHPRESENT; + input [8:0] CFGINTERRUPTMSITPHSTTAG; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [31:0] CFGINTERRUPTMSIXDATA; + input CFGINTERRUPTMSIXINT; + input [3:0] CFGINTERRUPTPENDING; + input CFGLINKTRAININGENABLE; + input [18:0] CFGMGMTADDR; + input [3:0] CFGMGMTBYTEENABLE; + input CFGMGMTREAD; + input CFGMGMTTYPE1CFGREGACCESS; + input CFGMGMTWRITE; + input [31:0] CFGMGMTWRITEDATA; + input CFGMSGTRANSMIT; + input [31:0] CFGMSGTRANSMITDATA; + input [2:0] CFGMSGTRANSMITTYPE; + input [2:0] CFGPERFUNCSTATUSCONTROL; + input [3:0] CFGPERFUNCTIONNUMBER; + input CFGPERFUNCTIONOUTPUTREQUEST; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input [7:0] CFGREVID; + input [15:0] CFGSUBSYSID; + input [15:0] CFGSUBSYSVENDID; + input [31:0] CFGTPHSTTREADDATA; + input CFGTPHSTTREADDATAVALID; + input [15:0] CFGVENDID; + input [7:0] CFGVFFLRDONE; + input CONFMCAPREQUESTBYCONF; + input [31:0] CONFREQDATA; + input [3:0] CONFREQREGNUM; + input [1:0] CONFREQTYPE; + input CONFREQVALID; + input CORECLK; + input CORECLKMICOMPLETIONRAML; + input CORECLKMICOMPLETIONRAMU; + input CORECLKMIREPLAYRAM; + input CORECLKMIREQUESTRAM; + input DBGCFGLOCALMGMTREGOVERRIDE; + input [3:0] DBGDATASEL; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input [13:0] LL2LMSAXISTXTUSER; + input LL2LMSAXISTXTVALID; + input [3:0] LL2LMTXTLPID0; + input [3:0] LL2LMTXTLPID1; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input MCAPCLK; + input MCAPPERST0B; + input MCAPPERST1B; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input [143:0] MICOMPLETIONRAMREADDATA; + input [143:0] MIREPLAYRAMREADDATA; + input [143:0] MIREQUESTRAMREADDATA; + input PCIECQNPREQ; + input PIPECLK; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input PIPERESETN; + input [1:0] PIPERX0CHARISK; + input [31:0] PIPERX0DATA; + input PIPERX0DATAVALID; + input PIPERX0ELECIDLE; + input PIPERX0EQDONE; + input PIPERX0EQLPADAPTDONE; + input PIPERX0EQLPLFFSSEL; + input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; + input PIPERX0PHYSTATUS; + input PIPERX0STARTBLOCK; + input [2:0] PIPERX0STATUS; + input [1:0] PIPERX0SYNCHEADER; + input PIPERX0VALID; + input [1:0] PIPERX1CHARISK; + input [31:0] PIPERX1DATA; + input PIPERX1DATAVALID; + input PIPERX1ELECIDLE; + input PIPERX1EQDONE; + input PIPERX1EQLPADAPTDONE; + input PIPERX1EQLPLFFSSEL; + input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; + input PIPERX1PHYSTATUS; + input PIPERX1STARTBLOCK; + input [2:0] PIPERX1STATUS; + input [1:0] PIPERX1SYNCHEADER; + input PIPERX1VALID; + input [1:0] PIPERX2CHARISK; + input [31:0] PIPERX2DATA; + input PIPERX2DATAVALID; + input PIPERX2ELECIDLE; + input PIPERX2EQDONE; + input PIPERX2EQLPADAPTDONE; + input PIPERX2EQLPLFFSSEL; + input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; + input PIPERX2PHYSTATUS; + input PIPERX2STARTBLOCK; + input [2:0] PIPERX2STATUS; + input [1:0] PIPERX2SYNCHEADER; + input PIPERX2VALID; + input [1:0] PIPERX3CHARISK; + input [31:0] PIPERX3DATA; + input PIPERX3DATAVALID; + input PIPERX3ELECIDLE; + input PIPERX3EQDONE; + input PIPERX3EQLPADAPTDONE; + input PIPERX3EQLPLFFSSEL; + input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; + input PIPERX3PHYSTATUS; + input PIPERX3STARTBLOCK; + input [2:0] PIPERX3STATUS; + input [1:0] PIPERX3SYNCHEADER; + input PIPERX3VALID; + input [1:0] PIPERX4CHARISK; + input [31:0] PIPERX4DATA; + input PIPERX4DATAVALID; + input PIPERX4ELECIDLE; + input PIPERX4EQDONE; + input PIPERX4EQLPADAPTDONE; + input PIPERX4EQLPLFFSSEL; + input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; + input PIPERX4PHYSTATUS; + input PIPERX4STARTBLOCK; + input [2:0] PIPERX4STATUS; + input [1:0] PIPERX4SYNCHEADER; + input PIPERX4VALID; + input [1:0] PIPERX5CHARISK; + input [31:0] PIPERX5DATA; + input PIPERX5DATAVALID; + input PIPERX5ELECIDLE; + input PIPERX5EQDONE; + input PIPERX5EQLPADAPTDONE; + input PIPERX5EQLPLFFSSEL; + input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; + input PIPERX5PHYSTATUS; + input PIPERX5STARTBLOCK; + input [2:0] PIPERX5STATUS; + input [1:0] PIPERX5SYNCHEADER; + input PIPERX5VALID; + input [1:0] PIPERX6CHARISK; + input [31:0] PIPERX6DATA; + input PIPERX6DATAVALID; + input PIPERX6ELECIDLE; + input PIPERX6EQDONE; + input PIPERX6EQLPADAPTDONE; + input PIPERX6EQLPLFFSSEL; + input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; + input PIPERX6PHYSTATUS; + input PIPERX6STARTBLOCK; + input [2:0] PIPERX6STATUS; + input [1:0] PIPERX6SYNCHEADER; + input PIPERX6VALID; + input [1:0] PIPERX7CHARISK; + input [31:0] PIPERX7DATA; + input PIPERX7DATAVALID; + input PIPERX7ELECIDLE; + input PIPERX7EQDONE; + input PIPERX7EQLPADAPTDONE; + input PIPERX7EQLPLFFSSEL; + input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; + input PIPERX7PHYSTATUS; + input PIPERX7STARTBLOCK; + input [2:0] PIPERX7STATUS; + input [1:0] PIPERX7SYNCHEADER; + input PIPERX7VALID; + input [17:0] PIPETX0EQCOEFF; + input PIPETX0EQDONE; + input [17:0] PIPETX1EQCOEFF; + input PIPETX1EQDONE; + input [17:0] PIPETX2EQCOEFF; + input PIPETX2EQDONE; + input [17:0] PIPETX3EQCOEFF; + input PIPETX3EQDONE; + input [17:0] PIPETX4EQCOEFF; + input PIPETX4EQDONE; + input [17:0] PIPETX5EQCOEFF; + input PIPETX5EQDONE; + input [17:0] PIPETX6EQCOEFF; + input PIPETX6EQDONE; + input [17:0] PIPETX7EQCOEFF; + input PIPETX7EQDONE; + input PLEQRESETEIEOSCOUNT; + input PLGEN2UPSTREAMPREFERDEEMPH; + input RESETN; + input [255:0] SAXISCCTDATA; + input [7:0] SAXISCCTKEEP; + input SAXISCCTLAST; + input [32:0] SAXISCCTUSER; + input SAXISCCTVALID; + input [255:0] SAXISRQTDATA; + input [7:0] SAXISRQTKEEP; + input SAXISRQTLAST; + input [59:0] SAXISRQTUSER; + input SAXISRQTVALID; + input [31:0] SPAREIN; + input USERCLK; +endmodule + +module PCIE40E4 (...); + parameter ARI_CAP_ENABLE = "FALSE"; + parameter AUTO_FLR_RESPONSE = "FALSE"; + parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; + parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20; + parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080; + parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE"; + parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE"; + parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; + parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE"; + parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE"; + parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; + parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; + parameter AXISTEN_IF_EXT_512 = "FALSE"; + parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE"; + parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE"; + parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE"; + parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE"; + parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE"; + parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE"; + parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; + parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0; + parameter AXISTEN_IF_RX_PARITY_EN = "TRUE"; + parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE"; + parameter AXISTEN_IF_TX_PARITY_EN = "TRUE"; + parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; + parameter CFG_BYPASS_MODE_ENABLE = "FALSE"; + parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; + parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; + parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000; + parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00; + parameter [3:0] DEBUG_CAR_SPARE = 4'h0; + parameter [15:0] DEBUG_CFG_SPARE = 16'h0000; + parameter [15:0] DEBUG_LL_SPARE = 16'h0000; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE"; + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE"; + parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE"; + parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE"; + parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE"; + parameter [15:0] DEBUG_PL_SPARE = 16'h0000; + parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE"; + parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; + parameter [15:0] DEBUG_TL_SPARE = 16'h0000; + parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; + parameter DSN_CAP_ENABLE = "FALSE"; + parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter HEADER_TYPE_OVERRIDE = "FALSE"; + parameter IS_SWITCH_PORT = "FALSE"; + parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; + parameter [8:0] LL_ACK_TIMEOUT = 9'h000; + parameter LL_ACK_TIMEOUT_EN = "FALSE"; + parameter integer LL_ACK_TIMEOUT_FUNC = 0; + parameter LL_DISABLE_SCHED_TX_NAK = "FALSE"; + parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE"; + parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; + parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; + parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; + parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE"; + parameter LL_RX_TLP_PARITY_GEN = "TRUE"; + parameter LL_TX_TLP_PARITY_CHK = "TRUE"; + parameter [15:0] LL_USER_SPARE = 16'h0000; + parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250; + parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; + parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; + parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; + parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; + parameter MCAP_ENABLE = "FALSE"; + parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; + parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; + parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; + parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; + parameter [15:0] MCAP_VSEC_ID = 16'h0000; + parameter [11:0] MCAP_VSEC_LEN = 12'h02C; + parameter [3:0] MCAP_VSEC_REV = 4'h0; + parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE"; + parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [3:0] PF0_ARI_CAP_VER = 4'h1; + parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_BAR1_CONTROL = 3'h0; + parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR3_CONTROL = 3'h0; + parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_BAR5_CONTROL = 3'h0; + parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF0_CLASS_CODE = 24'h000000; + parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; + parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; + parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; + parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; + parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; + parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; + parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; + parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; + parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; + parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; + parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; + parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; + parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7; + parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0; + parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; + parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; + parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; + parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_LTR_CAP_VER = 4'h1; + parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04; + parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; + parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF0_PM_CAP_ID = 8'h01; + parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; + parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; + parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; + parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; + parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; + parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; + parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; + parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; + parameter PF0_TPHR_CAP_ENABLE = "FALSE"; + parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; + parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; + parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; + parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; + parameter PF0_VC_CAP_ENABLE = "FALSE"; + parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; + parameter [3:0] PF0_VC_CAP_VER = 4'h1; + parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_BAR1_CONTROL = 3'h0; + parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR3_CONTROL = 3'h0; + parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_BAR5_CONTROL = 3'h0; + parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF1_CLASS_CODE = 24'h000000; + parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; + parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; + parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_BAR1_CONTROL = 3'h0; + parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR3_CONTROL = 3'h0; + parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_BAR5_CONTROL = 3'h0; + parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF2_CLASS_CODE = 24'h000000; + parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; + parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; + parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; + parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; + parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_BAR1_CONTROL = 3'h0; + parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR3_CONTROL = 3'h0; + parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_BAR5_CONTROL = 3'h0; + parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80; + parameter [23:0] PF3_CLASS_CODE = 24'h000000; + parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; + parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; + parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; + parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; + parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; + parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer PF3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; + parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; + parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; + parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00; + parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; + parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; + parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; + parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; + parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; + parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03; + parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; + parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; + parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; + parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; + parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; + parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; + parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; + parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; + parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; + parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; + parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; + parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE"; + parameter PL_DEEMPH_SOURCE_SELECT = "TRUE"; + parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE"; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; + parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE"; + parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; + parameter PL_DISABLE_DC_BALANCE = "FALSE"; + parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; + parameter PL_DISABLE_LANE_REVERSAL = "FALSE"; + parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0; + parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE"; + parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; + parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000; + parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; + parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0; + parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0; + parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; + parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; + parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0; + parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33; + parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44; + parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE"; + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0; + parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0; + parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; + parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE"; + parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE"; + parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE"; + parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE"; + parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE"; + parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00; + parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00; + parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4; + parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08; + parameter integer PL_N_FTS = 255; + parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE"; + parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE"; + parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00; + parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0; + parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0; + parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0; + parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0; + parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0; + parameter PL_SRIS_ENABLE = "FALSE"; + parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00; + parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00; + parameter PL_UPSTREAM_FACING = "TRUE"; + parameter [15:0] PL_USER_SPARE = 16'h0000; + parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500; + parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8; + parameter PM_ENABLE_L23_ENTRY = "FALSE"; + parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; + parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100; + parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000; + parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; + parameter SIM_VERSION = "1.0"; + parameter SPARE_BIT0 = "FALSE"; + parameter integer SPARE_BIT1 = 0; + parameter integer SPARE_BIT2 = 0; + parameter SPARE_BIT3 = "FALSE"; + parameter integer SPARE_BIT4 = 0; + parameter integer SPARE_BIT5 = 0; + parameter integer SPARE_BIT6 = 0; + parameter integer SPARE_BIT7 = 0; + parameter integer SPARE_BIT8 = 0; + parameter [7:0] SPARE_BYTE0 = 8'h00; + parameter [7:0] SPARE_BYTE1 = 8'h00; + parameter [7:0] SPARE_BYTE2 = 8'h00; + parameter [7:0] SPARE_BYTE3 = 8'h00; + parameter [31:0] SPARE_WORD0 = 32'h00000000; + parameter [31:0] SPARE_WORD1 = 32'h00000000; + parameter [31:0] SPARE_WORD2 = 32'h00000000; + parameter [31:0] SPARE_WORD3 = 32'h00000000; + parameter [3:0] SRIOV_CAP_ENABLE = 4'h0; + parameter TL2CFG_IF_PARITY_CHK = "TRUE"; + parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0; + parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1; + parameter [11:0] TL_CREDITS_CD = 12'h000; + parameter [7:0] TL_CREDITS_CH = 8'h00; + parameter [11:0] TL_CREDITS_NPD = 12'h004; + parameter [7:0] TL_CREDITS_NPH = 8'h20; + parameter [11:0] TL_CREDITS_PD = 12'h0E0; + parameter [7:0] TL_CREDITS_PH = 8'h20; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02; + parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08; + parameter [1:0] TL_PF_ENABLE_REG = 2'h0; + parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0; + parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE"; + parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE"; + parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; + parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE"; + parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE"; + parameter [15:0] TL_USER_SPARE = 16'h0000; + parameter TPH_FROM_RAM_PIPELINE = "FALSE"; + parameter TPH_TO_RAM_PIPELINE = "FALSE"; + parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80; + parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG0_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG1_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG2_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0; + parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000; + parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00; + parameter integer VFG3_MSIX_CAP_PBA_BIR = 0; + parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050; + parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0; + parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; + parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000; + parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00; + parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000; + parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0; + output [7:0] AXIUSEROUT; + output [7:0] CFGBUSNUMBER; + output [1:0] CFGCURRENTSPEED; + output CFGERRCOROUT; + output CFGERRFATALOUT; + output CFGERRNONFATALOUT; + output [7:0] CFGEXTFUNCTIONNUMBER; + output CFGEXTREADRECEIVED; + output [9:0] CFGEXTREGISTERNUMBER; + output [3:0] CFGEXTWRITEBYTEENABLE; + output [31:0] CFGEXTWRITEDATA; + output CFGEXTWRITERECEIVED; + output [11:0] CFGFCCPLD; + output [7:0] CFGFCCPLH; + output [11:0] CFGFCNPD; + output [7:0] CFGFCNPH; + output [11:0] CFGFCPD; + output [7:0] CFGFCPH; + output [3:0] CFGFLRINPROCESS; + output [11:0] CFGFUNCTIONPOWERSTATE; + output [15:0] CFGFUNCTIONSTATUS; + output CFGHOTRESETOUT; + output [31:0] CFGINTERRUPTMSIDATA; + output [3:0] CFGINTERRUPTMSIENABLE; + output CFGINTERRUPTMSIFAIL; + output CFGINTERRUPTMSIMASKUPDATE; + output [11:0] CFGINTERRUPTMSIMMENABLE; + output CFGINTERRUPTMSISENT; + output [3:0] CFGINTERRUPTMSIXENABLE; + output [3:0] CFGINTERRUPTMSIXMASK; + output CFGINTERRUPTMSIXVECPENDINGSTATUS; + output CFGINTERRUPTSENT; + output [1:0] CFGLINKPOWERSTATE; + output [4:0] CFGLOCALERROROUT; + output CFGLOCALERRORVALID; + output CFGLTRENABLE; + output [5:0] CFGLTSSMSTATE; + output [1:0] CFGMAXPAYLOAD; + output [2:0] CFGMAXREADREQ; + output [31:0] CFGMGMTREADDATA; + output CFGMGMTREADWRITEDONE; + output CFGMSGRECEIVED; + output [7:0] CFGMSGRECEIVEDDATA; + output [4:0] CFGMSGRECEIVEDTYPE; + output CFGMSGTRANSMITDONE; + output [12:0] CFGMSIXRAMADDRESS; + output CFGMSIXRAMREADENABLE; + output [3:0] CFGMSIXRAMWRITEBYTEENABLE; + output [35:0] CFGMSIXRAMWRITEDATA; + output [2:0] CFGNEGOTIATEDWIDTH; + output [1:0] CFGOBFFENABLE; + output CFGPHYLINKDOWN; + output [1:0] CFGPHYLINKSTATUS; + output CFGPLSTATUSCHANGE; + output CFGPOWERSTATECHANGEINTERRUPT; + output [3:0] CFGRCBSTATUS; + output [1:0] CFGRXPMSTATE; + output [11:0] CFGTPHRAMADDRESS; + output CFGTPHRAMREADENABLE; + output [3:0] CFGTPHRAMWRITEBYTEENABLE; + output [35:0] CFGTPHRAMWRITEDATA; + output [3:0] CFGTPHREQUESTERENABLE; + output [11:0] CFGTPHSTMODE; + output [1:0] CFGTXPMSTATE; + output CONFMCAPDESIGNSWITCH; + output CONFMCAPEOS; + output CONFMCAPINUSEBYPCIE; + output CONFREQREADY; + output [31:0] CONFRESPRDATA; + output CONFRESPVALID; + output [31:0] DBGCTRL0OUT; + output [31:0] DBGCTRL1OUT; + output [255:0] DBGDATA0OUT; + output [255:0] DBGDATA1OUT; + output [15:0] DRPDO; + output DRPRDY; + output [255:0] MAXISCQTDATA; + output [7:0] MAXISCQTKEEP; + output MAXISCQTLAST; + output [87:0] MAXISCQTUSER; + output MAXISCQTVALID; + output [255:0] MAXISRCTDATA; + output [7:0] MAXISRCTKEEP; + output MAXISRCTLAST; + output [74:0] MAXISRCTUSER; + output MAXISRCTVALID; + output [8:0] MIREPLAYRAMADDRESS0; + output [8:0] MIREPLAYRAMADDRESS1; + output MIREPLAYRAMREADENABLE0; + output MIREPLAYRAMREADENABLE1; + output [127:0] MIREPLAYRAMWRITEDATA0; + output [127:0] MIREPLAYRAMWRITEDATA1; + output MIREPLAYRAMWRITEENABLE0; + output MIREPLAYRAMWRITEENABLE1; + output [8:0] MIRXCOMPLETIONRAMREADADDRESS0; + output [8:0] MIRXCOMPLETIONRAMREADADDRESS1; + output [1:0] MIRXCOMPLETIONRAMREADENABLE0; + output [1:0] MIRXCOMPLETIONRAMREADENABLE1; + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0; + output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1; + output [143:0] MIRXCOMPLETIONRAMWRITEDATA0; + output [143:0] MIRXCOMPLETIONRAMWRITEDATA1; + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0; + output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1; + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0; + output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1; + output MIRXPOSTEDREQUESTRAMREADENABLE0; + output MIRXPOSTEDREQUESTRAMREADENABLE1; + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0; + output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1; + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0; + output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1; + output MIRXPOSTEDREQUESTRAMWRITEENABLE0; + output MIRXPOSTEDREQUESTRAMWRITEENABLE1; + output [5:0] PCIECQNPREQCOUNT; + output PCIEPERST0B; + output PCIEPERST1B; + output [5:0] PCIERQSEQNUM0; + output [5:0] PCIERQSEQNUM1; + output PCIERQSEQNUMVLD0; + output PCIERQSEQNUMVLD1; + output [7:0] PCIERQTAG0; + output [7:0] PCIERQTAG1; + output [3:0] PCIERQTAGAV; + output PCIERQTAGVLD0; + output PCIERQTAGVLD1; + output [3:0] PCIETFCNPDAV; + output [3:0] PCIETFCNPHAV; + output [1:0] PIPERX00EQCONTROL; + output PIPERX00POLARITY; + output [1:0] PIPERX01EQCONTROL; + output PIPERX01POLARITY; + output [1:0] PIPERX02EQCONTROL; + output PIPERX02POLARITY; + output [1:0] PIPERX03EQCONTROL; + output PIPERX03POLARITY; + output [1:0] PIPERX04EQCONTROL; + output PIPERX04POLARITY; + output [1:0] PIPERX05EQCONTROL; + output PIPERX05POLARITY; + output [1:0] PIPERX06EQCONTROL; + output PIPERX06POLARITY; + output [1:0] PIPERX07EQCONTROL; + output PIPERX07POLARITY; + output [1:0] PIPERX08EQCONTROL; + output PIPERX08POLARITY; + output [1:0] PIPERX09EQCONTROL; + output PIPERX09POLARITY; + output [1:0] PIPERX10EQCONTROL; + output PIPERX10POLARITY; + output [1:0] PIPERX11EQCONTROL; + output PIPERX11POLARITY; + output [1:0] PIPERX12EQCONTROL; + output PIPERX12POLARITY; + output [1:0] PIPERX13EQCONTROL; + output PIPERX13POLARITY; + output [1:0] PIPERX14EQCONTROL; + output PIPERX14POLARITY; + output [1:0] PIPERX15EQCONTROL; + output PIPERX15POLARITY; + output [5:0] PIPERXEQLPLFFS; + output [3:0] PIPERXEQLPTXPRESET; + output [1:0] PIPETX00CHARISK; + output PIPETX00COMPLIANCE; + output [31:0] PIPETX00DATA; + output PIPETX00DATAVALID; + output PIPETX00ELECIDLE; + output [1:0] PIPETX00EQCONTROL; + output [5:0] PIPETX00EQDEEMPH; + output [1:0] PIPETX00POWERDOWN; + output PIPETX00STARTBLOCK; + output [1:0] PIPETX00SYNCHEADER; + output [1:0] PIPETX01CHARISK; + output PIPETX01COMPLIANCE; + output [31:0] PIPETX01DATA; + output PIPETX01DATAVALID; + output PIPETX01ELECIDLE; + output [1:0] PIPETX01EQCONTROL; + output [5:0] PIPETX01EQDEEMPH; + output [1:0] PIPETX01POWERDOWN; + output PIPETX01STARTBLOCK; + output [1:0] PIPETX01SYNCHEADER; + output [1:0] PIPETX02CHARISK; + output PIPETX02COMPLIANCE; + output [31:0] PIPETX02DATA; + output PIPETX02DATAVALID; + output PIPETX02ELECIDLE; + output [1:0] PIPETX02EQCONTROL; + output [5:0] PIPETX02EQDEEMPH; + output [1:0] PIPETX02POWERDOWN; + output PIPETX02STARTBLOCK; + output [1:0] PIPETX02SYNCHEADER; + output [1:0] PIPETX03CHARISK; + output PIPETX03COMPLIANCE; + output [31:0] PIPETX03DATA; + output PIPETX03DATAVALID; + output PIPETX03ELECIDLE; + output [1:0] PIPETX03EQCONTROL; + output [5:0] PIPETX03EQDEEMPH; + output [1:0] PIPETX03POWERDOWN; + output PIPETX03STARTBLOCK; + output [1:0] PIPETX03SYNCHEADER; + output [1:0] PIPETX04CHARISK; + output PIPETX04COMPLIANCE; + output [31:0] PIPETX04DATA; + output PIPETX04DATAVALID; + output PIPETX04ELECIDLE; + output [1:0] PIPETX04EQCONTROL; + output [5:0] PIPETX04EQDEEMPH; + output [1:0] PIPETX04POWERDOWN; + output PIPETX04STARTBLOCK; + output [1:0] PIPETX04SYNCHEADER; + output [1:0] PIPETX05CHARISK; + output PIPETX05COMPLIANCE; + output [31:0] PIPETX05DATA; + output PIPETX05DATAVALID; + output PIPETX05ELECIDLE; + output [1:0] PIPETX05EQCONTROL; + output [5:0] PIPETX05EQDEEMPH; + output [1:0] PIPETX05POWERDOWN; + output PIPETX05STARTBLOCK; + output [1:0] PIPETX05SYNCHEADER; + output [1:0] PIPETX06CHARISK; + output PIPETX06COMPLIANCE; + output [31:0] PIPETX06DATA; + output PIPETX06DATAVALID; + output PIPETX06ELECIDLE; + output [1:0] PIPETX06EQCONTROL; + output [5:0] PIPETX06EQDEEMPH; + output [1:0] PIPETX06POWERDOWN; + output PIPETX06STARTBLOCK; + output [1:0] PIPETX06SYNCHEADER; + output [1:0] PIPETX07CHARISK; + output PIPETX07COMPLIANCE; + output [31:0] PIPETX07DATA; + output PIPETX07DATAVALID; + output PIPETX07ELECIDLE; + output [1:0] PIPETX07EQCONTROL; + output [5:0] PIPETX07EQDEEMPH; + output [1:0] PIPETX07POWERDOWN; + output PIPETX07STARTBLOCK; + output [1:0] PIPETX07SYNCHEADER; + output [1:0] PIPETX08CHARISK; + output PIPETX08COMPLIANCE; + output [31:0] PIPETX08DATA; + output PIPETX08DATAVALID; + output PIPETX08ELECIDLE; + output [1:0] PIPETX08EQCONTROL; + output [5:0] PIPETX08EQDEEMPH; + output [1:0] PIPETX08POWERDOWN; + output PIPETX08STARTBLOCK; + output [1:0] PIPETX08SYNCHEADER; + output [1:0] PIPETX09CHARISK; + output PIPETX09COMPLIANCE; + output [31:0] PIPETX09DATA; + output PIPETX09DATAVALID; + output PIPETX09ELECIDLE; + output [1:0] PIPETX09EQCONTROL; + output [5:0] PIPETX09EQDEEMPH; + output [1:0] PIPETX09POWERDOWN; + output PIPETX09STARTBLOCK; + output [1:0] PIPETX09SYNCHEADER; + output [1:0] PIPETX10CHARISK; + output PIPETX10COMPLIANCE; + output [31:0] PIPETX10DATA; + output PIPETX10DATAVALID; + output PIPETX10ELECIDLE; + output [1:0] PIPETX10EQCONTROL; + output [5:0] PIPETX10EQDEEMPH; + output [1:0] PIPETX10POWERDOWN; + output PIPETX10STARTBLOCK; + output [1:0] PIPETX10SYNCHEADER; + output [1:0] PIPETX11CHARISK; + output PIPETX11COMPLIANCE; + output [31:0] PIPETX11DATA; + output PIPETX11DATAVALID; + output PIPETX11ELECIDLE; + output [1:0] PIPETX11EQCONTROL; + output [5:0] PIPETX11EQDEEMPH; + output [1:0] PIPETX11POWERDOWN; + output PIPETX11STARTBLOCK; + output [1:0] PIPETX11SYNCHEADER; + output [1:0] PIPETX12CHARISK; + output PIPETX12COMPLIANCE; + output [31:0] PIPETX12DATA; + output PIPETX12DATAVALID; + output PIPETX12ELECIDLE; + output [1:0] PIPETX12EQCONTROL; + output [5:0] PIPETX12EQDEEMPH; + output [1:0] PIPETX12POWERDOWN; + output PIPETX12STARTBLOCK; + output [1:0] PIPETX12SYNCHEADER; + output [1:0] PIPETX13CHARISK; + output PIPETX13COMPLIANCE; + output [31:0] PIPETX13DATA; + output PIPETX13DATAVALID; + output PIPETX13ELECIDLE; + output [1:0] PIPETX13EQCONTROL; + output [5:0] PIPETX13EQDEEMPH; + output [1:0] PIPETX13POWERDOWN; + output PIPETX13STARTBLOCK; + output [1:0] PIPETX13SYNCHEADER; + output [1:0] PIPETX14CHARISK; + output PIPETX14COMPLIANCE; + output [31:0] PIPETX14DATA; + output PIPETX14DATAVALID; + output PIPETX14ELECIDLE; + output [1:0] PIPETX14EQCONTROL; + output [5:0] PIPETX14EQDEEMPH; + output [1:0] PIPETX14POWERDOWN; + output PIPETX14STARTBLOCK; + output [1:0] PIPETX14SYNCHEADER; + output [1:0] PIPETX15CHARISK; + output PIPETX15COMPLIANCE; + output [31:0] PIPETX15DATA; + output PIPETX15DATAVALID; + output PIPETX15ELECIDLE; + output [1:0] PIPETX15EQCONTROL; + output [5:0] PIPETX15EQDEEMPH; + output [1:0] PIPETX15POWERDOWN; + output PIPETX15STARTBLOCK; + output [1:0] PIPETX15SYNCHEADER; + output PIPETXDEEMPH; + output [2:0] PIPETXMARGIN; + output [1:0] PIPETXRATE; + output PIPETXRCVRDET; + output PIPETXRESET; + output PIPETXSWING; + output PLEQINPROGRESS; + output [1:0] PLEQPHASE; + output PLGEN34EQMISMATCH; + output [3:0] SAXISCCTREADY; + output [3:0] SAXISRQTREADY; + output [31:0] USERSPAREOUT; + input [7:0] AXIUSERIN; + input CFGCONFIGSPACEENABLE; + input [15:0] CFGDEVIDPF0; + input [15:0] CFGDEVIDPF1; + input [15:0] CFGDEVIDPF2; + input [15:0] CFGDEVIDPF3; + input [7:0] CFGDSBUSNUMBER; + input [4:0] CFGDSDEVICENUMBER; + input [2:0] CFGDSFUNCTIONNUMBER; + input [63:0] CFGDSN; + input [7:0] CFGDSPORTNUMBER; + input CFGERRCORIN; + input CFGERRUNCORIN; + input [31:0] CFGEXTREADDATA; + input CFGEXTREADDATAVALID; + input [2:0] CFGFCSEL; + input [3:0] CFGFLRDONE; + input CFGHOTRESETIN; + input [3:0] CFGINTERRUPTINT; + input [2:0] CFGINTERRUPTMSIATTR; + input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER; + input [31:0] CFGINTERRUPTMSIINT; + input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; + input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; + input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; + input [1:0] CFGINTERRUPTMSISELECT; + input CFGINTERRUPTMSITPHPRESENT; + input [7:0] CFGINTERRUPTMSITPHSTTAG; + input [1:0] CFGINTERRUPTMSITPHTYPE; + input [63:0] CFGINTERRUPTMSIXADDRESS; + input [31:0] CFGINTERRUPTMSIXDATA; + input CFGINTERRUPTMSIXINT; + input [1:0] CFGINTERRUPTMSIXVECPENDING; + input [3:0] CFGINTERRUPTPENDING; + input CFGLINKTRAININGENABLE; + input [9:0] CFGMGMTADDR; + input [3:0] CFGMGMTBYTEENABLE; + input CFGMGMTDEBUGACCESS; + input [7:0] CFGMGMTFUNCTIONNUMBER; + input CFGMGMTREAD; + input CFGMGMTWRITE; + input [31:0] CFGMGMTWRITEDATA; + input CFGMSGTRANSMIT; + input [31:0] CFGMSGTRANSMITDATA; + input [2:0] CFGMSGTRANSMITTYPE; + input [35:0] CFGMSIXRAMREADDATA; + input CFGPMASPML1ENTRYREJECT; + input CFGPMASPMTXL0SENTRYDISABLE; + input CFGPOWERSTATECHANGEACK; + input CFGREQPMTRANSITIONL23READY; + input [7:0] CFGREVIDPF0; + input [7:0] CFGREVIDPF1; + input [7:0] CFGREVIDPF2; + input [7:0] CFGREVIDPF3; + input [15:0] CFGSUBSYSIDPF0; + input [15:0] CFGSUBSYSIDPF1; + input [15:0] CFGSUBSYSIDPF2; + input [15:0] CFGSUBSYSIDPF3; + input [15:0] CFGSUBSYSVENDID; + input [35:0] CFGTPHRAMREADDATA; + input [15:0] CFGVENDID; + input CFGVFFLRDONE; + input [7:0] CFGVFFLRFUNCNUM; + input CONFMCAPREQUESTBYCONF; + input [31:0] CONFREQDATA; + input [3:0] CONFREQREGNUM; + input [1:0] CONFREQTYPE; + input CONFREQVALID; + input CORECLK; + input CORECLKMIREPLAYRAM0; + input CORECLKMIREPLAYRAM1; + input CORECLKMIRXCOMPLETIONRAM0; + input CORECLKMIRXCOMPLETIONRAM1; + input CORECLKMIRXPOSTEDREQUESTRAM0; + input CORECLKMIRXPOSTEDREQUESTRAM1; + input [5:0] DBGSEL0; + input [5:0] DBGSEL1; + input [9:0] DRPADDR; + input DRPCLK; + input [15:0] DRPDI; + input DRPEN; + input DRPWE; + input [21:0] MAXISCQTREADY; + input [21:0] MAXISRCTREADY; + input MCAPCLK; + input MCAPPERST0B; + input MCAPPERST1B; + input MGMTRESETN; + input MGMTSTICKYRESETN; + input [5:0] MIREPLAYRAMERRCOR; + input [5:0] MIREPLAYRAMERRUNCOR; + input [127:0] MIREPLAYRAMREADDATA0; + input [127:0] MIREPLAYRAMREADDATA1; + input [11:0] MIRXCOMPLETIONRAMERRCOR; + input [11:0] MIRXCOMPLETIONRAMERRUNCOR; + input [143:0] MIRXCOMPLETIONRAMREADDATA0; + input [143:0] MIRXCOMPLETIONRAMREADDATA1; + input [5:0] MIRXPOSTEDREQUESTRAMERRCOR; + input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR; + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0; + input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1; + input [1:0] PCIECOMPLDELIVERED; + input [7:0] PCIECOMPLDELIVEREDTAG0; + input [7:0] PCIECOMPLDELIVEREDTAG1; + input [1:0] PCIECQNPREQ; + input PCIECQNPUSERCREDITRCVD; + input PCIECQPIPELINEEMPTY; + input PCIEPOSTEDREQDELIVERED; + input PIPECLK; + input PIPECLKEN; + input [5:0] PIPEEQFS; + input [5:0] PIPEEQLF; + input PIPERESETN; + input [1:0] PIPERX00CHARISK; + input [31:0] PIPERX00DATA; + input PIPERX00DATAVALID; + input PIPERX00ELECIDLE; + input PIPERX00EQDONE; + input PIPERX00EQLPADAPTDONE; + input PIPERX00EQLPLFFSSEL; + input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET; + input PIPERX00PHYSTATUS; + input [1:0] PIPERX00STARTBLOCK; + input [2:0] PIPERX00STATUS; + input [1:0] PIPERX00SYNCHEADER; + input PIPERX00VALID; + input [1:0] PIPERX01CHARISK; + input [31:0] PIPERX01DATA; + input PIPERX01DATAVALID; + input PIPERX01ELECIDLE; + input PIPERX01EQDONE; + input PIPERX01EQLPADAPTDONE; + input PIPERX01EQLPLFFSSEL; + input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET; + input PIPERX01PHYSTATUS; + input [1:0] PIPERX01STARTBLOCK; + input [2:0] PIPERX01STATUS; + input [1:0] PIPERX01SYNCHEADER; + input PIPERX01VALID; + input [1:0] PIPERX02CHARISK; + input [31:0] PIPERX02DATA; + input PIPERX02DATAVALID; + input PIPERX02ELECIDLE; + input PIPERX02EQDONE; + input PIPERX02EQLPADAPTDONE; + input PIPERX02EQLPLFFSSEL; + input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET; + input PIPERX02PHYSTATUS; + input [1:0] PIPERX02STARTBLOCK; + input [2:0] PIPERX02STATUS; + input [1:0] PIPERX02SYNCHEADER; + input PIPERX02VALID; + input [1:0] PIPERX03CHARISK; + input [31:0] PIPERX03DATA; + input PIPERX03DATAVALID; + input PIPERX03ELECIDLE; + input PIPERX03EQDONE; + input PIPERX03EQLPADAPTDONE; + input PIPERX03EQLPLFFSSEL; + input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET; + input PIPERX03PHYSTATUS; + input [1:0] PIPERX03STARTBLOCK; + input [2:0] PIPERX03STATUS; + input [1:0] PIPERX03SYNCHEADER; + input PIPERX03VALID; + input [1:0] PIPERX04CHARISK; + input [31:0] PIPERX04DATA; + input PIPERX04DATAVALID; + input PIPERX04ELECIDLE; + input PIPERX04EQDONE; + input PIPERX04EQLPADAPTDONE; + input PIPERX04EQLPLFFSSEL; + input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET; + input PIPERX04PHYSTATUS; + input [1:0] PIPERX04STARTBLOCK; + input [2:0] PIPERX04STATUS; + input [1:0] PIPERX04SYNCHEADER; + input PIPERX04VALID; + input [1:0] PIPERX05CHARISK; + input [31:0] PIPERX05DATA; + input PIPERX05DATAVALID; + input PIPERX05ELECIDLE; + input PIPERX05EQDONE; + input PIPERX05EQLPADAPTDONE; + input PIPERX05EQLPLFFSSEL; + input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET; + input PIPERX05PHYSTATUS; + input [1:0] PIPERX05STARTBLOCK; + input [2:0] PIPERX05STATUS; + input [1:0] PIPERX05SYNCHEADER; + input PIPERX05VALID; + input [1:0] PIPERX06CHARISK; + input [31:0] PIPERX06DATA; + input PIPERX06DATAVALID; + input PIPERX06ELECIDLE; + input PIPERX06EQDONE; + input PIPERX06EQLPADAPTDONE; + input PIPERX06EQLPLFFSSEL; + input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET; + input PIPERX06PHYSTATUS; + input [1:0] PIPERX06STARTBLOCK; + input [2:0] PIPERX06STATUS; + input [1:0] PIPERX06SYNCHEADER; + input PIPERX06VALID; + input [1:0] PIPERX07CHARISK; + input [31:0] PIPERX07DATA; + input PIPERX07DATAVALID; + input PIPERX07ELECIDLE; + input PIPERX07EQDONE; + input PIPERX07EQLPADAPTDONE; + input PIPERX07EQLPLFFSSEL; + input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET; + input PIPERX07PHYSTATUS; + input [1:0] PIPERX07STARTBLOCK; + input [2:0] PIPERX07STATUS; + input [1:0] PIPERX07SYNCHEADER; + input PIPERX07VALID; + input [1:0] PIPERX08CHARISK; + input [31:0] PIPERX08DATA; + input PIPERX08DATAVALID; + input PIPERX08ELECIDLE; + input PIPERX08EQDONE; + input PIPERX08EQLPADAPTDONE; + input PIPERX08EQLPLFFSSEL; + input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET; + input PIPERX08PHYSTATUS; + input [1:0] PIPERX08STARTBLOCK; + input [2:0] PIPERX08STATUS; + input [1:0] PIPERX08SYNCHEADER; + input PIPERX08VALID; + input [1:0] PIPERX09CHARISK; + input [31:0] PIPERX09DATA; + input PIPERX09DATAVALID; + input PIPERX09ELECIDLE; + input PIPERX09EQDONE; + input PIPERX09EQLPADAPTDONE; + input PIPERX09EQLPLFFSSEL; + input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET; + input PIPERX09PHYSTATUS; + input [1:0] PIPERX09STARTBLOCK; + input [2:0] PIPERX09STATUS; + input [1:0] PIPERX09SYNCHEADER; + input PIPERX09VALID; + input [1:0] PIPERX10CHARISK; + input [31:0] PIPERX10DATA; + input PIPERX10DATAVALID; + input PIPERX10ELECIDLE; + input PIPERX10EQDONE; + input PIPERX10EQLPADAPTDONE; + input PIPERX10EQLPLFFSSEL; + input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET; + input PIPERX10PHYSTATUS; + input [1:0] PIPERX10STARTBLOCK; + input [2:0] PIPERX10STATUS; + input [1:0] PIPERX10SYNCHEADER; + input PIPERX10VALID; + input [1:0] PIPERX11CHARISK; + input [31:0] PIPERX11DATA; + input PIPERX11DATAVALID; + input PIPERX11ELECIDLE; + input PIPERX11EQDONE; + input PIPERX11EQLPADAPTDONE; + input PIPERX11EQLPLFFSSEL; + input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET; + input PIPERX11PHYSTATUS; + input [1:0] PIPERX11STARTBLOCK; + input [2:0] PIPERX11STATUS; + input [1:0] PIPERX11SYNCHEADER; + input PIPERX11VALID; + input [1:0] PIPERX12CHARISK; + input [31:0] PIPERX12DATA; + input PIPERX12DATAVALID; + input PIPERX12ELECIDLE; + input PIPERX12EQDONE; + input PIPERX12EQLPADAPTDONE; + input PIPERX12EQLPLFFSSEL; + input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET; + input PIPERX12PHYSTATUS; + input [1:0] PIPERX12STARTBLOCK; + input [2:0] PIPERX12STATUS; + input [1:0] PIPERX12SYNCHEADER; + input PIPERX12VALID; + input [1:0] PIPERX13CHARISK; + input [31:0] PIPERX13DATA; + input PIPERX13DATAVALID; + input PIPERX13ELECIDLE; + input PIPERX13EQDONE; + input PIPERX13EQLPADAPTDONE; + input PIPERX13EQLPLFFSSEL; + input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET; + input PIPERX13PHYSTATUS; + input [1:0] PIPERX13STARTBLOCK; + input [2:0] PIPERX13STATUS; + input [1:0] PIPERX13SYNCHEADER; + input PIPERX13VALID; + input [1:0] PIPERX14CHARISK; + input [31:0] PIPERX14DATA; + input PIPERX14DATAVALID; + input PIPERX14ELECIDLE; + input PIPERX14EQDONE; + input PIPERX14EQLPADAPTDONE; + input PIPERX14EQLPLFFSSEL; + input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET; + input PIPERX14PHYSTATUS; + input [1:0] PIPERX14STARTBLOCK; + input [2:0] PIPERX14STATUS; + input [1:0] PIPERX14SYNCHEADER; + input PIPERX14VALID; + input [1:0] PIPERX15CHARISK; + input [31:0] PIPERX15DATA; + input PIPERX15DATAVALID; + input PIPERX15ELECIDLE; + input PIPERX15EQDONE; + input PIPERX15EQLPADAPTDONE; + input PIPERX15EQLPLFFSSEL; + input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET; + input PIPERX15PHYSTATUS; + input [1:0] PIPERX15STARTBLOCK; + input [2:0] PIPERX15STATUS; + input [1:0] PIPERX15SYNCHEADER; + input PIPERX15VALID; + input [17:0] PIPETX00EQCOEFF; + input PIPETX00EQDONE; + input [17:0] PIPETX01EQCOEFF; + input PIPETX01EQDONE; + input [17:0] PIPETX02EQCOEFF; + input PIPETX02EQDONE; + input [17:0] PIPETX03EQCOEFF; + input PIPETX03EQDONE; + input [17:0] PIPETX04EQCOEFF; + input PIPETX04EQDONE; + input [17:0] PIPETX05EQCOEFF; + input PIPETX05EQDONE; + input [17:0] PIPETX06EQCOEFF; + input PIPETX06EQDONE; + input [17:0] PIPETX07EQCOEFF; + input PIPETX07EQDONE; + input [17:0] PIPETX08EQCOEFF; + input PIPETX08EQDONE; + input [17:0] PIPETX09EQCOEFF; + input PIPETX09EQDONE; + input [17:0] PIPETX10EQCOEFF; + input PIPETX10EQDONE; + input [17:0] PIPETX11EQCOEFF; + input PIPETX11EQDONE; + input [17:0] PIPETX12EQCOEFF; + input PIPETX12EQDONE; + input [17:0] PIPETX13EQCOEFF; + input PIPETX13EQDONE; + input [17:0] PIPETX14EQCOEFF; + input PIPETX14EQDONE; + input [17:0] PIPETX15EQCOEFF; + input PIPETX15EQDONE; + input PLEQRESETEIEOSCOUNT; + input PLGEN2UPSTREAMPREFERDEEMPH; + input PLGEN34REDOEQSPEED; + input PLGEN34REDOEQUALIZATION; + input RESETN; + input [255:0] SAXISCCTDATA; + input [7:0] SAXISCCTKEEP; + input SAXISCCTLAST; + input [32:0] SAXISCCTUSER; + input SAXISCCTVALID; + input [255:0] SAXISRQTDATA; + input [7:0] SAXISRQTKEEP; + input SAXISRQTLAST; + input [61:0] SAXISRQTUSER; + input SAXISRQTVALID; + input USERCLK; + input USERCLK2; + input USERCLKEN; + input [31:0] USERSPAREIN; +endmodule + +module EMAC (...); + parameter EMAC0_MODE = "RGMII"; + parameter EMAC1_MODE = "RGMII"; + output DCRHOSTDONEIR; + output EMAC0CLIENTANINTERRUPT; + output EMAC0CLIENTRXBADFRAME; + output EMAC0CLIENTRXCLIENTCLKOUT; + output EMAC0CLIENTRXDVLD; + output EMAC0CLIENTRXDVLDMSW; + output EMAC0CLIENTRXDVREG6; + output EMAC0CLIENTRXFRAMEDROP; + output EMAC0CLIENTRXGOODFRAME; + output EMAC0CLIENTRXSTATSBYTEVLD; + output EMAC0CLIENTRXSTATSVLD; + output EMAC0CLIENTTXACK; + output EMAC0CLIENTTXCLIENTCLKOUT; + output EMAC0CLIENTTXCOLLISION; + output EMAC0CLIENTTXGMIIMIICLKOUT; + output EMAC0CLIENTTXRETRANSMIT; + output EMAC0CLIENTTXSTATS; + output EMAC0CLIENTTXSTATSBYTEVLD; + output EMAC0CLIENTTXSTATSVLD; + output EMAC0PHYENCOMMAALIGN; + output EMAC0PHYLOOPBACKMSB; + output EMAC0PHYMCLKOUT; + output EMAC0PHYMDOUT; + output EMAC0PHYMDTRI; + output EMAC0PHYMGTRXRESET; + output EMAC0PHYMGTTXRESET; + output EMAC0PHYPOWERDOWN; + output EMAC0PHYSYNCACQSTATUS; + output EMAC0PHYTXCHARDISPMODE; + output EMAC0PHYTXCHARDISPVAL; + output EMAC0PHYTXCHARISK; + output EMAC0PHYTXCLK; + output EMAC0PHYTXEN; + output EMAC0PHYTXER; + output EMAC1CLIENTANINTERRUPT; + output EMAC1CLIENTRXBADFRAME; + output EMAC1CLIENTRXCLIENTCLKOUT; + output EMAC1CLIENTRXDVLD; + output EMAC1CLIENTRXDVLDMSW; + output EMAC1CLIENTRXDVREG6; + output EMAC1CLIENTRXFRAMEDROP; + output EMAC1CLIENTRXGOODFRAME; + output EMAC1CLIENTRXSTATSBYTEVLD; + output EMAC1CLIENTRXSTATSVLD; + output EMAC1CLIENTTXACK; + output EMAC1CLIENTTXCLIENTCLKOUT; + output EMAC1CLIENTTXCOLLISION; + output EMAC1CLIENTTXGMIIMIICLKOUT; + output EMAC1CLIENTTXRETRANSMIT; + output EMAC1CLIENTTXSTATS; + output EMAC1CLIENTTXSTATSBYTEVLD; + output EMAC1CLIENTTXSTATSVLD; + output EMAC1PHYENCOMMAALIGN; + output EMAC1PHYLOOPBACKMSB; + output EMAC1PHYMCLKOUT; + output EMAC1PHYMDOUT; + output EMAC1PHYMDTRI; + output EMAC1PHYMGTRXRESET; + output EMAC1PHYMGTTXRESET; + output EMAC1PHYPOWERDOWN; + output EMAC1PHYSYNCACQSTATUS; + output EMAC1PHYTXCHARDISPMODE; + output EMAC1PHYTXCHARDISPVAL; + output EMAC1PHYTXCHARISK; + output EMAC1PHYTXCLK; + output EMAC1PHYTXEN; + output EMAC1PHYTXER; + output EMACDCRACK; + output HOSTMIIMRDY; + output [0:31] EMACDCRDBUS; + output [15:0] EMAC0CLIENTRXD; + output [15:0] EMAC1CLIENTRXD; + output [31:0] HOSTRDDATA; + output [6:0] EMAC0CLIENTRXSTATS; + output [6:0] EMAC1CLIENTRXSTATS; + output [7:0] EMAC0PHYTXD; + output [7:0] EMAC1PHYTXD; + input CLIENTEMAC0DCMLOCKED; + input CLIENTEMAC0PAUSEREQ; + input CLIENTEMAC0RXCLIENTCLKIN; + input CLIENTEMAC0TXCLIENTCLKIN; + input CLIENTEMAC0TXDVLD; + input CLIENTEMAC0TXDVLDMSW; + input CLIENTEMAC0TXFIRSTBYTE; + input CLIENTEMAC0TXGMIIMIICLKIN; + input CLIENTEMAC0TXUNDERRUN; + input CLIENTEMAC1DCMLOCKED; + input CLIENTEMAC1PAUSEREQ; + input CLIENTEMAC1RXCLIENTCLKIN; + input CLIENTEMAC1TXCLIENTCLKIN; + input CLIENTEMAC1TXDVLD; + input CLIENTEMAC1TXDVLDMSW; + input CLIENTEMAC1TXFIRSTBYTE; + input CLIENTEMAC1TXGMIIMIICLKIN; + input CLIENTEMAC1TXUNDERRUN; + input DCREMACCLK; + input DCREMACENABLE; + input DCREMACREAD; + input DCREMACWRITE; + input HOSTCLK; + input HOSTEMAC1SEL; + input HOSTMIIMSEL; + input HOSTREQ; + input PHYEMAC0COL; + input PHYEMAC0CRS; + input PHYEMAC0GTXCLK; + input PHYEMAC0MCLKIN; + input PHYEMAC0MDIN; + input PHYEMAC0MIITXCLK; + input PHYEMAC0RXBUFERR; + input PHYEMAC0RXCHARISCOMMA; + input PHYEMAC0RXCHARISK; + input PHYEMAC0RXCHECKINGCRC; + input PHYEMAC0RXCLK; + input PHYEMAC0RXCOMMADET; + input PHYEMAC0RXDISPERR; + input PHYEMAC0RXDV; + input PHYEMAC0RXER; + input PHYEMAC0RXNOTINTABLE; + input PHYEMAC0RXRUNDISP; + input PHYEMAC0SIGNALDET; + input PHYEMAC0TXBUFERR; + input PHYEMAC1COL; + input PHYEMAC1CRS; + input PHYEMAC1GTXCLK; + input PHYEMAC1MCLKIN; + input PHYEMAC1MDIN; + input PHYEMAC1MIITXCLK; + input PHYEMAC1RXBUFERR; + input PHYEMAC1RXCHARISCOMMA; + input PHYEMAC1RXCHARISK; + input PHYEMAC1RXCHECKINGCRC; + input PHYEMAC1RXCLK; + input PHYEMAC1RXCOMMADET; + input PHYEMAC1RXDISPERR; + input PHYEMAC1RXDV; + input PHYEMAC1RXER; + input PHYEMAC1RXNOTINTABLE; + input PHYEMAC1RXRUNDISP; + input PHYEMAC1SIGNALDET; + input PHYEMAC1TXBUFERR; + input RESET; + input [0:31] DCREMACDBUS; + input [15:0] CLIENTEMAC0PAUSEVAL; + input [15:0] CLIENTEMAC0TXD; + input [15:0] CLIENTEMAC1PAUSEVAL; + input [15:0] CLIENTEMAC1TXD; + input [1:0] HOSTOPCODE; + input [1:0] PHYEMAC0RXBUFSTATUS; + input [1:0] PHYEMAC0RXLOSSOFSYNC; + input [1:0] PHYEMAC1RXBUFSTATUS; + input [1:0] PHYEMAC1RXLOSSOFSYNC; + input [2:0] PHYEMAC0RXCLKCORCNT; + input [2:0] PHYEMAC1RXCLKCORCNT; + input [31:0] HOSTWRDATA; + input [47:0] TIEEMAC0UNICASTADDR; + input [47:0] TIEEMAC1UNICASTADDR; + input [4:0] PHYEMAC0PHYAD; + input [4:0] PHYEMAC1PHYAD; + input [79:0] TIEEMAC0CONFIGVEC; + input [79:0] TIEEMAC1CONFIGVEC; + input [7:0] CLIENTEMAC0TXIFGDELAY; + input [7:0] CLIENTEMAC1TXIFGDELAY; + input [7:0] PHYEMAC0RXD; + input [7:0] PHYEMAC1RXD; + input [8:9] DCREMACABUS; + input [9:0] HOSTADDR; +endmodule + +module TEMAC (...); + parameter EMAC0_1000BASEX_ENABLE = "FALSE"; + parameter EMAC0_ADDRFILTER_ENABLE = "FALSE"; + parameter EMAC0_BYTEPHY = "FALSE"; + parameter EMAC0_CONFIGVEC_79 = "FALSE"; + parameter EMAC0_GTLOOPBACK = "FALSE"; + parameter EMAC0_HOST_ENABLE = "FALSE"; + parameter EMAC0_LTCHECK_DISABLE = "FALSE"; + parameter EMAC0_MDIO_ENABLE = "FALSE"; + parameter EMAC0_PHYINITAUTONEG_ENABLE = "FALSE"; + parameter EMAC0_PHYISOLATE = "FALSE"; + parameter EMAC0_PHYLOOPBACKMSB = "FALSE"; + parameter EMAC0_PHYPOWERDOWN = "FALSE"; + parameter EMAC0_PHYRESET = "FALSE"; + parameter EMAC0_RGMII_ENABLE = "FALSE"; + parameter EMAC0_RX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC0_RXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC0_RXHALFDUPLEX = "FALSE"; + parameter EMAC0_RXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC0_RXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC0_RXRESET = "FALSE"; + parameter EMAC0_RXVLAN_ENABLE = "FALSE"; + parameter EMAC0_RX_ENABLE = "FALSE"; + parameter EMAC0_SGMII_ENABLE = "FALSE"; + parameter EMAC0_SPEED_LSB = "FALSE"; + parameter EMAC0_SPEED_MSB = "FALSE"; + parameter EMAC0_TX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC0_TXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC0_TXHALFDUPLEX = "FALSE"; + parameter EMAC0_TXIFGADJUST_ENABLE = "FALSE"; + parameter EMAC0_TXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC0_TXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC0_TXRESET = "FALSE"; + parameter EMAC0_TXVLAN_ENABLE = "FALSE"; + parameter EMAC0_TX_ENABLE = "FALSE"; + parameter EMAC0_UNIDIRECTION_ENABLE = "FALSE"; + parameter EMAC0_USECLKEN = "FALSE"; + parameter EMAC1_1000BASEX_ENABLE = "FALSE"; + parameter EMAC1_ADDRFILTER_ENABLE = "FALSE"; + parameter EMAC1_BYTEPHY = "FALSE"; + parameter EMAC1_CONFIGVEC_79 = "FALSE"; + parameter EMAC1_GTLOOPBACK = "FALSE"; + parameter EMAC1_HOST_ENABLE = "FALSE"; + parameter EMAC1_LTCHECK_DISABLE = "FALSE"; + parameter EMAC1_MDIO_ENABLE = "FALSE"; + parameter EMAC1_PHYINITAUTONEG_ENABLE = "FALSE"; + parameter EMAC1_PHYISOLATE = "FALSE"; + parameter EMAC1_PHYLOOPBACKMSB = "FALSE"; + parameter EMAC1_PHYPOWERDOWN = "FALSE"; + parameter EMAC1_PHYRESET = "FALSE"; + parameter EMAC1_RGMII_ENABLE = "FALSE"; + parameter EMAC1_RX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC1_RXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC1_RXHALFDUPLEX = "FALSE"; + parameter EMAC1_RXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC1_RXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC1_RXRESET = "FALSE"; + parameter EMAC1_RXVLAN_ENABLE = "FALSE"; + parameter EMAC1_RX_ENABLE = "FALSE"; + parameter EMAC1_SGMII_ENABLE = "FALSE"; + parameter EMAC1_SPEED_LSB = "FALSE"; + parameter EMAC1_SPEED_MSB = "FALSE"; + parameter EMAC1_TX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC1_TXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC1_TXHALFDUPLEX = "FALSE"; + parameter EMAC1_TXIFGADJUST_ENABLE = "FALSE"; + parameter EMAC1_TXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC1_TXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC1_TXRESET = "FALSE"; + parameter EMAC1_TXVLAN_ENABLE = "FALSE"; + parameter EMAC1_TX_ENABLE = "FALSE"; + parameter EMAC1_UNIDIRECTION_ENABLE = "FALSE"; + parameter EMAC1_USECLKEN = "FALSE"; + parameter [0:7] EMAC0_DCRBASEADDR = 8'h00; + parameter [0:7] EMAC1_DCRBASEADDR = 8'h00; + parameter [47:0] EMAC0_PAUSEADDR = 48'h000000000000; + parameter [47:0] EMAC0_UNICASTADDR = 48'h000000000000; + parameter [47:0] EMAC1_PAUSEADDR = 48'h000000000000; + parameter [47:0] EMAC1_UNICASTADDR = 48'h000000000000; + parameter [8:0] EMAC0_LINKTIMERVAL = 9'h000; + parameter [8:0] EMAC1_LINKTIMERVAL = 9'h000; + output DCRHOSTDONEIR; + output EMAC0CLIENTANINTERRUPT; + output EMAC0CLIENTRXBADFRAME; + output EMAC0CLIENTRXCLIENTCLKOUT; + output EMAC0CLIENTRXDVLD; + output EMAC0CLIENTRXDVLDMSW; + output EMAC0CLIENTRXFRAMEDROP; + output EMAC0CLIENTRXGOODFRAME; + output EMAC0CLIENTRXSTATSBYTEVLD; + output EMAC0CLIENTRXSTATSVLD; + output EMAC0CLIENTTXACK; + output EMAC0CLIENTTXCLIENTCLKOUT; + output EMAC0CLIENTTXCOLLISION; + output EMAC0CLIENTTXRETRANSMIT; + output EMAC0CLIENTTXSTATS; + output EMAC0CLIENTTXSTATSBYTEVLD; + output EMAC0CLIENTTXSTATSVLD; + output EMAC0PHYENCOMMAALIGN; + output EMAC0PHYLOOPBACKMSB; + output EMAC0PHYMCLKOUT; + output EMAC0PHYMDOUT; + output EMAC0PHYMDTRI; + output EMAC0PHYMGTRXRESET; + output EMAC0PHYMGTTXRESET; + output EMAC0PHYPOWERDOWN; + output EMAC0PHYSYNCACQSTATUS; + output EMAC0PHYTXCHARDISPMODE; + output EMAC0PHYTXCHARDISPVAL; + output EMAC0PHYTXCHARISK; + output EMAC0PHYTXCLK; + output EMAC0PHYTXEN; + output EMAC0PHYTXER; + output EMAC0PHYTXGMIIMIICLKOUT; + output EMAC0SPEEDIS10100; + output EMAC1CLIENTANINTERRUPT; + output EMAC1CLIENTRXBADFRAME; + output EMAC1CLIENTRXCLIENTCLKOUT; + output EMAC1CLIENTRXDVLD; + output EMAC1CLIENTRXDVLDMSW; + output EMAC1CLIENTRXFRAMEDROP; + output EMAC1CLIENTRXGOODFRAME; + output EMAC1CLIENTRXSTATSBYTEVLD; + output EMAC1CLIENTRXSTATSVLD; + output EMAC1CLIENTTXACK; + output EMAC1CLIENTTXCLIENTCLKOUT; + output EMAC1CLIENTTXCOLLISION; + output EMAC1CLIENTTXRETRANSMIT; + output EMAC1CLIENTTXSTATS; + output EMAC1CLIENTTXSTATSBYTEVLD; + output EMAC1CLIENTTXSTATSVLD; + output EMAC1PHYENCOMMAALIGN; + output EMAC1PHYLOOPBACKMSB; + output EMAC1PHYMCLKOUT; + output EMAC1PHYMDOUT; + output EMAC1PHYMDTRI; + output EMAC1PHYMGTRXRESET; + output EMAC1PHYMGTTXRESET; + output EMAC1PHYPOWERDOWN; + output EMAC1PHYSYNCACQSTATUS; + output EMAC1PHYTXCHARDISPMODE; + output EMAC1PHYTXCHARDISPVAL; + output EMAC1PHYTXCHARISK; + output EMAC1PHYTXCLK; + output EMAC1PHYTXEN; + output EMAC1PHYTXER; + output EMAC1PHYTXGMIIMIICLKOUT; + output EMAC1SPEEDIS10100; + output EMACDCRACK; + output HOSTMIIMRDY; + output [0:31] EMACDCRDBUS; + output [15:0] EMAC0CLIENTRXD; + output [15:0] EMAC1CLIENTRXD; + output [31:0] HOSTRDDATA; + output [6:0] EMAC0CLIENTRXSTATS; + output [6:0] EMAC1CLIENTRXSTATS; + output [7:0] EMAC0PHYTXD; + output [7:0] EMAC1PHYTXD; + input CLIENTEMAC0DCMLOCKED; + input CLIENTEMAC0PAUSEREQ; + input CLIENTEMAC0RXCLIENTCLKIN; + input CLIENTEMAC0TXCLIENTCLKIN; + input CLIENTEMAC0TXDVLD; + input CLIENTEMAC0TXDVLDMSW; + input CLIENTEMAC0TXFIRSTBYTE; + input CLIENTEMAC0TXUNDERRUN; + input CLIENTEMAC1DCMLOCKED; + input CLIENTEMAC1PAUSEREQ; + input CLIENTEMAC1RXCLIENTCLKIN; + input CLIENTEMAC1TXCLIENTCLKIN; + input CLIENTEMAC1TXDVLD; + input CLIENTEMAC1TXDVLDMSW; + input CLIENTEMAC1TXFIRSTBYTE; + input CLIENTEMAC1TXUNDERRUN; + input DCREMACCLK; + input DCREMACENABLE; + input DCREMACREAD; + input DCREMACWRITE; + input HOSTCLK; + input HOSTEMAC1SEL; + input HOSTMIIMSEL; + input HOSTREQ; + input PHYEMAC0COL; + input PHYEMAC0CRS; + input PHYEMAC0GTXCLK; + input PHYEMAC0MCLKIN; + input PHYEMAC0MDIN; + input PHYEMAC0MIITXCLK; + input PHYEMAC0RXBUFERR; + input PHYEMAC0RXCHARISCOMMA; + input PHYEMAC0RXCHARISK; + input PHYEMAC0RXCHECKINGCRC; + input PHYEMAC0RXCLK; + input PHYEMAC0RXCOMMADET; + input PHYEMAC0RXDISPERR; + input PHYEMAC0RXDV; + input PHYEMAC0RXER; + input PHYEMAC0RXNOTINTABLE; + input PHYEMAC0RXRUNDISP; + input PHYEMAC0SIGNALDET; + input PHYEMAC0TXBUFERR; + input PHYEMAC0TXGMIIMIICLKIN; + input PHYEMAC1COL; + input PHYEMAC1CRS; + input PHYEMAC1GTXCLK; + input PHYEMAC1MCLKIN; + input PHYEMAC1MDIN; + input PHYEMAC1MIITXCLK; + input PHYEMAC1RXBUFERR; + input PHYEMAC1RXCHARISCOMMA; + input PHYEMAC1RXCHARISK; + input PHYEMAC1RXCHECKINGCRC; + input PHYEMAC1RXCLK; + input PHYEMAC1RXCOMMADET; + input PHYEMAC1RXDISPERR; + input PHYEMAC1RXDV; + input PHYEMAC1RXER; + input PHYEMAC1RXNOTINTABLE; + input PHYEMAC1RXRUNDISP; + input PHYEMAC1SIGNALDET; + input PHYEMAC1TXBUFERR; + input PHYEMAC1TXGMIIMIICLKIN; + input RESET; + input [0:31] DCREMACDBUS; + input [0:9] DCREMACABUS; + input [15:0] CLIENTEMAC0PAUSEVAL; + input [15:0] CLIENTEMAC0TXD; + input [15:0] CLIENTEMAC1PAUSEVAL; + input [15:0] CLIENTEMAC1TXD; + input [1:0] HOSTOPCODE; + input [1:0] PHYEMAC0RXBUFSTATUS; + input [1:0] PHYEMAC0RXLOSSOFSYNC; + input [1:0] PHYEMAC1RXBUFSTATUS; + input [1:0] PHYEMAC1RXLOSSOFSYNC; + input [2:0] PHYEMAC0RXCLKCORCNT; + input [2:0] PHYEMAC1RXCLKCORCNT; + input [31:0] HOSTWRDATA; + input [4:0] PHYEMAC0PHYAD; + input [4:0] PHYEMAC1PHYAD; + input [7:0] CLIENTEMAC0TXIFGDELAY; + input [7:0] CLIENTEMAC1TXIFGDELAY; + input [7:0] PHYEMAC0RXD; + input [7:0] PHYEMAC1RXD; + input [9:0] HOSTADDR; +endmodule + +module TEMAC_SINGLE (...); + parameter EMAC_1000BASEX_ENABLE = "FALSE"; + parameter EMAC_ADDRFILTER_ENABLE = "FALSE"; + parameter EMAC_BYTEPHY = "FALSE"; + parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE"; + parameter [0:7] EMAC_DCRBASEADDR = 8'h00; + parameter EMAC_GTLOOPBACK = "FALSE"; + parameter EMAC_HOST_ENABLE = "FALSE"; + parameter [8:0] EMAC_LINKTIMERVAL = 9'h000; + parameter EMAC_LTCHECK_DISABLE = "FALSE"; + parameter EMAC_MDIO_ENABLE = "FALSE"; + parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE"; + parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000; + parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE"; + parameter EMAC_PHYISOLATE = "FALSE"; + parameter EMAC_PHYLOOPBACKMSB = "FALSE"; + parameter EMAC_PHYPOWERDOWN = "FALSE"; + parameter EMAC_PHYRESET = "FALSE"; + parameter EMAC_RGMII_ENABLE = "FALSE"; + parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC_RXHALFDUPLEX = "FALSE"; + parameter EMAC_RXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC_RXRESET = "FALSE"; + parameter EMAC_RXVLAN_ENABLE = "FALSE"; + parameter EMAC_RX_ENABLE = "TRUE"; + parameter EMAC_SGMII_ENABLE = "FALSE"; + parameter EMAC_SPEED_LSB = "FALSE"; + parameter EMAC_SPEED_MSB = "FALSE"; + parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE"; + parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE"; + parameter EMAC_TXHALFDUPLEX = "FALSE"; + parameter EMAC_TXIFGADJUST_ENABLE = "FALSE"; + parameter EMAC_TXINBANDFCS_ENABLE = "FALSE"; + parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE"; + parameter EMAC_TXRESET = "FALSE"; + parameter EMAC_TXVLAN_ENABLE = "FALSE"; + parameter EMAC_TX_ENABLE = "TRUE"; + parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000; + parameter EMAC_UNIDIRECTION_ENABLE = "FALSE"; + parameter EMAC_USECLKEN = "FALSE"; + parameter SIM_VERSION = "1.0"; + output DCRHOSTDONEIR; + output EMACCLIENTANINTERRUPT; + output EMACCLIENTRXBADFRAME; + output EMACCLIENTRXCLIENTCLKOUT; + output EMACCLIENTRXDVLD; + output EMACCLIENTRXDVLDMSW; + output EMACCLIENTRXFRAMEDROP; + output EMACCLIENTRXGOODFRAME; + output EMACCLIENTRXSTATSBYTEVLD; + output EMACCLIENTRXSTATSVLD; + output EMACCLIENTTXACK; + output EMACCLIENTTXCLIENTCLKOUT; + output EMACCLIENTTXCOLLISION; + output EMACCLIENTTXRETRANSMIT; + output EMACCLIENTTXSTATS; + output EMACCLIENTTXSTATSBYTEVLD; + output EMACCLIENTTXSTATSVLD; + output EMACDCRACK; + output EMACPHYENCOMMAALIGN; + output EMACPHYLOOPBACKMSB; + output EMACPHYMCLKOUT; + output EMACPHYMDOUT; + output EMACPHYMDTRI; + output EMACPHYMGTRXRESET; + output EMACPHYMGTTXRESET; + output EMACPHYPOWERDOWN; + output EMACPHYSYNCACQSTATUS; + output EMACPHYTXCHARDISPMODE; + output EMACPHYTXCHARDISPVAL; + output EMACPHYTXCHARISK; + output EMACPHYTXCLK; + output EMACPHYTXEN; + output EMACPHYTXER; + output EMACPHYTXGMIIMIICLKOUT; + output EMACSPEEDIS10100; + output HOSTMIIMRDY; + output [0:31] EMACDCRDBUS; + output [15:0] EMACCLIENTRXD; + output [31:0] HOSTRDDATA; + output [6:0] EMACCLIENTRXSTATS; + output [7:0] EMACPHYTXD; + input CLIENTEMACDCMLOCKED; + input CLIENTEMACPAUSEREQ; + input CLIENTEMACRXCLIENTCLKIN; + input CLIENTEMACTXCLIENTCLKIN; + input CLIENTEMACTXDVLD; + input CLIENTEMACTXDVLDMSW; + input CLIENTEMACTXFIRSTBYTE; + input CLIENTEMACTXUNDERRUN; + input DCREMACCLK; + input DCREMACENABLE; + input DCREMACREAD; + input DCREMACWRITE; + input HOSTCLK; + input HOSTMIIMSEL; + input HOSTREQ; + input PHYEMACCOL; + input PHYEMACCRS; + input PHYEMACGTXCLK; + input PHYEMACMCLKIN; + input PHYEMACMDIN; + input PHYEMACMIITXCLK; + input PHYEMACRXCHARISCOMMA; + input PHYEMACRXCHARISK; + input PHYEMACRXCLK; + input PHYEMACRXDISPERR; + input PHYEMACRXDV; + input PHYEMACRXER; + input PHYEMACRXNOTINTABLE; + input PHYEMACRXRUNDISP; + input PHYEMACSIGNALDET; + input PHYEMACTXBUFERR; + input PHYEMACTXGMIIMIICLKIN; + input RESET; + input [0:31] DCREMACDBUS; + input [0:9] DCREMACABUS; + input [15:0] CLIENTEMACPAUSEVAL; + input [15:0] CLIENTEMACTXD; + input [1:0] HOSTOPCODE; + input [1:0] PHYEMACRXBUFSTATUS; + input [2:0] PHYEMACRXCLKCORCNT; + input [31:0] HOSTWRDATA; + input [4:0] PHYEMACPHYAD; + input [7:0] CLIENTEMACTXIFGDELAY; + input [7:0] PHYEMACRXD; + input [9:0] HOSTADDR; +endmodule + +module CMAC (...); + parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; + parameter CTL_RX_CHECK_ACK = "TRUE"; + parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; + parameter CTL_RX_CHECK_SFD = "FALSE"; + parameter CTL_RX_DELETE_FCS = "TRUE"; + parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808; + parameter CTL_RX_FORWARD_CONTROL = "FALSE"; + parameter CTL_RX_IGNORE_FCS = "FALSE"; + parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580; + parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40; + parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001; + parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF; + parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF; + parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000; + parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000; + parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001; + parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001; + parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000; + parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000; + parameter CTL_RX_PROCESS_LFI = "FALSE"; + parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF; + parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00; + parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100; + parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600; + parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00; + parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; + parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; + parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500; + parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; + parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; + parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800; + parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500; + parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; + parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700; + parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; + parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600; + parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; + parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; + parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900; + parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900; + parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400; + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; + parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001; + parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001; + parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808; + parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808; + parameter CTL_TX_FCS_INS_ENABLE = "TRUE"; + parameter CTL_TX_IGNORE_FCS = "FALSE"; + parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001; + parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001; + parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE"; + parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1; + parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000; + parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000; + parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF; + parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00; + parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100; + parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600; + parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00; + parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; + parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; + parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500; + parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; + parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; + parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800; + parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500; + parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; + parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700; + parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; + parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600; + parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; + parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; + parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900; + parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900; + parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400; + parameter SIM_VERSION = "2.0"; + parameter TEST_MODE_PIN_CHAR = "FALSE"; + output [15:0] DRP_DO; + output DRP_RDY; + output [127:0] RX_DATAOUT0; + output [127:0] RX_DATAOUT1; + output [127:0] RX_DATAOUT2; + output [127:0] RX_DATAOUT3; + output RX_ENAOUT0; + output RX_ENAOUT1; + output RX_ENAOUT2; + output RX_ENAOUT3; + output RX_EOPOUT0; + output RX_EOPOUT1; + output RX_EOPOUT2; + output RX_EOPOUT3; + output RX_ERROUT0; + output RX_ERROUT1; + output RX_ERROUT2; + output RX_ERROUT3; + output [6:0] RX_LANE_ALIGNER_FILL_0; + output [6:0] RX_LANE_ALIGNER_FILL_1; + output [6:0] RX_LANE_ALIGNER_FILL_10; + output [6:0] RX_LANE_ALIGNER_FILL_11; + output [6:0] RX_LANE_ALIGNER_FILL_12; + output [6:0] RX_LANE_ALIGNER_FILL_13; + output [6:0] RX_LANE_ALIGNER_FILL_14; + output [6:0] RX_LANE_ALIGNER_FILL_15; + output [6:0] RX_LANE_ALIGNER_FILL_16; + output [6:0] RX_LANE_ALIGNER_FILL_17; + output [6:0] RX_LANE_ALIGNER_FILL_18; + output [6:0] RX_LANE_ALIGNER_FILL_19; + output [6:0] RX_LANE_ALIGNER_FILL_2; + output [6:0] RX_LANE_ALIGNER_FILL_3; + output [6:0] RX_LANE_ALIGNER_FILL_4; + output [6:0] RX_LANE_ALIGNER_FILL_5; + output [6:0] RX_LANE_ALIGNER_FILL_6; + output [6:0] RX_LANE_ALIGNER_FILL_7; + output [6:0] RX_LANE_ALIGNER_FILL_8; + output [6:0] RX_LANE_ALIGNER_FILL_9; + output [3:0] RX_MTYOUT0; + output [3:0] RX_MTYOUT1; + output [3:0] RX_MTYOUT2; + output [3:0] RX_MTYOUT3; + output [4:0] RX_PTP_PCSLANE_OUT; + output [79:0] RX_PTP_TSTAMP_OUT; + output RX_SOPOUT0; + output RX_SOPOUT1; + output RX_SOPOUT2; + output RX_SOPOUT3; + output STAT_RX_ALIGNED; + output STAT_RX_ALIGNED_ERR; + output [6:0] STAT_RX_BAD_CODE; + output [3:0] STAT_RX_BAD_FCS; + output STAT_RX_BAD_PREAMBLE; + output STAT_RX_BAD_SFD; + output STAT_RX_BIP_ERR_0; + output STAT_RX_BIP_ERR_1; + output STAT_RX_BIP_ERR_10; + output STAT_RX_BIP_ERR_11; + output STAT_RX_BIP_ERR_12; + output STAT_RX_BIP_ERR_13; + output STAT_RX_BIP_ERR_14; + output STAT_RX_BIP_ERR_15; + output STAT_RX_BIP_ERR_16; + output STAT_RX_BIP_ERR_17; + output STAT_RX_BIP_ERR_18; + output STAT_RX_BIP_ERR_19; + output STAT_RX_BIP_ERR_2; + output STAT_RX_BIP_ERR_3; + output STAT_RX_BIP_ERR_4; + output STAT_RX_BIP_ERR_5; + output STAT_RX_BIP_ERR_6; + output STAT_RX_BIP_ERR_7; + output STAT_RX_BIP_ERR_8; + output STAT_RX_BIP_ERR_9; + output [19:0] STAT_RX_BLOCK_LOCK; + output STAT_RX_BROADCAST; + output [3:0] STAT_RX_FRAGMENT; + output [3:0] STAT_RX_FRAMING_ERR_0; + output [3:0] STAT_RX_FRAMING_ERR_1; + output [3:0] STAT_RX_FRAMING_ERR_10; + output [3:0] STAT_RX_FRAMING_ERR_11; + output [3:0] STAT_RX_FRAMING_ERR_12; + output [3:0] STAT_RX_FRAMING_ERR_13; + output [3:0] STAT_RX_FRAMING_ERR_14; + output [3:0] STAT_RX_FRAMING_ERR_15; + output [3:0] STAT_RX_FRAMING_ERR_16; + output [3:0] STAT_RX_FRAMING_ERR_17; + output [3:0] STAT_RX_FRAMING_ERR_18; + output [3:0] STAT_RX_FRAMING_ERR_19; + output [3:0] STAT_RX_FRAMING_ERR_2; + output [3:0] STAT_RX_FRAMING_ERR_3; + output [3:0] STAT_RX_FRAMING_ERR_4; + output [3:0] STAT_RX_FRAMING_ERR_5; + output [3:0] STAT_RX_FRAMING_ERR_6; + output [3:0] STAT_RX_FRAMING_ERR_7; + output [3:0] STAT_RX_FRAMING_ERR_8; + output [3:0] STAT_RX_FRAMING_ERR_9; + output STAT_RX_FRAMING_ERR_VALID_0; + output STAT_RX_FRAMING_ERR_VALID_1; + output STAT_RX_FRAMING_ERR_VALID_10; + output STAT_RX_FRAMING_ERR_VALID_11; + output STAT_RX_FRAMING_ERR_VALID_12; + output STAT_RX_FRAMING_ERR_VALID_13; + output STAT_RX_FRAMING_ERR_VALID_14; + output STAT_RX_FRAMING_ERR_VALID_15; + output STAT_RX_FRAMING_ERR_VALID_16; + output STAT_RX_FRAMING_ERR_VALID_17; + output STAT_RX_FRAMING_ERR_VALID_18; + output STAT_RX_FRAMING_ERR_VALID_19; + output STAT_RX_FRAMING_ERR_VALID_2; + output STAT_RX_FRAMING_ERR_VALID_3; + output STAT_RX_FRAMING_ERR_VALID_4; + output STAT_RX_FRAMING_ERR_VALID_5; + output STAT_RX_FRAMING_ERR_VALID_6; + output STAT_RX_FRAMING_ERR_VALID_7; + output STAT_RX_FRAMING_ERR_VALID_8; + output STAT_RX_FRAMING_ERR_VALID_9; + output STAT_RX_GOT_SIGNAL_OS; + output STAT_RX_HI_BER; + output STAT_RX_INRANGEERR; + output STAT_RX_INTERNAL_LOCAL_FAULT; + output STAT_RX_JABBER; + output [7:0] STAT_RX_LANE0_VLM_BIP7; + output STAT_RX_LANE0_VLM_BIP7_VALID; + output STAT_RX_LOCAL_FAULT; + output [19:0] STAT_RX_MF_ERR; + output [19:0] STAT_RX_MF_LEN_ERR; + output [19:0] STAT_RX_MF_REPEAT_ERR; + output STAT_RX_MISALIGNED; + output STAT_RX_MULTICAST; + output STAT_RX_OVERSIZE; + output STAT_RX_PACKET_1024_1518_BYTES; + output STAT_RX_PACKET_128_255_BYTES; + output STAT_RX_PACKET_1519_1522_BYTES; + output STAT_RX_PACKET_1523_1548_BYTES; + output STAT_RX_PACKET_1549_2047_BYTES; + output STAT_RX_PACKET_2048_4095_BYTES; + output STAT_RX_PACKET_256_511_BYTES; + output STAT_RX_PACKET_4096_8191_BYTES; + output STAT_RX_PACKET_512_1023_BYTES; + output STAT_RX_PACKET_64_BYTES; + output STAT_RX_PACKET_65_127_BYTES; + output STAT_RX_PACKET_8192_9215_BYTES; + output STAT_RX_PACKET_BAD_FCS; + output STAT_RX_PACKET_LARGE; + output [3:0] STAT_RX_PACKET_SMALL; + output STAT_RX_PAUSE; + output [15:0] STAT_RX_PAUSE_QUANTA0; + output [15:0] STAT_RX_PAUSE_QUANTA1; + output [15:0] STAT_RX_PAUSE_QUANTA2; + output [15:0] STAT_RX_PAUSE_QUANTA3; + output [15:0] STAT_RX_PAUSE_QUANTA4; + output [15:0] STAT_RX_PAUSE_QUANTA5; + output [15:0] STAT_RX_PAUSE_QUANTA6; + output [15:0] STAT_RX_PAUSE_QUANTA7; + output [15:0] STAT_RX_PAUSE_QUANTA8; + output [8:0] STAT_RX_PAUSE_REQ; + output [8:0] STAT_RX_PAUSE_VALID; + output STAT_RX_RECEIVED_LOCAL_FAULT; + output STAT_RX_REMOTE_FAULT; + output STAT_RX_STATUS; + output [3:0] STAT_RX_STOMPED_FCS; + output [19:0] STAT_RX_SYNCED; + output [19:0] STAT_RX_SYNCED_ERR; + output [2:0] STAT_RX_TEST_PATTERN_MISMATCH; + output STAT_RX_TOOLONG; + output [7:0] STAT_RX_TOTAL_BYTES; + output [13:0] STAT_RX_TOTAL_GOOD_BYTES; + output STAT_RX_TOTAL_GOOD_PACKETS; + output [3:0] STAT_RX_TOTAL_PACKETS; + output STAT_RX_TRUNCATED; + output [3:0] STAT_RX_UNDERSIZE; + output STAT_RX_UNICAST; + output STAT_RX_USER_PAUSE; + output STAT_RX_VLAN; + output [19:0] STAT_RX_VL_DEMUXED; + output [4:0] STAT_RX_VL_NUMBER_0; + output [4:0] STAT_RX_VL_NUMBER_1; + output [4:0] STAT_RX_VL_NUMBER_10; + output [4:0] STAT_RX_VL_NUMBER_11; + output [4:0] STAT_RX_VL_NUMBER_12; + output [4:0] STAT_RX_VL_NUMBER_13; + output [4:0] STAT_RX_VL_NUMBER_14; + output [4:0] STAT_RX_VL_NUMBER_15; + output [4:0] STAT_RX_VL_NUMBER_16; + output [4:0] STAT_RX_VL_NUMBER_17; + output [4:0] STAT_RX_VL_NUMBER_18; + output [4:0] STAT_RX_VL_NUMBER_19; + output [4:0] STAT_RX_VL_NUMBER_2; + output [4:0] STAT_RX_VL_NUMBER_3; + output [4:0] STAT_RX_VL_NUMBER_4; + output [4:0] STAT_RX_VL_NUMBER_5; + output [4:0] STAT_RX_VL_NUMBER_6; + output [4:0] STAT_RX_VL_NUMBER_7; + output [4:0] STAT_RX_VL_NUMBER_8; + output [4:0] STAT_RX_VL_NUMBER_9; + output STAT_TX_BAD_FCS; + output STAT_TX_BROADCAST; + output STAT_TX_FRAME_ERROR; + output STAT_TX_LOCAL_FAULT; + output STAT_TX_MULTICAST; + output STAT_TX_PACKET_1024_1518_BYTES; + output STAT_TX_PACKET_128_255_BYTES; + output STAT_TX_PACKET_1519_1522_BYTES; + output STAT_TX_PACKET_1523_1548_BYTES; + output STAT_TX_PACKET_1549_2047_BYTES; + output STAT_TX_PACKET_2048_4095_BYTES; + output STAT_TX_PACKET_256_511_BYTES; + output STAT_TX_PACKET_4096_8191_BYTES; + output STAT_TX_PACKET_512_1023_BYTES; + output STAT_TX_PACKET_64_BYTES; + output STAT_TX_PACKET_65_127_BYTES; + output STAT_TX_PACKET_8192_9215_BYTES; + output STAT_TX_PACKET_LARGE; + output STAT_TX_PACKET_SMALL; + output STAT_TX_PAUSE; + output [8:0] STAT_TX_PAUSE_VALID; + output STAT_TX_PTP_FIFO_READ_ERROR; + output STAT_TX_PTP_FIFO_WRITE_ERROR; + output [6:0] STAT_TX_TOTAL_BYTES; + output [13:0] STAT_TX_TOTAL_GOOD_BYTES; + output STAT_TX_TOTAL_GOOD_PACKETS; + output STAT_TX_TOTAL_PACKETS; + output STAT_TX_UNICAST; + output STAT_TX_USER_PAUSE; + output STAT_TX_VLAN; + output TX_OVFOUT; + output [4:0] TX_PTP_PCSLANE_OUT; + output [79:0] TX_PTP_TSTAMP_OUT; + output [15:0] TX_PTP_TSTAMP_TAG_OUT; + output TX_PTP_TSTAMP_VALID_OUT; + output TX_RDYOUT; + output [15:0] TX_SERDES_ALT_DATA0; + output [15:0] TX_SERDES_ALT_DATA1; + output [15:0] TX_SERDES_ALT_DATA2; + output [15:0] TX_SERDES_ALT_DATA3; + output [63:0] TX_SERDES_DATA0; + output [63:0] TX_SERDES_DATA1; + output [63:0] TX_SERDES_DATA2; + output [63:0] TX_SERDES_DATA3; + output [31:0] TX_SERDES_DATA4; + output [31:0] TX_SERDES_DATA5; + output [31:0] TX_SERDES_DATA6; + output [31:0] TX_SERDES_DATA7; + output [31:0] TX_SERDES_DATA8; + output [31:0] TX_SERDES_DATA9; + output TX_UNFOUT; + input CTL_CAUI4_MODE; + input CTL_RX_CHECK_ETYPE_GCP; + input CTL_RX_CHECK_ETYPE_GPP; + input CTL_RX_CHECK_ETYPE_PCP; + input CTL_RX_CHECK_ETYPE_PPP; + input CTL_RX_CHECK_MCAST_GCP; + input CTL_RX_CHECK_MCAST_GPP; + input CTL_RX_CHECK_MCAST_PCP; + input CTL_RX_CHECK_MCAST_PPP; + input CTL_RX_CHECK_OPCODE_GCP; + input CTL_RX_CHECK_OPCODE_GPP; + input CTL_RX_CHECK_OPCODE_PCP; + input CTL_RX_CHECK_OPCODE_PPP; + input CTL_RX_CHECK_SA_GCP; + input CTL_RX_CHECK_SA_GPP; + input CTL_RX_CHECK_SA_PCP; + input CTL_RX_CHECK_SA_PPP; + input CTL_RX_CHECK_UCAST_GCP; + input CTL_RX_CHECK_UCAST_GPP; + input CTL_RX_CHECK_UCAST_PCP; + input CTL_RX_CHECK_UCAST_PPP; + input CTL_RX_ENABLE; + input CTL_RX_ENABLE_GCP; + input CTL_RX_ENABLE_GPP; + input CTL_RX_ENABLE_PCP; + input CTL_RX_ENABLE_PPP; + input CTL_RX_FORCE_RESYNC; + input [8:0] CTL_RX_PAUSE_ACK; + input [8:0] CTL_RX_PAUSE_ENABLE; + input [79:0] CTL_RX_SYSTEMTIMERIN; + input CTL_RX_TEST_PATTERN; + input CTL_TX_ENABLE; + input CTL_TX_LANE0_VLM_BIP7_OVERRIDE; + input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; + input [8:0] CTL_TX_PAUSE_ENABLE; + input [15:0] CTL_TX_PAUSE_QUANTA0; + input [15:0] CTL_TX_PAUSE_QUANTA1; + input [15:0] CTL_TX_PAUSE_QUANTA2; + input [15:0] CTL_TX_PAUSE_QUANTA3; + input [15:0] CTL_TX_PAUSE_QUANTA4; + input [15:0] CTL_TX_PAUSE_QUANTA5; + input [15:0] CTL_TX_PAUSE_QUANTA6; + input [15:0] CTL_TX_PAUSE_QUANTA7; + input [15:0] CTL_TX_PAUSE_QUANTA8; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8; + input [8:0] CTL_TX_PAUSE_REQ; + input CTL_TX_PTP_VLANE_ADJUST_MODE; + input CTL_TX_RESEND_PAUSE; + input CTL_TX_SEND_IDLE; + input CTL_TX_SEND_RFI; + input [79:0] CTL_TX_SYSTEMTIMERIN; + input CTL_TX_TEST_PATTERN; + input [9:0] DRP_ADDR; + input DRP_CLK; + input [15:0] DRP_DI; + input DRP_EN; + input DRP_WE; + input RX_CLK; + input RX_RESET; + input [15:0] RX_SERDES_ALT_DATA0; + input [15:0] RX_SERDES_ALT_DATA1; + input [15:0] RX_SERDES_ALT_DATA2; + input [15:0] RX_SERDES_ALT_DATA3; + input [9:0] RX_SERDES_CLK; + input [63:0] RX_SERDES_DATA0; + input [63:0] RX_SERDES_DATA1; + input [63:0] RX_SERDES_DATA2; + input [63:0] RX_SERDES_DATA3; + input [31:0] RX_SERDES_DATA4; + input [31:0] RX_SERDES_DATA5; + input [31:0] RX_SERDES_DATA6; + input [31:0] RX_SERDES_DATA7; + input [31:0] RX_SERDES_DATA8; + input [31:0] RX_SERDES_DATA9; + input [9:0] RX_SERDES_RESET; + input TX_CLK; + input [127:0] TX_DATAIN0; + input [127:0] TX_DATAIN1; + input [127:0] TX_DATAIN2; + input [127:0] TX_DATAIN3; + input TX_ENAIN0; + input TX_ENAIN1; + input TX_ENAIN2; + input TX_ENAIN3; + input TX_EOPIN0; + input TX_EOPIN1; + input TX_EOPIN2; + input TX_EOPIN3; + input TX_ERRIN0; + input TX_ERRIN1; + input TX_ERRIN2; + input TX_ERRIN3; + input [3:0] TX_MTYIN0; + input [3:0] TX_MTYIN1; + input [3:0] TX_MTYIN2; + input [3:0] TX_MTYIN3; + input [1:0] TX_PTP_1588OP_IN; + input [15:0] TX_PTP_CHKSUM_OFFSET_IN; + input [63:0] TX_PTP_RXTSTAMP_IN; + input [15:0] TX_PTP_TAG_FIELD_IN; + input [15:0] TX_PTP_TSTAMP_OFFSET_IN; + input TX_PTP_UPD_CHKSUM_IN; + input TX_RESET; + input TX_SOPIN0; + input TX_SOPIN1; + input TX_SOPIN2; + input TX_SOPIN3; +endmodule + +module CMACE4 (...); + parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; + parameter CTL_RX_CHECK_ACK = "TRUE"; + parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; + parameter CTL_RX_CHECK_SFD = "FALSE"; + parameter CTL_RX_DELETE_FCS = "TRUE"; + parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808; + parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808; + parameter CTL_RX_FORWARD_CONTROL = "FALSE"; + parameter CTL_RX_IGNORE_FCS = "FALSE"; + parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580; + parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40; + parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001; + parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF; + parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF; + parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000; + parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000; + parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001; + parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001; + parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000; + parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000; + parameter CTL_RX_PROCESS_LFI = "FALSE"; + parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046; + parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0; + parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF; + parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00; + parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100; + parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600; + parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00; + parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; + parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; + parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500; + parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; + parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; + parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800; + parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500; + parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; + parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700; + parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; + parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600; + parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; + parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; + parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900; + parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900; + parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400; + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; + parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE"; + parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001; + parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001; + parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808; + parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808; + parameter CTL_TX_FCS_INS_ENABLE = "TRUE"; + parameter CTL_TX_IGNORE_FCS = "FALSE"; + parameter [3:0] CTL_TX_IPG_VALUE = 4'hC; + parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001; + parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001; + parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE"; + parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1; + parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000; + parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000; + parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF; + parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00; + parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100; + parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600; + parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00; + parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; + parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; + parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500; + parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; + parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; + parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800; + parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500; + parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; + parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700; + parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; + parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600; + parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; + parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; + parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900; + parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900; + parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter TEST_MODE_PIN_CHAR = "FALSE"; + output [15:0] DRP_DO; + output DRP_RDY; + output [329:0] RSFEC_BYPASS_RX_DOUT; + output RSFEC_BYPASS_RX_DOUT_CW_START; + output RSFEC_BYPASS_RX_DOUT_VALID; + output [329:0] RSFEC_BYPASS_TX_DOUT; + output RSFEC_BYPASS_TX_DOUT_CW_START; + output RSFEC_BYPASS_TX_DOUT_VALID; + output [127:0] RX_DATAOUT0; + output [127:0] RX_DATAOUT1; + output [127:0] RX_DATAOUT2; + output [127:0] RX_DATAOUT3; + output RX_ENAOUT0; + output RX_ENAOUT1; + output RX_ENAOUT2; + output RX_ENAOUT3; + output RX_EOPOUT0; + output RX_EOPOUT1; + output RX_EOPOUT2; + output RX_EOPOUT3; + output RX_ERROUT0; + output RX_ERROUT1; + output RX_ERROUT2; + output RX_ERROUT3; + output [6:0] RX_LANE_ALIGNER_FILL_0; + output [6:0] RX_LANE_ALIGNER_FILL_1; + output [6:0] RX_LANE_ALIGNER_FILL_10; + output [6:0] RX_LANE_ALIGNER_FILL_11; + output [6:0] RX_LANE_ALIGNER_FILL_12; + output [6:0] RX_LANE_ALIGNER_FILL_13; + output [6:0] RX_LANE_ALIGNER_FILL_14; + output [6:0] RX_LANE_ALIGNER_FILL_15; + output [6:0] RX_LANE_ALIGNER_FILL_16; + output [6:0] RX_LANE_ALIGNER_FILL_17; + output [6:0] RX_LANE_ALIGNER_FILL_18; + output [6:0] RX_LANE_ALIGNER_FILL_19; + output [6:0] RX_LANE_ALIGNER_FILL_2; + output [6:0] RX_LANE_ALIGNER_FILL_3; + output [6:0] RX_LANE_ALIGNER_FILL_4; + output [6:0] RX_LANE_ALIGNER_FILL_5; + output [6:0] RX_LANE_ALIGNER_FILL_6; + output [6:0] RX_LANE_ALIGNER_FILL_7; + output [6:0] RX_LANE_ALIGNER_FILL_8; + output [6:0] RX_LANE_ALIGNER_FILL_9; + output [3:0] RX_MTYOUT0; + output [3:0] RX_MTYOUT1; + output [3:0] RX_MTYOUT2; + output [3:0] RX_MTYOUT3; + output [7:0] RX_OTN_BIP8_0; + output [7:0] RX_OTN_BIP8_1; + output [7:0] RX_OTN_BIP8_2; + output [7:0] RX_OTN_BIP8_3; + output [7:0] RX_OTN_BIP8_4; + output [65:0] RX_OTN_DATA_0; + output [65:0] RX_OTN_DATA_1; + output [65:0] RX_OTN_DATA_2; + output [65:0] RX_OTN_DATA_3; + output [65:0] RX_OTN_DATA_4; + output RX_OTN_ENA; + output RX_OTN_LANE0; + output RX_OTN_VLMARKER; + output [55:0] RX_PREOUT; + output [4:0] RX_PTP_PCSLANE_OUT; + output [79:0] RX_PTP_TSTAMP_OUT; + output RX_SOPOUT0; + output RX_SOPOUT1; + output RX_SOPOUT2; + output RX_SOPOUT3; + output STAT_RX_ALIGNED; + output STAT_RX_ALIGNED_ERR; + output [2:0] STAT_RX_BAD_CODE; + output [2:0] STAT_RX_BAD_FCS; + output STAT_RX_BAD_PREAMBLE; + output STAT_RX_BAD_SFD; + output STAT_RX_BIP_ERR_0; + output STAT_RX_BIP_ERR_1; + output STAT_RX_BIP_ERR_10; + output STAT_RX_BIP_ERR_11; + output STAT_RX_BIP_ERR_12; + output STAT_RX_BIP_ERR_13; + output STAT_RX_BIP_ERR_14; + output STAT_RX_BIP_ERR_15; + output STAT_RX_BIP_ERR_16; + output STAT_RX_BIP_ERR_17; + output STAT_RX_BIP_ERR_18; + output STAT_RX_BIP_ERR_19; + output STAT_RX_BIP_ERR_2; + output STAT_RX_BIP_ERR_3; + output STAT_RX_BIP_ERR_4; + output STAT_RX_BIP_ERR_5; + output STAT_RX_BIP_ERR_6; + output STAT_RX_BIP_ERR_7; + output STAT_RX_BIP_ERR_8; + output STAT_RX_BIP_ERR_9; + output [19:0] STAT_RX_BLOCK_LOCK; + output STAT_RX_BROADCAST; + output [2:0] STAT_RX_FRAGMENT; + output [1:0] STAT_RX_FRAMING_ERR_0; + output [1:0] STAT_RX_FRAMING_ERR_1; + output [1:0] STAT_RX_FRAMING_ERR_10; + output [1:0] STAT_RX_FRAMING_ERR_11; + output [1:0] STAT_RX_FRAMING_ERR_12; + output [1:0] STAT_RX_FRAMING_ERR_13; + output [1:0] STAT_RX_FRAMING_ERR_14; + output [1:0] STAT_RX_FRAMING_ERR_15; + output [1:0] STAT_RX_FRAMING_ERR_16; + output [1:0] STAT_RX_FRAMING_ERR_17; + output [1:0] STAT_RX_FRAMING_ERR_18; + output [1:0] STAT_RX_FRAMING_ERR_19; + output [1:0] STAT_RX_FRAMING_ERR_2; + output [1:0] STAT_RX_FRAMING_ERR_3; + output [1:0] STAT_RX_FRAMING_ERR_4; + output [1:0] STAT_RX_FRAMING_ERR_5; + output [1:0] STAT_RX_FRAMING_ERR_6; + output [1:0] STAT_RX_FRAMING_ERR_7; + output [1:0] STAT_RX_FRAMING_ERR_8; + output [1:0] STAT_RX_FRAMING_ERR_9; + output STAT_RX_FRAMING_ERR_VALID_0; + output STAT_RX_FRAMING_ERR_VALID_1; + output STAT_RX_FRAMING_ERR_VALID_10; + output STAT_RX_FRAMING_ERR_VALID_11; + output STAT_RX_FRAMING_ERR_VALID_12; + output STAT_RX_FRAMING_ERR_VALID_13; + output STAT_RX_FRAMING_ERR_VALID_14; + output STAT_RX_FRAMING_ERR_VALID_15; + output STAT_RX_FRAMING_ERR_VALID_16; + output STAT_RX_FRAMING_ERR_VALID_17; + output STAT_RX_FRAMING_ERR_VALID_18; + output STAT_RX_FRAMING_ERR_VALID_19; + output STAT_RX_FRAMING_ERR_VALID_2; + output STAT_RX_FRAMING_ERR_VALID_3; + output STAT_RX_FRAMING_ERR_VALID_4; + output STAT_RX_FRAMING_ERR_VALID_5; + output STAT_RX_FRAMING_ERR_VALID_6; + output STAT_RX_FRAMING_ERR_VALID_7; + output STAT_RX_FRAMING_ERR_VALID_8; + output STAT_RX_FRAMING_ERR_VALID_9; + output STAT_RX_GOT_SIGNAL_OS; + output STAT_RX_HI_BER; + output STAT_RX_INRANGEERR; + output STAT_RX_INTERNAL_LOCAL_FAULT; + output STAT_RX_JABBER; + output [7:0] STAT_RX_LANE0_VLM_BIP7; + output STAT_RX_LANE0_VLM_BIP7_VALID; + output STAT_RX_LOCAL_FAULT; + output [19:0] STAT_RX_MF_ERR; + output [19:0] STAT_RX_MF_LEN_ERR; + output [19:0] STAT_RX_MF_REPEAT_ERR; + output STAT_RX_MISALIGNED; + output STAT_RX_MULTICAST; + output STAT_RX_OVERSIZE; + output STAT_RX_PACKET_1024_1518_BYTES; + output STAT_RX_PACKET_128_255_BYTES; + output STAT_RX_PACKET_1519_1522_BYTES; + output STAT_RX_PACKET_1523_1548_BYTES; + output STAT_RX_PACKET_1549_2047_BYTES; + output STAT_RX_PACKET_2048_4095_BYTES; + output STAT_RX_PACKET_256_511_BYTES; + output STAT_RX_PACKET_4096_8191_BYTES; + output STAT_RX_PACKET_512_1023_BYTES; + output STAT_RX_PACKET_64_BYTES; + output STAT_RX_PACKET_65_127_BYTES; + output STAT_RX_PACKET_8192_9215_BYTES; + output STAT_RX_PACKET_BAD_FCS; + output STAT_RX_PACKET_LARGE; + output [2:0] STAT_RX_PACKET_SMALL; + output STAT_RX_PAUSE; + output [15:0] STAT_RX_PAUSE_QUANTA0; + output [15:0] STAT_RX_PAUSE_QUANTA1; + output [15:0] STAT_RX_PAUSE_QUANTA2; + output [15:0] STAT_RX_PAUSE_QUANTA3; + output [15:0] STAT_RX_PAUSE_QUANTA4; + output [15:0] STAT_RX_PAUSE_QUANTA5; + output [15:0] STAT_RX_PAUSE_QUANTA6; + output [15:0] STAT_RX_PAUSE_QUANTA7; + output [15:0] STAT_RX_PAUSE_QUANTA8; + output [8:0] STAT_RX_PAUSE_REQ; + output [8:0] STAT_RX_PAUSE_VALID; + output STAT_RX_RECEIVED_LOCAL_FAULT; + output STAT_RX_REMOTE_FAULT; + output STAT_RX_RSFEC_AM_LOCK0; + output STAT_RX_RSFEC_AM_LOCK1; + output STAT_RX_RSFEC_AM_LOCK2; + output STAT_RX_RSFEC_AM_LOCK3; + output STAT_RX_RSFEC_CORRECTED_CW_INC; + output STAT_RX_RSFEC_CW_INC; + output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC; + output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC; + output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC; + output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC; + output STAT_RX_RSFEC_HI_SER; + output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS; + output [13:0] STAT_RX_RSFEC_LANE_FILL_0; + output [13:0] STAT_RX_RSFEC_LANE_FILL_1; + output [13:0] STAT_RX_RSFEC_LANE_FILL_2; + output [13:0] STAT_RX_RSFEC_LANE_FILL_3; + output [7:0] STAT_RX_RSFEC_LANE_MAPPING; + output [31:0] STAT_RX_RSFEC_RSVD; + output STAT_RX_RSFEC_UNCORRECTED_CW_INC; + output STAT_RX_STATUS; + output [2:0] STAT_RX_STOMPED_FCS; + output [19:0] STAT_RX_SYNCED; + output [19:0] STAT_RX_SYNCED_ERR; + output [2:0] STAT_RX_TEST_PATTERN_MISMATCH; + output STAT_RX_TOOLONG; + output [6:0] STAT_RX_TOTAL_BYTES; + output [13:0] STAT_RX_TOTAL_GOOD_BYTES; + output STAT_RX_TOTAL_GOOD_PACKETS; + output [2:0] STAT_RX_TOTAL_PACKETS; + output STAT_RX_TRUNCATED; + output [2:0] STAT_RX_UNDERSIZE; + output STAT_RX_UNICAST; + output STAT_RX_USER_PAUSE; + output STAT_RX_VLAN; + output [19:0] STAT_RX_VL_DEMUXED; + output [4:0] STAT_RX_VL_NUMBER_0; + output [4:0] STAT_RX_VL_NUMBER_1; + output [4:0] STAT_RX_VL_NUMBER_10; + output [4:0] STAT_RX_VL_NUMBER_11; + output [4:0] STAT_RX_VL_NUMBER_12; + output [4:0] STAT_RX_VL_NUMBER_13; + output [4:0] STAT_RX_VL_NUMBER_14; + output [4:0] STAT_RX_VL_NUMBER_15; + output [4:0] STAT_RX_VL_NUMBER_16; + output [4:0] STAT_RX_VL_NUMBER_17; + output [4:0] STAT_RX_VL_NUMBER_18; + output [4:0] STAT_RX_VL_NUMBER_19; + output [4:0] STAT_RX_VL_NUMBER_2; + output [4:0] STAT_RX_VL_NUMBER_3; + output [4:0] STAT_RX_VL_NUMBER_4; + output [4:0] STAT_RX_VL_NUMBER_5; + output [4:0] STAT_RX_VL_NUMBER_6; + output [4:0] STAT_RX_VL_NUMBER_7; + output [4:0] STAT_RX_VL_NUMBER_8; + output [4:0] STAT_RX_VL_NUMBER_9; + output STAT_TX_BAD_FCS; + output STAT_TX_BROADCAST; + output STAT_TX_FRAME_ERROR; + output STAT_TX_LOCAL_FAULT; + output STAT_TX_MULTICAST; + output STAT_TX_PACKET_1024_1518_BYTES; + output STAT_TX_PACKET_128_255_BYTES; + output STAT_TX_PACKET_1519_1522_BYTES; + output STAT_TX_PACKET_1523_1548_BYTES; + output STAT_TX_PACKET_1549_2047_BYTES; + output STAT_TX_PACKET_2048_4095_BYTES; + output STAT_TX_PACKET_256_511_BYTES; + output STAT_TX_PACKET_4096_8191_BYTES; + output STAT_TX_PACKET_512_1023_BYTES; + output STAT_TX_PACKET_64_BYTES; + output STAT_TX_PACKET_65_127_BYTES; + output STAT_TX_PACKET_8192_9215_BYTES; + output STAT_TX_PACKET_LARGE; + output STAT_TX_PACKET_SMALL; + output STAT_TX_PAUSE; + output [8:0] STAT_TX_PAUSE_VALID; + output STAT_TX_PTP_FIFO_READ_ERROR; + output STAT_TX_PTP_FIFO_WRITE_ERROR; + output [5:0] STAT_TX_TOTAL_BYTES; + output [13:0] STAT_TX_TOTAL_GOOD_BYTES; + output STAT_TX_TOTAL_GOOD_PACKETS; + output STAT_TX_TOTAL_PACKETS; + output STAT_TX_UNICAST; + output STAT_TX_USER_PAUSE; + output STAT_TX_VLAN; + output TX_OVFOUT; + output [4:0] TX_PTP_PCSLANE_OUT; + output [79:0] TX_PTP_TSTAMP_OUT; + output [15:0] TX_PTP_TSTAMP_TAG_OUT; + output TX_PTP_TSTAMP_VALID_OUT; + output TX_RDYOUT; + output [15:0] TX_SERDES_ALT_DATA0; + output [15:0] TX_SERDES_ALT_DATA1; + output [15:0] TX_SERDES_ALT_DATA2; + output [15:0] TX_SERDES_ALT_DATA3; + output [63:0] TX_SERDES_DATA0; + output [63:0] TX_SERDES_DATA1; + output [63:0] TX_SERDES_DATA2; + output [63:0] TX_SERDES_DATA3; + output [31:0] TX_SERDES_DATA4; + output [31:0] TX_SERDES_DATA5; + output [31:0] TX_SERDES_DATA6; + output [31:0] TX_SERDES_DATA7; + output [31:0] TX_SERDES_DATA8; + output [31:0] TX_SERDES_DATA9; + output TX_UNFOUT; + input CTL_CAUI4_MODE; + input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE; + input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE; + input CTL_RX_CHECK_ETYPE_GCP; + input CTL_RX_CHECK_ETYPE_GPP; + input CTL_RX_CHECK_ETYPE_PCP; + input CTL_RX_CHECK_ETYPE_PPP; + input CTL_RX_CHECK_MCAST_GCP; + input CTL_RX_CHECK_MCAST_GPP; + input CTL_RX_CHECK_MCAST_PCP; + input CTL_RX_CHECK_MCAST_PPP; + input CTL_RX_CHECK_OPCODE_GCP; + input CTL_RX_CHECK_OPCODE_GPP; + input CTL_RX_CHECK_OPCODE_PCP; + input CTL_RX_CHECK_OPCODE_PPP; + input CTL_RX_CHECK_SA_GCP; + input CTL_RX_CHECK_SA_GPP; + input CTL_RX_CHECK_SA_PCP; + input CTL_RX_CHECK_SA_PPP; + input CTL_RX_CHECK_UCAST_GCP; + input CTL_RX_CHECK_UCAST_GPP; + input CTL_RX_CHECK_UCAST_PCP; + input CTL_RX_CHECK_UCAST_PPP; + input CTL_RX_ENABLE; + input CTL_RX_ENABLE_GCP; + input CTL_RX_ENABLE_GPP; + input CTL_RX_ENABLE_PCP; + input CTL_RX_ENABLE_PPP; + input CTL_RX_FORCE_RESYNC; + input [8:0] CTL_RX_PAUSE_ACK; + input [8:0] CTL_RX_PAUSE_ENABLE; + input CTL_RX_RSFEC_ENABLE; + input CTL_RX_RSFEC_ENABLE_CORRECTION; + input CTL_RX_RSFEC_ENABLE_INDICATION; + input [79:0] CTL_RX_SYSTEMTIMERIN; + input CTL_RX_TEST_PATTERN; + input CTL_TX_ENABLE; + input CTL_TX_LANE0_VLM_BIP7_OVERRIDE; + input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; + input [8:0] CTL_TX_PAUSE_ENABLE; + input [15:0] CTL_TX_PAUSE_QUANTA0; + input [15:0] CTL_TX_PAUSE_QUANTA1; + input [15:0] CTL_TX_PAUSE_QUANTA2; + input [15:0] CTL_TX_PAUSE_QUANTA3; + input [15:0] CTL_TX_PAUSE_QUANTA4; + input [15:0] CTL_TX_PAUSE_QUANTA5; + input [15:0] CTL_TX_PAUSE_QUANTA6; + input [15:0] CTL_TX_PAUSE_QUANTA7; + input [15:0] CTL_TX_PAUSE_QUANTA8; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7; + input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8; + input [8:0] CTL_TX_PAUSE_REQ; + input CTL_TX_PTP_VLANE_ADJUST_MODE; + input CTL_TX_RESEND_PAUSE; + input CTL_TX_RSFEC_ENABLE; + input CTL_TX_SEND_IDLE; + input CTL_TX_SEND_LFI; + input CTL_TX_SEND_RFI; + input [79:0] CTL_TX_SYSTEMTIMERIN; + input CTL_TX_TEST_PATTERN; + input [9:0] DRP_ADDR; + input DRP_CLK; + input [15:0] DRP_DI; + input DRP_EN; + input DRP_WE; + input [329:0] RSFEC_BYPASS_RX_DIN; + input RSFEC_BYPASS_RX_DIN_CW_START; + input [329:0] RSFEC_BYPASS_TX_DIN; + input RSFEC_BYPASS_TX_DIN_CW_START; + input RX_CLK; + input RX_RESET; + input [15:0] RX_SERDES_ALT_DATA0; + input [15:0] RX_SERDES_ALT_DATA1; + input [15:0] RX_SERDES_ALT_DATA2; + input [15:0] RX_SERDES_ALT_DATA3; + input [9:0] RX_SERDES_CLK; + input [63:0] RX_SERDES_DATA0; + input [63:0] RX_SERDES_DATA1; + input [63:0] RX_SERDES_DATA2; + input [63:0] RX_SERDES_DATA3; + input [31:0] RX_SERDES_DATA4; + input [31:0] RX_SERDES_DATA5; + input [31:0] RX_SERDES_DATA6; + input [31:0] RX_SERDES_DATA7; + input [31:0] RX_SERDES_DATA8; + input [31:0] RX_SERDES_DATA9; + input [9:0] RX_SERDES_RESET; + input TX_CLK; + input [127:0] TX_DATAIN0; + input [127:0] TX_DATAIN1; + input [127:0] TX_DATAIN2; + input [127:0] TX_DATAIN3; + input TX_ENAIN0; + input TX_ENAIN1; + input TX_ENAIN2; + input TX_ENAIN3; + input TX_EOPIN0; + input TX_EOPIN1; + input TX_EOPIN2; + input TX_EOPIN3; + input TX_ERRIN0; + input TX_ERRIN1; + input TX_ERRIN2; + input TX_ERRIN3; + input [3:0] TX_MTYIN0; + input [3:0] TX_MTYIN1; + input [3:0] TX_MTYIN2; + input [3:0] TX_MTYIN3; + input [55:0] TX_PREIN; + input [1:0] TX_PTP_1588OP_IN; + input [15:0] TX_PTP_CHKSUM_OFFSET_IN; + input [63:0] TX_PTP_RXTSTAMP_IN; + input [15:0] TX_PTP_TAG_FIELD_IN; + input [15:0] TX_PTP_TSTAMP_OFFSET_IN; + input TX_PTP_UPD_CHKSUM_IN; + input TX_RESET; + input TX_SOPIN0; + input TX_SOPIN1; + input TX_SOPIN2; + input TX_SOPIN3; +endmodule + +module PPC405_ADV (...); + parameter in_delay=100; + parameter out_delay=100; + output APUFCMDECODED; + output APUFCMDECUDIVALID; + output APUFCMENDIAN; + output APUFCMFLUSH; + output APUFCMINSTRVALID; + output APUFCMLOADDVALID; + output APUFCMOPERANDVALID; + output APUFCMWRITEBACKOK; + output APUFCMXERCA; + output C405CPMCORESLEEPREQ; + output C405CPMMSRCE; + output C405CPMMSREE; + output C405CPMTIMERIRQ; + output C405CPMTIMERRESETREQ; + output C405DBGLOADDATAONAPUDBUS; + output C405DBGMSRWE; + output C405DBGSTOPACK; + output C405DBGWBCOMPLETE; + output C405DBGWBFULL; + output C405JTGCAPTUREDR; + output C405JTGEXTEST; + output C405JTGPGMOUT; + output C405JTGSHIFTDR; + output C405JTGTDO; + output C405JTGTDOEN; + output C405JTGUPDATEDR; + output C405PLBDCUABORT; + output C405PLBDCUCACHEABLE; + output C405PLBDCUGUARDED; + output C405PLBDCUREQUEST; + output C405PLBDCURNW; + output C405PLBDCUSIZE2; + output C405PLBDCUU0ATTR; + output C405PLBDCUWRITETHRU; + output C405PLBICUABORT; + output C405PLBICUCACHEABLE; + output C405PLBICUREQUEST; + output C405PLBICUU0ATTR; + output C405RSTCHIPRESETREQ; + output C405RSTCORERESETREQ; + output C405RSTSYSRESETREQ; + output C405TRCCYCLE; + output C405TRCTRIGGEREVENTOUT; + output C405XXXMACHINECHECK; + output DCREMACCLK; + output DCREMACENABLER; + output DCREMACREAD; + output DCREMACWRITE; + output DSOCMBRAMEN; + output DSOCMBUSY; + output DSOCMRDADDRVALID; + output DSOCMWRADDRVALID; + output EXTDCRREAD; + output EXTDCRWRITE; + output ISOCMBRAMEN; + output ISOCMBRAMEVENWRITEEN; + output ISOCMBRAMODDWRITEEN; + output ISOCMDCRBRAMEVENEN; + output ISOCMDCRBRAMODDEN; + output ISOCMDCRBRAMRDSELECT; + output [0:10] C405TRCTRIGGEREVENTTYPE; + output [0:1] C405PLBDCUPRIORITY; + output [0:1] C405PLBICUPRIORITY; + output [0:1] C405TRCEVENEXECUTIONSTATUS; + output [0:1] C405TRCODDEXECUTIONSTATUS; + output [0:29] C405DBGWBIAR; + output [0:29] C405PLBICUABUS; + output [0:2] APUFCMDECUDI; + output [0:31] APUFCMINSTRUCTION; + output [0:31] APUFCMLOADDATA; + output [0:31] APUFCMRADATA; + output [0:31] APUFCMRBDATA; + output [0:31] C405PLBDCUABUS; + output [0:31] DCREMACDBUS; + output [0:31] DSOCMBRAMWRDBUS; + output [0:31] EXTDCRDBUSOUT; + output [0:31] ISOCMBRAMWRDBUS; + output [0:3] APUFCMLOADBYTEEN; + output [0:3] C405TRCTRACESTATUS; + output [0:3] DSOCMBRAMBYTEWRITE; + output [0:63] C405PLBDCUWRDBUS; + output [0:7] C405PLBDCUBE; + output [0:9] EXTDCRABUS; + output [2:3] C405PLBICUSIZE; + output [8:28] ISOCMBRAMRDABUS; + output [8:28] ISOCMBRAMWRABUS; + output [8:29] DSOCMBRAMABUS; + output [8:9] DCREMACABUS; + input BRAMDSOCMCLK; + input BRAMISOCMCLK; + input CPMC405CLOCK; + input CPMC405CORECLKINACTIVE; + input CPMC405CPUCLKEN; + input CPMC405JTAGCLKEN; + input CPMC405SYNCBYPASS; + input CPMC405TIMERCLKEN; + input CPMC405TIMERTICK; + input CPMDCRCLK; + input CPMFCMCLK; + input DBGC405DEBUGHALT; + input DBGC405EXTBUSHOLDACK; + input DBGC405UNCONDDEBUGEVENT; + input DSOCMRWCOMPLETE; + input EICC405CRITINPUTIRQ; + input EICC405EXTINPUTIRQ; + input EMACDCRACK; + input EXTDCRACK; + input FCMAPUDCDCREN; + input FCMAPUDCDFORCEALIGN; + input FCMAPUDCDFORCEBESTEERING; + input FCMAPUDCDFPUOP; + input FCMAPUDCDGPRWRITE; + input FCMAPUDCDLDSTBYTE; + input FCMAPUDCDLDSTDW; + input FCMAPUDCDLDSTHW; + input FCMAPUDCDLDSTQW; + input FCMAPUDCDLDSTWD; + input FCMAPUDCDLOAD; + input FCMAPUDCDPRIVOP; + input FCMAPUDCDRAEN; + input FCMAPUDCDRBEN; + input FCMAPUDCDSTORE; + input FCMAPUDCDTRAPBE; + input FCMAPUDCDTRAPLE; + input FCMAPUDCDUPDATE; + input FCMAPUDCDXERCAEN; + input FCMAPUDCDXEROVEN; + input FCMAPUDECODEBUSY; + input FCMAPUDONE; + input FCMAPUEXCEPTION; + input FCMAPUEXEBLOCKINGMCO; + input FCMAPUEXENONBLOCKINGMCO; + input FCMAPUINSTRACK; + input FCMAPULOADWAIT; + input FCMAPURESULTVALID; + input FCMAPUSLEEPNOTREADY; + input FCMAPUXERCA; + input FCMAPUXEROV; + input JTGC405BNDSCANTDO; + input JTGC405TCK; + input JTGC405TDI; + input JTGC405TMS; + input JTGC405TRSTNEG; + input MCBCPUCLKEN; + input MCBJTAGEN; + input MCBTIMEREN; + input MCPPCRST; + input PLBC405DCUADDRACK; + input PLBC405DCUBUSY; + input PLBC405DCUERR; + input PLBC405DCURDDACK; + input PLBC405DCUSSIZE1; + input PLBC405DCUWRDACK; + input PLBC405ICUADDRACK; + input PLBC405ICUBUSY; + input PLBC405ICUERR; + input PLBC405ICURDDACK; + input PLBC405ICUSSIZE1; + input PLBCLK; + input RSTC405RESETCHIP; + input RSTC405RESETCORE; + input RSTC405RESETSYS; + input TIEC405DETERMINISTICMULT; + input TIEC405DISOPERANDFWD; + input TIEC405MMUEN; + input TIEPVRBIT10; + input TIEPVRBIT11; + input TIEPVRBIT28; + input TIEPVRBIT29; + input TIEPVRBIT30; + input TIEPVRBIT31; + input TIEPVRBIT8; + input TIEPVRBIT9; + input TRCC405TRACEDISABLE; + input TRCC405TRIGGEREVENTIN; + input [0:15] TIEAPUCONTROL; + input [0:23] TIEAPUUDI1; + input [0:23] TIEAPUUDI2; + input [0:23] TIEAPUUDI3; + input [0:23] TIEAPUUDI4; + input [0:23] TIEAPUUDI5; + input [0:23] TIEAPUUDI6; + input [0:23] TIEAPUUDI7; + input [0:23] TIEAPUUDI8; + input [0:2] FCMAPUEXECRFIELD; + input [0:31] BRAMDSOCMRDDBUS; + input [0:31] BRAMISOCMDCRRDDBUS; + input [0:31] EMACDCRDBUS; + input [0:31] EXTDCRDBUSIN; + input [0:31] FCMAPURESULT; + input [0:3] FCMAPUCR; + input [0:5] TIEDCRADDR; + input [0:63] BRAMISOCMRDDBUS; + input [0:63] PLBC405DCURDDBUS; + input [0:63] PLBC405ICURDDBUS; + input [0:7] DSARCVALUE; + input [0:7] DSCNTLVALUE; + input [0:7] ISARCVALUE; + input [0:7] ISCNTLVALUE; + input [1:3] PLBC405DCURDWDADDR; + input [1:3] PLBC405ICURDWDADDR; +endmodule + +module PPC440 (...); + parameter CLOCK_DELAY = "FALSE"; + parameter DCR_AUTOLOCK_ENABLE = "TRUE"; + parameter PPCDM_ASYNCMODE = "FALSE"; + parameter PPCDS_ASYNCMODE = "FALSE"; + parameter PPCS0_WIDTH_128N64 = "TRUE"; + parameter PPCS1_WIDTH_128N64 = "TRUE"; + parameter [0:16] APU_CONTROL = 17'h02000; + parameter [0:23] APU_UDI0 = 24'h000000; + parameter [0:23] APU_UDI1 = 24'h000000; + parameter [0:23] APU_UDI10 = 24'h000000; + parameter [0:23] APU_UDI11 = 24'h000000; + parameter [0:23] APU_UDI12 = 24'h000000; + parameter [0:23] APU_UDI13 = 24'h000000; + parameter [0:23] APU_UDI14 = 24'h000000; + parameter [0:23] APU_UDI15 = 24'h000000; + parameter [0:23] APU_UDI2 = 24'h000000; + parameter [0:23] APU_UDI3 = 24'h000000; + parameter [0:23] APU_UDI4 = 24'h000000; + parameter [0:23] APU_UDI5 = 24'h000000; + parameter [0:23] APU_UDI6 = 24'h000000; + parameter [0:23] APU_UDI7 = 24'h000000; + parameter [0:23] APU_UDI8 = 24'h000000; + parameter [0:23] APU_UDI9 = 24'h000000; + parameter [0:31] DMA0_RXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA0_TXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA1_RXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA1_TXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA2_RXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA2_TXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA3_RXCHANNELCTRL = 32'h01010000; + parameter [0:31] DMA3_TXCHANNELCTRL = 32'h01010000; + parameter [0:31] INTERCONNECT_IMASK = 32'hFFFFFFFF; + parameter [0:31] INTERCONNECT_TMPL_SEL = 32'h3FFFFFFF; + parameter [0:31] MI_ARBCONFIG = 32'h00432010; + parameter [0:31] MI_BANKCONFLICT_MASK = 32'h00000000; + parameter [0:31] MI_CONTROL = 32'h0000008F; + parameter [0:31] MI_ROWCONFLICT_MASK = 32'h00000000; + parameter [0:31] PPCM_ARBCONFIG = 32'h00432010; + parameter [0:31] PPCM_CONTROL = 32'h8000019F; + parameter [0:31] PPCM_COUNTER = 32'h00000500; + parameter [0:31] PPCS0_ADDRMAP_TMPL0 = 32'hFFFFFFFF; + parameter [0:31] PPCS0_ADDRMAP_TMPL1 = 32'hFFFFFFFF; + parameter [0:31] PPCS0_ADDRMAP_TMPL2 = 32'hFFFFFFFF; + parameter [0:31] PPCS0_ADDRMAP_TMPL3 = 32'hFFFFFFFF; + parameter [0:31] PPCS0_CONTROL = 32'h8033336C; + parameter [0:31] PPCS1_ADDRMAP_TMPL0 = 32'hFFFFFFFF; + parameter [0:31] PPCS1_ADDRMAP_TMPL1 = 32'hFFFFFFFF; + parameter [0:31] PPCS1_ADDRMAP_TMPL2 = 32'hFFFFFFFF; + parameter [0:31] PPCS1_ADDRMAP_TMPL3 = 32'hFFFFFFFF; + parameter [0:31] PPCS1_CONTROL = 32'h8033336C; + parameter [0:31] XBAR_ADDRMAP_TMPL0 = 32'hFFFF0000; + parameter [0:31] XBAR_ADDRMAP_TMPL1 = 32'h00000000; + parameter [0:31] XBAR_ADDRMAP_TMPL2 = 32'h00000000; + parameter [0:31] XBAR_ADDRMAP_TMPL3 = 32'h00000000; + parameter [0:7] DMA0_CONTROL = 8'h00; + parameter [0:7] DMA1_CONTROL = 8'h00; + parameter [0:7] DMA2_CONTROL = 8'h00; + parameter [0:7] DMA3_CONTROL = 8'h00; + parameter [0:9] DMA0_RXIRQTIMER = 10'h3FF; + parameter [0:9] DMA0_TXIRQTIMER = 10'h3FF; + parameter [0:9] DMA1_RXIRQTIMER = 10'h3FF; + parameter [0:9] DMA1_TXIRQTIMER = 10'h3FF; + parameter [0:9] DMA2_RXIRQTIMER = 10'h3FF; + parameter [0:9] DMA2_TXIRQTIMER = 10'h3FF; + parameter [0:9] DMA3_RXIRQTIMER = 10'h3FF; + parameter [0:9] DMA3_TXIRQTIMER = 10'h3FF; + output APUFCMDECFPUOP; + output APUFCMDECLOAD; + output APUFCMDECNONAUTON; + output APUFCMDECSTORE; + output APUFCMDECUDIVALID; + output APUFCMENDIAN; + output APUFCMFLUSH; + output APUFCMINSTRVALID; + output APUFCMLOADDVALID; + output APUFCMMSRFE0; + output APUFCMMSRFE1; + output APUFCMNEXTINSTRREADY; + output APUFCMOPERANDVALID; + output APUFCMWRITEBACKOK; + output C440CPMCORESLEEPREQ; + output C440CPMDECIRPTREQ; + output C440CPMFITIRPTREQ; + output C440CPMMSRCE; + output C440CPMMSREE; + output C440CPMTIMERRESETREQ; + output C440CPMWDIRPTREQ; + output C440JTGTDO; + output C440JTGTDOEN; + output C440MACHINECHECK; + output C440RSTCHIPRESETREQ; + output C440RSTCORERESETREQ; + output C440RSTSYSTEMRESETREQ; + output C440TRCCYCLE; + output C440TRCTRIGGEREVENTOUT; + output DMA0LLRSTENGINEACK; + output DMA0LLRXDSTRDYN; + output DMA0LLTXEOFN; + output DMA0LLTXEOPN; + output DMA0LLTXSOFN; + output DMA0LLTXSOPN; + output DMA0LLTXSRCRDYN; + output DMA0RXIRQ; + output DMA0TXIRQ; + output DMA1LLRSTENGINEACK; + output DMA1LLRXDSTRDYN; + output DMA1LLTXEOFN; + output DMA1LLTXEOPN; + output DMA1LLTXSOFN; + output DMA1LLTXSOPN; + output DMA1LLTXSRCRDYN; + output DMA1RXIRQ; + output DMA1TXIRQ; + output DMA2LLRSTENGINEACK; + output DMA2LLRXDSTRDYN; + output DMA2LLTXEOFN; + output DMA2LLTXEOPN; + output DMA2LLTXSOFN; + output DMA2LLTXSOPN; + output DMA2LLTXSRCRDYN; + output DMA2RXIRQ; + output DMA2TXIRQ; + output DMA3LLRSTENGINEACK; + output DMA3LLRXDSTRDYN; + output DMA3LLTXEOFN; + output DMA3LLTXEOPN; + output DMA3LLTXSOFN; + output DMA3LLTXSOPN; + output DMA3LLTXSRCRDYN; + output DMA3RXIRQ; + output DMA3TXIRQ; + output MIMCADDRESSVALID; + output MIMCBANKCONFLICT; + output MIMCREADNOTWRITE; + output MIMCROWCONFLICT; + output MIMCWRITEDATAVALID; + output PPCCPMINTERCONNECTBUSY; + output PPCDMDCRREAD; + output PPCDMDCRWRITE; + output PPCDSDCRACK; + output PPCDSDCRTIMEOUTWAIT; + output PPCEICINTERCONNECTIRQ; + output PPCMPLBABORT; + output PPCMPLBBUSLOCK; + output PPCMPLBLOCKERR; + output PPCMPLBRDBURST; + output PPCMPLBREQUEST; + output PPCMPLBRNW; + output PPCMPLBWRBURST; + output PPCS0PLBADDRACK; + output PPCS0PLBRDBTERM; + output PPCS0PLBRDCOMP; + output PPCS0PLBRDDACK; + output PPCS0PLBREARBITRATE; + output PPCS0PLBWAIT; + output PPCS0PLBWRBTERM; + output PPCS0PLBWRCOMP; + output PPCS0PLBWRDACK; + output PPCS1PLBADDRACK; + output PPCS1PLBRDBTERM; + output PPCS1PLBRDCOMP; + output PPCS1PLBRDDACK; + output PPCS1PLBREARBITRATE; + output PPCS1PLBWAIT; + output PPCS1PLBWRBTERM; + output PPCS1PLBWRCOMP; + output PPCS1PLBWRDACK; + output [0:127] APUFCMLOADDATA; + output [0:127] MIMCWRITEDATA; + output [0:127] PPCMPLBWRDBUS; + output [0:127] PPCS0PLBRDDBUS; + output [0:127] PPCS1PLBRDDBUS; + output [0:13] C440TRCTRIGGEREVENTTYPE; + output [0:15] MIMCBYTEENABLE; + output [0:15] PPCMPLBBE; + output [0:15] PPCMPLBTATTRIBUTE; + output [0:1] PPCMPLBPRIORITY; + output [0:1] PPCS0PLBSSIZE; + output [0:1] PPCS1PLBSSIZE; + output [0:2] APUFCMDECLDSTXFERSIZE; + output [0:2] C440TRCBRANCHSTATUS; + output [0:2] PPCMPLBTYPE; + output [0:31] APUFCMINSTRUCTION; + output [0:31] APUFCMRADATA; + output [0:31] APUFCMRBDATA; + output [0:31] DMA0LLTXD; + output [0:31] DMA1LLTXD; + output [0:31] DMA2LLTXD; + output [0:31] DMA3LLTXD; + output [0:31] PPCDMDCRDBUSOUT; + output [0:31] PPCDSDCRDBUSIN; + output [0:31] PPCMPLBABUS; + output [0:35] MIMCADDRESS; + output [0:3] APUFCMDECUDI; + output [0:3] APUFCMLOADBYTEADDR; + output [0:3] DMA0LLTXREM; + output [0:3] DMA1LLTXREM; + output [0:3] DMA2LLTXREM; + output [0:3] DMA3LLTXREM; + output [0:3] PPCMPLBSIZE; + output [0:3] PPCS0PLBMBUSY; + output [0:3] PPCS0PLBMIRQ; + output [0:3] PPCS0PLBMRDERR; + output [0:3] PPCS0PLBMWRERR; + output [0:3] PPCS0PLBRDWDADDR; + output [0:3] PPCS1PLBMBUSY; + output [0:3] PPCS1PLBMIRQ; + output [0:3] PPCS1PLBMRDERR; + output [0:3] PPCS1PLBMWRERR; + output [0:3] PPCS1PLBRDWDADDR; + output [0:4] C440TRCEXECUTIONSTATUS; + output [0:6] C440TRCTRACESTATUS; + output [0:7] C440DBGSYSTEMCONTROL; + output [0:9] PPCDMDCRABUS; + output [20:21] PPCDMDCRUABUS; + output [28:31] PPCMPLBUABUS; + input CPMC440CLK; + input CPMC440CLKEN; + input CPMC440CORECLOCKINACTIVE; + input CPMC440TIMERCLOCK; + input CPMDCRCLK; + input CPMDMA0LLCLK; + input CPMDMA1LLCLK; + input CPMDMA2LLCLK; + input CPMDMA3LLCLK; + input CPMFCMCLK; + input CPMINTERCONNECTCLK; + input CPMINTERCONNECTCLKEN; + input CPMINTERCONNECTCLKNTO1; + input CPMMCCLK; + input CPMPPCMPLBCLK; + input CPMPPCS0PLBCLK; + input CPMPPCS1PLBCLK; + input DBGC440DEBUGHALT; + input DBGC440UNCONDDEBUGEVENT; + input DCRPPCDMACK; + input DCRPPCDMTIMEOUTWAIT; + input DCRPPCDSREAD; + input DCRPPCDSWRITE; + input EICC440CRITIRQ; + input EICC440EXTIRQ; + input FCMAPUCONFIRMINSTR; + input FCMAPUDONE; + input FCMAPUEXCEPTION; + input FCMAPUFPSCRFEX; + input FCMAPURESULTVALID; + input FCMAPUSLEEPNOTREADY; + input JTGC440TCK; + input JTGC440TDI; + input JTGC440TMS; + input JTGC440TRSTNEG; + input LLDMA0RSTENGINEREQ; + input LLDMA0RXEOFN; + input LLDMA0RXEOPN; + input LLDMA0RXSOFN; + input LLDMA0RXSOPN; + input LLDMA0RXSRCRDYN; + input LLDMA0TXDSTRDYN; + input LLDMA1RSTENGINEREQ; + input LLDMA1RXEOFN; + input LLDMA1RXEOPN; + input LLDMA1RXSOFN; + input LLDMA1RXSOPN; + input LLDMA1RXSRCRDYN; + input LLDMA1TXDSTRDYN; + input LLDMA2RSTENGINEREQ; + input LLDMA2RXEOFN; + input LLDMA2RXEOPN; + input LLDMA2RXSOFN; + input LLDMA2RXSOPN; + input LLDMA2RXSRCRDYN; + input LLDMA2TXDSTRDYN; + input LLDMA3RSTENGINEREQ; + input LLDMA3RXEOFN; + input LLDMA3RXEOPN; + input LLDMA3RXSOFN; + input LLDMA3RXSOPN; + input LLDMA3RXSRCRDYN; + input LLDMA3TXDSTRDYN; + input MCMIADDRREADYTOACCEPT; + input MCMIREADDATAERR; + input MCMIREADDATAVALID; + input PLBPPCMADDRACK; + input PLBPPCMMBUSY; + input PLBPPCMMIRQ; + input PLBPPCMMRDERR; + input PLBPPCMMWRERR; + input PLBPPCMRDBTERM; + input PLBPPCMRDDACK; + input PLBPPCMRDPENDREQ; + input PLBPPCMREARBITRATE; + input PLBPPCMTIMEOUT; + input PLBPPCMWRBTERM; + input PLBPPCMWRDACK; + input PLBPPCMWRPENDREQ; + input PLBPPCS0ABORT; + input PLBPPCS0BUSLOCK; + input PLBPPCS0LOCKERR; + input PLBPPCS0PAVALID; + input PLBPPCS0RDBURST; + input PLBPPCS0RDPENDREQ; + input PLBPPCS0RDPRIM; + input PLBPPCS0RNW; + input PLBPPCS0SAVALID; + input PLBPPCS0WRBURST; + input PLBPPCS0WRPENDREQ; + input PLBPPCS0WRPRIM; + input PLBPPCS1ABORT; + input PLBPPCS1BUSLOCK; + input PLBPPCS1LOCKERR; + input PLBPPCS1PAVALID; + input PLBPPCS1RDBURST; + input PLBPPCS1RDPENDREQ; + input PLBPPCS1RDPRIM; + input PLBPPCS1RNW; + input PLBPPCS1SAVALID; + input PLBPPCS1WRBURST; + input PLBPPCS1WRPENDREQ; + input PLBPPCS1WRPRIM; + input RSTC440RESETCHIP; + input RSTC440RESETCORE; + input RSTC440RESETSYSTEM; + input TIEC440ENDIANRESET; + input TRCC440TRACEDISABLE; + input TRCC440TRIGGEREVENTIN; + input [0:127] FCMAPUSTOREDATA; + input [0:127] MCMIREADDATA; + input [0:127] PLBPPCMRDDBUS; + input [0:127] PLBPPCS0WRDBUS; + input [0:127] PLBPPCS1WRDBUS; + input [0:15] PLBPPCS0BE; + input [0:15] PLBPPCS0TATTRIBUTE; + input [0:15] PLBPPCS1BE; + input [0:15] PLBPPCS1TATTRIBUTE; + input [0:1] PLBPPCMRDPENDPRI; + input [0:1] PLBPPCMREQPRI; + input [0:1] PLBPPCMSSIZE; + input [0:1] PLBPPCMWRPENDPRI; + input [0:1] PLBPPCS0MASTERID; + input [0:1] PLBPPCS0MSIZE; + input [0:1] PLBPPCS0RDPENDPRI; + input [0:1] PLBPPCS0REQPRI; + input [0:1] PLBPPCS0WRPENDPRI; + input [0:1] PLBPPCS1MASTERID; + input [0:1] PLBPPCS1MSIZE; + input [0:1] PLBPPCS1RDPENDPRI; + input [0:1] PLBPPCS1REQPRI; + input [0:1] PLBPPCS1WRPENDPRI; + input [0:1] TIEC440DCURDLDCACHEPLBPRIO; + input [0:1] TIEC440DCURDNONCACHEPLBPRIO; + input [0:1] TIEC440DCURDTOUCHPLBPRIO; + input [0:1] TIEC440DCURDURGENTPLBPRIO; + input [0:1] TIEC440DCUWRFLUSHPLBPRIO; + input [0:1] TIEC440DCUWRSTOREPLBPRIO; + input [0:1] TIEC440DCUWRURGENTPLBPRIO; + input [0:1] TIEC440ICURDFETCHPLBPRIO; + input [0:1] TIEC440ICURDSPECPLBPRIO; + input [0:1] TIEC440ICURDTOUCHPLBPRIO; + input [0:1] TIEDCRBASEADDR; + input [0:2] PLBPPCS0TYPE; + input [0:2] PLBPPCS1TYPE; + input [0:31] DCRPPCDMDBUSIN; + input [0:31] DCRPPCDSDBUSOUT; + input [0:31] FCMAPURESULT; + input [0:31] LLDMA0RXD; + input [0:31] LLDMA1RXD; + input [0:31] LLDMA2RXD; + input [0:31] LLDMA3RXD; + input [0:31] PLBPPCS0ABUS; + input [0:31] PLBPPCS1ABUS; + input [0:3] FCMAPUCR; + input [0:3] LLDMA0RXREM; + input [0:3] LLDMA1RXREM; + input [0:3] LLDMA2RXREM; + input [0:3] LLDMA3RXREM; + input [0:3] PLBPPCMRDWDADDR; + input [0:3] PLBPPCS0SIZE; + input [0:3] PLBPPCS1SIZE; + input [0:3] TIEC440ERPNRESET; + input [0:3] TIEC440USERRESET; + input [0:4] DBGC440SYSTEMSTATUS; + input [0:9] DCRPPCDSABUS; + input [28:31] PLBPPCS0UABUS; + input [28:31] PLBPPCS1UABUS; + input [28:31] TIEC440PIR; + input [28:31] TIEC440PVR; +endmodule + +module MCB (...); + parameter integer ARB_NUM_TIME_SLOTS = 12; + parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111; + parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111; + parameter [2:0] CAL_BA = 3'h0; + parameter CAL_BYPASS = "YES"; + parameter [11:0] CAL_CA = 12'h000; + parameter CAL_CALIBRATION_MODE = "NOCALIBRATION"; + parameter integer CAL_CLK_DIV = 1; + parameter CAL_DELAY = "QUARTER"; + parameter [14:0] CAL_RA = 15'h0000; + parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"; + parameter integer MEM_BA_SIZE = 3; + parameter integer MEM_BURST_LEN = 8; + parameter integer MEM_CAS_LATENCY = 4; + parameter integer MEM_CA_SIZE = 11; + parameter MEM_DDR1_2_ODS = "FULL"; + parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"; + parameter MEM_DDR2_3_PA_SR = "FULL"; + parameter integer MEM_DDR2_ADD_LATENCY = 0; + parameter MEM_DDR2_DIFF_DQS_EN = "YES"; + parameter MEM_DDR2_RTT = "50OHMS"; + parameter integer MEM_DDR2_WRT_RECOVERY = 4; + parameter MEM_DDR3_ADD_LATENCY = "OFF"; + parameter MEM_DDR3_AUTO_SR = "ENABLED"; + parameter integer MEM_DDR3_CAS_LATENCY = 7; + parameter integer MEM_DDR3_CAS_WR_LATENCY = 5; + parameter MEM_DDR3_DYN_WRT_ODT = "OFF"; + parameter MEM_DDR3_ODS = "DIV7"; + parameter MEM_DDR3_RTT = "DIV2"; + parameter integer MEM_DDR3_WRT_RECOVERY = 7; + parameter MEM_MDDR_ODS = "FULL"; + parameter MEM_MOBILE_PA_SR = "FULL"; + parameter integer MEM_MOBILE_TC_SR = 0; + parameter integer MEM_RAS_VAL = 0; + parameter integer MEM_RA_SIZE = 13; + parameter integer MEM_RCD_VAL = 1; + parameter integer MEM_REFI_VAL = 0; + parameter integer MEM_RFC_VAL = 0; + parameter integer MEM_RP_VAL = 0; + parameter integer MEM_RTP_VAL = 0; + parameter MEM_TYPE = "DDR3"; + parameter integer MEM_WIDTH = 4; + parameter integer MEM_WR_VAL = 0; + parameter integer MEM_WTR_VAL = 3; + parameter PORT_CONFIG = "B32_B32_B32_B32"; + output CAS; + output CKE; + output DQIOWEN0; + output DQSIOWEN90N; + output DQSIOWEN90P; + output IOIDRPADD; + output IOIDRPBROADCAST; + output IOIDRPCLK; + output IOIDRPCS; + output IOIDRPSDO; + output IOIDRPTRAIN; + output IOIDRPUPDATE; + output LDMN; + output LDMP; + output ODT; + output P0CMDEMPTY; + output P0CMDFULL; + output P0RDEMPTY; + output P0RDERROR; + output P0RDFULL; + output P0RDOVERFLOW; + output P0WREMPTY; + output P0WRERROR; + output P0WRFULL; + output P0WRUNDERRUN; + output P1CMDEMPTY; + output P1CMDFULL; + output P1RDEMPTY; + output P1RDERROR; + output P1RDFULL; + output P1RDOVERFLOW; + output P1WREMPTY; + output P1WRERROR; + output P1WRFULL; + output P1WRUNDERRUN; + output P2CMDEMPTY; + output P2CMDFULL; + output P2EMPTY; + output P2ERROR; + output P2FULL; + output P2RDOVERFLOW; + output P2WRUNDERRUN; + output P3CMDEMPTY; + output P3CMDFULL; + output P3EMPTY; + output P3ERROR; + output P3FULL; + output P3RDOVERFLOW; + output P3WRUNDERRUN; + output P4CMDEMPTY; + output P4CMDFULL; + output P4EMPTY; + output P4ERROR; + output P4FULL; + output P4RDOVERFLOW; + output P4WRUNDERRUN; + output P5CMDEMPTY; + output P5CMDFULL; + output P5EMPTY; + output P5ERROR; + output P5FULL; + output P5RDOVERFLOW; + output P5WRUNDERRUN; + output RAS; + output RST; + output SELFREFRESHMODE; + output UDMN; + output UDMP; + output UOCALSTART; + output UOCMDREADYIN; + output UODATAVALID; + output UODONECAL; + output UOREFRSHFLAG; + output UOSDO; + output WE; + output [14:0] ADDR; + output [15:0] DQON; + output [15:0] DQOP; + output [2:0] BA; + output [31:0] P0RDDATA; + output [31:0] P1RDDATA; + output [31:0] P2RDDATA; + output [31:0] P3RDDATA; + output [31:0] P4RDDATA; + output [31:0] P5RDDATA; + output [31:0] STATUS; + output [4:0] IOIDRPADDR; + output [6:0] P0RDCOUNT; + output [6:0] P0WRCOUNT; + output [6:0] P1RDCOUNT; + output [6:0] P1WRCOUNT; + output [6:0] P2COUNT; + output [6:0] P3COUNT; + output [6:0] P4COUNT; + output [6:0] P5COUNT; + output [7:0] UODATA; + input DQSIOIN; + input DQSIOIP; + input IOIDRPSDI; + input P0ARBEN; + input P0CMDCLK; + input P0CMDEN; + input P0RDCLK; + input P0RDEN; + input P0WRCLK; + input P0WREN; + input P1ARBEN; + input P1CMDCLK; + input P1CMDEN; + input P1RDCLK; + input P1RDEN; + input P1WRCLK; + input P1WREN; + input P2ARBEN; + input P2CLK; + input P2CMDCLK; + input P2CMDEN; + input P2EN; + input P3ARBEN; + input P3CLK; + input P3CMDCLK; + input P3CMDEN; + input P3EN; + input P4ARBEN; + input P4CLK; + input P4CMDCLK; + input P4CMDEN; + input P4EN; + input P5ARBEN; + input P5CLK; + input P5CMDCLK; + input P5CMDEN; + input P5EN; + input PLLLOCK; + input RECAL; + input SELFREFRESHENTER; + input SYSRST; + input UDQSIOIN; + input UDQSIOIP; + input UIADD; + input UIBROADCAST; + input UICLK; + input UICMD; + input UICMDEN; + input UICMDIN; + input UICS; + input UIDONECAL; + input UIDQLOWERDEC; + input UIDQLOWERINC; + input UIDQUPPERDEC; + input UIDQUPPERINC; + input UIDRPUPDATE; + input UILDQSDEC; + input UILDQSINC; + input UIREAD; + input UISDI; + input UIUDQSDEC; + input UIUDQSINC; + input [11:0] P0CMDCA; + input [11:0] P1CMDCA; + input [11:0] P2CMDCA; + input [11:0] P3CMDCA; + input [11:0] P4CMDCA; + input [11:0] P5CMDCA; + input [14:0] P0CMDRA; + input [14:0] P1CMDRA; + input [14:0] P2CMDRA; + input [14:0] P3CMDRA; + input [14:0] P4CMDRA; + input [14:0] P5CMDRA; + input [15:0] DQI; + input [1:0] PLLCE; + input [1:0] PLLCLK; + input [2:0] P0CMDBA; + input [2:0] P0CMDINSTR; + input [2:0] P1CMDBA; + input [2:0] P1CMDINSTR; + input [2:0] P2CMDBA; + input [2:0] P2CMDINSTR; + input [2:0] P3CMDBA; + input [2:0] P3CMDINSTR; + input [2:0] P4CMDBA; + input [2:0] P4CMDINSTR; + input [2:0] P5CMDBA; + input [2:0] P5CMDINSTR; + input [31:0] P0WRDATA; + input [31:0] P1WRDATA; + input [31:0] P2WRDATA; + input [31:0] P3WRDATA; + input [31:0] P4WRDATA; + input [31:0] P5WRDATA; + input [3:0] P0RWRMASK; + input [3:0] P1RWRMASK; + input [3:0] P2WRMASK; + input [3:0] P3WRMASK; + input [3:0] P4WRMASK; + input [3:0] P5WRMASK; + input [3:0] UIDQCOUNT; + input [4:0] UIADDR; + input [5:0] P0CMDBL; + input [5:0] P1CMDBL; + input [5:0] P2CMDBL; + input [5:0] P3CMDBL; + input [5:0] P4CMDBL; + input [5:0] P5CMDBL; +endmodule + +(* keep *) +module PS7 (...); + output DMA0DAVALID; + output DMA0DRREADY; + output DMA0RSTN; + output DMA1DAVALID; + output DMA1DRREADY; + output DMA1RSTN; + output DMA2DAVALID; + output DMA2DRREADY; + output DMA2RSTN; + output DMA3DAVALID; + output DMA3DRREADY; + output DMA3RSTN; + output EMIOCAN0PHYTX; + output EMIOCAN1PHYTX; + output EMIOENET0GMIITXEN; + output EMIOENET0GMIITXER; + output EMIOENET0MDIOMDC; + output EMIOENET0MDIOO; + output EMIOENET0MDIOTN; + output EMIOENET0PTPDELAYREQRX; + output EMIOENET0PTPDELAYREQTX; + output EMIOENET0PTPPDELAYREQRX; + output EMIOENET0PTPPDELAYREQTX; + output EMIOENET0PTPPDELAYRESPRX; + output EMIOENET0PTPPDELAYRESPTX; + output EMIOENET0PTPSYNCFRAMERX; + output EMIOENET0PTPSYNCFRAMETX; + output EMIOENET0SOFRX; + output EMIOENET0SOFTX; + output EMIOENET1GMIITXEN; + output EMIOENET1GMIITXER; + output EMIOENET1MDIOMDC; + output EMIOENET1MDIOO; + output EMIOENET1MDIOTN; + output EMIOENET1PTPDELAYREQRX; + output EMIOENET1PTPDELAYREQTX; + output EMIOENET1PTPPDELAYREQRX; + output EMIOENET1PTPPDELAYREQTX; + output EMIOENET1PTPPDELAYRESPRX; + output EMIOENET1PTPPDELAYRESPTX; + output EMIOENET1PTPSYNCFRAMERX; + output EMIOENET1PTPSYNCFRAMETX; + output EMIOENET1SOFRX; + output EMIOENET1SOFTX; + output EMIOI2C0SCLO; + output EMIOI2C0SCLTN; + output EMIOI2C0SDAO; + output EMIOI2C0SDATN; + output EMIOI2C1SCLO; + output EMIOI2C1SCLTN; + output EMIOI2C1SDAO; + output EMIOI2C1SDATN; + output EMIOPJTAGTDO; + output EMIOPJTAGTDTN; + output EMIOSDIO0BUSPOW; + output EMIOSDIO0CLK; + output EMIOSDIO0CMDO; + output EMIOSDIO0CMDTN; + output EMIOSDIO0LED; + output EMIOSDIO1BUSPOW; + output EMIOSDIO1CLK; + output EMIOSDIO1CMDO; + output EMIOSDIO1CMDTN; + output EMIOSDIO1LED; + output EMIOSPI0MO; + output EMIOSPI0MOTN; + output EMIOSPI0SCLKO; + output EMIOSPI0SCLKTN; + output EMIOSPI0SO; + output EMIOSPI0SSNTN; + output EMIOSPI0STN; + output EMIOSPI1MO; + output EMIOSPI1MOTN; + output EMIOSPI1SCLKO; + output EMIOSPI1SCLKTN; + output EMIOSPI1SO; + output EMIOSPI1SSNTN; + output EMIOSPI1STN; + output EMIOTRACECTL; + output EMIOUART0DTRN; + output EMIOUART0RTSN; + output EMIOUART0TX; + output EMIOUART1DTRN; + output EMIOUART1RTSN; + output EMIOUART1TX; + output EMIOUSB0VBUSPWRSELECT; + output EMIOUSB1VBUSPWRSELECT; + output EMIOWDTRSTO; + output EVENTEVENTO; + output MAXIGP0ARESETN; + output MAXIGP0ARVALID; + output MAXIGP0AWVALID; + output MAXIGP0BREADY; + output MAXIGP0RREADY; + output MAXIGP0WLAST; + output MAXIGP0WVALID; + output MAXIGP1ARESETN; + output MAXIGP1ARVALID; + output MAXIGP1AWVALID; + output MAXIGP1BREADY; + output MAXIGP1RREADY; + output MAXIGP1WLAST; + output MAXIGP1WVALID; + output SAXIACPARESETN; + output SAXIACPARREADY; + output SAXIACPAWREADY; + output SAXIACPBVALID; + output SAXIACPRLAST; + output SAXIACPRVALID; + output SAXIACPWREADY; + output SAXIGP0ARESETN; + output SAXIGP0ARREADY; + output SAXIGP0AWREADY; + output SAXIGP0BVALID; + output SAXIGP0RLAST; + output SAXIGP0RVALID; + output SAXIGP0WREADY; + output SAXIGP1ARESETN; + output SAXIGP1ARREADY; + output SAXIGP1AWREADY; + output SAXIGP1BVALID; + output SAXIGP1RLAST; + output SAXIGP1RVALID; + output SAXIGP1WREADY; + output SAXIHP0ARESETN; + output SAXIHP0ARREADY; + output SAXIHP0AWREADY; + output SAXIHP0BVALID; + output SAXIHP0RLAST; + output SAXIHP0RVALID; + output SAXIHP0WREADY; + output SAXIHP1ARESETN; + output SAXIHP1ARREADY; + output SAXIHP1AWREADY; + output SAXIHP1BVALID; + output SAXIHP1RLAST; + output SAXIHP1RVALID; + output SAXIHP1WREADY; + output SAXIHP2ARESETN; + output SAXIHP2ARREADY; + output SAXIHP2AWREADY; + output SAXIHP2BVALID; + output SAXIHP2RLAST; + output SAXIHP2RVALID; + output SAXIHP2WREADY; + output SAXIHP3ARESETN; + output SAXIHP3ARREADY; + output SAXIHP3AWREADY; + output SAXIHP3BVALID; + output SAXIHP3RLAST; + output SAXIHP3RVALID; + output SAXIHP3WREADY; + output [11:0] MAXIGP0ARID; + output [11:0] MAXIGP0AWID; + output [11:0] MAXIGP0WID; + output [11:0] MAXIGP1ARID; + output [11:0] MAXIGP1AWID; + output [11:0] MAXIGP1WID; + output [1:0] DMA0DATYPE; + output [1:0] DMA1DATYPE; + output [1:0] DMA2DATYPE; + output [1:0] DMA3DATYPE; + output [1:0] EMIOUSB0PORTINDCTL; + output [1:0] EMIOUSB1PORTINDCTL; + output [1:0] EVENTSTANDBYWFE; + output [1:0] EVENTSTANDBYWFI; + output [1:0] MAXIGP0ARBURST; + output [1:0] MAXIGP0ARLOCK; + output [1:0] MAXIGP0ARSIZE; + output [1:0] MAXIGP0AWBURST; + output [1:0] MAXIGP0AWLOCK; + output [1:0] MAXIGP0AWSIZE; + output [1:0] MAXIGP1ARBURST; + output [1:0] MAXIGP1ARLOCK; + output [1:0] MAXIGP1ARSIZE; + output [1:0] MAXIGP1AWBURST; + output [1:0] MAXIGP1AWLOCK; + output [1:0] MAXIGP1AWSIZE; + output [1:0] SAXIACPBRESP; + output [1:0] SAXIACPRRESP; + output [1:0] SAXIGP0BRESP; + output [1:0] SAXIGP0RRESP; + output [1:0] SAXIGP1BRESP; + output [1:0] SAXIGP1RRESP; + output [1:0] SAXIHP0BRESP; + output [1:0] SAXIHP0RRESP; + output [1:0] SAXIHP1BRESP; + output [1:0] SAXIHP1RRESP; + output [1:0] SAXIHP2BRESP; + output [1:0] SAXIHP2RRESP; + output [1:0] SAXIHP3BRESP; + output [1:0] SAXIHP3RRESP; + output [28:0] IRQP2F; + output [2:0] EMIOSDIO0BUSVOLT; + output [2:0] EMIOSDIO1BUSVOLT; + output [2:0] EMIOSPI0SSON; + output [2:0] EMIOSPI1SSON; + output [2:0] EMIOTTC0WAVEO; + output [2:0] EMIOTTC1WAVEO; + output [2:0] MAXIGP0ARPROT; + output [2:0] MAXIGP0AWPROT; + output [2:0] MAXIGP1ARPROT; + output [2:0] MAXIGP1AWPROT; + output [2:0] SAXIACPBID; + output [2:0] SAXIACPRID; + output [2:0] SAXIHP0RACOUNT; + output [2:0] SAXIHP1RACOUNT; + output [2:0] SAXIHP2RACOUNT; + output [2:0] SAXIHP3RACOUNT; + output [31:0] EMIOTRACEDATA; + output [31:0] FTMTP2FDEBUG; + output [31:0] MAXIGP0ARADDR; + output [31:0] MAXIGP0AWADDR; + output [31:0] MAXIGP0WDATA; + output [31:0] MAXIGP1ARADDR; + output [31:0] MAXIGP1AWADDR; + output [31:0] MAXIGP1WDATA; + output [31:0] SAXIGP0RDATA; + output [31:0] SAXIGP1RDATA; + output [3:0] EMIOSDIO0DATAO; + output [3:0] EMIOSDIO0DATATN; + output [3:0] EMIOSDIO1DATAO; + output [3:0] EMIOSDIO1DATATN; + output [3:0] FCLKCLK; + output [3:0] FCLKRESETN; + output [3:0] FTMTF2PTRIGACK; + output [3:0] FTMTP2FTRIG; + output [3:0] MAXIGP0ARCACHE; + output [3:0] MAXIGP0ARLEN; + output [3:0] MAXIGP0ARQOS; + output [3:0] MAXIGP0AWCACHE; + output [3:0] MAXIGP0AWLEN; + output [3:0] MAXIGP0AWQOS; + output [3:0] MAXIGP0WSTRB; + output [3:0] MAXIGP1ARCACHE; + output [3:0] MAXIGP1ARLEN; + output [3:0] MAXIGP1ARQOS; + output [3:0] MAXIGP1AWCACHE; + output [3:0] MAXIGP1AWLEN; + output [3:0] MAXIGP1AWQOS; + output [3:0] MAXIGP1WSTRB; + output [5:0] SAXIGP0BID; + output [5:0] SAXIGP0RID; + output [5:0] SAXIGP1BID; + output [5:0] SAXIGP1RID; + output [5:0] SAXIHP0BID; + output [5:0] SAXIHP0RID; + output [5:0] SAXIHP0WACOUNT; + output [5:0] SAXIHP1BID; + output [5:0] SAXIHP1RID; + output [5:0] SAXIHP1WACOUNT; + output [5:0] SAXIHP2BID; + output [5:0] SAXIHP2RID; + output [5:0] SAXIHP2WACOUNT; + output [5:0] SAXIHP3BID; + output [5:0] SAXIHP3RID; + output [5:0] SAXIHP3WACOUNT; + output [63:0] EMIOGPIOO; + output [63:0] EMIOGPIOTN; + output [63:0] SAXIACPRDATA; + output [63:0] SAXIHP0RDATA; + output [63:0] SAXIHP1RDATA; + output [63:0] SAXIHP2RDATA; + output [63:0] SAXIHP3RDATA; + output [7:0] EMIOENET0GMIITXD; + output [7:0] EMIOENET1GMIITXD; + output [7:0] SAXIHP0RCOUNT; + output [7:0] SAXIHP0WCOUNT; + output [7:0] SAXIHP1RCOUNT; + output [7:0] SAXIHP1WCOUNT; + output [7:0] SAXIHP2RCOUNT; + output [7:0] SAXIHP2WCOUNT; + output [7:0] SAXIHP3RCOUNT; + output [7:0] SAXIHP3WCOUNT; + inout DDRCASB; + inout DDRCKE; + inout DDRCKN; + inout DDRCKP; + inout DDRCSB; + inout DDRDRSTB; + inout DDRODT; + inout DDRRASB; + inout DDRVRN; + inout DDRVRP; + inout DDRWEB; + inout PSCLK; + inout PSPORB; + inout PSSRSTB; + inout [14:0] DDRA; + inout [2:0] DDRBA; + inout [31:0] DDRDQ; + inout [3:0] DDRDM; + inout [3:0] DDRDQSN; + inout [3:0] DDRDQSP; + inout [53:0] MIO; + input DMA0ACLK; + input DMA0DAREADY; + input DMA0DRLAST; + input DMA0DRVALID; + input DMA1ACLK; + input DMA1DAREADY; + input DMA1DRLAST; + input DMA1DRVALID; + input DMA2ACLK; + input DMA2DAREADY; + input DMA2DRLAST; + input DMA2DRVALID; + input DMA3ACLK; + input DMA3DAREADY; + input DMA3DRLAST; + input DMA3DRVALID; + input EMIOCAN0PHYRX; + input EMIOCAN1PHYRX; + input EMIOENET0EXTINTIN; + input EMIOENET0GMIICOL; + input EMIOENET0GMIICRS; + input EMIOENET0GMIIRXCLK; + input EMIOENET0GMIIRXDV; + input EMIOENET0GMIIRXER; + input EMIOENET0GMIITXCLK; + input EMIOENET0MDIOI; + input EMIOENET1EXTINTIN; + input EMIOENET1GMIICOL; + input EMIOENET1GMIICRS; + input EMIOENET1GMIIRXCLK; + input EMIOENET1GMIIRXDV; + input EMIOENET1GMIIRXER; + input EMIOENET1GMIITXCLK; + input EMIOENET1MDIOI; + input EMIOI2C0SCLI; + input EMIOI2C0SDAI; + input EMIOI2C1SCLI; + input EMIOI2C1SDAI; + input EMIOPJTAGTCK; + input EMIOPJTAGTDI; + input EMIOPJTAGTMS; + input EMIOSDIO0CDN; + input EMIOSDIO0CLKFB; + input EMIOSDIO0CMDI; + input EMIOSDIO0WP; + input EMIOSDIO1CDN; + input EMIOSDIO1CLKFB; + input EMIOSDIO1CMDI; + input EMIOSDIO1WP; + input EMIOSPI0MI; + input EMIOSPI0SCLKI; + input EMIOSPI0SI; + input EMIOSPI0SSIN; + input EMIOSPI1MI; + input EMIOSPI1SCLKI; + input EMIOSPI1SI; + input EMIOSPI1SSIN; + input EMIOSRAMINTIN; + input EMIOTRACECLK; + input EMIOUART0CTSN; + input EMIOUART0DCDN; + input EMIOUART0DSRN; + input EMIOUART0RIN; + input EMIOUART0RX; + input EMIOUART1CTSN; + input EMIOUART1DCDN; + input EMIOUART1DSRN; + input EMIOUART1RIN; + input EMIOUART1RX; + input EMIOUSB0VBUSPWRFAULT; + input EMIOUSB1VBUSPWRFAULT; + input EMIOWDTCLKI; + input EVENTEVENTI; + input FPGAIDLEN; + input FTMDTRACEINCLOCK; + input FTMDTRACEINVALID; + input MAXIGP0ACLK; + input MAXIGP0ARREADY; + input MAXIGP0AWREADY; + input MAXIGP0BVALID; + input MAXIGP0RLAST; + input MAXIGP0RVALID; + input MAXIGP0WREADY; + input MAXIGP1ACLK; + input MAXIGP1ARREADY; + input MAXIGP1AWREADY; + input MAXIGP1BVALID; + input MAXIGP1RLAST; + input MAXIGP1RVALID; + input MAXIGP1WREADY; + input SAXIACPACLK; + input SAXIACPARVALID; + input SAXIACPAWVALID; + input SAXIACPBREADY; + input SAXIACPRREADY; + input SAXIACPWLAST; + input SAXIACPWVALID; + input SAXIGP0ACLK; + input SAXIGP0ARVALID; + input SAXIGP0AWVALID; + input SAXIGP0BREADY; + input SAXIGP0RREADY; + input SAXIGP0WLAST; + input SAXIGP0WVALID; + input SAXIGP1ACLK; + input SAXIGP1ARVALID; + input SAXIGP1AWVALID; + input SAXIGP1BREADY; + input SAXIGP1RREADY; + input SAXIGP1WLAST; + input SAXIGP1WVALID; + input SAXIHP0ACLK; + input SAXIHP0ARVALID; + input SAXIHP0AWVALID; + input SAXIHP0BREADY; + input SAXIHP0RDISSUECAP1EN; + input SAXIHP0RREADY; + input SAXIHP0WLAST; + input SAXIHP0WRISSUECAP1EN; + input SAXIHP0WVALID; + input SAXIHP1ACLK; + input SAXIHP1ARVALID; + input SAXIHP1AWVALID; + input SAXIHP1BREADY; + input SAXIHP1RDISSUECAP1EN; + input SAXIHP1RREADY; + input SAXIHP1WLAST; + input SAXIHP1WRISSUECAP1EN; + input SAXIHP1WVALID; + input SAXIHP2ACLK; + input SAXIHP2ARVALID; + input SAXIHP2AWVALID; + input SAXIHP2BREADY; + input SAXIHP2RDISSUECAP1EN; + input SAXIHP2RREADY; + input SAXIHP2WLAST; + input SAXIHP2WRISSUECAP1EN; + input SAXIHP2WVALID; + input SAXIHP3ACLK; + input SAXIHP3ARVALID; + input SAXIHP3AWVALID; + input SAXIHP3BREADY; + input SAXIHP3RDISSUECAP1EN; + input SAXIHP3RREADY; + input SAXIHP3WLAST; + input SAXIHP3WRISSUECAP1EN; + input SAXIHP3WVALID; + input [11:0] MAXIGP0BID; + input [11:0] MAXIGP0RID; + input [11:0] MAXIGP1BID; + input [11:0] MAXIGP1RID; + input [19:0] IRQF2P; + input [1:0] DMA0DRTYPE; + input [1:0] DMA1DRTYPE; + input [1:0] DMA2DRTYPE; + input [1:0] DMA3DRTYPE; + input [1:0] MAXIGP0BRESP; + input [1:0] MAXIGP0RRESP; + input [1:0] MAXIGP1BRESP; + input [1:0] MAXIGP1RRESP; + input [1:0] SAXIACPARBURST; + input [1:0] SAXIACPARLOCK; + input [1:0] SAXIACPARSIZE; + input [1:0] SAXIACPAWBURST; + input [1:0] SAXIACPAWLOCK; + input [1:0] SAXIACPAWSIZE; + input [1:0] SAXIGP0ARBURST; + input [1:0] SAXIGP0ARLOCK; + input [1:0] SAXIGP0ARSIZE; + input [1:0] SAXIGP0AWBURST; + input [1:0] SAXIGP0AWLOCK; + input [1:0] SAXIGP0AWSIZE; + input [1:0] SAXIGP1ARBURST; + input [1:0] SAXIGP1ARLOCK; + input [1:0] SAXIGP1ARSIZE; + input [1:0] SAXIGP1AWBURST; + input [1:0] SAXIGP1AWLOCK; + input [1:0] SAXIGP1AWSIZE; + input [1:0] SAXIHP0ARBURST; + input [1:0] SAXIHP0ARLOCK; + input [1:0] SAXIHP0ARSIZE; + input [1:0] SAXIHP0AWBURST; + input [1:0] SAXIHP0AWLOCK; + input [1:0] SAXIHP0AWSIZE; + input [1:0] SAXIHP1ARBURST; + input [1:0] SAXIHP1ARLOCK; + input [1:0] SAXIHP1ARSIZE; + input [1:0] SAXIHP1AWBURST; + input [1:0] SAXIHP1AWLOCK; + input [1:0] SAXIHP1AWSIZE; + input [1:0] SAXIHP2ARBURST; + input [1:0] SAXIHP2ARLOCK; + input [1:0] SAXIHP2ARSIZE; + input [1:0] SAXIHP2AWBURST; + input [1:0] SAXIHP2AWLOCK; + input [1:0] SAXIHP2AWSIZE; + input [1:0] SAXIHP3ARBURST; + input [1:0] SAXIHP3ARLOCK; + input [1:0] SAXIHP3ARSIZE; + input [1:0] SAXIHP3AWBURST; + input [1:0] SAXIHP3AWLOCK; + input [1:0] SAXIHP3AWSIZE; + input [2:0] EMIOTTC0CLKI; + input [2:0] EMIOTTC1CLKI; + input [2:0] SAXIACPARID; + input [2:0] SAXIACPARPROT; + input [2:0] SAXIACPAWID; + input [2:0] SAXIACPAWPROT; + input [2:0] SAXIACPWID; + input [2:0] SAXIGP0ARPROT; + input [2:0] SAXIGP0AWPROT; + input [2:0] SAXIGP1ARPROT; + input [2:0] SAXIGP1AWPROT; + input [2:0] SAXIHP0ARPROT; + input [2:0] SAXIHP0AWPROT; + input [2:0] SAXIHP1ARPROT; + input [2:0] SAXIHP1AWPROT; + input [2:0] SAXIHP2ARPROT; + input [2:0] SAXIHP2AWPROT; + input [2:0] SAXIHP3ARPROT; + input [2:0] SAXIHP3AWPROT; + input [31:0] FTMDTRACEINDATA; + input [31:0] FTMTF2PDEBUG; + input [31:0] MAXIGP0RDATA; + input [31:0] MAXIGP1RDATA; + input [31:0] SAXIACPARADDR; + input [31:0] SAXIACPAWADDR; + input [31:0] SAXIGP0ARADDR; + input [31:0] SAXIGP0AWADDR; + input [31:0] SAXIGP0WDATA; + input [31:0] SAXIGP1ARADDR; + input [31:0] SAXIGP1AWADDR; + input [31:0] SAXIGP1WDATA; + input [31:0] SAXIHP0ARADDR; + input [31:0] SAXIHP0AWADDR; + input [31:0] SAXIHP1ARADDR; + input [31:0] SAXIHP1AWADDR; + input [31:0] SAXIHP2ARADDR; + input [31:0] SAXIHP2AWADDR; + input [31:0] SAXIHP3ARADDR; + input [31:0] SAXIHP3AWADDR; + input [3:0] DDRARB; + input [3:0] EMIOSDIO0DATAI; + input [3:0] EMIOSDIO1DATAI; + input [3:0] FCLKCLKTRIGN; + input [3:0] FTMDTRACEINATID; + input [3:0] FTMTF2PTRIG; + input [3:0] FTMTP2FTRIGACK; + input [3:0] SAXIACPARCACHE; + input [3:0] SAXIACPARLEN; + input [3:0] SAXIACPARQOS; + input [3:0] SAXIACPAWCACHE; + input [3:0] SAXIACPAWLEN; + input [3:0] SAXIACPAWQOS; + input [3:0] SAXIGP0ARCACHE; + input [3:0] SAXIGP0ARLEN; + input [3:0] SAXIGP0ARQOS; + input [3:0] SAXIGP0AWCACHE; + input [3:0] SAXIGP0AWLEN; + input [3:0] SAXIGP0AWQOS; + input [3:0] SAXIGP0WSTRB; + input [3:0] SAXIGP1ARCACHE; + input [3:0] SAXIGP1ARLEN; + input [3:0] SAXIGP1ARQOS; + input [3:0] SAXIGP1AWCACHE; + input [3:0] SAXIGP1AWLEN; + input [3:0] SAXIGP1AWQOS; + input [3:0] SAXIGP1WSTRB; + input [3:0] SAXIHP0ARCACHE; + input [3:0] SAXIHP0ARLEN; + input [3:0] SAXIHP0ARQOS; + input [3:0] SAXIHP0AWCACHE; + input [3:0] SAXIHP0AWLEN; + input [3:0] SAXIHP0AWQOS; + input [3:0] SAXIHP1ARCACHE; + input [3:0] SAXIHP1ARLEN; + input [3:0] SAXIHP1ARQOS; + input [3:0] SAXIHP1AWCACHE; + input [3:0] SAXIHP1AWLEN; + input [3:0] SAXIHP1AWQOS; + input [3:0] SAXIHP2ARCACHE; + input [3:0] SAXIHP2ARLEN; + input [3:0] SAXIHP2ARQOS; + input [3:0] SAXIHP2AWCACHE; + input [3:0] SAXIHP2AWLEN; + input [3:0] SAXIHP2AWQOS; + input [3:0] SAXIHP3ARCACHE; + input [3:0] SAXIHP3ARLEN; + input [3:0] SAXIHP3ARQOS; + input [3:0] SAXIHP3AWCACHE; + input [3:0] SAXIHP3AWLEN; + input [3:0] SAXIHP3AWQOS; + input [4:0] SAXIACPARUSER; + input [4:0] SAXIACPAWUSER; + input [5:0] SAXIGP0ARID; + input [5:0] SAXIGP0AWID; + input [5:0] SAXIGP0WID; + input [5:0] SAXIGP1ARID; + input [5:0] SAXIGP1AWID; + input [5:0] SAXIGP1WID; + input [5:0] SAXIHP0ARID; + input [5:0] SAXIHP0AWID; + input [5:0] SAXIHP0WID; + input [5:0] SAXIHP1ARID; + input [5:0] SAXIHP1AWID; + input [5:0] SAXIHP1WID; + input [5:0] SAXIHP2ARID; + input [5:0] SAXIHP2AWID; + input [5:0] SAXIHP2WID; + input [5:0] SAXIHP3ARID; + input [5:0] SAXIHP3AWID; + input [5:0] SAXIHP3WID; + input [63:0] EMIOGPIOI; + input [63:0] SAXIACPWDATA; + input [63:0] SAXIHP0WDATA; + input [63:0] SAXIHP1WDATA; + input [63:0] SAXIHP2WDATA; + input [63:0] SAXIHP3WDATA; + input [7:0] EMIOENET0GMIIRXD; + input [7:0] EMIOENET1GMIIRXD; + input [7:0] SAXIACPWSTRB; + input [7:0] SAXIHP0WSTRB; + input [7:0] SAXIHP1WSTRB; + input [7:0] SAXIHP2WSTRB; + input [7:0] SAXIHP3WSTRB; +endmodule + +(* keep *) +module PS8 (...); + output [7:0] ADMA2PLCACK; + output [7:0] ADMA2PLTVLD; + output DPAUDIOREFCLK; + output DPAUXDATAOEN; + output DPAUXDATAOUT; + output DPLIVEVIDEODEOUT; + output [31:0] DPMAXISMIXEDAUDIOTDATA; + output DPMAXISMIXEDAUDIOTID; + output DPMAXISMIXEDAUDIOTVALID; + output DPSAXISAUDIOTREADY; + output DPVIDEOOUTHSYNC; + output [35:0] DPVIDEOOUTPIXEL1; + output DPVIDEOOUTVSYNC; + output DPVIDEOREFCLK; + output EMIOCAN0PHYTX; + output EMIOCAN1PHYTX; + output [1:0] EMIOENET0DMABUSWIDTH; + output EMIOENET0DMATXENDTOG; + output [93:0] EMIOENET0GEMTSUTIMERCNT; + output [7:0] EMIOENET0GMIITXD; + output EMIOENET0GMIITXEN; + output EMIOENET0GMIITXER; + output EMIOENET0MDIOMDC; + output EMIOENET0MDIOO; + output EMIOENET0MDIOTN; + output [7:0] EMIOENET0RXWDATA; + output EMIOENET0RXWEOP; + output EMIOENET0RXWERR; + output EMIOENET0RXWFLUSH; + output EMIOENET0RXWSOP; + output [44:0] EMIOENET0RXWSTATUS; + output EMIOENET0RXWWR; + output [2:0] EMIOENET0SPEEDMODE; + output EMIOENET0TXRRD; + output [3:0] EMIOENET0TXRSTATUS; + output [1:0] EMIOENET1DMABUSWIDTH; + output EMIOENET1DMATXENDTOG; + output [7:0] EMIOENET1GMIITXD; + output EMIOENET1GMIITXEN; + output EMIOENET1GMIITXER; + output EMIOENET1MDIOMDC; + output EMIOENET1MDIOO; + output EMIOENET1MDIOTN; + output [7:0] EMIOENET1RXWDATA; + output EMIOENET1RXWEOP; + output EMIOENET1RXWERR; + output EMIOENET1RXWFLUSH; + output EMIOENET1RXWSOP; + output [44:0] EMIOENET1RXWSTATUS; + output EMIOENET1RXWWR; + output [2:0] EMIOENET1SPEEDMODE; + output EMIOENET1TXRRD; + output [3:0] EMIOENET1TXRSTATUS; + output [1:0] EMIOENET2DMABUSWIDTH; + output EMIOENET2DMATXENDTOG; + output [7:0] EMIOENET2GMIITXD; + output EMIOENET2GMIITXEN; + output EMIOENET2GMIITXER; + output EMIOENET2MDIOMDC; + output EMIOENET2MDIOO; + output EMIOENET2MDIOTN; + output [7:0] EMIOENET2RXWDATA; + output EMIOENET2RXWEOP; + output EMIOENET2RXWERR; + output EMIOENET2RXWFLUSH; + output EMIOENET2RXWSOP; + output [44:0] EMIOENET2RXWSTATUS; + output EMIOENET2RXWWR; + output [2:0] EMIOENET2SPEEDMODE; + output EMIOENET2TXRRD; + output [3:0] EMIOENET2TXRSTATUS; + output [1:0] EMIOENET3DMABUSWIDTH; + output EMIOENET3DMATXENDTOG; + output [7:0] EMIOENET3GMIITXD; + output EMIOENET3GMIITXEN; + output EMIOENET3GMIITXER; + output EMIOENET3MDIOMDC; + output EMIOENET3MDIOO; + output EMIOENET3MDIOTN; + output [7:0] EMIOENET3RXWDATA; + output EMIOENET3RXWEOP; + output EMIOENET3RXWERR; + output EMIOENET3RXWFLUSH; + output EMIOENET3RXWSOP; + output [44:0] EMIOENET3RXWSTATUS; + output EMIOENET3RXWWR; + output [2:0] EMIOENET3SPEEDMODE; + output EMIOENET3TXRRD; + output [3:0] EMIOENET3TXRSTATUS; + output EMIOGEM0DELAYREQRX; + output EMIOGEM0DELAYREQTX; + output EMIOGEM0PDELAYREQRX; + output EMIOGEM0PDELAYREQTX; + output EMIOGEM0PDELAYRESPRX; + output EMIOGEM0PDELAYRESPTX; + output EMIOGEM0RXSOF; + output EMIOGEM0SYNCFRAMERX; + output EMIOGEM0SYNCFRAMETX; + output EMIOGEM0TSUTIMERCMPVAL; + output EMIOGEM0TXRFIXEDLAT; + output EMIOGEM0TXSOF; + output EMIOGEM1DELAYREQRX; + output EMIOGEM1DELAYREQTX; + output EMIOGEM1PDELAYREQRX; + output EMIOGEM1PDELAYREQTX; + output EMIOGEM1PDELAYRESPRX; + output EMIOGEM1PDELAYRESPTX; + output EMIOGEM1RXSOF; + output EMIOGEM1SYNCFRAMERX; + output EMIOGEM1SYNCFRAMETX; + output EMIOGEM1TSUTIMERCMPVAL; + output EMIOGEM1TXRFIXEDLAT; + output EMIOGEM1TXSOF; + output EMIOGEM2DELAYREQRX; + output EMIOGEM2DELAYREQTX; + output EMIOGEM2PDELAYREQRX; + output EMIOGEM2PDELAYREQTX; + output EMIOGEM2PDELAYRESPRX; + output EMIOGEM2PDELAYRESPTX; + output EMIOGEM2RXSOF; + output EMIOGEM2SYNCFRAMERX; + output EMIOGEM2SYNCFRAMETX; + output EMIOGEM2TSUTIMERCMPVAL; + output EMIOGEM2TXRFIXEDLAT; + output EMIOGEM2TXSOF; + output EMIOGEM3DELAYREQRX; + output EMIOGEM3DELAYREQTX; + output EMIOGEM3PDELAYREQRX; + output EMIOGEM3PDELAYREQTX; + output EMIOGEM3PDELAYRESPRX; + output EMIOGEM3PDELAYRESPTX; + output EMIOGEM3RXSOF; + output EMIOGEM3SYNCFRAMERX; + output EMIOGEM3SYNCFRAMETX; + output EMIOGEM3TSUTIMERCMPVAL; + output EMIOGEM3TXRFIXEDLAT; + output EMIOGEM3TXSOF; + output [95:0] EMIOGPIOO; + output [95:0] EMIOGPIOTN; + output EMIOI2C0SCLO; + output EMIOI2C0SCLTN; + output EMIOI2C0SDAO; + output EMIOI2C0SDATN; + output EMIOI2C1SCLO; + output EMIOI2C1SCLTN; + output EMIOI2C1SDAO; + output EMIOI2C1SDATN; + output EMIOSDIO0BUSPOWER; + output [2:0] EMIOSDIO0BUSVOLT; + output EMIOSDIO0CLKOUT; + output EMIOSDIO0CMDENA; + output EMIOSDIO0CMDOUT; + output [7:0] EMIOSDIO0DATAENA; + output [7:0] EMIOSDIO0DATAOUT; + output EMIOSDIO0LEDCONTROL; + output EMIOSDIO1BUSPOWER; + output [2:0] EMIOSDIO1BUSVOLT; + output EMIOSDIO1CLKOUT; + output EMIOSDIO1CMDENA; + output EMIOSDIO1CMDOUT; + output [7:0] EMIOSDIO1DATAENA; + output [7:0] EMIOSDIO1DATAOUT; + output EMIOSDIO1LEDCONTROL; + output EMIOSPI0MO; + output EMIOSPI0MOTN; + output EMIOSPI0SCLKO; + output EMIOSPI0SCLKTN; + output EMIOSPI0SO; + output EMIOSPI0SSNTN; + output [2:0] EMIOSPI0SSON; + output EMIOSPI0STN; + output EMIOSPI1MO; + output EMIOSPI1MOTN; + output EMIOSPI1SCLKO; + output EMIOSPI1SCLKTN; + output EMIOSPI1SO; + output EMIOSPI1SSNTN; + output [2:0] EMIOSPI1SSON; + output EMIOSPI1STN; + output [2:0] EMIOTTC0WAVEO; + output [2:0] EMIOTTC1WAVEO; + output [2:0] EMIOTTC2WAVEO; + output [2:0] EMIOTTC3WAVEO; + output EMIOU2DSPORTVBUSCTRLUSB30; + output EMIOU2DSPORTVBUSCTRLUSB31; + output EMIOU3DSPORTVBUSCTRLUSB30; + output EMIOU3DSPORTVBUSCTRLUSB31; + output EMIOUART0DTRN; + output EMIOUART0RTSN; + output EMIOUART0TX; + output EMIOUART1DTRN; + output EMIOUART1RTSN; + output EMIOUART1TX; + output EMIOWDT0RSTO; + output EMIOWDT1RSTO; + output FMIOGEM0FIFORXCLKTOPLBUFG; + output FMIOGEM0FIFOTXCLKTOPLBUFG; + output FMIOGEM1FIFORXCLKTOPLBUFG; + output FMIOGEM1FIFOTXCLKTOPLBUFG; + output FMIOGEM2FIFORXCLKTOPLBUFG; + output FMIOGEM2FIFOTXCLKTOPLBUFG; + output FMIOGEM3FIFORXCLKTOPLBUFG; + output FMIOGEM3FIFOTXCLKTOPLBUFG; + output FMIOGEMTSUCLKTOPLBUFG; + output [31:0] FTMGPO; + output [7:0] GDMA2PLCACK; + output [7:0] GDMA2PLTVLD; + output [39:0] MAXIGP0ARADDR; + output [1:0] MAXIGP0ARBURST; + output [3:0] MAXIGP0ARCACHE; + output [15:0] MAXIGP0ARID; + output [7:0] MAXIGP0ARLEN; + output MAXIGP0ARLOCK; + output [2:0] MAXIGP0ARPROT; + output [3:0] MAXIGP0ARQOS; + output [2:0] MAXIGP0ARSIZE; + output [15:0] MAXIGP0ARUSER; + output MAXIGP0ARVALID; + output [39:0] MAXIGP0AWADDR; + output [1:0] MAXIGP0AWBURST; + output [3:0] MAXIGP0AWCACHE; + output [15:0] MAXIGP0AWID; + output [7:0] MAXIGP0AWLEN; + output MAXIGP0AWLOCK; + output [2:0] MAXIGP0AWPROT; + output [3:0] MAXIGP0AWQOS; + output [2:0] MAXIGP0AWSIZE; + output [15:0] MAXIGP0AWUSER; + output MAXIGP0AWVALID; + output MAXIGP0BREADY; + output MAXIGP0RREADY; + output [127:0] MAXIGP0WDATA; + output MAXIGP0WLAST; + output [15:0] MAXIGP0WSTRB; + output MAXIGP0WVALID; + output [39:0] MAXIGP1ARADDR; + output [1:0] MAXIGP1ARBURST; + output [3:0] MAXIGP1ARCACHE; + output [15:0] MAXIGP1ARID; + output [7:0] MAXIGP1ARLEN; + output MAXIGP1ARLOCK; + output [2:0] MAXIGP1ARPROT; + output [3:0] MAXIGP1ARQOS; + output [2:0] MAXIGP1ARSIZE; + output [15:0] MAXIGP1ARUSER; + output MAXIGP1ARVALID; + output [39:0] MAXIGP1AWADDR; + output [1:0] MAXIGP1AWBURST; + output [3:0] MAXIGP1AWCACHE; + output [15:0] MAXIGP1AWID; + output [7:0] MAXIGP1AWLEN; + output MAXIGP1AWLOCK; + output [2:0] MAXIGP1AWPROT; + output [3:0] MAXIGP1AWQOS; + output [2:0] MAXIGP1AWSIZE; + output [15:0] MAXIGP1AWUSER; + output MAXIGP1AWVALID; + output MAXIGP1BREADY; + output MAXIGP1RREADY; + output [127:0] MAXIGP1WDATA; + output MAXIGP1WLAST; + output [15:0] MAXIGP1WSTRB; + output MAXIGP1WVALID; + output [39:0] MAXIGP2ARADDR; + output [1:0] MAXIGP2ARBURST; + output [3:0] MAXIGP2ARCACHE; + output [15:0] MAXIGP2ARID; + output [7:0] MAXIGP2ARLEN; + output MAXIGP2ARLOCK; + output [2:0] MAXIGP2ARPROT; + output [3:0] MAXIGP2ARQOS; + output [2:0] MAXIGP2ARSIZE; + output [15:0] MAXIGP2ARUSER; + output MAXIGP2ARVALID; + output [39:0] MAXIGP2AWADDR; + output [1:0] MAXIGP2AWBURST; + output [3:0] MAXIGP2AWCACHE; + output [15:0] MAXIGP2AWID; + output [7:0] MAXIGP2AWLEN; + output MAXIGP2AWLOCK; + output [2:0] MAXIGP2AWPROT; + output [3:0] MAXIGP2AWQOS; + output [2:0] MAXIGP2AWSIZE; + output [15:0] MAXIGP2AWUSER; + output MAXIGP2AWVALID; + output MAXIGP2BREADY; + output MAXIGP2RREADY; + output [127:0] MAXIGP2WDATA; + output MAXIGP2WLAST; + output [15:0] MAXIGP2WSTRB; + output MAXIGP2WVALID; + output OSCRTCCLK; + output [3:0] PLCLK; + output PMUAIBAFIFMFPDREQ; + output PMUAIBAFIFMLPDREQ; + output [46:0] PMUERRORTOPL; + output [31:0] PMUPLGPO; + output PSPLEVENTO; + output [63:0] PSPLIRQFPD; + output [99:0] PSPLIRQLPD; + output [3:0] PSPLSTANDBYWFE; + output [3:0] PSPLSTANDBYWFI; + output PSPLTRACECTL; + output [31:0] PSPLTRACEDATA; + output [3:0] PSPLTRIGACK; + output [3:0] PSPLTRIGGER; + output PSS_ALTO_CORE_PAD_MGTTXN0OUT; + output PSS_ALTO_CORE_PAD_MGTTXN1OUT; + output PSS_ALTO_CORE_PAD_MGTTXN2OUT; + output PSS_ALTO_CORE_PAD_MGTTXN3OUT; + output PSS_ALTO_CORE_PAD_MGTTXP0OUT; + output PSS_ALTO_CORE_PAD_MGTTXP1OUT; + output PSS_ALTO_CORE_PAD_MGTTXP2OUT; + output PSS_ALTO_CORE_PAD_MGTTXP3OUT; + output PSS_ALTO_CORE_PAD_PADO; + output RPUEVENTO0; + output RPUEVENTO1; + output [43:0] SACEFPDACADDR; + output [2:0] SACEFPDACPROT; + output [3:0] SACEFPDACSNOOP; + output SACEFPDACVALID; + output SACEFPDARREADY; + output SACEFPDAWREADY; + output [5:0] SACEFPDBID; + output [1:0] SACEFPDBRESP; + output SACEFPDBUSER; + output SACEFPDBVALID; + output SACEFPDCDREADY; + output SACEFPDCRREADY; + output [127:0] SACEFPDRDATA; + output [5:0] SACEFPDRID; + output SACEFPDRLAST; + output [3:0] SACEFPDRRESP; + output SACEFPDRUSER; + output SACEFPDRVALID; + output SACEFPDWREADY; + output SAXIACPARREADY; + output SAXIACPAWREADY; + output [4:0] SAXIACPBID; + output [1:0] SAXIACPBRESP; + output SAXIACPBVALID; + output [127:0] SAXIACPRDATA; + output [4:0] SAXIACPRID; + output SAXIACPRLAST; + output [1:0] SAXIACPRRESP; + output SAXIACPRVALID; + output SAXIACPWREADY; + output SAXIGP0ARREADY; + output SAXIGP0AWREADY; + output [5:0] SAXIGP0BID; + output [1:0] SAXIGP0BRESP; + output SAXIGP0BVALID; + output [3:0] SAXIGP0RACOUNT; + output [7:0] SAXIGP0RCOUNT; + output [127:0] SAXIGP0RDATA; + output [5:0] SAXIGP0RID; + output SAXIGP0RLAST; + output [1:0] SAXIGP0RRESP; + output SAXIGP0RVALID; + output [3:0] SAXIGP0WACOUNT; + output [7:0] SAXIGP0WCOUNT; + output SAXIGP0WREADY; + output SAXIGP1ARREADY; + output SAXIGP1AWREADY; + output [5:0] SAXIGP1BID; + output [1:0] SAXIGP1BRESP; + output SAXIGP1BVALID; + output [3:0] SAXIGP1RACOUNT; + output [7:0] SAXIGP1RCOUNT; + output [127:0] SAXIGP1RDATA; + output [5:0] SAXIGP1RID; + output SAXIGP1RLAST; + output [1:0] SAXIGP1RRESP; + output SAXIGP1RVALID; + output [3:0] SAXIGP1WACOUNT; + output [7:0] SAXIGP1WCOUNT; + output SAXIGP1WREADY; + output SAXIGP2ARREADY; + output SAXIGP2AWREADY; + output [5:0] SAXIGP2BID; + output [1:0] SAXIGP2BRESP; + output SAXIGP2BVALID; + output [3:0] SAXIGP2RACOUNT; + output [7:0] SAXIGP2RCOUNT; + output [127:0] SAXIGP2RDATA; + output [5:0] SAXIGP2RID; + output SAXIGP2RLAST; + output [1:0] SAXIGP2RRESP; + output SAXIGP2RVALID; + output [3:0] SAXIGP2WACOUNT; + output [7:0] SAXIGP2WCOUNT; + output SAXIGP2WREADY; + output SAXIGP3ARREADY; + output SAXIGP3AWREADY; + output [5:0] SAXIGP3BID; + output [1:0] SAXIGP3BRESP; + output SAXIGP3BVALID; + output [3:0] SAXIGP3RACOUNT; + output [7:0] SAXIGP3RCOUNT; + output [127:0] SAXIGP3RDATA; + output [5:0] SAXIGP3RID; + output SAXIGP3RLAST; + output [1:0] SAXIGP3RRESP; + output SAXIGP3RVALID; + output [3:0] SAXIGP3WACOUNT; + output [7:0] SAXIGP3WCOUNT; + output SAXIGP3WREADY; + output SAXIGP4ARREADY; + output SAXIGP4AWREADY; + output [5:0] SAXIGP4BID; + output [1:0] SAXIGP4BRESP; + output SAXIGP4BVALID; + output [3:0] SAXIGP4RACOUNT; + output [7:0] SAXIGP4RCOUNT; + output [127:0] SAXIGP4RDATA; + output [5:0] SAXIGP4RID; + output SAXIGP4RLAST; + output [1:0] SAXIGP4RRESP; + output SAXIGP4RVALID; + output [3:0] SAXIGP4WACOUNT; + output [7:0] SAXIGP4WCOUNT; + output SAXIGP4WREADY; + output SAXIGP5ARREADY; + output SAXIGP5AWREADY; + output [5:0] SAXIGP5BID; + output [1:0] SAXIGP5BRESP; + output SAXIGP5BVALID; + output [3:0] SAXIGP5RACOUNT; + output [7:0] SAXIGP5RCOUNT; + output [127:0] SAXIGP5RDATA; + output [5:0] SAXIGP5RID; + output SAXIGP5RLAST; + output [1:0] SAXIGP5RRESP; + output SAXIGP5RVALID; + output [3:0] SAXIGP5WACOUNT; + output [7:0] SAXIGP5WCOUNT; + output SAXIGP5WREADY; + output SAXIGP6ARREADY; + output SAXIGP6AWREADY; + output [5:0] SAXIGP6BID; + output [1:0] SAXIGP6BRESP; + output SAXIGP6BVALID; + output [3:0] SAXIGP6RACOUNT; + output [7:0] SAXIGP6RCOUNT; + output [127:0] SAXIGP6RDATA; + output [5:0] SAXIGP6RID; + output SAXIGP6RLAST; + output [1:0] SAXIGP6RRESP; + output SAXIGP6RVALID; + output [3:0] SAXIGP6WACOUNT; + output [7:0] SAXIGP6WCOUNT; + output SAXIGP6WREADY; + inout [3:0] PSS_ALTO_CORE_PAD_BOOTMODE; + inout PSS_ALTO_CORE_PAD_CLK; + inout PSS_ALTO_CORE_PAD_DONEB; + inout [17:0] PSS_ALTO_CORE_PAD_DRAMA; + inout PSS_ALTO_CORE_PAD_DRAMACTN; + inout PSS_ALTO_CORE_PAD_DRAMALERTN; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMBA; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMBG; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCK; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKE; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKN; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMCSN; + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDM; + inout [71:0] PSS_ALTO_CORE_PAD_DRAMDQ; + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQS; + inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQSN; + inout [1:0] PSS_ALTO_CORE_PAD_DRAMODT; + inout PSS_ALTO_CORE_PAD_DRAMPARITY; + inout PSS_ALTO_CORE_PAD_DRAMRAMRSTN; + inout PSS_ALTO_CORE_PAD_ERROROUT; + inout PSS_ALTO_CORE_PAD_ERRORSTATUS; + inout PSS_ALTO_CORE_PAD_INITB; + inout PSS_ALTO_CORE_PAD_JTAGTCK; + inout PSS_ALTO_CORE_PAD_JTAGTDI; + inout PSS_ALTO_CORE_PAD_JTAGTDO; + inout PSS_ALTO_CORE_PAD_JTAGTMS; + inout [77:0] PSS_ALTO_CORE_PAD_MIO; + inout PSS_ALTO_CORE_PAD_PORB; + inout PSS_ALTO_CORE_PAD_PROGB; + inout PSS_ALTO_CORE_PAD_RCALIBINOUT; + inout PSS_ALTO_CORE_PAD_SRSTB; + inout PSS_ALTO_CORE_PAD_ZQ; + input [7:0] ADMAFCICLK; + input AIBPMUAFIFMFPDACK; + input AIBPMUAFIFMLPDACK; + input DDRCEXTREFRESHRANK0REQ; + input DDRCEXTREFRESHRANK1REQ; + input DDRCREFRESHPLCLK; + input DPAUXDATAIN; + input DPEXTERNALCUSTOMEVENT1; + input DPEXTERNALCUSTOMEVENT2; + input DPEXTERNALVSYNCEVENT; + input DPHOTPLUGDETECT; + input [7:0] DPLIVEGFXALPHAIN; + input [35:0] DPLIVEGFXPIXEL1IN; + input DPLIVEVIDEOINDE; + input DPLIVEVIDEOINHSYNC; + input [35:0] DPLIVEVIDEOINPIXEL1; + input DPLIVEVIDEOINVSYNC; + input DPMAXISMIXEDAUDIOTREADY; + input DPSAXISAUDIOCLK; + input [31:0] DPSAXISAUDIOTDATA; + input DPSAXISAUDIOTID; + input DPSAXISAUDIOTVALID; + input DPVIDEOINCLK; + input EMIOCAN0PHYRX; + input EMIOCAN1PHYRX; + input EMIOENET0DMATXSTATUSTOG; + input EMIOENET0EXTINTIN; + input EMIOENET0GMIICOL; + input EMIOENET0GMIICRS; + input EMIOENET0GMIIRXCLK; + input [7:0] EMIOENET0GMIIRXD; + input EMIOENET0GMIIRXDV; + input EMIOENET0GMIIRXER; + input EMIOENET0GMIITXCLK; + input EMIOENET0MDIOI; + input EMIOENET0RXWOVERFLOW; + input EMIOENET0TXRCONTROL; + input [7:0] EMIOENET0TXRDATA; + input EMIOENET0TXRDATARDY; + input EMIOENET0TXREOP; + input EMIOENET0TXRERR; + input EMIOENET0TXRFLUSHED; + input EMIOENET0TXRSOP; + input EMIOENET0TXRUNDERFLOW; + input EMIOENET0TXRVALID; + input EMIOENET1DMATXSTATUSTOG; + input EMIOENET1EXTINTIN; + input EMIOENET1GMIICOL; + input EMIOENET1GMIICRS; + input EMIOENET1GMIIRXCLK; + input [7:0] EMIOENET1GMIIRXD; + input EMIOENET1GMIIRXDV; + input EMIOENET1GMIIRXER; + input EMIOENET1GMIITXCLK; + input EMIOENET1MDIOI; + input EMIOENET1RXWOVERFLOW; + input EMIOENET1TXRCONTROL; + input [7:0] EMIOENET1TXRDATA; + input EMIOENET1TXRDATARDY; + input EMIOENET1TXREOP; + input EMIOENET1TXRERR; + input EMIOENET1TXRFLUSHED; + input EMIOENET1TXRSOP; + input EMIOENET1TXRUNDERFLOW; + input EMIOENET1TXRVALID; + input EMIOENET2DMATXSTATUSTOG; + input EMIOENET2EXTINTIN; + input EMIOENET2GMIICOL; + input EMIOENET2GMIICRS; + input EMIOENET2GMIIRXCLK; + input [7:0] EMIOENET2GMIIRXD; + input EMIOENET2GMIIRXDV; + input EMIOENET2GMIIRXER; + input EMIOENET2GMIITXCLK; + input EMIOENET2MDIOI; + input EMIOENET2RXWOVERFLOW; + input EMIOENET2TXRCONTROL; + input [7:0] EMIOENET2TXRDATA; + input EMIOENET2TXRDATARDY; + input EMIOENET2TXREOP; + input EMIOENET2TXRERR; + input EMIOENET2TXRFLUSHED; + input EMIOENET2TXRSOP; + input EMIOENET2TXRUNDERFLOW; + input EMIOENET2TXRVALID; + input EMIOENET3DMATXSTATUSTOG; + input EMIOENET3EXTINTIN; + input EMIOENET3GMIICOL; + input EMIOENET3GMIICRS; + input EMIOENET3GMIIRXCLK; + input [7:0] EMIOENET3GMIIRXD; + input EMIOENET3GMIIRXDV; + input EMIOENET3GMIIRXER; + input EMIOENET3GMIITXCLK; + input EMIOENET3MDIOI; + input EMIOENET3RXWOVERFLOW; + input EMIOENET3TXRCONTROL; + input [7:0] EMIOENET3TXRDATA; + input EMIOENET3TXRDATARDY; + input EMIOENET3TXREOP; + input EMIOENET3TXRERR; + input EMIOENET3TXRFLUSHED; + input EMIOENET3TXRSOP; + input EMIOENET3TXRUNDERFLOW; + input EMIOENET3TXRVALID; + input EMIOENETTSUCLK; + input [1:0] EMIOGEM0TSUINCCTRL; + input [1:0] EMIOGEM1TSUINCCTRL; + input [1:0] EMIOGEM2TSUINCCTRL; + input [1:0] EMIOGEM3TSUINCCTRL; + input [95:0] EMIOGPIOI; + input EMIOHUBPORTOVERCRNTUSB20; + input EMIOHUBPORTOVERCRNTUSB21; + input EMIOHUBPORTOVERCRNTUSB30; + input EMIOHUBPORTOVERCRNTUSB31; + input EMIOI2C0SCLI; + input EMIOI2C0SDAI; + input EMIOI2C1SCLI; + input EMIOI2C1SDAI; + input EMIOSDIO0CDN; + input EMIOSDIO0CMDIN; + input [7:0] EMIOSDIO0DATAIN; + input EMIOSDIO0FBCLKIN; + input EMIOSDIO0WP; + input EMIOSDIO1CDN; + input EMIOSDIO1CMDIN; + input [7:0] EMIOSDIO1DATAIN; + input EMIOSDIO1FBCLKIN; + input EMIOSDIO1WP; + input EMIOSPI0MI; + input EMIOSPI0SCLKI; + input EMIOSPI0SI; + input EMIOSPI0SSIN; + input EMIOSPI1MI; + input EMIOSPI1SCLKI; + input EMIOSPI1SI; + input EMIOSPI1SSIN; + input [2:0] EMIOTTC0CLKI; + input [2:0] EMIOTTC1CLKI; + input [2:0] EMIOTTC2CLKI; + input [2:0] EMIOTTC3CLKI; + input EMIOUART0CTSN; + input EMIOUART0DCDN; + input EMIOUART0DSRN; + input EMIOUART0RIN; + input EMIOUART0RX; + input EMIOUART1CTSN; + input EMIOUART1DCDN; + input EMIOUART1DSRN; + input EMIOUART1RIN; + input EMIOUART1RX; + input EMIOWDT0CLKI; + input EMIOWDT1CLKI; + input FMIOGEM0FIFORXCLKFROMPL; + input FMIOGEM0FIFOTXCLKFROMPL; + input FMIOGEM0SIGNALDETECT; + input FMIOGEM1FIFORXCLKFROMPL; + input FMIOGEM1FIFOTXCLKFROMPL; + input FMIOGEM1SIGNALDETECT; + input FMIOGEM2FIFORXCLKFROMPL; + input FMIOGEM2FIFOTXCLKFROMPL; + input FMIOGEM2SIGNALDETECT; + input FMIOGEM3FIFORXCLKFROMPL; + input FMIOGEM3FIFOTXCLKFROMPL; + input FMIOGEM3SIGNALDETECT; + input FMIOGEMTSUCLKFROMPL; + input [31:0] FTMGPI; + input [7:0] GDMAFCICLK; + input MAXIGP0ACLK; + input MAXIGP0ARREADY; + input MAXIGP0AWREADY; + input [15:0] MAXIGP0BID; + input [1:0] MAXIGP0BRESP; + input MAXIGP0BVALID; + input [127:0] MAXIGP0RDATA; + input [15:0] MAXIGP0RID; + input MAXIGP0RLAST; + input [1:0] MAXIGP0RRESP; + input MAXIGP0RVALID; + input MAXIGP0WREADY; + input MAXIGP1ACLK; + input MAXIGP1ARREADY; + input MAXIGP1AWREADY; + input [15:0] MAXIGP1BID; + input [1:0] MAXIGP1BRESP; + input MAXIGP1BVALID; + input [127:0] MAXIGP1RDATA; + input [15:0] MAXIGP1RID; + input MAXIGP1RLAST; + input [1:0] MAXIGP1RRESP; + input MAXIGP1RVALID; + input MAXIGP1WREADY; + input MAXIGP2ACLK; + input MAXIGP2ARREADY; + input MAXIGP2AWREADY; + input [15:0] MAXIGP2BID; + input [1:0] MAXIGP2BRESP; + input MAXIGP2BVALID; + input [127:0] MAXIGP2RDATA; + input [15:0] MAXIGP2RID; + input MAXIGP2RLAST; + input [1:0] MAXIGP2RRESP; + input MAXIGP2RVALID; + input MAXIGP2WREADY; + input NFIQ0LPDRPU; + input NFIQ1LPDRPU; + input NIRQ0LPDRPU; + input NIRQ1LPDRPU; + input [7:0] PL2ADMACVLD; + input [7:0] PL2ADMATACK; + input [7:0] PL2GDMACVLD; + input [7:0] PL2GDMATACK; + input PLACECLK; + input PLACPINACT; + input [3:0] PLFPGASTOP; + input [2:0] PLLAUXREFCLKFPD; + input [1:0] PLLAUXREFCLKLPD; + input [31:0] PLPMUGPI; + input [3:0] PLPSAPUGICFIQ; + input [3:0] PLPSAPUGICIRQ; + input PLPSEVENTI; + input [7:0] PLPSIRQ0; + input [7:0] PLPSIRQ1; + input PLPSTRACECLK; + input [3:0] PLPSTRIGACK; + input [3:0] PLPSTRIGGER; + input [3:0] PMUERRORFROMPL; + input PSS_ALTO_CORE_PAD_MGTRXN0IN; + input PSS_ALTO_CORE_PAD_MGTRXN1IN; + input PSS_ALTO_CORE_PAD_MGTRXN2IN; + input PSS_ALTO_CORE_PAD_MGTRXN3IN; + input PSS_ALTO_CORE_PAD_MGTRXP0IN; + input PSS_ALTO_CORE_PAD_MGTRXP1IN; + input PSS_ALTO_CORE_PAD_MGTRXP2IN; + input PSS_ALTO_CORE_PAD_MGTRXP3IN; + input PSS_ALTO_CORE_PAD_PADI; + input PSS_ALTO_CORE_PAD_REFN0IN; + input PSS_ALTO_CORE_PAD_REFN1IN; + input PSS_ALTO_CORE_PAD_REFN2IN; + input PSS_ALTO_CORE_PAD_REFN3IN; + input PSS_ALTO_CORE_PAD_REFP0IN; + input PSS_ALTO_CORE_PAD_REFP1IN; + input PSS_ALTO_CORE_PAD_REFP2IN; + input PSS_ALTO_CORE_PAD_REFP3IN; + input RPUEVENTI0; + input RPUEVENTI1; + input SACEFPDACREADY; + input [43:0] SACEFPDARADDR; + input [1:0] SACEFPDARBAR; + input [1:0] SACEFPDARBURST; + input [3:0] SACEFPDARCACHE; + input [1:0] SACEFPDARDOMAIN; + input [5:0] SACEFPDARID; + input [7:0] SACEFPDARLEN; + input SACEFPDARLOCK; + input [2:0] SACEFPDARPROT; + input [3:0] SACEFPDARQOS; + input [3:0] SACEFPDARREGION; + input [2:0] SACEFPDARSIZE; + input [3:0] SACEFPDARSNOOP; + input [15:0] SACEFPDARUSER; + input SACEFPDARVALID; + input [43:0] SACEFPDAWADDR; + input [1:0] SACEFPDAWBAR; + input [1:0] SACEFPDAWBURST; + input [3:0] SACEFPDAWCACHE; + input [1:0] SACEFPDAWDOMAIN; + input [5:0] SACEFPDAWID; + input [7:0] SACEFPDAWLEN; + input SACEFPDAWLOCK; + input [2:0] SACEFPDAWPROT; + input [3:0] SACEFPDAWQOS; + input [3:0] SACEFPDAWREGION; + input [2:0] SACEFPDAWSIZE; + input [2:0] SACEFPDAWSNOOP; + input [15:0] SACEFPDAWUSER; + input SACEFPDAWVALID; + input SACEFPDBREADY; + input [127:0] SACEFPDCDDATA; + input SACEFPDCDLAST; + input SACEFPDCDVALID; + input [4:0] SACEFPDCRRESP; + input SACEFPDCRVALID; + input SACEFPDRACK; + input SACEFPDRREADY; + input SACEFPDWACK; + input [127:0] SACEFPDWDATA; + input SACEFPDWLAST; + input [15:0] SACEFPDWSTRB; + input SACEFPDWUSER; + input SACEFPDWVALID; + input SAXIACPACLK; + input [39:0] SAXIACPARADDR; + input [1:0] SAXIACPARBURST; + input [3:0] SAXIACPARCACHE; + input [4:0] SAXIACPARID; + input [7:0] SAXIACPARLEN; + input SAXIACPARLOCK; + input [2:0] SAXIACPARPROT; + input [3:0] SAXIACPARQOS; + input [2:0] SAXIACPARSIZE; + input [1:0] SAXIACPARUSER; + input SAXIACPARVALID; + input [39:0] SAXIACPAWADDR; + input [1:0] SAXIACPAWBURST; + input [3:0] SAXIACPAWCACHE; + input [4:0] SAXIACPAWID; + input [7:0] SAXIACPAWLEN; + input SAXIACPAWLOCK; + input [2:0] SAXIACPAWPROT; + input [3:0] SAXIACPAWQOS; + input [2:0] SAXIACPAWSIZE; + input [1:0] SAXIACPAWUSER; + input SAXIACPAWVALID; + input SAXIACPBREADY; + input SAXIACPRREADY; + input [127:0] SAXIACPWDATA; + input SAXIACPWLAST; + input [15:0] SAXIACPWSTRB; + input SAXIACPWVALID; + input [48:0] SAXIGP0ARADDR; + input [1:0] SAXIGP0ARBURST; + input [3:0] SAXIGP0ARCACHE; + input [5:0] SAXIGP0ARID; + input [7:0] SAXIGP0ARLEN; + input SAXIGP0ARLOCK; + input [2:0] SAXIGP0ARPROT; + input [3:0] SAXIGP0ARQOS; + input [2:0] SAXIGP0ARSIZE; + input SAXIGP0ARUSER; + input SAXIGP0ARVALID; + input [48:0] SAXIGP0AWADDR; + input [1:0] SAXIGP0AWBURST; + input [3:0] SAXIGP0AWCACHE; + input [5:0] SAXIGP0AWID; + input [7:0] SAXIGP0AWLEN; + input SAXIGP0AWLOCK; + input [2:0] SAXIGP0AWPROT; + input [3:0] SAXIGP0AWQOS; + input [2:0] SAXIGP0AWSIZE; + input SAXIGP0AWUSER; + input SAXIGP0AWVALID; + input SAXIGP0BREADY; + input SAXIGP0RCLK; + input SAXIGP0RREADY; + input SAXIGP0WCLK; + input [127:0] SAXIGP0WDATA; + input SAXIGP0WLAST; + input [15:0] SAXIGP0WSTRB; + input SAXIGP0WVALID; + input [48:0] SAXIGP1ARADDR; + input [1:0] SAXIGP1ARBURST; + input [3:0] SAXIGP1ARCACHE; + input [5:0] SAXIGP1ARID; + input [7:0] SAXIGP1ARLEN; + input SAXIGP1ARLOCK; + input [2:0] SAXIGP1ARPROT; + input [3:0] SAXIGP1ARQOS; + input [2:0] SAXIGP1ARSIZE; + input SAXIGP1ARUSER; + input SAXIGP1ARVALID; + input [48:0] SAXIGP1AWADDR; + input [1:0] SAXIGP1AWBURST; + input [3:0] SAXIGP1AWCACHE; + input [5:0] SAXIGP1AWID; + input [7:0] SAXIGP1AWLEN; + input SAXIGP1AWLOCK; + input [2:0] SAXIGP1AWPROT; + input [3:0] SAXIGP1AWQOS; + input [2:0] SAXIGP1AWSIZE; + input SAXIGP1AWUSER; + input SAXIGP1AWVALID; + input SAXIGP1BREADY; + input SAXIGP1RCLK; + input SAXIGP1RREADY; + input SAXIGP1WCLK; + input [127:0] SAXIGP1WDATA; + input SAXIGP1WLAST; + input [15:0] SAXIGP1WSTRB; + input SAXIGP1WVALID; + input [48:0] SAXIGP2ARADDR; + input [1:0] SAXIGP2ARBURST; + input [3:0] SAXIGP2ARCACHE; + input [5:0] SAXIGP2ARID; + input [7:0] SAXIGP2ARLEN; + input SAXIGP2ARLOCK; + input [2:0] SAXIGP2ARPROT; + input [3:0] SAXIGP2ARQOS; + input [2:0] SAXIGP2ARSIZE; + input SAXIGP2ARUSER; + input SAXIGP2ARVALID; + input [48:0] SAXIGP2AWADDR; + input [1:0] SAXIGP2AWBURST; + input [3:0] SAXIGP2AWCACHE; + input [5:0] SAXIGP2AWID; + input [7:0] SAXIGP2AWLEN; + input SAXIGP2AWLOCK; + input [2:0] SAXIGP2AWPROT; + input [3:0] SAXIGP2AWQOS; + input [2:0] SAXIGP2AWSIZE; + input SAXIGP2AWUSER; + input SAXIGP2AWVALID; + input SAXIGP2BREADY; + input SAXIGP2RCLK; + input SAXIGP2RREADY; + input SAXIGP2WCLK; + input [127:0] SAXIGP2WDATA; + input SAXIGP2WLAST; + input [15:0] SAXIGP2WSTRB; + input SAXIGP2WVALID; + input [48:0] SAXIGP3ARADDR; + input [1:0] SAXIGP3ARBURST; + input [3:0] SAXIGP3ARCACHE; + input [5:0] SAXIGP3ARID; + input [7:0] SAXIGP3ARLEN; + input SAXIGP3ARLOCK; + input [2:0] SAXIGP3ARPROT; + input [3:0] SAXIGP3ARQOS; + input [2:0] SAXIGP3ARSIZE; + input SAXIGP3ARUSER; + input SAXIGP3ARVALID; + input [48:0] SAXIGP3AWADDR; + input [1:0] SAXIGP3AWBURST; + input [3:0] SAXIGP3AWCACHE; + input [5:0] SAXIGP3AWID; + input [7:0] SAXIGP3AWLEN; + input SAXIGP3AWLOCK; + input [2:0] SAXIGP3AWPROT; + input [3:0] SAXIGP3AWQOS; + input [2:0] SAXIGP3AWSIZE; + input SAXIGP3AWUSER; + input SAXIGP3AWVALID; + input SAXIGP3BREADY; + input SAXIGP3RCLK; + input SAXIGP3RREADY; + input SAXIGP3WCLK; + input [127:0] SAXIGP3WDATA; + input SAXIGP3WLAST; + input [15:0] SAXIGP3WSTRB; + input SAXIGP3WVALID; + input [48:0] SAXIGP4ARADDR; + input [1:0] SAXIGP4ARBURST; + input [3:0] SAXIGP4ARCACHE; + input [5:0] SAXIGP4ARID; + input [7:0] SAXIGP4ARLEN; + input SAXIGP4ARLOCK; + input [2:0] SAXIGP4ARPROT; + input [3:0] SAXIGP4ARQOS; + input [2:0] SAXIGP4ARSIZE; + input SAXIGP4ARUSER; + input SAXIGP4ARVALID; + input [48:0] SAXIGP4AWADDR; + input [1:0] SAXIGP4AWBURST; + input [3:0] SAXIGP4AWCACHE; + input [5:0] SAXIGP4AWID; + input [7:0] SAXIGP4AWLEN; + input SAXIGP4AWLOCK; + input [2:0] SAXIGP4AWPROT; + input [3:0] SAXIGP4AWQOS; + input [2:0] SAXIGP4AWSIZE; + input SAXIGP4AWUSER; + input SAXIGP4AWVALID; + input SAXIGP4BREADY; + input SAXIGP4RCLK; + input SAXIGP4RREADY; + input SAXIGP4WCLK; + input [127:0] SAXIGP4WDATA; + input SAXIGP4WLAST; + input [15:0] SAXIGP4WSTRB; + input SAXIGP4WVALID; + input [48:0] SAXIGP5ARADDR; + input [1:0] SAXIGP5ARBURST; + input [3:0] SAXIGP5ARCACHE; + input [5:0] SAXIGP5ARID; + input [7:0] SAXIGP5ARLEN; + input SAXIGP5ARLOCK; + input [2:0] SAXIGP5ARPROT; + input [3:0] SAXIGP5ARQOS; + input [2:0] SAXIGP5ARSIZE; + input SAXIGP5ARUSER; + input SAXIGP5ARVALID; + input [48:0] SAXIGP5AWADDR; + input [1:0] SAXIGP5AWBURST; + input [3:0] SAXIGP5AWCACHE; + input [5:0] SAXIGP5AWID; + input [7:0] SAXIGP5AWLEN; + input SAXIGP5AWLOCK; + input [2:0] SAXIGP5AWPROT; + input [3:0] SAXIGP5AWQOS; + input [2:0] SAXIGP5AWSIZE; + input SAXIGP5AWUSER; + input SAXIGP5AWVALID; + input SAXIGP5BREADY; + input SAXIGP5RCLK; + input SAXIGP5RREADY; + input SAXIGP5WCLK; + input [127:0] SAXIGP5WDATA; + input SAXIGP5WLAST; + input [15:0] SAXIGP5WSTRB; + input SAXIGP5WVALID; + input [48:0] SAXIGP6ARADDR; + input [1:0] SAXIGP6ARBURST; + input [3:0] SAXIGP6ARCACHE; + input [5:0] SAXIGP6ARID; + input [7:0] SAXIGP6ARLEN; + input SAXIGP6ARLOCK; + input [2:0] SAXIGP6ARPROT; + input [3:0] SAXIGP6ARQOS; + input [2:0] SAXIGP6ARSIZE; + input SAXIGP6ARUSER; + input SAXIGP6ARVALID; + input [48:0] SAXIGP6AWADDR; + input [1:0] SAXIGP6AWBURST; + input [3:0] SAXIGP6AWCACHE; + input [5:0] SAXIGP6AWID; + input [7:0] SAXIGP6AWLEN; + input SAXIGP6AWLOCK; + input [2:0] SAXIGP6AWPROT; + input [3:0] SAXIGP6AWQOS; + input [2:0] SAXIGP6AWSIZE; + input SAXIGP6AWUSER; + input SAXIGP6AWVALID; + input SAXIGP6BREADY; + input SAXIGP6RCLK; + input SAXIGP6RREADY; + input SAXIGP6WCLK; + input [127:0] SAXIGP6WDATA; + input SAXIGP6WLAST; + input [15:0] SAXIGP6WSTRB; + input SAXIGP6WVALID; + input [59:0] STMEVENT; +endmodule + +module ILKN (...); + parameter BYPASS = "FALSE"; + parameter [1:0] CTL_RX_BURSTMAX = 2'h3; + parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; + parameter [3:0] CTL_RX_LAST_LANE = 4'hB; + parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF; + parameter CTL_RX_PACKET_MODE = "TRUE"; + parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0; + parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2; + parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0000; + parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0008; + parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000; + parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00; + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; + parameter [1:0] CTL_TX_BURSTMAX = 2'h3; + parameter [2:0] CTL_TX_BURSTSHORT = 3'h1; + parameter [1:0] CTL_TX_CHAN_EXT = 2'h0; + parameter CTL_TX_DISABLE_SKIPWORD = "TRUE"; + parameter [6:0] CTL_TX_FC_CALLEN = 7'h00; + parameter [3:0] CTL_TX_LAST_LANE = 4'hB; + parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF; + parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800; + parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0; + parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3; + parameter MODE = "TRUE"; + parameter SIM_VERSION = "2.0"; + parameter TEST_MODE_PIN_CHAR = "FALSE"; + output [15:0] DRP_DO; + output DRP_RDY; + output [65:0] RX_BYPASS_DATAOUT00; + output [65:0] RX_BYPASS_DATAOUT01; + output [65:0] RX_BYPASS_DATAOUT02; + output [65:0] RX_BYPASS_DATAOUT03; + output [65:0] RX_BYPASS_DATAOUT04; + output [65:0] RX_BYPASS_DATAOUT05; + output [65:0] RX_BYPASS_DATAOUT06; + output [65:0] RX_BYPASS_DATAOUT07; + output [65:0] RX_BYPASS_DATAOUT08; + output [65:0] RX_BYPASS_DATAOUT09; + output [65:0] RX_BYPASS_DATAOUT10; + output [65:0] RX_BYPASS_DATAOUT11; + output [11:0] RX_BYPASS_ENAOUT; + output [11:0] RX_BYPASS_IS_AVAILOUT; + output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT; + output [11:0] RX_BYPASS_IS_OVERFLOWOUT; + output [11:0] RX_BYPASS_IS_SYNCEDOUT; + output [11:0] RX_BYPASS_IS_SYNCWORDOUT; + output [10:0] RX_CHANOUT0; + output [10:0] RX_CHANOUT1; + output [10:0] RX_CHANOUT2; + output [10:0] RX_CHANOUT3; + output [127:0] RX_DATAOUT0; + output [127:0] RX_DATAOUT1; + output [127:0] RX_DATAOUT2; + output [127:0] RX_DATAOUT3; + output RX_ENAOUT0; + output RX_ENAOUT1; + output RX_ENAOUT2; + output RX_ENAOUT3; + output RX_EOPOUT0; + output RX_EOPOUT1; + output RX_EOPOUT2; + output RX_EOPOUT3; + output RX_ERROUT0; + output RX_ERROUT1; + output RX_ERROUT2; + output RX_ERROUT3; + output [3:0] RX_MTYOUT0; + output [3:0] RX_MTYOUT1; + output [3:0] RX_MTYOUT2; + output [3:0] RX_MTYOUT3; + output RX_OVFOUT; + output RX_SOPOUT0; + output RX_SOPOUT1; + output RX_SOPOUT2; + output RX_SOPOUT3; + output STAT_RX_ALIGNED; + output STAT_RX_ALIGNED_ERR; + output [11:0] STAT_RX_BAD_TYPE_ERR; + output STAT_RX_BURSTMAX_ERR; + output STAT_RX_BURST_ERR; + output STAT_RX_CRC24_ERR; + output [11:0] STAT_RX_CRC32_ERR; + output [11:0] STAT_RX_CRC32_VALID; + output [11:0] STAT_RX_DESCRAM_ERR; + output [11:0] STAT_RX_DIAGWORD_INTFSTAT; + output [11:0] STAT_RX_DIAGWORD_LANESTAT; + output [255:0] STAT_RX_FC_STAT; + output [11:0] STAT_RX_FRAMING_ERR; + output STAT_RX_MEOP_ERR; + output [11:0] STAT_RX_MF_ERR; + output [11:0] STAT_RX_MF_LEN_ERR; + output [11:0] STAT_RX_MF_REPEAT_ERR; + output STAT_RX_MISALIGNED; + output STAT_RX_MSOP_ERR; + output [7:0] STAT_RX_MUBITS; + output STAT_RX_MUBITS_UPDATED; + output STAT_RX_OVERFLOW_ERR; + output STAT_RX_RETRANS_CRC24_ERR; + output STAT_RX_RETRANS_DISC; + output [15:0] STAT_RX_RETRANS_LATENCY; + output STAT_RX_RETRANS_REQ; + output STAT_RX_RETRANS_RETRY_ERR; + output [7:0] STAT_RX_RETRANS_SEQ; + output STAT_RX_RETRANS_SEQ_UPDATED; + output [2:0] STAT_RX_RETRANS_STATE; + output [4:0] STAT_RX_RETRANS_SUBSEQ; + output STAT_RX_RETRANS_WDOG_ERR; + output STAT_RX_RETRANS_WRAP_ERR; + output [11:0] STAT_RX_SYNCED; + output [11:0] STAT_RX_SYNCED_ERR; + output [11:0] STAT_RX_WORD_SYNC; + output STAT_TX_BURST_ERR; + output STAT_TX_ERRINJ_BITERR_DONE; + output STAT_TX_OVERFLOW_ERR; + output STAT_TX_RETRANS_BURST_ERR; + output STAT_TX_RETRANS_BUSY; + output STAT_TX_RETRANS_RAM_PERROUT; + output [8:0] STAT_TX_RETRANS_RAM_RADDR; + output STAT_TX_RETRANS_RAM_RD_B0; + output STAT_TX_RETRANS_RAM_RD_B1; + output STAT_TX_RETRANS_RAM_RD_B2; + output STAT_TX_RETRANS_RAM_RD_B3; + output [1:0] STAT_TX_RETRANS_RAM_RSEL; + output [8:0] STAT_TX_RETRANS_RAM_WADDR; + output [643:0] STAT_TX_RETRANS_RAM_WDATA; + output STAT_TX_RETRANS_RAM_WE_B0; + output STAT_TX_RETRANS_RAM_WE_B1; + output STAT_TX_RETRANS_RAM_WE_B2; + output STAT_TX_RETRANS_RAM_WE_B3; + output STAT_TX_UNDERFLOW_ERR; + output TX_OVFOUT; + output TX_RDYOUT; + output [63:0] TX_SERDES_DATA00; + output [63:0] TX_SERDES_DATA01; + output [63:0] TX_SERDES_DATA02; + output [63:0] TX_SERDES_DATA03; + output [63:0] TX_SERDES_DATA04; + output [63:0] TX_SERDES_DATA05; + output [63:0] TX_SERDES_DATA06; + output [63:0] TX_SERDES_DATA07; + output [63:0] TX_SERDES_DATA08; + output [63:0] TX_SERDES_DATA09; + output [63:0] TX_SERDES_DATA10; + output [63:0] TX_SERDES_DATA11; + input CORE_CLK; + input CTL_RX_FORCE_RESYNC; + input CTL_RX_RETRANS_ACK; + input CTL_RX_RETRANS_ENABLE; + input CTL_RX_RETRANS_ERRIN; + input CTL_RX_RETRANS_FORCE_REQ; + input CTL_RX_RETRANS_RESET; + input CTL_RX_RETRANS_RESET_MODE; + input CTL_TX_DIAGWORD_INTFSTAT; + input [11:0] CTL_TX_DIAGWORD_LANESTAT; + input CTL_TX_ENABLE; + input CTL_TX_ERRINJ_BITERR_GO; + input [3:0] CTL_TX_ERRINJ_BITERR_LANE; + input [255:0] CTL_TX_FC_STAT; + input [7:0] CTL_TX_MUBITS; + input CTL_TX_RETRANS_ENABLE; + input CTL_TX_RETRANS_RAM_PERRIN; + input [643:0] CTL_TX_RETRANS_RAM_RDATA; + input CTL_TX_RETRANS_REQ; + input CTL_TX_RETRANS_REQ_VALID; + input [11:0] CTL_TX_RLIM_DELTA; + input CTL_TX_RLIM_ENABLE; + input [7:0] CTL_TX_RLIM_INTV; + input [11:0] CTL_TX_RLIM_MAX; + input [9:0] DRP_ADDR; + input DRP_CLK; + input [15:0] DRP_DI; + input DRP_EN; + input DRP_WE; + input LBUS_CLK; + input RX_BYPASS_FORCE_REALIGNIN; + input RX_BYPASS_RDIN; + input RX_RESET; + input [11:0] RX_SERDES_CLK; + input [63:0] RX_SERDES_DATA00; + input [63:0] RX_SERDES_DATA01; + input [63:0] RX_SERDES_DATA02; + input [63:0] RX_SERDES_DATA03; + input [63:0] RX_SERDES_DATA04; + input [63:0] RX_SERDES_DATA05; + input [63:0] RX_SERDES_DATA06; + input [63:0] RX_SERDES_DATA07; + input [63:0] RX_SERDES_DATA08; + input [63:0] RX_SERDES_DATA09; + input [63:0] RX_SERDES_DATA10; + input [63:0] RX_SERDES_DATA11; + input [11:0] RX_SERDES_RESET; + input TX_BCTLIN0; + input TX_BCTLIN1; + input TX_BCTLIN2; + input TX_BCTLIN3; + input [11:0] TX_BYPASS_CTRLIN; + input [63:0] TX_BYPASS_DATAIN00; + input [63:0] TX_BYPASS_DATAIN01; + input [63:0] TX_BYPASS_DATAIN02; + input [63:0] TX_BYPASS_DATAIN03; + input [63:0] TX_BYPASS_DATAIN04; + input [63:0] TX_BYPASS_DATAIN05; + input [63:0] TX_BYPASS_DATAIN06; + input [63:0] TX_BYPASS_DATAIN07; + input [63:0] TX_BYPASS_DATAIN08; + input [63:0] TX_BYPASS_DATAIN09; + input [63:0] TX_BYPASS_DATAIN10; + input [63:0] TX_BYPASS_DATAIN11; + input TX_BYPASS_ENAIN; + input [7:0] TX_BYPASS_GEARBOX_SEQIN; + input [3:0] TX_BYPASS_MFRAMER_STATEIN; + input [10:0] TX_CHANIN0; + input [10:0] TX_CHANIN1; + input [10:0] TX_CHANIN2; + input [10:0] TX_CHANIN3; + input [127:0] TX_DATAIN0; + input [127:0] TX_DATAIN1; + input [127:0] TX_DATAIN2; + input [127:0] TX_DATAIN3; + input TX_ENAIN0; + input TX_ENAIN1; + input TX_ENAIN2; + input TX_ENAIN3; + input TX_EOPIN0; + input TX_EOPIN1; + input TX_EOPIN2; + input TX_EOPIN3; + input TX_ERRIN0; + input TX_ERRIN1; + input TX_ERRIN2; + input TX_ERRIN3; + input [3:0] TX_MTYIN0; + input [3:0] TX_MTYIN1; + input [3:0] TX_MTYIN2; + input [3:0] TX_MTYIN3; + input TX_RESET; + input TX_SERDES_REFCLK; + input TX_SERDES_REFCLK_RESET; + input TX_SOPIN0; + input TX_SOPIN1; + input TX_SOPIN2; + input TX_SOPIN3; +endmodule + +module ILKNE4 (...); + parameter BYPASS = "FALSE"; + parameter [1:0] CTL_RX_BURSTMAX = 2'h3; + parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; + parameter [3:0] CTL_RX_LAST_LANE = 4'hB; + parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF; + parameter CTL_RX_PACKET_MODE = "FALSE"; + parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0; + parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2; + parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0009; + parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0000; + parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000; + parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00; + parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; + parameter [1:0] CTL_TX_BURSTMAX = 2'h3; + parameter [2:0] CTL_TX_BURSTSHORT = 3'h1; + parameter [1:0] CTL_TX_CHAN_EXT = 2'h0; + parameter CTL_TX_DISABLE_SKIPWORD = "FALSE"; + parameter [3:0] CTL_TX_FC_CALLEN = 4'hF; + parameter [3:0] CTL_TX_LAST_LANE = 4'hB; + parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF; + parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800; + parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0; + parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3; + parameter MODE = "TRUE"; + parameter SIM_DEVICE = "ULTRASCALE_PLUS"; + parameter TEST_MODE_PIN_CHAR = "FALSE"; + output [15:0] DRP_DO; + output DRP_RDY; + output [65:0] RX_BYPASS_DATAOUT00; + output [65:0] RX_BYPASS_DATAOUT01; + output [65:0] RX_BYPASS_DATAOUT02; + output [65:0] RX_BYPASS_DATAOUT03; + output [65:0] RX_BYPASS_DATAOUT04; + output [65:0] RX_BYPASS_DATAOUT05; + output [65:0] RX_BYPASS_DATAOUT06; + output [65:0] RX_BYPASS_DATAOUT07; + output [65:0] RX_BYPASS_DATAOUT08; + output [65:0] RX_BYPASS_DATAOUT09; + output [65:0] RX_BYPASS_DATAOUT10; + output [65:0] RX_BYPASS_DATAOUT11; + output [11:0] RX_BYPASS_ENAOUT; + output [11:0] RX_BYPASS_IS_AVAILOUT; + output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT; + output [11:0] RX_BYPASS_IS_OVERFLOWOUT; + output [11:0] RX_BYPASS_IS_SYNCEDOUT; + output [11:0] RX_BYPASS_IS_SYNCWORDOUT; + output [10:0] RX_CHANOUT0; + output [10:0] RX_CHANOUT1; + output [10:0] RX_CHANOUT2; + output [10:0] RX_CHANOUT3; + output [127:0] RX_DATAOUT0; + output [127:0] RX_DATAOUT1; + output [127:0] RX_DATAOUT2; + output [127:0] RX_DATAOUT3; + output RX_ENAOUT0; + output RX_ENAOUT1; + output RX_ENAOUT2; + output RX_ENAOUT3; + output RX_EOPOUT0; + output RX_EOPOUT1; + output RX_EOPOUT2; + output RX_EOPOUT3; + output RX_ERROUT0; + output RX_ERROUT1; + output RX_ERROUT2; + output RX_ERROUT3; + output [3:0] RX_MTYOUT0; + output [3:0] RX_MTYOUT1; + output [3:0] RX_MTYOUT2; + output [3:0] RX_MTYOUT3; + output RX_OVFOUT; + output RX_SOPOUT0; + output RX_SOPOUT1; + output RX_SOPOUT2; + output RX_SOPOUT3; + output STAT_RX_ALIGNED; + output STAT_RX_ALIGNED_ERR; + output [11:0] STAT_RX_BAD_TYPE_ERR; + output STAT_RX_BURSTMAX_ERR; + output STAT_RX_BURST_ERR; + output STAT_RX_CRC24_ERR; + output [11:0] STAT_RX_CRC32_ERR; + output [11:0] STAT_RX_CRC32_VALID; + output [11:0] STAT_RX_DESCRAM_ERR; + output [11:0] STAT_RX_DIAGWORD_INTFSTAT; + output [11:0] STAT_RX_DIAGWORD_LANESTAT; + output [255:0] STAT_RX_FC_STAT; + output [11:0] STAT_RX_FRAMING_ERR; + output STAT_RX_MEOP_ERR; + output [11:0] STAT_RX_MF_ERR; + output [11:0] STAT_RX_MF_LEN_ERR; + output [11:0] STAT_RX_MF_REPEAT_ERR; + output STAT_RX_MISALIGNED; + output STAT_RX_MSOP_ERR; + output [7:0] STAT_RX_MUBITS; + output STAT_RX_MUBITS_UPDATED; + output STAT_RX_OVERFLOW_ERR; + output STAT_RX_RETRANS_CRC24_ERR; + output STAT_RX_RETRANS_DISC; + output [15:0] STAT_RX_RETRANS_LATENCY; + output STAT_RX_RETRANS_REQ; + output STAT_RX_RETRANS_RETRY_ERR; + output [7:0] STAT_RX_RETRANS_SEQ; + output STAT_RX_RETRANS_SEQ_UPDATED; + output [2:0] STAT_RX_RETRANS_STATE; + output [4:0] STAT_RX_RETRANS_SUBSEQ; + output STAT_RX_RETRANS_WDOG_ERR; + output STAT_RX_RETRANS_WRAP_ERR; + output [11:0] STAT_RX_SYNCED; + output [11:0] STAT_RX_SYNCED_ERR; + output [11:0] STAT_RX_WORD_SYNC; + output STAT_TX_BURST_ERR; + output STAT_TX_ERRINJ_BITERR_DONE; + output STAT_TX_OVERFLOW_ERR; + output STAT_TX_RETRANS_BURST_ERR; + output STAT_TX_RETRANS_BUSY; + output STAT_TX_RETRANS_RAM_PERROUT; + output [8:0] STAT_TX_RETRANS_RAM_RADDR; + output STAT_TX_RETRANS_RAM_RD_B0; + output STAT_TX_RETRANS_RAM_RD_B1; + output STAT_TX_RETRANS_RAM_RD_B2; + output STAT_TX_RETRANS_RAM_RD_B3; + output [1:0] STAT_TX_RETRANS_RAM_RSEL; + output [8:0] STAT_TX_RETRANS_RAM_WADDR; + output [643:0] STAT_TX_RETRANS_RAM_WDATA; + output STAT_TX_RETRANS_RAM_WE_B0; + output STAT_TX_RETRANS_RAM_WE_B1; + output STAT_TX_RETRANS_RAM_WE_B2; + output STAT_TX_RETRANS_RAM_WE_B3; + output STAT_TX_UNDERFLOW_ERR; + output TX_OVFOUT; + output TX_RDYOUT; + output [63:0] TX_SERDES_DATA00; + output [63:0] TX_SERDES_DATA01; + output [63:0] TX_SERDES_DATA02; + output [63:0] TX_SERDES_DATA03; + output [63:0] TX_SERDES_DATA04; + output [63:0] TX_SERDES_DATA05; + output [63:0] TX_SERDES_DATA06; + output [63:0] TX_SERDES_DATA07; + output [63:0] TX_SERDES_DATA08; + output [63:0] TX_SERDES_DATA09; + output [63:0] TX_SERDES_DATA10; + output [63:0] TX_SERDES_DATA11; + input CORE_CLK; + input CTL_RX_FORCE_RESYNC; + input CTL_RX_RETRANS_ACK; + input CTL_RX_RETRANS_ENABLE; + input CTL_RX_RETRANS_ERRIN; + input CTL_RX_RETRANS_FORCE_REQ; + input CTL_RX_RETRANS_RESET; + input CTL_RX_RETRANS_RESET_MODE; + input CTL_TX_DIAGWORD_INTFSTAT; + input [11:0] CTL_TX_DIAGWORD_LANESTAT; + input CTL_TX_ENABLE; + input CTL_TX_ERRINJ_BITERR_GO; + input [3:0] CTL_TX_ERRINJ_BITERR_LANE; + input [255:0] CTL_TX_FC_STAT; + input [7:0] CTL_TX_MUBITS; + input CTL_TX_RETRANS_ENABLE; + input CTL_TX_RETRANS_RAM_PERRIN; + input [643:0] CTL_TX_RETRANS_RAM_RDATA; + input CTL_TX_RETRANS_REQ; + input CTL_TX_RETRANS_REQ_VALID; + input [11:0] CTL_TX_RLIM_DELTA; + input CTL_TX_RLIM_ENABLE; + input [7:0] CTL_TX_RLIM_INTV; + input [11:0] CTL_TX_RLIM_MAX; + input [9:0] DRP_ADDR; + input DRP_CLK; + input [15:0] DRP_DI; + input DRP_EN; + input DRP_WE; + input LBUS_CLK; + input RX_BYPASS_FORCE_REALIGNIN; + input RX_BYPASS_RDIN; + input RX_RESET; + input [11:0] RX_SERDES_CLK; + input [63:0] RX_SERDES_DATA00; + input [63:0] RX_SERDES_DATA01; + input [63:0] RX_SERDES_DATA02; + input [63:0] RX_SERDES_DATA03; + input [63:0] RX_SERDES_DATA04; + input [63:0] RX_SERDES_DATA05; + input [63:0] RX_SERDES_DATA06; + input [63:0] RX_SERDES_DATA07; + input [63:0] RX_SERDES_DATA08; + input [63:0] RX_SERDES_DATA09; + input [63:0] RX_SERDES_DATA10; + input [63:0] RX_SERDES_DATA11; + input [11:0] RX_SERDES_RESET; + input TX_BCTLIN0; + input TX_BCTLIN1; + input TX_BCTLIN2; + input TX_BCTLIN3; + input [11:0] TX_BYPASS_CTRLIN; + input [63:0] TX_BYPASS_DATAIN00; + input [63:0] TX_BYPASS_DATAIN01; + input [63:0] TX_BYPASS_DATAIN02; + input [63:0] TX_BYPASS_DATAIN03; + input [63:0] TX_BYPASS_DATAIN04; + input [63:0] TX_BYPASS_DATAIN05; + input [63:0] TX_BYPASS_DATAIN06; + input [63:0] TX_BYPASS_DATAIN07; + input [63:0] TX_BYPASS_DATAIN08; + input [63:0] TX_BYPASS_DATAIN09; + input [63:0] TX_BYPASS_DATAIN10; + input [63:0] TX_BYPASS_DATAIN11; + input TX_BYPASS_ENAIN; + input [7:0] TX_BYPASS_GEARBOX_SEQIN; + input [3:0] TX_BYPASS_MFRAMER_STATEIN; + input [10:0] TX_CHANIN0; + input [10:0] TX_CHANIN1; + input [10:0] TX_CHANIN2; + input [10:0] TX_CHANIN3; + input [127:0] TX_DATAIN0; + input [127:0] TX_DATAIN1; + input [127:0] TX_DATAIN2; + input [127:0] TX_DATAIN3; + input TX_ENAIN0; + input TX_ENAIN1; + input TX_ENAIN2; + input TX_ENAIN3; + input TX_EOPIN0; + input TX_EOPIN1; + input TX_EOPIN2; + input TX_EOPIN3; + input TX_ERRIN0; + input TX_ERRIN1; + input TX_ERRIN2; + input TX_ERRIN3; + input [3:0] TX_MTYIN0; + input [3:0] TX_MTYIN1; + input [3:0] TX_MTYIN2; + input [3:0] TX_MTYIN3; + input TX_RESET; + input TX_SERDES_REFCLK; + input TX_SERDES_REFCLK_RESET; + input TX_SOPIN0; + input TX_SOPIN1; + input TX_SOPIN2; + input TX_SOPIN3; +endmodule + diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 69b071d34..3d4a65c5d 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -46,7 +46,7 @@ struct SynthXilinxPass : public ScriptPass log(" -top \n"); log(" use the specified module as top module\n"); log("\n"); - log(" -family {xcup|xcu|xc7|xc6v|xc6s}\n"); + log(" -family {xcup|xcu|xc7|xc6v|xc5v|xc6s}\n"); log(" run synthesis for the specified Xilinx architecture\n"); log(" generate the synthesis netlist for the specified family.\n"); log(" default: xc7\n"); @@ -260,7 +260,7 @@ struct SynthXilinxPass : public ScriptPass } extra_args(args, argidx, design); - if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc6s") + if (family != "xcup" && family != "xcu" && family != "xc7" && family != "xc6v" && family != "xc5v" && family != "xc6s") log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str()); if (widemux != 0 && widemux < 2) @@ -296,26 +296,7 @@ struct SynthXilinxPass : public ScriptPass else run("read_verilog -lib +/xilinx/cells_sim.v"); - if (help_mode) - run("read_verilog -lib +/xilinx/{family}_cells_xtra.v"); - else if (family == "xc6s") - run("read_verilog -lib +/xilinx/xc6s_cells_xtra.v"); - else if (family == "xc6v") - run("read_verilog -lib +/xilinx/xc6v_cells_xtra.v"); - else if (family == "xc7") - run("read_verilog -lib +/xilinx/xc7_cells_xtra.v"); - else if (family == "xcu" || family == "xcup") - run("read_verilog -lib +/xilinx/xcu_cells_xtra.v"); - - if (help_mode) { - run("read_verilog -lib +/xilinx/{family}_brams_bb.v"); - } else if (family == "xc6s") { - run("read_verilog -lib +/xilinx/xc6s_brams_bb.v"); - } else if (family == "xc6v" || family == "xc7") { - run("read_verilog -lib +/xilinx/xc7_brams_bb.v"); - } else if (family == "xcu" || family == "xcup") { - run("read_verilog -lib +/xilinx/xcu_brams_bb.v"); - } + run("read_verilog -lib +/xilinx/cells_xtra.v"); run(stringf("hierarchy -check %s", top_opt.c_str())); } diff --git a/techlibs/xilinx/xc6s_brams_bb.v b/techlibs/xilinx/xc6s_brams_bb.v deleted file mode 100644 index 3c323a90b..000000000 --- a/techlibs/xilinx/xc6s_brams_bb.v +++ /dev/null @@ -1,223 +0,0 @@ -module RAMB8BWER ( - (* clkbuf_sink *) - input CLKAWRCLK, - (* clkbuf_sink *) - input CLKBRDCLK, - input ENAWREN, - input ENBRDEN, - input REGCEA, - input REGCEBREGCE, - input RSTA, - input RSTBRST, - - input [12:0] ADDRAWRADDR, - input [12:0] ADDRBRDADDR, - input [15:0] DIADI, - input [15:0] DIBDI, - input [1:0] DIPADIP, - input [1:0] DIPBDIP, - input [1:0] WEAWEL, - input [1:0] WEBWEU, - - /* (* abc9_arrival= *) */ - output [15:0] DOADO, - /* (* abc9_arrival= *) */ - output [15:0] DOBDO, - /* (* abc9_arrival= *) */ - output [1:0] DOPADOP, - /* (* abc9_arrival= *) */ - output [1:0] DOPBDOP -); - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - parameter RAM_MODE = "TDP"; - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - - parameter integer DATA_WIDTH_A = 0; - parameter integer DATA_WIDTH_B = 0; - - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - - parameter EN_RSTRAM_A = "TRUE"; - parameter EN_RSTRAM_B = "TRUE"; - - parameter INIT_A = 18'h000000000; - parameter INIT_B = 18'h000000000; - parameter SRVAL_A = 18'h000000000; - parameter SRVAL_B = 18'h000000000; - - parameter RST_PRIORITY_A = "CE"; - parameter RST_PRIORITY_B = "CE"; - - parameter RSTTYPE = "SYNC"; - - parameter SIM_COLLISION_CHECK = "ALL"; -endmodule - -module RAMB16BWER ( - (* clkbuf_sink *) - input CLKA, - (* clkbuf_sink *) - input CLKB, - input ENA, - input ENB, - input REGCEA, - input REGCEB, - input RSTA, - input RSTB, - - input [13:0] ADDRA, - input [13:0] ADDRB, - input [31:0] DIA, - input [31:0] DIB, - input [3:0] DIPA, - input [3:0] DIPB, - input [3:0] WEA, - input [3:0] WEB, - - /* (* abc9_arrival= *) */ - output [31:0] DOA, - /* (* abc9_arrival= *) */ - output [31:0] DOB, - /* (* abc9_arrival= *) */ - output [3:0] DOPA, - /* (* abc9_arrival= *) */ - output [3:0] DOPB -); - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - - parameter integer DATA_WIDTH_A = 0; - parameter integer DATA_WIDTH_B = 0; - - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - - parameter EN_RSTRAM_A = "TRUE"; - parameter EN_RSTRAM_B = "TRUE"; - - parameter INIT_A = 36'h000000000; - parameter INIT_B = 36'h000000000; - parameter SRVAL_A = 36'h000000000; - parameter SRVAL_B = 36'h000000000; - - parameter RST_PRIORITY_A = "CE"; - parameter RST_PRIORITY_B = "CE"; - - parameter RSTTYPE = "SYNC"; - - parameter SIM_COLLISION_CHECK = "ALL"; -endmodule - diff --git a/techlibs/xilinx/xc6s_cells_xtra.v b/techlibs/xilinx/xc6s_cells_xtra.v deleted file mode 100644 index 7c0462b52..000000000 --- a/techlibs/xilinx/xc6s_cells_xtra.v +++ /dev/null @@ -1,1819 +0,0 @@ -// Created by cells_xtra.py from Xilinx models - -module MCB (...); - parameter integer ARB_NUM_TIME_SLOTS = 12; - parameter [17:0] ARB_TIME_SLOT_0 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_1 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_10 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_11 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_2 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_3 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_4 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_5 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_6 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_7 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_8 = 18'b111111111111111111; - parameter [17:0] ARB_TIME_SLOT_9 = 18'b111111111111111111; - parameter [2:0] CAL_BA = 3'h0; - parameter CAL_BYPASS = "YES"; - parameter [11:0] CAL_CA = 12'h000; - parameter CAL_CALIBRATION_MODE = "NOCALIBRATION"; - parameter integer CAL_CLK_DIV = 1; - parameter CAL_DELAY = "QUARTER"; - parameter [14:0] CAL_RA = 15'h0000; - parameter MEM_ADDR_ORDER = "BANK_ROW_COLUMN"; - parameter integer MEM_BA_SIZE = 3; - parameter integer MEM_BURST_LEN = 8; - parameter integer MEM_CAS_LATENCY = 4; - parameter integer MEM_CA_SIZE = 11; - parameter MEM_DDR1_2_ODS = "FULL"; - parameter MEM_DDR2_3_HIGH_TEMP_SR = "NORMAL"; - parameter MEM_DDR2_3_PA_SR = "FULL"; - parameter integer MEM_DDR2_ADD_LATENCY = 0; - parameter MEM_DDR2_DIFF_DQS_EN = "YES"; - parameter MEM_DDR2_RTT = "50OHMS"; - parameter integer MEM_DDR2_WRT_RECOVERY = 4; - parameter MEM_DDR3_ADD_LATENCY = "OFF"; - parameter MEM_DDR3_AUTO_SR = "ENABLED"; - parameter integer MEM_DDR3_CAS_LATENCY = 7; - parameter integer MEM_DDR3_CAS_WR_LATENCY = 5; - parameter MEM_DDR3_DYN_WRT_ODT = "OFF"; - parameter MEM_DDR3_ODS = "DIV7"; - parameter MEM_DDR3_RTT = "DIV2"; - parameter integer MEM_DDR3_WRT_RECOVERY = 7; - parameter MEM_MDDR_ODS = "FULL"; - parameter MEM_MOBILE_PA_SR = "FULL"; - parameter integer MEM_MOBILE_TC_SR = 0; - parameter integer MEM_RAS_VAL = 0; - parameter integer MEM_RA_SIZE = 13; - parameter integer MEM_RCD_VAL = 1; - parameter integer MEM_REFI_VAL = 0; - parameter integer MEM_RFC_VAL = 0; - parameter integer MEM_RP_VAL = 0; - parameter integer MEM_RTP_VAL = 0; - parameter MEM_TYPE = "DDR3"; - parameter integer MEM_WIDTH = 4; - parameter integer MEM_WR_VAL = 0; - parameter integer MEM_WTR_VAL = 3; - parameter PORT_CONFIG = "B32_B32_B32_B32"; - output CAS; - output CKE; - output DQIOWEN0; - output DQSIOWEN90N; - output DQSIOWEN90P; - output IOIDRPADD; - output IOIDRPBROADCAST; - output IOIDRPCLK; - output IOIDRPCS; - output IOIDRPSDO; - output IOIDRPTRAIN; - output IOIDRPUPDATE; - output LDMN; - output LDMP; - output ODT; - output P0CMDEMPTY; - output P0CMDFULL; - output P0RDEMPTY; - output P0RDERROR; - output P0RDFULL; - output P0RDOVERFLOW; - output P0WREMPTY; - output P0WRERROR; - output P0WRFULL; - output P0WRUNDERRUN; - output P1CMDEMPTY; - output P1CMDFULL; - output P1RDEMPTY; - output P1RDERROR; - output P1RDFULL; - output P1RDOVERFLOW; - output P1WREMPTY; - output P1WRERROR; - output P1WRFULL; - output P1WRUNDERRUN; - output P2CMDEMPTY; - output P2CMDFULL; - output P2EMPTY; - output P2ERROR; - output P2FULL; - output P2RDOVERFLOW; - output P2WRUNDERRUN; - output P3CMDEMPTY; - output P3CMDFULL; - output P3EMPTY; - output P3ERROR; - output P3FULL; - output P3RDOVERFLOW; - output P3WRUNDERRUN; - output P4CMDEMPTY; - output P4CMDFULL; - output P4EMPTY; - output P4ERROR; - output P4FULL; - output P4RDOVERFLOW; - output P4WRUNDERRUN; - output P5CMDEMPTY; - output P5CMDFULL; - output P5EMPTY; - output P5ERROR; - output P5FULL; - output P5RDOVERFLOW; - output P5WRUNDERRUN; - output RAS; - output RST; - output SELFREFRESHMODE; - output UDMN; - output UDMP; - output UOCALSTART; - output UOCMDREADYIN; - output UODATAVALID; - output UODONECAL; - output UOREFRSHFLAG; - output UOSDO; - output WE; - output [14:0] ADDR; - output [15:0] DQON; - output [15:0] DQOP; - output [2:0] BA; - output [31:0] P0RDDATA; - output [31:0] P1RDDATA; - output [31:0] P2RDDATA; - output [31:0] P3RDDATA; - output [31:0] P4RDDATA; - output [31:0] P5RDDATA; - output [31:0] STATUS; - output [4:0] IOIDRPADDR; - output [6:0] P0RDCOUNT; - output [6:0] P0WRCOUNT; - output [6:0] P1RDCOUNT; - output [6:0] P1WRCOUNT; - output [6:0] P2COUNT; - output [6:0] P3COUNT; - output [6:0] P4COUNT; - output [6:0] P5COUNT; - output [7:0] UODATA; - input DQSIOIN; - input DQSIOIP; - input IOIDRPSDI; - input P0ARBEN; - input P0CMDCLK; - input P0CMDEN; - input P0RDCLK; - input P0RDEN; - input P0WRCLK; - input P0WREN; - input P1ARBEN; - input P1CMDCLK; - input P1CMDEN; - input P1RDCLK; - input P1RDEN; - input P1WRCLK; - input P1WREN; - input P2ARBEN; - input P2CLK; - input P2CMDCLK; - input P2CMDEN; - input P2EN; - input P3ARBEN; - input P3CLK; - input P3CMDCLK; - input P3CMDEN; - input P3EN; - input P4ARBEN; - input P4CLK; - input P4CMDCLK; - input P4CMDEN; - input P4EN; - input P5ARBEN; - input P5CLK; - input P5CMDCLK; - input P5CMDEN; - input P5EN; - input PLLLOCK; - input RECAL; - input SELFREFRESHENTER; - input SYSRST; - input UDQSIOIN; - input UDQSIOIP; - input UIADD; - input UIBROADCAST; - input UICLK; - input UICMD; - input UICMDEN; - input UICMDIN; - input UICS; - input UIDONECAL; - input UIDQLOWERDEC; - input UIDQLOWERINC; - input UIDQUPPERDEC; - input UIDQUPPERINC; - input UIDRPUPDATE; - input UILDQSDEC; - input UILDQSINC; - input UIREAD; - input UISDI; - input UIUDQSDEC; - input UIUDQSINC; - input [11:0] P0CMDCA; - input [11:0] P1CMDCA; - input [11:0] P2CMDCA; - input [11:0] P3CMDCA; - input [11:0] P4CMDCA; - input [11:0] P5CMDCA; - input [14:0] P0CMDRA; - input [14:0] P1CMDRA; - input [14:0] P2CMDRA; - input [14:0] P3CMDRA; - input [14:0] P4CMDRA; - input [14:0] P5CMDRA; - input [15:0] DQI; - input [1:0] PLLCE; - input [1:0] PLLCLK; - input [2:0] P0CMDBA; - input [2:0] P0CMDINSTR; - input [2:0] P1CMDBA; - input [2:0] P1CMDINSTR; - input [2:0] P2CMDBA; - input [2:0] P2CMDINSTR; - input [2:0] P3CMDBA; - input [2:0] P3CMDINSTR; - input [2:0] P4CMDBA; - input [2:0] P4CMDINSTR; - input [2:0] P5CMDBA; - input [2:0] P5CMDINSTR; - input [31:0] P0WRDATA; - input [31:0] P1WRDATA; - input [31:0] P2WRDATA; - input [31:0] P3WRDATA; - input [31:0] P4WRDATA; - input [31:0] P5WRDATA; - input [3:0] P0RWRMASK; - input [3:0] P1RWRMASK; - input [3:0] P2WRMASK; - input [3:0] P3WRMASK; - input [3:0] P4WRMASK; - input [3:0] P5WRMASK; - input [3:0] UIDQCOUNT; - input [4:0] UIADDR; - input [5:0] P0CMDBL; - input [5:0] P1CMDBL; - input [5:0] P2CMDBL; - input [5:0] P3CMDBL; - input [5:0] P4CMDBL; - input [5:0] P5CMDBL; -endmodule - -module PCIE_A1 (...); - parameter [31:0] BAR0 = 32'h00000000; - parameter [31:0] BAR1 = 32'h00000000; - parameter [31:0] BAR2 = 32'h00000000; - parameter [31:0] BAR3 = 32'h00000000; - parameter [31:0] BAR4 = 32'h00000000; - parameter [31:0] BAR5 = 32'h00000000; - parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; - parameter [23:0] CLASS_CODE = 24'h000000; - parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 7; - parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 7; - parameter DEV_CAP_EXT_TAG_SUPPORTED = "FALSE"; - parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; - parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; - parameter DISABLE_BAR_FILTERING = "FALSE"; - parameter DISABLE_ID_CHECK = "FALSE"; - parameter DISABLE_SCRAMBLING = "FALSE"; - parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; - parameter [21:0] EXPANSION_ROM = 22'h000000; - parameter FAST_TRAIN = "FALSE"; - parameter integer GTP_SEL = 0; - parameter integer LINK_CAP_ASPM_SUPPORT = 1; - parameter integer LINK_CAP_L0S_EXIT_LATENCY = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY = 7; - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "FALSE"; - parameter [14:0] LL_ACK_TIMEOUT = 15'h0204; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter [14:0] LL_REPLAY_TIMEOUT = 15'h060D; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer MSI_CAP_MULTIMSGCAP = 0; - parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; - parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h1; - parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; - parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'b00000; - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; - parameter [11:0] PCIE_GENERIC = 12'h000; - parameter PLM_AUTO_CONFIG = "FALSE"; - parameter integer PM_CAP_AUXCURRENT = 0; - parameter PM_CAP_D1SUPPORT = "TRUE"; - parameter PM_CAP_D2SUPPORT = "TRUE"; - parameter PM_CAP_DSI = "FALSE"; - parameter [4:0] PM_CAP_PMESUPPORT = 5'b01111; - parameter PM_CAP_PME_CLOCK = "FALSE"; - parameter integer PM_CAP_VERSION = 3; - parameter [7:0] PM_DATA0 = 8'h1E; - parameter [7:0] PM_DATA1 = 8'h1E; - parameter [7:0] PM_DATA2 = 8'h1E; - parameter [7:0] PM_DATA3 = 8'h1E; - parameter [7:0] PM_DATA4 = 8'h1E; - parameter [7:0] PM_DATA5 = 8'h1E; - parameter [7:0] PM_DATA6 = 8'h1E; - parameter [7:0] PM_DATA7 = 8'h1E; - parameter [1:0] PM_DATA_SCALE0 = 2'b01; - parameter [1:0] PM_DATA_SCALE1 = 2'b01; - parameter [1:0] PM_DATA_SCALE2 = 2'b01; - parameter [1:0] PM_DATA_SCALE3 = 2'b01; - parameter [1:0] PM_DATA_SCALE4 = 2'b01; - parameter [1:0] PM_DATA_SCALE5 = 2'b01; - parameter [1:0] PM_DATA_SCALE6 = 2'b01; - parameter [1:0] PM_DATA_SCALE7 = 2'b01; - parameter SIM_VERSION = "1.0"; - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; - parameter integer TL_RX_RAM_RADDR_LATENCY = 1; - parameter integer TL_RX_RAM_RDATA_LATENCY = 2; - parameter integer TL_RX_RAM_WRITE_LATENCY = 0; - parameter TL_TFC_DISABLE = "FALSE"; - parameter TL_TX_CHECKS_DISABLE = "FALSE"; - parameter integer TL_TX_RAM_RADDR_LATENCY = 0; - parameter integer TL_TX_RAM_RDATA_LATENCY = 2; - parameter USR_CFG = "FALSE"; - parameter USR_EXT_CFG = "FALSE"; - parameter VC0_CPL_INFINITE = "TRUE"; - parameter [11:0] VC0_RX_RAM_LIMIT = 12'h01E; - parameter integer VC0_TOTAL_CREDITS_CD = 104; - parameter integer VC0_TOTAL_CREDITS_CH = 36; - parameter integer VC0_TOTAL_CREDITS_NPH = 8; - parameter integer VC0_TOTAL_CREDITS_PD = 288; - parameter integer VC0_TOTAL_CREDITS_PH = 32; - parameter integer VC0_TX_LASTPACKET = 31; - output CFGCOMMANDBUSMASTERENABLE; - output CFGCOMMANDINTERRUPTDISABLE; - output CFGCOMMANDIOENABLE; - output CFGCOMMANDMEMENABLE; - output CFGCOMMANDSERREN; - output CFGDEVCONTROLAUXPOWEREN; - output CFGDEVCONTROLCORRERRREPORTINGEN; - output CFGDEVCONTROLENABLERO; - output CFGDEVCONTROLEXTTAGEN; - output CFGDEVCONTROLFATALERRREPORTINGEN; - output CFGDEVCONTROLNONFATALREPORTINGEN; - output CFGDEVCONTROLNOSNOOPEN; - output CFGDEVCONTROLPHANTOMEN; - output CFGDEVCONTROLURERRREPORTINGEN; - output CFGDEVSTATUSCORRERRDETECTED; - output CFGDEVSTATUSFATALERRDETECTED; - output CFGDEVSTATUSNONFATALERRDETECTED; - output CFGDEVSTATUSURDETECTED; - output CFGERRCPLRDYN; - output CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTRDYN; - output CFGLINKCONTOLRCB; - output CFGLINKCONTROLCOMMONCLOCK; - output CFGLINKCONTROLEXTENDEDSYNC; - output CFGRDWRDONEN; - output CFGTOTURNOFFN; - output DBGBADDLLPSTATUS; - output DBGBADTLPLCRC; - output DBGBADTLPSEQNUM; - output DBGBADTLPSTATUS; - output DBGDLPROTOCOLSTATUS; - output DBGFCPROTOCOLERRSTATUS; - output DBGMLFRMDLENGTH; - output DBGMLFRMDMPS; - output DBGMLFRMDTCVC; - output DBGMLFRMDTLPSTATUS; - output DBGMLFRMDUNRECTYPE; - output DBGPOISTLPSTATUS; - output DBGRCVROVERFLOWSTATUS; - output DBGREGDETECTEDCORRECTABLE; - output DBGREGDETECTEDFATAL; - output DBGREGDETECTEDNONFATAL; - output DBGREGDETECTEDUNSUPPORTED; - output DBGRPLYROLLOVERSTATUS; - output DBGRPLYTIMEOUTSTATUS; - output DBGURNOBARHIT; - output DBGURPOISCFGWR; - output DBGURSTATUS; - output DBGURUNSUPMSG; - output MIMRXREN; - output MIMRXWEN; - output MIMTXREN; - output MIMTXWEN; - output PIPEGTTXELECIDLEA; - output PIPEGTTXELECIDLEB; - output PIPERXPOLARITYA; - output PIPERXPOLARITYB; - output PIPERXRESETA; - output PIPERXRESETB; - output PIPETXRCVRDETA; - output PIPETXRCVRDETB; - output RECEIVEDHOTRESET; - output TRNLNKUPN; - output TRNREOFN; - output TRNRERRFWDN; - output TRNRSOFN; - output TRNRSRCDSCN; - output TRNRSRCRDYN; - output TRNTCFGREQN; - output TRNTDSTRDYN; - output TRNTERRDROPN; - output USERRSTN; - output [11:0] MIMRXRADDR; - output [11:0] MIMRXWADDR; - output [11:0] MIMTXRADDR; - output [11:0] MIMTXWADDR; - output [11:0] TRNFCCPLD; - output [11:0] TRNFCNPD; - output [11:0] TRNFCPD; - output [15:0] PIPETXDATAA; - output [15:0] PIPETXDATAB; - output [1:0] CFGLINKCONTROLASPMCONTROL; - output [1:0] PIPEGTPOWERDOWNA; - output [1:0] PIPEGTPOWERDOWNB; - output [1:0] PIPETXCHARDISPMODEA; - output [1:0] PIPETXCHARDISPMODEB; - output [1:0] PIPETXCHARDISPVALA; - output [1:0] PIPETXCHARDISPVALB; - output [1:0] PIPETXCHARISKA; - output [1:0] PIPETXCHARISKB; - output [2:0] CFGDEVCONTROLMAXPAYLOAD; - output [2:0] CFGDEVCONTROLMAXREADREQ; - output [2:0] CFGFUNCTIONNUMBER; - output [2:0] CFGINTERRUPTMMENABLE; - output [2:0] CFGPCIELINKSTATEN; - output [31:0] CFGDO; - output [31:0] TRNRD; - output [34:0] MIMRXWDATA; - output [35:0] MIMTXWDATA; - output [4:0] CFGDEVICENUMBER; - output [4:0] CFGLTSSMSTATE; - output [5:0] TRNTBUFAV; - output [6:0] TRNRBARHITN; - output [7:0] CFGBUSNUMBER; - output [7:0] CFGINTERRUPTDO; - output [7:0] TRNFCCPLH; - output [7:0] TRNFCNPH; - output [7:0] TRNFCPH; - input CFGERRCORN; - input CFGERRCPLABORTN; - input CFGERRCPLTIMEOUTN; - input CFGERRECRCN; - input CFGERRLOCKEDN; - input CFGERRPOSTEDN; - input CFGERRURN; - input CFGINTERRUPTASSERTN; - input CFGINTERRUPTN; - input CFGPMWAKEN; - input CFGRDENN; - input CFGTRNPENDINGN; - input CFGTURNOFFOKN; - input CLOCKLOCKED; - input MGTCLK; - input PIPEGTRESETDONEA; - input PIPEGTRESETDONEB; - input PIPEPHYSTATUSA; - input PIPEPHYSTATUSB; - input PIPERXENTERELECIDLEA; - input PIPERXENTERELECIDLEB; - input SYSRESETN; - input TRNRDSTRDYN; - input TRNRNPOKN; - input TRNTCFGGNTN; - input TRNTEOFN; - input TRNTERRFWDN; - input TRNTSOFN; - input TRNTSRCDSCN; - input TRNTSRCRDYN; - input TRNTSTRN; - input USERCLK; - input [15:0] CFGDEVID; - input [15:0] CFGSUBSYSID; - input [15:0] CFGSUBSYSVENID; - input [15:0] CFGVENID; - input [15:0] PIPERXDATAA; - input [15:0] PIPERXDATAB; - input [1:0] PIPERXCHARISKA; - input [1:0] PIPERXCHARISKB; - input [2:0] PIPERXSTATUSA; - input [2:0] PIPERXSTATUSB; - input [2:0] TRNFCSEL; - input [31:0] TRNTD; - input [34:0] MIMRXRDATA; - input [35:0] MIMTXRDATA; - input [47:0] CFGERRTLPCPLHEADER; - input [63:0] CFGDSN; - input [7:0] CFGINTERRUPTDI; - input [7:0] CFGREVID; - input [9:0] CFGDWADDR; -endmodule - -module DSP48A1 (...); - parameter integer A0REG = 0; - parameter integer A1REG = 1; - parameter integer B0REG = 0; - parameter integer B1REG = 1; - parameter integer CARRYINREG = 1; - parameter integer CARRYOUTREG = 1; - parameter CARRYINSEL = "OPMODE5"; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter RSTTYPE = "SYNC"; - output [17:0] BCOUT; - output CARRYOUT; - output CARRYOUTF; - output [35:0] M; - output [47:0] P; - output [47:0] PCOUT; - input [17:0] A; - input [17:0] B; - input [47:0] C; - input CARRYIN; - input CEA; - input CEB; - input CEC; - input CECARRYIN; - input CED; - input CEM; - input CEOPMODE; - input CEP; - (* clkbuf_sink *) - input CLK; - input [17:0] D; - input [7:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTB; - input RSTC; - input RSTCARRYIN; - input RSTD; - input RSTM; - input RSTOPMODE; - input RSTP; -endmodule - -module BUFGCE (...); - parameter CE_TYPE = "SYNC"; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_I_INVERTED = 1'b0; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_I_INVERTED" *) - input I; -endmodule - -module BUFGCE_1 (...); - (* clkbuf_driver *) - output O; - input CE; - input I; -endmodule - -module BUFGMUX (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_1 (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFH (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFIO2 (...); - parameter DIVIDE_BYPASS = "TRUE"; - parameter integer DIVIDE = 1; - parameter I_INVERT = "FALSE"; - parameter USE_DOUBLER = "FALSE"; - (* clkbuf_driver *) - output DIVCLK; - (* clkbuf_driver *) - output IOCLK; - output SERDESSTROBE; - input I; -endmodule - -module BUFIO2_2CLK (...); - parameter integer DIVIDE = 2; - (* clkbuf_driver *) - output DIVCLK; - (* clkbuf_driver *) - output IOCLK; - output SERDESSTROBE; - input I; - input IB; -endmodule - -module BUFIO2FB (...); - parameter DIVIDE_BYPASS = "TRUE"; - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFPLL_MCB (...); - parameter integer DIVIDE = 2; - parameter LOCK_SRC = "LOCK_TO_0"; - (* clkbuf_driver *) - output IOCLK0; - (* clkbuf_driver *) - output IOCLK1; - output LOCK; - output SERDESSTROBE0; - output SERDESSTROBE1; - input GCLK; - input LOCKED; - input PLLIN0; - input PLLIN1; -endmodule - -module DCM_CLKGEN (...); - parameter SPREAD_SPECTRUM = "NONE"; - parameter STARTUP_WAIT = "FALSE"; - parameter integer CLKFXDV_DIVIDE = 2; - parameter integer CLKFX_DIVIDE = 1; - parameter integer CLKFX_MULTIPLY = 4; - parameter real CLKFX_MD_MAX = 0.0; - parameter real CLKIN_PERIOD = 0.0; - output CLKFX180; - output CLKFX; - output CLKFXDV; - output LOCKED; - output PROGDONE; - output [2:1] STATUS; - input CLKIN; - input FREEZEDCM; - input PROGCLK; - input PROGDATA; - input PROGEN; - input RST; -endmodule - -module DCM_SP (...); - parameter real CLKDV_DIVIDE = 2.0; - parameter integer CLKFX_DIVIDE = 1; - parameter integer CLKFX_MULTIPLY = 4; - parameter CLKIN_DIVIDE_BY_2 = "FALSE"; - parameter real CLKIN_PERIOD = 10.0; - parameter CLKOUT_PHASE_SHIFT = "NONE"; - parameter CLK_FEEDBACK = "1X"; - parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS"; - parameter DFS_FREQUENCY_MODE = "LOW"; - parameter DLL_FREQUENCY_MODE = "LOW"; - parameter DSS_MODE = "NONE"; - parameter DUTY_CYCLE_CORRECTION = "TRUE"; - parameter FACTORY_JF = 16'hC080; - parameter integer PHASE_SHIFT = 0; - parameter STARTUP_WAIT = "FALSE"; - input CLKFB; - input CLKIN; - input DSSEN; - input PSCLK; - input PSEN; - input PSINCDEC; - input RST; - output CLK0; - output CLK180; - output CLK270; - output CLK2X; - output CLK2X180; - output CLK90; - output CLKDV; - output CLKFX; - output CLKFX180; - output LOCKED; - output PSDONE; - output [7:0] STATUS; -endmodule - -module PLL_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter integer CLKFBOUT_MULT = 1; - parameter real CLKFBOUT_PHASE = 0.0; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.5; - parameter real CLKOUT0_PHASE = 0.0; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.5; - parameter real CLKOUT1_PHASE = 0.0; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.5; - parameter real CLKOUT2_PHASE = 0.0; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.5; - parameter real CLKOUT3_PHASE = 0.0; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.5; - parameter real CLKOUT4_PHASE = 0.0; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.5; - parameter real CLKOUT5_PHASE = 0.0; - parameter CLK_FEEDBACK = "CLKFBOUT"; - parameter COMPENSATION = "SYSTEM_SYNCHRONOUS"; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER = 0.100; - parameter RESET_ON_LOSS_OF_LOCK = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output LOCKED; - input CLKFBIN; - input CLKIN; - input RST; -endmodule - -(* keep *) -module BSCAN_SPARTAN6 (...); - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output RUNTEST; - output SEL; - output SHIFT; - output TCK; - output TDI; - output TMS; - output UPDATE; - input TDO; -endmodule - -module DNA_PORT (...); - parameter [56:0] SIM_DNA_VALUE = 57'h0; - output DOUT; - input CLK; - input DIN; - input READ; - input SHIFT; -endmodule - -(* keep *) -module ICAP_SPARTAN6 (...); - parameter DEVICE_ID = 32'h04000093; - parameter SIM_CFG_FILE_NAME = "NONE"; - output BUSY; - output [15:0] O; - input CLK; - input CE; - input WRITE; - input [15:0] I; -endmodule - -module POST_CRC_INTERNAL (...); - output CRCERROR; -endmodule - -(* keep *) -module STARTUP_SPARTAN6 (...); - output CFGCLK; - output CFGMCLK; - output EOS; - input CLK; - input GSR; - input GTS; - input KEYCLEARB; -endmodule - -(* keep *) -module SUSPEND_SYNC (...); - output SREQ; - input CLK; - input SACK; -endmodule - -module GTPA1_DUAL (...); - parameter AC_CAP_DIS_0 = "TRUE"; - parameter AC_CAP_DIS_1 = "TRUE"; - parameter integer ALIGN_COMMA_WORD_0 = 1; - parameter integer ALIGN_COMMA_WORD_1 = 1; - parameter integer CB2_INH_CC_PERIOD_0 = 8; - parameter integer CB2_INH_CC_PERIOD_1 = 8; - parameter [4:0] CDR_PH_ADJ_TIME_0 = 5'b01010; - parameter [4:0] CDR_PH_ADJ_TIME_1 = 5'b01010; - parameter integer CHAN_BOND_1_MAX_SKEW_0 = 7; - parameter integer CHAN_BOND_1_MAX_SKEW_1 = 7; - parameter integer CHAN_BOND_2_MAX_SKEW_0 = 1; - parameter integer CHAN_BOND_2_MAX_SKEW_1 = 1; - parameter CHAN_BOND_KEEP_ALIGN_0 = "FALSE"; - parameter CHAN_BOND_KEEP_ALIGN_1 = "FALSE"; - parameter [9:0] CHAN_BOND_SEQ_1_1_0 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_2_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3_0 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3_1 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_4_0 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_1_4_1 = 10'b0110111100; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_0 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE_1 = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1_0 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_1_1 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_2_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_2_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_4_0 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_4_1 = 10'b0100111100; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_0 = 4'b1111; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE_1 = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE_0 = "FALSE"; - parameter CHAN_BOND_SEQ_2_USE_1 = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN_0 = 1; - parameter integer CHAN_BOND_SEQ_LEN_1 = 1; - parameter integer CLK25_DIVIDER_0 = 4; - parameter integer CLK25_DIVIDER_1 = 4; - parameter CLKINDC_B_0 = "TRUE"; - parameter CLKINDC_B_1 = "TRUE"; - parameter CLKRCV_TRST_0 = "TRUE"; - parameter CLKRCV_TRST_1 = "TRUE"; - parameter CLK_CORRECT_USE_0 = "TRUE"; - parameter CLK_CORRECT_USE_1 = "TRUE"; - parameter integer CLK_COR_ADJ_LEN_0 = 1; - parameter integer CLK_COR_ADJ_LEN_1 = 1; - parameter integer CLK_COR_DET_LEN_0 = 1; - parameter integer CLK_COR_DET_LEN_1 = 1; - parameter CLK_COR_INSERT_IDLE_FLAG_0 = "FALSE"; - parameter CLK_COR_INSERT_IDLE_FLAG_1 = "FALSE"; - parameter CLK_COR_KEEP_IDLE_0 = "FALSE"; - parameter CLK_COR_KEEP_IDLE_1 = "FALSE"; - parameter integer CLK_COR_MAX_LAT_0 = 20; - parameter integer CLK_COR_MAX_LAT_1 = 20; - parameter integer CLK_COR_MIN_LAT_0 = 18; - parameter integer CLK_COR_MIN_LAT_1 = 18; - parameter CLK_COR_PRECEDENCE_0 = "TRUE"; - parameter CLK_COR_PRECEDENCE_1 = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT_0 = 0; - parameter integer CLK_COR_REPEAT_WAIT_1 = 0; - parameter [9:0] CLK_COR_SEQ_1_1_0 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_2_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4_1 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE_0 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_1_ENABLE_1 = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_1_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_2_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_2_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_3_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_3_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_4_0 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_4_1 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE_0 = 4'b1111; - parameter [3:0] CLK_COR_SEQ_2_ENABLE_1 = 4'b1111; - parameter CLK_COR_SEQ_2_USE_0 = "FALSE"; - parameter CLK_COR_SEQ_2_USE_1 = "FALSE"; - parameter CLK_OUT_GTP_SEL_0 = "REFCLKPLL0"; - parameter CLK_OUT_GTP_SEL_1 = "REFCLKPLL1"; - parameter [1:0] CM_TRIM_0 = 2'b00; - parameter [1:0] CM_TRIM_1 = 2'b00; - parameter [9:0] COMMA_10B_ENABLE_0 = 10'b1111111111; - parameter [9:0] COMMA_10B_ENABLE_1 = 10'b1111111111; - parameter [3:0] COM_BURST_VAL_0 = 4'b1111; - parameter [3:0] COM_BURST_VAL_1 = 4'b1111; - parameter DEC_MCOMMA_DETECT_0 = "TRUE"; - parameter DEC_MCOMMA_DETECT_1 = "TRUE"; - parameter DEC_PCOMMA_DETECT_0 = "TRUE"; - parameter DEC_PCOMMA_DETECT_1 = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_0 = "TRUE"; - parameter DEC_VALID_COMMA_ONLY_1 = "TRUE"; - parameter GTP_CFG_PWRUP_0 = "TRUE"; - parameter GTP_CFG_PWRUP_1 = "TRUE"; - parameter [9:0] MCOMMA_10B_VALUE_0 = 10'b1010000011; - parameter [9:0] MCOMMA_10B_VALUE_1 = 10'b1010000011; - parameter MCOMMA_DETECT_0 = "TRUE"; - parameter MCOMMA_DETECT_1 = "TRUE"; - parameter [2:0] OOBDETECT_THRESHOLD_0 = 3'b110; - parameter [2:0] OOBDETECT_THRESHOLD_1 = 3'b110; - parameter integer OOB_CLK_DIVIDER_0 = 4; - parameter integer OOB_CLK_DIVIDER_1 = 4; - parameter PCI_EXPRESS_MODE_0 = "FALSE"; - parameter PCI_EXPRESS_MODE_1 = "FALSE"; - parameter [9:0] PCOMMA_10B_VALUE_0 = 10'b0101111100; - parameter [9:0] PCOMMA_10B_VALUE_1 = 10'b0101111100; - parameter PCOMMA_DETECT_0 = "TRUE"; - parameter PCOMMA_DETECT_1 = "TRUE"; - parameter [2:0] PLLLKDET_CFG_0 = 3'b101; - parameter [2:0] PLLLKDET_CFG_1 = 3'b101; - parameter [23:0] PLL_COM_CFG_0 = 24'h21680A; - parameter [23:0] PLL_COM_CFG_1 = 24'h21680A; - parameter [7:0] PLL_CP_CFG_0 = 8'h00; - parameter [7:0] PLL_CP_CFG_1 = 8'h00; - parameter integer PLL_DIVSEL_FB_0 = 5; - parameter integer PLL_DIVSEL_FB_1 = 5; - parameter integer PLL_DIVSEL_REF_0 = 2; - parameter integer PLL_DIVSEL_REF_1 = 2; - parameter integer PLL_RXDIVSEL_OUT_0 = 1; - parameter integer PLL_RXDIVSEL_OUT_1 = 1; - parameter PLL_SATA_0 = "FALSE"; - parameter PLL_SATA_1 = "FALSE"; - parameter PLL_SOURCE_0 = "PLL0"; - parameter PLL_SOURCE_1 = "PLL0"; - parameter integer PLL_TXDIVSEL_OUT_0 = 1; - parameter integer PLL_TXDIVSEL_OUT_1 = 1; - parameter [26:0] PMA_CDR_SCAN_0 = 27'h6404040; - parameter [26:0] PMA_CDR_SCAN_1 = 27'h6404040; - parameter [35:0] PMA_COM_CFG_EAST = 36'h000008000; - parameter [35:0] PMA_COM_CFG_WEST = 36'h00000A000; - parameter [6:0] PMA_RXSYNC_CFG_0 = 7'h00; - parameter [6:0] PMA_RXSYNC_CFG_1 = 7'h00; - parameter [24:0] PMA_RX_CFG_0 = 25'h05CE048; - parameter [24:0] PMA_RX_CFG_1 = 25'h05CE048; - parameter [19:0] PMA_TX_CFG_0 = 20'h00082; - parameter [19:0] PMA_TX_CFG_1 = 20'h00082; - parameter RCV_TERM_GND_0 = "FALSE"; - parameter RCV_TERM_GND_1 = "FALSE"; - parameter RCV_TERM_VTTRX_0 = "TRUE"; - parameter RCV_TERM_VTTRX_1 = "TRUE"; - parameter [7:0] RXEQ_CFG_0 = 8'b01111011; - parameter [7:0] RXEQ_CFG_1 = 8'b01111011; - parameter [0:0] RXPRBSERR_LOOPBACK_0 = 1'b0; - parameter [0:0] RXPRBSERR_LOOPBACK_1 = 1'b0; - parameter RX_BUFFER_USE_0 = "TRUE"; - parameter RX_BUFFER_USE_1 = "TRUE"; - parameter RX_DECODE_SEQ_MATCH_0 = "TRUE"; - parameter RX_DECODE_SEQ_MATCH_1 = "TRUE"; - parameter RX_EN_IDLE_HOLD_CDR_0 = "FALSE"; - parameter RX_EN_IDLE_HOLD_CDR_1 = "FALSE"; - parameter RX_EN_IDLE_RESET_BUF_0 = "TRUE"; - parameter RX_EN_IDLE_RESET_BUF_1 = "TRUE"; - parameter RX_EN_IDLE_RESET_FR_0 = "TRUE"; - parameter RX_EN_IDLE_RESET_FR_1 = "TRUE"; - parameter RX_EN_IDLE_RESET_PH_0 = "TRUE"; - parameter RX_EN_IDLE_RESET_PH_1 = "TRUE"; - parameter RX_EN_MODE_RESET_BUF_0 = "TRUE"; - parameter RX_EN_MODE_RESET_BUF_1 = "TRUE"; - parameter [3:0] RX_IDLE_HI_CNT_0 = 4'b1000; - parameter [3:0] RX_IDLE_HI_CNT_1 = 4'b1000; - parameter [3:0] RX_IDLE_LO_CNT_0 = 4'b0000; - parameter [3:0] RX_IDLE_LO_CNT_1 = 4'b0000; - parameter RX_LOSS_OF_SYNC_FSM_0 = "FALSE"; - parameter RX_LOSS_OF_SYNC_FSM_1 = "FALSE"; - parameter integer RX_LOS_INVALID_INCR_0 = 1; - parameter integer RX_LOS_INVALID_INCR_1 = 1; - parameter integer RX_LOS_THRESHOLD_0 = 4; - parameter integer RX_LOS_THRESHOLD_1 = 4; - parameter RX_SLIDE_MODE_0 = "PCS"; - parameter RX_SLIDE_MODE_1 = "PCS"; - parameter RX_STATUS_FMT_0 = "PCIE"; - parameter RX_STATUS_FMT_1 = "PCIE"; - parameter RX_XCLK_SEL_0 = "RXREC"; - parameter RX_XCLK_SEL_1 = "RXREC"; - parameter [2:0] SATA_BURST_VAL_0 = 3'b100; - parameter [2:0] SATA_BURST_VAL_1 = 3'b100; - parameter [2:0] SATA_IDLE_VAL_0 = 3'b011; - parameter [2:0] SATA_IDLE_VAL_1 = 3'b011; - parameter integer SATA_MAX_BURST_0 = 7; - parameter integer SATA_MAX_BURST_1 = 7; - parameter integer SATA_MAX_INIT_0 = 22; - parameter integer SATA_MAX_INIT_1 = 22; - parameter integer SATA_MAX_WAKE_0 = 7; - parameter integer SATA_MAX_WAKE_1 = 7; - parameter integer SATA_MIN_BURST_0 = 4; - parameter integer SATA_MIN_BURST_1 = 4; - parameter integer SATA_MIN_INIT_0 = 12; - parameter integer SATA_MIN_INIT_1 = 12; - parameter integer SATA_MIN_WAKE_0 = 4; - parameter integer SATA_MIN_WAKE_1 = 4; - parameter integer SIM_GTPRESET_SPEEDUP = 0; - parameter SIM_RECEIVER_DETECT_PASS = "FALSE"; - parameter [2:0] SIM_REFCLK0_SOURCE = 3'b000; - parameter [2:0] SIM_REFCLK1_SOURCE = 3'b000; - parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; - parameter SIM_VERSION = "2.0"; - parameter [4:0] TERMINATION_CTRL_0 = 5'b10100; - parameter [4:0] TERMINATION_CTRL_1 = 5'b10100; - parameter TERMINATION_OVRD_0 = "FALSE"; - parameter TERMINATION_OVRD_1 = "FALSE"; - parameter [11:0] TRANS_TIME_FROM_P2_0 = 12'h03C; - parameter [11:0] TRANS_TIME_FROM_P2_1 = 12'h03C; - parameter [7:0] TRANS_TIME_NON_P2_0 = 8'h19; - parameter [7:0] TRANS_TIME_NON_P2_1 = 8'h19; - parameter [9:0] TRANS_TIME_TO_P2_0 = 10'h064; - parameter [9:0] TRANS_TIME_TO_P2_1 = 10'h064; - parameter [31:0] TST_ATTR_0 = 32'h00000000; - parameter [31:0] TST_ATTR_1 = 32'h00000000; - parameter [2:0] TXRX_INVERT_0 = 3'b011; - parameter [2:0] TXRX_INVERT_1 = 3'b011; - parameter TX_BUFFER_USE_0 = "FALSE"; - parameter TX_BUFFER_USE_1 = "FALSE"; - parameter [13:0] TX_DETECT_RX_CFG_0 = 14'h1832; - parameter [13:0] TX_DETECT_RX_CFG_1 = 14'h1832; - parameter [2:0] TX_IDLE_DELAY_0 = 3'b011; - parameter [2:0] TX_IDLE_DELAY_1 = 3'b011; - parameter [1:0] TX_TDCC_CFG_0 = 2'b00; - parameter [1:0] TX_TDCC_CFG_1 = 2'b00; - parameter TX_XCLK_SEL_0 = "TXUSR"; - parameter TX_XCLK_SEL_1 = "TXUSR"; - output DRDY; - output PHYSTATUS0; - output PHYSTATUS1; - output PLLLKDET0; - output PLLLKDET1; - output REFCLKOUT0; - output REFCLKOUT1; - output REFCLKPLL0; - output REFCLKPLL1; - output RESETDONE0; - output RESETDONE1; - output RXBYTEISALIGNED0; - output RXBYTEISALIGNED1; - output RXBYTEREALIGN0; - output RXBYTEREALIGN1; - output RXCHANBONDSEQ0; - output RXCHANBONDSEQ1; - output RXCHANISALIGNED0; - output RXCHANISALIGNED1; - output RXCHANREALIGN0; - output RXCHANREALIGN1; - output RXCOMMADET0; - output RXCOMMADET1; - output RXELECIDLE0; - output RXELECIDLE1; - output RXPRBSERR0; - output RXPRBSERR1; - output RXRECCLK0; - output RXRECCLK1; - output RXVALID0; - output RXVALID1; - output TXN0; - output TXN1; - output TXOUTCLK0; - output TXOUTCLK1; - output TXP0; - output TXP1; - output [15:0] DRPDO; - output [1:0] GTPCLKFBEAST; - output [1:0] GTPCLKFBWEST; - output [1:0] GTPCLKOUT0; - output [1:0] GTPCLKOUT1; - output [1:0] RXLOSSOFSYNC0; - output [1:0] RXLOSSOFSYNC1; - output [1:0] TXBUFSTATUS0; - output [1:0] TXBUFSTATUS1; - output [2:0] RXBUFSTATUS0; - output [2:0] RXBUFSTATUS1; - output [2:0] RXCHBONDO; - output [2:0] RXCLKCORCNT0; - output [2:0] RXCLKCORCNT1; - output [2:0] RXSTATUS0; - output [2:0] RXSTATUS1; - output [31:0] RXDATA0; - output [31:0] RXDATA1; - output [3:0] RXCHARISCOMMA0; - output [3:0] RXCHARISCOMMA1; - output [3:0] RXCHARISK0; - output [3:0] RXCHARISK1; - output [3:0] RXDISPERR0; - output [3:0] RXDISPERR1; - output [3:0] RXNOTINTABLE0; - output [3:0] RXNOTINTABLE1; - output [3:0] RXRUNDISP0; - output [3:0] RXRUNDISP1; - output [3:0] TXKERR0; - output [3:0] TXKERR1; - output [3:0] TXRUNDISP0; - output [3:0] TXRUNDISP1; - output [4:0] RCALOUTEAST; - output [4:0] RCALOUTWEST; - output [4:0] TSTOUT0; - output [4:0] TSTOUT1; - input CLK00; - input CLK01; - input CLK10; - input CLK11; - input CLKINEAST0; - input CLKINEAST1; - input CLKINWEST0; - input CLKINWEST1; - input DCLK; - input DEN; - input DWE; - input GATERXELECIDLE0; - input GATERXELECIDLE1; - input GCLK00; - input GCLK01; - input GCLK10; - input GCLK11; - input GTPRESET0; - input GTPRESET1; - input IGNORESIGDET0; - input IGNORESIGDET1; - input INTDATAWIDTH0; - input INTDATAWIDTH1; - input PLLCLK00; - input PLLCLK01; - input PLLCLK10; - input PLLCLK11; - input PLLLKDETEN0; - input PLLLKDETEN1; - input PLLPOWERDOWN0; - input PLLPOWERDOWN1; - input PRBSCNTRESET0; - input PRBSCNTRESET1; - input REFCLKPWRDNB0; - input REFCLKPWRDNB1; - input RXBUFRESET0; - input RXBUFRESET1; - input RXCDRRESET0; - input RXCDRRESET1; - input RXCHBONDMASTER0; - input RXCHBONDMASTER1; - input RXCHBONDSLAVE0; - input RXCHBONDSLAVE1; - input RXCOMMADETUSE0; - input RXCOMMADETUSE1; - input RXDEC8B10BUSE0; - input RXDEC8B10BUSE1; - input RXENCHANSYNC0; - input RXENCHANSYNC1; - input RXENMCOMMAALIGN0; - input RXENMCOMMAALIGN1; - input RXENPCOMMAALIGN0; - input RXENPCOMMAALIGN1; - input RXENPMAPHASEALIGN0; - input RXENPMAPHASEALIGN1; - input RXN0; - input RXN1; - input RXP0; - input RXP1; - input RXPMASETPHASE0; - input RXPMASETPHASE1; - input RXPOLARITY0; - input RXPOLARITY1; - input RXRESET0; - input RXRESET1; - input RXSLIDE0; - input RXSLIDE1; - input RXUSRCLK0; - input RXUSRCLK1; - input RXUSRCLK20; - input RXUSRCLK21; - input TSTCLK0; - input TSTCLK1; - input TXCOMSTART0; - input TXCOMSTART1; - input TXCOMTYPE0; - input TXCOMTYPE1; - input TXDETECTRX0; - input TXDETECTRX1; - input TXELECIDLE0; - input TXELECIDLE1; - input TXENC8B10BUSE0; - input TXENC8B10BUSE1; - input TXENPMAPHASEALIGN0; - input TXENPMAPHASEALIGN1; - input TXINHIBIT0; - input TXINHIBIT1; - input TXPDOWNASYNCH0; - input TXPDOWNASYNCH1; - input TXPMASETPHASE0; - input TXPMASETPHASE1; - input TXPOLARITY0; - input TXPOLARITY1; - input TXPRBSFORCEERR0; - input TXPRBSFORCEERR1; - input TXRESET0; - input TXRESET1; - input TXUSRCLK0; - input TXUSRCLK1; - input TXUSRCLK20; - input TXUSRCLK21; - input USRCODEERR0; - input USRCODEERR1; - input [11:0] TSTIN0; - input [11:0] TSTIN1; - input [15:0] DI; - input [1:0] GTPCLKFBSEL0EAST; - input [1:0] GTPCLKFBSEL0WEST; - input [1:0] GTPCLKFBSEL1EAST; - input [1:0] GTPCLKFBSEL1WEST; - input [1:0] RXDATAWIDTH0; - input [1:0] RXDATAWIDTH1; - input [1:0] RXEQMIX0; - input [1:0] RXEQMIX1; - input [1:0] RXPOWERDOWN0; - input [1:0] RXPOWERDOWN1; - input [1:0] TXDATAWIDTH0; - input [1:0] TXDATAWIDTH1; - input [1:0] TXPOWERDOWN0; - input [1:0] TXPOWERDOWN1; - input [2:0] LOOPBACK0; - input [2:0] LOOPBACK1; - input [2:0] REFSELDYPLL0; - input [2:0] REFSELDYPLL1; - input [2:0] RXCHBONDI; - input [2:0] RXENPRBSTST0; - input [2:0] RXENPRBSTST1; - input [2:0] TXBUFDIFFCTRL0; - input [2:0] TXBUFDIFFCTRL1; - input [2:0] TXENPRBSTST0; - input [2:0] TXENPRBSTST1; - input [2:0] TXPREEMPHASIS0; - input [2:0] TXPREEMPHASIS1; - input [31:0] TXDATA0; - input [31:0] TXDATA1; - input [3:0] TXBYPASS8B10B0; - input [3:0] TXBYPASS8B10B1; - input [3:0] TXCHARDISPMODE0; - input [3:0] TXCHARDISPMODE1; - input [3:0] TXCHARDISPVAL0; - input [3:0] TXCHARDISPVAL1; - input [3:0] TXCHARISK0; - input [3:0] TXCHARISK1; - input [3:0] TXDIFFCTRL0; - input [3:0] TXDIFFCTRL1; - input [4:0] RCALINEAST; - input [4:0] RCALINWEST; - input [7:0] DADDR; - input [7:0] GTPTEST0; - input [7:0] GTPTEST1; -endmodule - -module IBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IFD_DELAY_VALUE = "AUTO"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFGDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFGDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IOBUF (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input T; -endmodule - -module IOBUFDS (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - inout IOB; - input I; - input T; -endmodule - -module IODELAY2 (...); - parameter COUNTER_WRAPAROUND = "WRAPAROUND"; - parameter DATA_RATE = "SDR"; - parameter DELAY_SRC = "IO"; - parameter integer IDELAY2_VALUE = 0; - parameter IDELAY_MODE = "NORMAL"; - parameter IDELAY_TYPE = "DEFAULT"; - parameter integer IDELAY_VALUE = 0; - parameter integer ODELAY_VALUE = 0; - parameter SERDES_MODE = "NONE"; - parameter integer SIM_TAPDELAY_VALUE = 75; - output BUSY; - output DATAOUT2; - output DATAOUT; - output DOUT; - output TOUT; - input CAL; - input CE; - (* clkbuf_sink *) - input CLK; - input IDATAIN; - input INC; - (* clkbuf_sink *) - input IOCLK0; - (* clkbuf_sink *) - input IOCLK1; - input ODATAIN; - input RST; - input T; -endmodule - -module IODRP2 (...); - parameter DATA_RATE = "SDR"; - parameter integer SIM_TAPDELAY_VALUE = 75; - output DATAOUT2; - output DATAOUT; - output DOUT; - output SDO; - output TOUT; - input ADD; - input BKST; - (* clkbuf_sink *) - input CLK; - input CS; - input IDATAIN; - (* clkbuf_sink *) - input IOCLK0; - (* clkbuf_sink *) - input IOCLK1; - input ODATAIN; - input SDI; - input T; -endmodule - -module IODRP2_MCB (...); - parameter DATA_RATE = "SDR"; - parameter integer IDELAY_VALUE = 0; - parameter integer MCB_ADDRESS = 0; - parameter integer ODELAY_VALUE = 0; - parameter SERDES_MODE = "NONE"; - parameter integer SIM_TAPDELAY_VALUE = 75; - output AUXSDO; - output DATAOUT2; - output DATAOUT; - output DOUT; - output DQSOUTN; - output DQSOUTP; - output SDO; - output TOUT; - input ADD; - input AUXSDOIN; - input BKST; - (* clkbuf_sink *) - input CLK; - input CS; - input IDATAIN; - (* clkbuf_sink *) - input IOCLK0; - (* clkbuf_sink *) - input IOCLK1; - input MEMUPDATE; - input ODATAIN; - input SDI; - input T; - input [4:0] AUXADDR; -endmodule - -module ISERDES2 (...); - parameter BITSLIP_ENABLE = "FALSE"; - parameter DATA_RATE = "SDR"; - parameter integer DATA_WIDTH = 1; - parameter INTERFACE_TYPE = "NETWORKING"; - parameter SERDES_MODE = "NONE"; - output CFB0; - output CFB1; - output DFB; - output FABRICOUT; - output INCDEC; - output Q1; - output Q2; - output Q3; - output Q4; - output SHIFTOUT; - output VALID; - input BITSLIP; - input CE0; - (* clkbuf_sink *) - input CLK0; - (* clkbuf_sink *) - input CLK1; - (* clkbuf_sink *) - input CLKDIV; - input D; - input IOCE; - input RST; - input SHIFTIN; -endmodule - -module KEEPER (...); - inout O; -endmodule - -module OBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; -endmodule - -module OBUFT (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter integer DRIVE = 12; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - input I; - input T; -endmodule - -module OBUFTDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; - input T; -endmodule - -module OSERDES2 (...); - parameter BYPASS_GCLK_FF = "FALSE"; - parameter DATA_RATE_OQ = "DDR"; - parameter DATA_RATE_OT = "DDR"; - parameter integer DATA_WIDTH = 2; - parameter OUTPUT_MODE = "SINGLE_ENDED"; - parameter SERDES_MODE = "NONE"; - parameter integer TRAIN_PATTERN = 0; - output OQ; - output SHIFTOUT1; - output SHIFTOUT2; - output SHIFTOUT3; - output SHIFTOUT4; - output TQ; - (* clkbuf_sink *) - input CLK0; - (* clkbuf_sink *) - input CLK1; - (* clkbuf_sink *) - input CLKDIV; - input D1; - input D2; - input D3; - input D4; - input IOCE; - input OCE; - input RST; - input SHIFTIN1; - input SHIFTIN2; - input SHIFTIN3; - input SHIFTIN4; - input T1; - input T2; - input T3; - input T4; - input TCE; - input TRAIN; -endmodule - -module PULLDOWN (...); - output O; -endmodule - -module PULLUP (...); - output O; -endmodule - -module RAM128X1S (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM256X1S (...); - parameter [255:0] INIT = 256'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input [7:0] A; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [1:0] DOA; - output [1:0] DOB; - output [1:0] DOC; - output [1:0] DOD; - input [4:0] ADDRA; - input [4:0] ADDRB; - input [4:0] ADDRC; - input [4:0] ADDRD; - input [1:0] DIA; - input [1:0] DIB; - input [1:0] DIC; - input [1:0] DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S_1 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X2S (...); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input A4; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DOA; - output DOB; - output DOC; - output DOD; - input [5:0] ADDRA; - input [5:0] ADDRB; - input [5:0] ADDRC; - input [5:0] ADDRD; - input DIA; - input DIB; - input DIC; - input DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S_1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X2S (...); - parameter [63:0] INIT_00 = 64'h0000000000000000; - parameter [63:0] INIT_01 = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module ROM128X1 (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; -endmodule - -module ROM256X1 (...); - parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input A7; -endmodule - -module ROM32X1 (...); - parameter [31:0] INIT = 32'h00000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; -endmodule - -module ROM64X1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; -endmodule - -module IDDR2 (...); - parameter DDR_ALIGNMENT = "NONE"; - parameter [0:0] INIT_Q0 = 1'b0; - parameter [0:0] INIT_Q1 = 1'b0; - parameter SRTYPE = "SYNC"; - output Q0; - output Q1; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input D; - input R; - input S; -endmodule - -module ODDR2 (...); - parameter DDR_ALIGNMENT = "NONE"; - parameter [0:0] INIT = 1'b0; - parameter SRTYPE = "SYNC"; - output Q; - (* clkbuf_sink *) - input C0; - (* clkbuf_sink *) - input C1; - input CE; - input D0; - input D1; - input R; - input S; -endmodule - -module CFGLUT5 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - output CDO; - output O5; - output O6; - input I4; - input I3; - input I2; - input I1; - input I0; - input CDI; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; -endmodule - diff --git a/techlibs/xilinx/xc6v_cells_xtra.v b/techlibs/xilinx/xc6v_cells_xtra.v deleted file mode 100644 index 87656fa49..000000000 --- a/techlibs/xilinx/xc6v_cells_xtra.v +++ /dev/null @@ -1,2592 +0,0 @@ -// Created by cells_xtra.py from Xilinx models - -module PCIE_2_0 (...); - parameter [11:0] AER_BASE_PTR = 12'h128; - parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [15:0] AER_CAP_ID = 16'h0001; - parameter [4:0] AER_CAP_INT_MSG_NUM_MSI = 5'h0A; - parameter [4:0] AER_CAP_INT_MSG_NUM_MSIX = 5'h15; - parameter [11:0] AER_CAP_NEXTPTR = 12'h160; - parameter AER_CAP_ON = "FALSE"; - parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; - parameter [3:0] AER_CAP_VERSION = 4'h1; - parameter ALLOW_X8_GEN2 = "FALSE"; - parameter [31:0] BAR0 = 32'hFFFFFF00; - parameter [31:0] BAR1 = 32'hFFFF0000; - parameter [31:0] BAR2 = 32'hFFFF000C; - parameter [31:0] BAR3 = 32'hFFFFFFFF; - parameter [31:0] BAR4 = 32'h00000000; - parameter [31:0] BAR5 = 32'h00000000; - parameter [7:0] CAPABILITIES_PTR = 8'h40; - parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; - parameter [23:0] CLASS_CODE = 24'h000000; - parameter CMD_INTX_IMPLEMENTED = "TRUE"; - parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; - parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; - parameter [6:0] CRM_MODULE_RSTS = 7'h00; - parameter [15:0] DEVICE_ID = 16'h0007; - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; - parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; - parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; - parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; - parameter integer DEV_CAP_RSVD_14_12 = 0; - parameter integer DEV_CAP_RSVD_17_16 = 0; - parameter integer DEV_CAP_RSVD_31_29 = 0; - parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; - parameter DISABLE_ASPM_L1_TIMER = "FALSE"; - parameter DISABLE_BAR_FILTERING = "FALSE"; - parameter DISABLE_ID_CHECK = "FALSE"; - parameter DISABLE_LANE_REVERSAL = "FALSE"; - parameter DISABLE_RX_TC_FILTER = "FALSE"; - parameter DISABLE_SCRAMBLING = "FALSE"; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter [11:0] DSN_BASE_PTR = 12'h100; - parameter [15:0] DSN_CAP_ID = 16'h0003; - parameter [11:0] DSN_CAP_NEXTPTR = 12'h000; - parameter DSN_CAP_ON = "TRUE"; - parameter [3:0] DSN_CAP_VERSION = 4'h1; - parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; - parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; - parameter ENTER_RVRY_EI_L0 = "TRUE"; - parameter EXIT_LOOPBACK_ON_EI = "TRUE"; - parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; - parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; - parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; - parameter [7:0] HEADER_TYPE = 8'h00; - parameter [4:0] INFER_EI = 5'h00; - parameter [7:0] INTERRUPT_PIN = 8'h01; - parameter IS_SWITCH = "FALSE"; - parameter [9:0] LAST_CONFIG_DWORD = 10'h042; - parameter integer LINK_CAP_ASPM_SUPPORT = 1; - parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; - parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; - parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; - parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; - parameter integer LINK_CAP_RSVD_23_22 = 0; - parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; - parameter integer LINK_CONTROL_RCB = 0; - parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; - parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; - parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; - parameter [7:0] MSIX_BASE_PTR = 8'h9C; - parameter [7:0] MSIX_CAP_ID = 8'h11; - parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; - parameter MSIX_CAP_ON = "FALSE"; - parameter integer MSIX_CAP_PBA_BIR = 0; - parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] MSI_BASE_PTR = 8'h48; - parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; - parameter [7:0] MSI_CAP_ID = 8'h05; - parameter integer MSI_CAP_MULTIMSGCAP = 0; - parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; - parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; - parameter MSI_CAP_ON = "FALSE"; - parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; - parameter integer N_FTS_COMCLK_GEN1 = 255; - parameter integer N_FTS_COMCLK_GEN2 = 255; - parameter integer N_FTS_GEN1 = 255; - parameter integer N_FTS_GEN2 = 255; - parameter [7:0] PCIE_BASE_PTR = 8'h60; - parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; - parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; - parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; - parameter [4:0] PCIE_CAP_INT_MSG_NUM = 5'h00; - parameter [7:0] PCIE_CAP_NEXTPTR = 8'h00; - parameter PCIE_CAP_ON = "TRUE"; - parameter integer PCIE_CAP_RSVD_15_14 = 0; - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; - parameter integer PCIE_REVISION = 2; - parameter integer PGL0_LANE = 0; - parameter integer PGL1_LANE = 1; - parameter integer PGL2_LANE = 2; - parameter integer PGL3_LANE = 3; - parameter integer PGL4_LANE = 4; - parameter integer PGL5_LANE = 5; - parameter integer PGL6_LANE = 6; - parameter integer PGL7_LANE = 7; - parameter integer PL_AUTO_CONFIG = 0; - parameter PL_FAST_TRAIN = "FALSE"; - parameter [7:0] PM_BASE_PTR = 8'h40; - parameter integer PM_CAP_AUXCURRENT = 0; - parameter PM_CAP_D1SUPPORT = "TRUE"; - parameter PM_CAP_D2SUPPORT = "TRUE"; - parameter PM_CAP_DSI = "FALSE"; - parameter [7:0] PM_CAP_ID = 8'h01; - parameter [7:0] PM_CAP_NEXTPTR = 8'h48; - parameter PM_CAP_ON = "TRUE"; - parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; - parameter PM_CAP_PME_CLOCK = "FALSE"; - parameter integer PM_CAP_RSVD_04 = 0; - parameter integer PM_CAP_VERSION = 3; - parameter PM_CSR_B2B3 = "FALSE"; - parameter PM_CSR_BPCCEN = "FALSE"; - parameter PM_CSR_NOSOFTRST = "TRUE"; - parameter [7:0] PM_DATA0 = 8'h01; - parameter [7:0] PM_DATA1 = 8'h01; - parameter [7:0] PM_DATA2 = 8'h01; - parameter [7:0] PM_DATA3 = 8'h01; - parameter [7:0] PM_DATA4 = 8'h01; - parameter [7:0] PM_DATA5 = 8'h01; - parameter [7:0] PM_DATA6 = 8'h01; - parameter [7:0] PM_DATA7 = 8'h01; - parameter [1:0] PM_DATA_SCALE0 = 2'h1; - parameter [1:0] PM_DATA_SCALE1 = 2'h1; - parameter [1:0] PM_DATA_SCALE2 = 2'h1; - parameter [1:0] PM_DATA_SCALE3 = 2'h1; - parameter [1:0] PM_DATA_SCALE4 = 2'h1; - parameter [1:0] PM_DATA_SCALE5 = 2'h1; - parameter [1:0] PM_DATA_SCALE6 = 2'h1; - parameter [1:0] PM_DATA_SCALE7 = 2'h1; - parameter integer RECRC_CHK = 0; - parameter RECRC_CHK_TRIM = "FALSE"; - parameter [7:0] REVISION_ID = 8'h00; - parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; - parameter SELECT_DLL_IF = "FALSE"; - parameter SIM_VERSION = "1.0"; - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; - parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; - parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; - parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; - parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; - parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; - parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; - parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; - parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; - parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; - parameter integer SPARE_BIT0 = 0; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter integer SPARE_BIT3 = 0; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter [15:0] SUBSYSTEM_ID = 16'h0007; - parameter [15:0] SUBSYSTEM_VENDOR_ID = 16'h10EE; - parameter TL_RBYPASS = "FALSE"; - parameter integer TL_RX_RAM_RADDR_LATENCY = 0; - parameter integer TL_RX_RAM_RDATA_LATENCY = 2; - parameter integer TL_RX_RAM_WRITE_LATENCY = 0; - parameter TL_TFC_DISABLE = "FALSE"; - parameter TL_TX_CHECKS_DISABLE = "FALSE"; - parameter integer TL_TX_RAM_RADDR_LATENCY = 0; - parameter integer TL_TX_RAM_RDATA_LATENCY = 2; - parameter integer TL_TX_RAM_WRITE_LATENCY = 0; - parameter UPCONFIG_CAPABLE = "TRUE"; - parameter UPSTREAM_FACING = "TRUE"; - parameter UR_INV_REQ = "TRUE"; - parameter integer USER_CLK_FREQ = 3; - parameter VC0_CPL_INFINITE = "TRUE"; - parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; - parameter integer VC0_TOTAL_CREDITS_CD = 127; - parameter integer VC0_TOTAL_CREDITS_CH = 31; - parameter integer VC0_TOTAL_CREDITS_NPH = 12; - parameter integer VC0_TOTAL_CREDITS_PD = 288; - parameter integer VC0_TOTAL_CREDITS_PH = 32; - parameter integer VC0_TX_LASTPACKET = 31; - parameter [11:0] VC_BASE_PTR = 12'h10C; - parameter [15:0] VC_CAP_ID = 16'h0002; - parameter [11:0] VC_CAP_NEXTPTR = 12'h000; - parameter VC_CAP_ON = "FALSE"; - parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; - parameter [3:0] VC_CAP_VERSION = 4'h1; - parameter [15:0] VENDOR_ID = 16'h10EE; - parameter [11:0] VSEC_BASE_PTR = 12'h160; - parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; - parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; - parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; - parameter [15:0] VSEC_CAP_ID = 16'h000B; - parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; - parameter [11:0] VSEC_CAP_NEXTPTR = 12'h000; - parameter VSEC_CAP_ON = "FALSE"; - parameter [3:0] VSEC_CAP_VERSION = 4'h1; - output CFGAERECRCCHECKEN; - output CFGAERECRCGENEN; - output CFGCOMMANDBUSMASTERENABLE; - output CFGCOMMANDINTERRUPTDISABLE; - output CFGCOMMANDIOENABLE; - output CFGCOMMANDMEMENABLE; - output CFGCOMMANDSERREN; - output CFGDEVCONTROL2CPLTIMEOUTDIS; - output CFGDEVCONTROLAUXPOWEREN; - output CFGDEVCONTROLCORRERRREPORTINGEN; - output CFGDEVCONTROLENABLERO; - output CFGDEVCONTROLEXTTAGEN; - output CFGDEVCONTROLFATALERRREPORTINGEN; - output CFGDEVCONTROLNONFATALREPORTINGEN; - output CFGDEVCONTROLNOSNOOPEN; - output CFGDEVCONTROLPHANTOMEN; - output CFGDEVCONTROLURERRREPORTINGEN; - output CFGDEVSTATUSCORRERRDETECTED; - output CFGDEVSTATUSFATALERRDETECTED; - output CFGDEVSTATUSNONFATALERRDETECTED; - output CFGDEVSTATUSURDETECTED; - output CFGERRAERHEADERLOGSETN; - output CFGERRCPLRDYN; - output CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIXENABLE; - output CFGINTERRUPTMSIXFM; - output CFGINTERRUPTRDYN; - output CFGLINKCONTROLAUTOBANDWIDTHINTEN; - output CFGLINKCONTROLBANDWIDTHINTEN; - output CFGLINKCONTROLCLOCKPMEN; - output CFGLINKCONTROLCOMMONCLOCK; - output CFGLINKCONTROLEXTENDEDSYNC; - output CFGLINKCONTROLHWAUTOWIDTHDIS; - output CFGLINKCONTROLLINKDISABLE; - output CFGLINKCONTROLRCB; - output CFGLINKCONTROLRETRAINLINK; - output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; - output CFGLINKSTATUSBANDWITHSTATUS; - output CFGLINKSTATUSDLLACTIVE; - output CFGLINKSTATUSLINKTRAINING; - output CFGMSGRECEIVED; - output CFGMSGRECEIVEDASSERTINTA; - output CFGMSGRECEIVEDASSERTINTB; - output CFGMSGRECEIVEDASSERTINTC; - output CFGMSGRECEIVEDASSERTINTD; - output CFGMSGRECEIVEDDEASSERTINTA; - output CFGMSGRECEIVEDDEASSERTINTB; - output CFGMSGRECEIVEDDEASSERTINTC; - output CFGMSGRECEIVEDDEASSERTINTD; - output CFGMSGRECEIVEDERRCOR; - output CFGMSGRECEIVEDERRFATAL; - output CFGMSGRECEIVEDERRNONFATAL; - output CFGMSGRECEIVEDPMASNAK; - output CFGMSGRECEIVEDPMETO; - output CFGMSGRECEIVEDPMETOACK; - output CFGMSGRECEIVEDPMPME; - output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; - output CFGMSGRECEIVEDUNLOCK; - output CFGPMCSRPMEEN; - output CFGPMCSRPMESTATUS; - output CFGPMRCVASREQL1N; - output CFGPMRCVENTERL1N; - output CFGPMRCVENTERL23N; - output CFGPMRCVREQACKN; - output CFGRDWRDONEN; - output CFGSLOTCONTROLELECTROMECHILCTLPULSE; - output CFGTRANSACTION; - output CFGTRANSACTIONTYPE; - output DBGSCLRA; - output DBGSCLRB; - output DBGSCLRC; - output DBGSCLRD; - output DBGSCLRE; - output DBGSCLRF; - output DBGSCLRG; - output DBGSCLRH; - output DBGSCLRI; - output DBGSCLRJ; - output DBGSCLRK; - output DRPDRDY; - output LL2BADDLLPERRN; - output LL2BADTLPERRN; - output LL2PROTOCOLERRN; - output LL2REPLAYROERRN; - output LL2REPLAYTOERRN; - output LL2SUSPENDOKN; - output LL2TFCINIT1SEQN; - output LL2TFCINIT2SEQN; - output LNKCLKEN; - output MIMRXRCE; - output MIMRXREN; - output MIMRXWEN; - output MIMTXRCE; - output MIMTXREN; - output MIMTXWEN; - output PIPERX0POLARITY; - output PIPERX1POLARITY; - output PIPERX2POLARITY; - output PIPERX3POLARITY; - output PIPERX4POLARITY; - output PIPERX5POLARITY; - output PIPERX6POLARITY; - output PIPERX7POLARITY; - output PIPETX0COMPLIANCE; - output PIPETX0ELECIDLE; - output PIPETX1COMPLIANCE; - output PIPETX1ELECIDLE; - output PIPETX2COMPLIANCE; - output PIPETX2ELECIDLE; - output PIPETX3COMPLIANCE; - output PIPETX3ELECIDLE; - output PIPETX4COMPLIANCE; - output PIPETX4ELECIDLE; - output PIPETX5COMPLIANCE; - output PIPETX5ELECIDLE; - output PIPETX6COMPLIANCE; - output PIPETX6ELECIDLE; - output PIPETX7COMPLIANCE; - output PIPETX7ELECIDLE; - output PIPETXDEEMPH; - output PIPETXRATE; - output PIPETXRCVRDET; - output PIPETXRESET; - output PL2LINKUPN; - output PL2RECEIVERERRN; - output PL2RECOVERYN; - output PL2RXELECIDLE; - output PL2SUSPENDOK; - output PLLINKGEN2CAP; - output PLLINKPARTNERGEN2SUPPORTED; - output PLLINKUPCFGCAP; - output PLPHYLNKUPN; - output PLRECEIVEDHOTRST; - output PLSELLNKRATE; - output RECEIVEDFUNCLVLRSTN; - output TL2ASPMSUSPENDCREDITCHECKOKN; - output TL2ASPMSUSPENDREQN; - output TL2PPMSUSPENDOKN; - output TRNLNKUPN; - output TRNRDLLPSRCRDYN; - output TRNRECRCERRN; - output TRNREOFN; - output TRNRERRFWDN; - output TRNRREMN; - output TRNRSOFN; - output TRNRSRCDSCN; - output TRNRSRCRDYN; - output TRNTCFGREQN; - output TRNTDLLPDSTRDYN; - output TRNTDSTRDYN; - output TRNTERRDROPN; - output USERRSTN; - output [11:0] DBGVECC; - output [11:0] PLDBGVEC; - output [11:0] TRNFCCPLD; - output [11:0] TRNFCNPD; - output [11:0] TRNFCPD; - output [12:0] MIMRXRADDR; - output [12:0] MIMRXWADDR; - output [12:0] MIMTXRADDR; - output [12:0] MIMTXWADDR; - output [15:0] CFGMSGDATA; - output [15:0] DRPDO; - output [15:0] PIPETX0DATA; - output [15:0] PIPETX1DATA; - output [15:0] PIPETX2DATA; - output [15:0] PIPETX3DATA; - output [15:0] PIPETX4DATA; - output [15:0] PIPETX5DATA; - output [15:0] PIPETX6DATA; - output [15:0] PIPETX7DATA; - output [1:0] CFGLINKCONTROLASPMCONTROL; - output [1:0] CFGLINKSTATUSCURRENTSPEED; - output [1:0] CFGPMCSRPOWERSTATE; - output [1:0] PIPETX0CHARISK; - output [1:0] PIPETX0POWERDOWN; - output [1:0] PIPETX1CHARISK; - output [1:0] PIPETX1POWERDOWN; - output [1:0] PIPETX2CHARISK; - output [1:0] PIPETX2POWERDOWN; - output [1:0] PIPETX3CHARISK; - output [1:0] PIPETX3POWERDOWN; - output [1:0] PIPETX4CHARISK; - output [1:0] PIPETX4POWERDOWN; - output [1:0] PIPETX5CHARISK; - output [1:0] PIPETX5POWERDOWN; - output [1:0] PIPETX6CHARISK; - output [1:0] PIPETX6POWERDOWN; - output [1:0] PIPETX7CHARISK; - output [1:0] PIPETX7POWERDOWN; - output [1:0] PLLANEREVERSALMODE; - output [1:0] PLRXPMSTATE; - output [1:0] PLSELLNKWIDTH; - output [2:0] CFGDEVCONTROLMAXPAYLOAD; - output [2:0] CFGDEVCONTROLMAXREADREQ; - output [2:0] CFGINTERRUPTMMENABLE; - output [2:0] CFGPCIELINKSTATE; - output [2:0] PIPETXMARGIN; - output [2:0] PLINITIALLINKWIDTH; - output [2:0] PLTXPMSTATE; - output [31:0] CFGDO; - output [31:0] TRNRDLLPDATA; - output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; - output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; - output [5:0] PLLTSSMSTATE; - output [5:0] TRNTBUFAV; - output [63:0] DBGVECA; - output [63:0] DBGVECB; - output [63:0] TRNRD; - output [67:0] MIMRXWDATA; - output [68:0] MIMTXWDATA; - output [6:0] CFGTRANSACTIONADDR; - output [6:0] CFGVCTCVCMAP; - output [6:0] TRNRBARHITN; - output [7:0] CFGINTERRUPTDO; - output [7:0] TRNFCCPLH; - output [7:0] TRNFCNPH; - output [7:0] TRNFCPH; - input CFGERRACSN; - input CFGERRCORN; - input CFGERRCPLABORTN; - input CFGERRCPLTIMEOUTN; - input CFGERRCPLUNEXPECTN; - input CFGERRECRCN; - input CFGERRLOCKEDN; - input CFGERRPOSTEDN; - input CFGERRURN; - input CFGINTERRUPTASSERTN; - input CFGINTERRUPTN; - input CFGPMDIRECTASPML1N; - input CFGPMSENDPMACKN; - input CFGPMSENDPMETON; - input CFGPMSENDPMNAKN; - input CFGPMTURNOFFOKN; - input CFGPMWAKEN; - input CFGRDENN; - input CFGTRNPENDINGN; - input CFGWRENN; - input CFGWRREADONLYN; - input CFGWRRW1CASRWN; - input CMRSTN; - input CMSTICKYRSTN; - input DBGSUBMODE; - input DLRSTN; - input DRPCLK; - input DRPDEN; - input DRPDWE; - input FUNCLVLRSTN; - input LL2SENDASREQL1N; - input LL2SENDENTERL1N; - input LL2SENDENTERL23N; - input LL2SUSPENDNOWN; - input LL2TLPRCVN; - input PIPECLK; - input PIPERX0CHANISALIGNED; - input PIPERX0ELECIDLE; - input PIPERX0PHYSTATUS; - input PIPERX0VALID; - input PIPERX1CHANISALIGNED; - input PIPERX1ELECIDLE; - input PIPERX1PHYSTATUS; - input PIPERX1VALID; - input PIPERX2CHANISALIGNED; - input PIPERX2ELECIDLE; - input PIPERX2PHYSTATUS; - input PIPERX2VALID; - input PIPERX3CHANISALIGNED; - input PIPERX3ELECIDLE; - input PIPERX3PHYSTATUS; - input PIPERX3VALID; - input PIPERX4CHANISALIGNED; - input PIPERX4ELECIDLE; - input PIPERX4PHYSTATUS; - input PIPERX4VALID; - input PIPERX5CHANISALIGNED; - input PIPERX5ELECIDLE; - input PIPERX5PHYSTATUS; - input PIPERX5VALID; - input PIPERX6CHANISALIGNED; - input PIPERX6ELECIDLE; - input PIPERX6PHYSTATUS; - input PIPERX6VALID; - input PIPERX7CHANISALIGNED; - input PIPERX7ELECIDLE; - input PIPERX7PHYSTATUS; - input PIPERX7VALID; - input PLDIRECTEDLINKAUTON; - input PLDIRECTEDLINKSPEED; - input PLDOWNSTREAMDEEMPHSOURCE; - input PLRSTN; - input PLTRANSMITHOTRST; - input PLUPSTREAMPREFERDEEMPH; - input SYSRSTN; - input TL2ASPMSUSPENDCREDITCHECKN; - input TL2PPMSUSPENDREQN; - input TLRSTN; - input TRNRDSTRDYN; - input TRNRNPOKN; - input TRNTCFGGNTN; - input TRNTDLLPSRCRDYN; - input TRNTECRCGENN; - input TRNTEOFN; - input TRNTERRFWDN; - input TRNTREMN; - input TRNTSOFN; - input TRNTSRCDSCN; - input TRNTSRCRDYN; - input TRNTSTRN; - input USERCLK; - input [127:0] CFGERRAERHEADERLOG; - input [15:0] DRPDI; - input [15:0] PIPERX0DATA; - input [15:0] PIPERX1DATA; - input [15:0] PIPERX2DATA; - input [15:0] PIPERX3DATA; - input [15:0] PIPERX4DATA; - input [15:0] PIPERX5DATA; - input [15:0] PIPERX6DATA; - input [15:0] PIPERX7DATA; - input [1:0] DBGMODE; - input [1:0] PIPERX0CHARISK; - input [1:0] PIPERX1CHARISK; - input [1:0] PIPERX2CHARISK; - input [1:0] PIPERX3CHARISK; - input [1:0] PIPERX4CHARISK; - input [1:0] PIPERX5CHARISK; - input [1:0] PIPERX6CHARISK; - input [1:0] PIPERX7CHARISK; - input [1:0] PLDIRECTEDLINKCHANGE; - input [1:0] PLDIRECTEDLINKWIDTH; - input [2:0] CFGDSFUNCTIONNUMBER; - input [2:0] PIPERX0STATUS; - input [2:0] PIPERX1STATUS; - input [2:0] PIPERX2STATUS; - input [2:0] PIPERX3STATUS; - input [2:0] PIPERX4STATUS; - input [2:0] PIPERX5STATUS; - input [2:0] PIPERX6STATUS; - input [2:0] PIPERX7STATUS; - input [2:0] PLDBGMODE; - input [2:0] TRNFCSEL; - input [31:0] CFGDI; - input [31:0] TRNTDLLPDATA; - input [3:0] CFGBYTEENN; - input [47:0] CFGERRTLPCPLHEADER; - input [4:0] CFGDSDEVICENUMBER; - input [4:0] PL2DIRECTEDLSTATE; - input [63:0] CFGDSN; - input [63:0] TRNTD; - input [67:0] MIMRXRDATA; - input [68:0] MIMTXRDATA; - input [7:0] CFGDSBUSNUMBER; - input [7:0] CFGINTERRUPTDI; - input [7:0] CFGPORTNUMBER; - input [8:0] DRPDADDR; - input [9:0] CFGDWADDR; -endmodule - -module SYSMON (...); - parameter [15:0] INIT_40 = 16'h0; - parameter [15:0] INIT_41 = 16'h0; - parameter [15:0] INIT_42 = 16'h0800; - parameter [15:0] INIT_43 = 16'h0; - parameter [15:0] INIT_44 = 16'h0; - parameter [15:0] INIT_45 = 16'h0; - parameter [15:0] INIT_46 = 16'h0; - parameter [15:0] INIT_47 = 16'h0; - parameter [15:0] INIT_48 = 16'h0; - parameter [15:0] INIT_49 = 16'h0; - parameter [15:0] INIT_4A = 16'h0; - parameter [15:0] INIT_4B = 16'h0; - parameter [15:0] INIT_4C = 16'h0; - parameter [15:0] INIT_4D = 16'h0; - parameter [15:0] INIT_4E = 16'h0; - parameter [15:0] INIT_4F = 16'h0; - parameter [15:0] INIT_50 = 16'h0; - parameter [15:0] INIT_51 = 16'h0; - parameter [15:0] INIT_52 = 16'h0; - parameter [15:0] INIT_53 = 16'h0; - parameter [15:0] INIT_54 = 16'h0; - parameter [15:0] INIT_55 = 16'h0; - parameter [15:0] INIT_56 = 16'h0; - parameter [15:0] INIT_57 = 16'h0; - parameter SIM_DEVICE = "VIRTEX5"; - parameter SIM_MONITOR_FILE = "design.txt"; - output BUSY; - output DRDY; - output EOC; - output EOS; - output JTAGBUSY; - output JTAGLOCKED; - output JTAGMODIFIED; - output OT; - output [15:0] DO; - output [2:0] ALM; - output [4:0] CHANNEL; - input CONVST; - input CONVSTCLK; - input DCLK; - input DEN; - input DWE; - input RESET; - input VN; - input VP; - input [15:0] DI; - input [15:0] VAUXN; - input [15:0] VAUXP; - input [6:0] DADDR; -endmodule - -module BUFGCE (...); - parameter CE_TYPE = "SYNC"; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_I_INVERTED = 1'b0; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_I_INVERTED" *) - input I; -endmodule - -module BUFGCE_1 (...); - (* clkbuf_driver *) - output O; - input CE; - input I; -endmodule - -module BUFGMUX (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_1 (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_CTRL (...); - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFH (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFIO (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFIODQS (...); - parameter DQSMASK_ENABLE = "FALSE"; - (* clkbuf_driver *) - output O; - input DQSMASK; - input I; -endmodule - -module BUFR (...); - parameter BUFR_DIVIDE = "BYPASS"; - parameter SIM_DEVICE = "7SERIES"; - (* clkbuf_driver *) - output O; - input CE; - input CLR; - input I; -endmodule - -module IBUFDS_GTXE1 (...); - parameter CLKCM_CFG = "TRUE"; - parameter CLKRCV_TRST = "TRUE"; - parameter [9:0] REFCLKOUT_DLY = 10'b0000000000; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module MMCM_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter CLOCK_HOLD = "FALSE"; - parameter COMPENSATION = "ZHOLD"; - parameter STARTUP_WAIT = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter integer CLKOUT2_DIVIDE = 1; - parameter integer CLKOUT3_DIVIDE = 1; - parameter integer CLKOUT4_DIVIDE = 1; - parameter integer CLKOUT5_DIVIDE = 1; - parameter integer CLKOUT6_DIVIDE = 1; - parameter integer DIVCLK_DIVIDE = 1; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter real VCOCLK_FREQ_MAX = 1600.0; - parameter real VCOCLK_FREQ_MIN = 600.0; - parameter real CLKIN_FREQ_MAX = 800.0; - parameter real CLKIN_FREQ_MIN = 10.0; - parameter real CLKPFD_FREQ_MAX = 550.0; - parameter real CLKPFD_FREQ_MIN = 10.0; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output DRDY; - output LOCKED; - output PSDONE; - output [15:0] DO; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - input CLKINSEL; - input DCLK; - input DEN; - input DWE; - input PSCLK; - input PSEN; - input PSINCDEC; - input PWRDWN; - input RST; - input [15:0] DI; - input [6:0] DADDR; -endmodule - -module MMCM_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLOCK_HOLD = "FALSE"; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - input CLKFBIN; - input CLKIN1; - input PWRDWN; - input RST; -endmodule - -(* keep *) -module BSCAN_VIRTEX6 (...); - parameter DISABLE_JTAG = "FALSE"; - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output RUNTEST; - output SEL; - output SHIFT; - output TCK; - output TDI; - output TMS; - output UPDATE; - input TDO; -endmodule - -(* keep *) -module CAPTURE_VIRTEX6 (...); - parameter ONESHOT = "TRUE"; - input CAP; - input CLK; -endmodule - -module DNA_PORT (...); - parameter [56:0] SIM_DNA_VALUE = 57'h0; - output DOUT; - input CLK; - input DIN; - input READ; - input SHIFT; -endmodule - -module EFUSE_USR (...); - parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; - output [31:0] EFUSEUSR; -endmodule - -module FRAME_ECC_VIRTEX6 (...); - parameter FARSRC = "EFAR"; - parameter FRAME_RBT_IN_FILENAME = "NONE"; - output CRCERROR; - output ECCERROR; - output ECCERRORSINGLE; - output SYNDROMEVALID; - output [12:0] SYNDROME; - output [23:0] FAR; - output [4:0] SYNBIT; - output [6:0] SYNWORD; -endmodule - -(* keep *) -module ICAP_VIRTEX6 (...); - parameter [31:0] DEVICE_ID = 32'h04244093; - parameter ICAP_WIDTH = "X8"; - parameter SIM_CFG_FILE_NAME = "NONE"; - output BUSY; - output [31:0] O; - input CLK; - input CSB; - input RDWRB; - input [31:0] I; -endmodule - -(* keep *) -module STARTUP_VIRTEX6 (...); - parameter PROG_USR = "FALSE"; - output CFGCLK; - output CFGMCLK; - output DINSPI; - output EOS; - output PREQ; - output TCKSPI; - input CLK; - input GSR; - input GTS; - input KEYCLEARB; - input PACK; - input USRCCLKO; - input USRCCLKTS; - input USRDONEO; - input USRDONETS; -endmodule - -module USR_ACCESS_VIRTEX6 (...); - output CFGCLK; - output [31:0] DATA; - output DATAVALID; -endmodule - -(* keep *) -module DCIRESET (...); - output LOCKED; - input RST; -endmodule - -module GTHE1_QUAD (...); - parameter [15:0] BER_CONST_PTRN0 = 16'h0000; - parameter [15:0] BER_CONST_PTRN1 = 16'h0000; - parameter [15:0] BUFFER_CONFIG_LANE0 = 16'h4004; - parameter [15:0] BUFFER_CONFIG_LANE1 = 16'h4004; - parameter [15:0] BUFFER_CONFIG_LANE2 = 16'h4004; - parameter [15:0] BUFFER_CONFIG_LANE3 = 16'h4004; - parameter [15:0] DFE_TRAIN_CTRL_LANE0 = 16'h0000; - parameter [15:0] DFE_TRAIN_CTRL_LANE1 = 16'h0000; - parameter [15:0] DFE_TRAIN_CTRL_LANE2 = 16'h0000; - parameter [15:0] DFE_TRAIN_CTRL_LANE3 = 16'h0000; - parameter [15:0] DLL_CFG0 = 16'h8202; - parameter [15:0] DLL_CFG1 = 16'h0000; - parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE0 = 16'h0000; - parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE1 = 16'h0000; - parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE2 = 16'h0000; - parameter [15:0] E10GBASEKR_LD_COEFF_UPD_LANE3 = 16'h0000; - parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE0 = 16'h0000; - parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE1 = 16'h0000; - parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE2 = 16'h0000; - parameter [15:0] E10GBASEKR_LP_COEFF_UPD_LANE3 = 16'h0000; - parameter [15:0] E10GBASEKR_PMA_CTRL_LANE0 = 16'h0002; - parameter [15:0] E10GBASEKR_PMA_CTRL_LANE1 = 16'h0002; - parameter [15:0] E10GBASEKR_PMA_CTRL_LANE2 = 16'h0002; - parameter [15:0] E10GBASEKR_PMA_CTRL_LANE3 = 16'h0002; - parameter [15:0] E10GBASEKX_CTRL_LANE0 = 16'h0000; - parameter [15:0] E10GBASEKX_CTRL_LANE1 = 16'h0000; - parameter [15:0] E10GBASEKX_CTRL_LANE2 = 16'h0000; - parameter [15:0] E10GBASEKX_CTRL_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_CFG_LANE0 = 16'h070C; - parameter [15:0] E10GBASER_PCS_CFG_LANE1 = 16'h070C; - parameter [15:0] E10GBASER_PCS_CFG_LANE2 = 16'h070C; - parameter [15:0] E10GBASER_PCS_CFG_LANE3 = 16'h070C; - parameter [15:0] E10GBASER_PCS_SEEDA0_LANE0 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDA0_LANE1 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDA0_LANE2 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDA0_LANE3 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDA1_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA1_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA1_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA1_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA2_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA2_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA2_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA2_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA3_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA3_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA3_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDA3_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB0_LANE0 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDB0_LANE1 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDB0_LANE2 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDB0_LANE3 = 16'h0001; - parameter [15:0] E10GBASER_PCS_SEEDB1_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB1_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB1_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB1_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB2_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB2_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB2_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB2_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB3_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB3_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB3_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_SEEDB3_LANE3 = 16'h0000; - parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE0 = 16'h0000; - parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE1 = 16'h0000; - parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE2 = 16'h0000; - parameter [15:0] E10GBASER_PCS_TEST_CTRL_LANE3 = 16'h0000; - parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE0 = 16'h0000; - parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE1 = 16'h0000; - parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE2 = 16'h0000; - parameter [15:0] E10GBASEX_PCS_TSTCTRL_LANE3 = 16'h0000; - parameter [15:0] GLBL0_NOISE_CTRL = 16'hF0B8; - parameter [15:0] GLBL_AMON_SEL = 16'h0000; - parameter [15:0] GLBL_DMON_SEL = 16'h0200; - parameter [15:0] GLBL_PWR_CTRL = 16'h0000; - parameter [0:0] GTH_CFG_PWRUP_LANE0 = 1'b1; - parameter [0:0] GTH_CFG_PWRUP_LANE1 = 1'b1; - parameter [0:0] GTH_CFG_PWRUP_LANE2 = 1'b1; - parameter [0:0] GTH_CFG_PWRUP_LANE3 = 1'b1; - parameter [15:0] LANE_AMON_SEL = 16'h00F0; - parameter [15:0] LANE_DMON_SEL = 16'h0000; - parameter [15:0] LANE_LNK_CFGOVRD = 16'h0000; - parameter [15:0] LANE_PWR_CTRL_LANE0 = 16'h0400; - parameter [15:0] LANE_PWR_CTRL_LANE1 = 16'h0400; - parameter [15:0] LANE_PWR_CTRL_LANE2 = 16'h0400; - parameter [15:0] LANE_PWR_CTRL_LANE3 = 16'h0400; - parameter [15:0] LNK_TRN_CFG_LANE0 = 16'h0000; - parameter [15:0] LNK_TRN_CFG_LANE1 = 16'h0000; - parameter [15:0] LNK_TRN_CFG_LANE2 = 16'h0000; - parameter [15:0] LNK_TRN_CFG_LANE3 = 16'h0000; - parameter [15:0] LNK_TRN_COEFF_REQ_LANE0 = 16'h0000; - parameter [15:0] LNK_TRN_COEFF_REQ_LANE1 = 16'h0000; - parameter [15:0] LNK_TRN_COEFF_REQ_LANE2 = 16'h0000; - parameter [15:0] LNK_TRN_COEFF_REQ_LANE3 = 16'h0000; - parameter [15:0] MISC_CFG = 16'h0008; - parameter [15:0] MODE_CFG1 = 16'h0000; - parameter [15:0] MODE_CFG2 = 16'h0000; - parameter [15:0] MODE_CFG3 = 16'h0000; - parameter [15:0] MODE_CFG4 = 16'h0000; - parameter [15:0] MODE_CFG5 = 16'h0000; - parameter [15:0] MODE_CFG6 = 16'h0000; - parameter [15:0] MODE_CFG7 = 16'h0000; - parameter [15:0] PCS_ABILITY_LANE0 = 16'h0010; - parameter [15:0] PCS_ABILITY_LANE1 = 16'h0010; - parameter [15:0] PCS_ABILITY_LANE2 = 16'h0010; - parameter [15:0] PCS_ABILITY_LANE3 = 16'h0010; - parameter [15:0] PCS_CTRL1_LANE0 = 16'h2040; - parameter [15:0] PCS_CTRL1_LANE1 = 16'h2040; - parameter [15:0] PCS_CTRL1_LANE2 = 16'h2040; - parameter [15:0] PCS_CTRL1_LANE3 = 16'h2040; - parameter [15:0] PCS_CTRL2_LANE0 = 16'h0000; - parameter [15:0] PCS_CTRL2_LANE1 = 16'h0000; - parameter [15:0] PCS_CTRL2_LANE2 = 16'h0000; - parameter [15:0] PCS_CTRL2_LANE3 = 16'h0000; - parameter [15:0] PCS_MISC_CFG_0_LANE0 = 16'h1116; - parameter [15:0] PCS_MISC_CFG_0_LANE1 = 16'h1116; - parameter [15:0] PCS_MISC_CFG_0_LANE2 = 16'h1116; - parameter [15:0] PCS_MISC_CFG_0_LANE3 = 16'h1116; - parameter [15:0] PCS_MISC_CFG_1_LANE0 = 16'h0000; - parameter [15:0] PCS_MISC_CFG_1_LANE1 = 16'h0000; - parameter [15:0] PCS_MISC_CFG_1_LANE2 = 16'h0000; - parameter [15:0] PCS_MISC_CFG_1_LANE3 = 16'h0000; - parameter [15:0] PCS_MODE_LANE0 = 16'h0000; - parameter [15:0] PCS_MODE_LANE1 = 16'h0000; - parameter [15:0] PCS_MODE_LANE2 = 16'h0000; - parameter [15:0] PCS_MODE_LANE3 = 16'h0000; - parameter [15:0] PCS_RESET_1_LANE0 = 16'h0002; - parameter [15:0] PCS_RESET_1_LANE1 = 16'h0002; - parameter [15:0] PCS_RESET_1_LANE2 = 16'h0002; - parameter [15:0] PCS_RESET_1_LANE3 = 16'h0002; - parameter [15:0] PCS_RESET_LANE0 = 16'h0000; - parameter [15:0] PCS_RESET_LANE1 = 16'h0000; - parameter [15:0] PCS_RESET_LANE2 = 16'h0000; - parameter [15:0] PCS_RESET_LANE3 = 16'h0000; - parameter [15:0] PCS_TYPE_LANE0 = 16'h002C; - parameter [15:0] PCS_TYPE_LANE1 = 16'h002C; - parameter [15:0] PCS_TYPE_LANE2 = 16'h002C; - parameter [15:0] PCS_TYPE_LANE3 = 16'h002C; - parameter [15:0] PLL_CFG0 = 16'h95DF; - parameter [15:0] PLL_CFG1 = 16'h81C0; - parameter [15:0] PLL_CFG2 = 16'h0424; - parameter [15:0] PMA_CTRL1_LANE0 = 16'h0000; - parameter [15:0] PMA_CTRL1_LANE1 = 16'h0000; - parameter [15:0] PMA_CTRL1_LANE2 = 16'h0000; - parameter [15:0] PMA_CTRL1_LANE3 = 16'h0000; - parameter [15:0] PMA_CTRL2_LANE0 = 16'h000B; - parameter [15:0] PMA_CTRL2_LANE1 = 16'h000B; - parameter [15:0] PMA_CTRL2_LANE2 = 16'h000B; - parameter [15:0] PMA_CTRL2_LANE3 = 16'h000B; - parameter [15:0] PMA_LPBK_CTRL_LANE0 = 16'h0004; - parameter [15:0] PMA_LPBK_CTRL_LANE1 = 16'h0004; - parameter [15:0] PMA_LPBK_CTRL_LANE2 = 16'h0004; - parameter [15:0] PMA_LPBK_CTRL_LANE3 = 16'h0004; - parameter [15:0] PRBS_BER_CFG0_LANE0 = 16'h0000; - parameter [15:0] PRBS_BER_CFG0_LANE1 = 16'h0000; - parameter [15:0] PRBS_BER_CFG0_LANE2 = 16'h0000; - parameter [15:0] PRBS_BER_CFG0_LANE3 = 16'h0000; - parameter [15:0] PRBS_BER_CFG1_LANE0 = 16'h0000; - parameter [15:0] PRBS_BER_CFG1_LANE1 = 16'h0000; - parameter [15:0] PRBS_BER_CFG1_LANE2 = 16'h0000; - parameter [15:0] PRBS_BER_CFG1_LANE3 = 16'h0000; - parameter [15:0] PRBS_CFG_LANE0 = 16'h000A; - parameter [15:0] PRBS_CFG_LANE1 = 16'h000A; - parameter [15:0] PRBS_CFG_LANE2 = 16'h000A; - parameter [15:0] PRBS_CFG_LANE3 = 16'h000A; - parameter [15:0] PTRN_CFG0_LSB = 16'h5555; - parameter [15:0] PTRN_CFG0_MSB = 16'h5555; - parameter [15:0] PTRN_LEN_CFG = 16'h001F; - parameter [15:0] PWRUP_DLY = 16'h0000; - parameter [15:0] RX_AEQ_VAL0_LANE0 = 16'h03C0; - parameter [15:0] RX_AEQ_VAL0_LANE1 = 16'h03C0; - parameter [15:0] RX_AEQ_VAL0_LANE2 = 16'h03C0; - parameter [15:0] RX_AEQ_VAL0_LANE3 = 16'h03C0; - parameter [15:0] RX_AEQ_VAL1_LANE0 = 16'h0000; - parameter [15:0] RX_AEQ_VAL1_LANE1 = 16'h0000; - parameter [15:0] RX_AEQ_VAL1_LANE2 = 16'h0000; - parameter [15:0] RX_AEQ_VAL1_LANE3 = 16'h0000; - parameter [15:0] RX_AGC_CTRL_LANE0 = 16'h0000; - parameter [15:0] RX_AGC_CTRL_LANE1 = 16'h0000; - parameter [15:0] RX_AGC_CTRL_LANE2 = 16'h0000; - parameter [15:0] RX_AGC_CTRL_LANE3 = 16'h0000; - parameter [15:0] RX_CDR_CTRL0_LANE0 = 16'h0005; - parameter [15:0] RX_CDR_CTRL0_LANE1 = 16'h0005; - parameter [15:0] RX_CDR_CTRL0_LANE2 = 16'h0005; - parameter [15:0] RX_CDR_CTRL0_LANE3 = 16'h0005; - parameter [15:0] RX_CDR_CTRL1_LANE0 = 16'h4200; - parameter [15:0] RX_CDR_CTRL1_LANE1 = 16'h4200; - parameter [15:0] RX_CDR_CTRL1_LANE2 = 16'h4200; - parameter [15:0] RX_CDR_CTRL1_LANE3 = 16'h4200; - parameter [15:0] RX_CDR_CTRL2_LANE0 = 16'h2000; - parameter [15:0] RX_CDR_CTRL2_LANE1 = 16'h2000; - parameter [15:0] RX_CDR_CTRL2_LANE2 = 16'h2000; - parameter [15:0] RX_CDR_CTRL2_LANE3 = 16'h2000; - parameter [15:0] RX_CFG0_LANE0 = 16'h0500; - parameter [15:0] RX_CFG0_LANE1 = 16'h0500; - parameter [15:0] RX_CFG0_LANE2 = 16'h0500; - parameter [15:0] RX_CFG0_LANE3 = 16'h0500; - parameter [15:0] RX_CFG1_LANE0 = 16'h821F; - parameter [15:0] RX_CFG1_LANE1 = 16'h821F; - parameter [15:0] RX_CFG1_LANE2 = 16'h821F; - parameter [15:0] RX_CFG1_LANE3 = 16'h821F; - parameter [15:0] RX_CFG2_LANE0 = 16'h1001; - parameter [15:0] RX_CFG2_LANE1 = 16'h1001; - parameter [15:0] RX_CFG2_LANE2 = 16'h1001; - parameter [15:0] RX_CFG2_LANE3 = 16'h1001; - parameter [15:0] RX_CTLE_CTRL_LANE0 = 16'h008F; - parameter [15:0] RX_CTLE_CTRL_LANE1 = 16'h008F; - parameter [15:0] RX_CTLE_CTRL_LANE2 = 16'h008F; - parameter [15:0] RX_CTLE_CTRL_LANE3 = 16'h008F; - parameter [15:0] RX_CTRL_OVRD_LANE0 = 16'h000C; - parameter [15:0] RX_CTRL_OVRD_LANE1 = 16'h000C; - parameter [15:0] RX_CTRL_OVRD_LANE2 = 16'h000C; - parameter [15:0] RX_CTRL_OVRD_LANE3 = 16'h000C; - parameter integer RX_FABRIC_WIDTH0 = 6466; - parameter integer RX_FABRIC_WIDTH1 = 6466; - parameter integer RX_FABRIC_WIDTH2 = 6466; - parameter integer RX_FABRIC_WIDTH3 = 6466; - parameter [15:0] RX_LOOP_CTRL_LANE0 = 16'h007F; - parameter [15:0] RX_LOOP_CTRL_LANE1 = 16'h007F; - parameter [15:0] RX_LOOP_CTRL_LANE2 = 16'h007F; - parameter [15:0] RX_LOOP_CTRL_LANE3 = 16'h007F; - parameter [15:0] RX_MVAL0_LANE0 = 16'h0000; - parameter [15:0] RX_MVAL0_LANE1 = 16'h0000; - parameter [15:0] RX_MVAL0_LANE2 = 16'h0000; - parameter [15:0] RX_MVAL0_LANE3 = 16'h0000; - parameter [15:0] RX_MVAL1_LANE0 = 16'h0000; - parameter [15:0] RX_MVAL1_LANE1 = 16'h0000; - parameter [15:0] RX_MVAL1_LANE2 = 16'h0000; - parameter [15:0] RX_MVAL1_LANE3 = 16'h0000; - parameter [15:0] RX_P0S_CTRL = 16'h1206; - parameter [15:0] RX_P0_CTRL = 16'h11F0; - parameter [15:0] RX_P1_CTRL = 16'h120F; - parameter [15:0] RX_P2_CTRL = 16'h0E0F; - parameter [15:0] RX_PI_CTRL0 = 16'hD2F0; - parameter [15:0] RX_PI_CTRL1 = 16'h0080; - parameter integer SIM_GTHRESET_SPEEDUP = 1; - parameter SIM_VERSION = "1.0"; - parameter [15:0] SLICE_CFG = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_0_LANE01 = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_0_LANE23 = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_1_LANE01 = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_1_LANE23 = 16'h0000; - parameter [15:0] SLICE_NOISE_CTRL_2_LANE01 = 16'h7FFF; - parameter [15:0] SLICE_NOISE_CTRL_2_LANE23 = 16'h7FFF; - parameter [15:0] SLICE_TX_RESET_LANE01 = 16'h0000; - parameter [15:0] SLICE_TX_RESET_LANE23 = 16'h0000; - parameter [15:0] TERM_CTRL_LANE0 = 16'h5007; - parameter [15:0] TERM_CTRL_LANE1 = 16'h5007; - parameter [15:0] TERM_CTRL_LANE2 = 16'h5007; - parameter [15:0] TERM_CTRL_LANE3 = 16'h5007; - parameter [15:0] TX_CFG0_LANE0 = 16'h203D; - parameter [15:0] TX_CFG0_LANE1 = 16'h203D; - parameter [15:0] TX_CFG0_LANE2 = 16'h203D; - parameter [15:0] TX_CFG0_LANE3 = 16'h203D; - parameter [15:0] TX_CFG1_LANE0 = 16'h0F00; - parameter [15:0] TX_CFG1_LANE1 = 16'h0F00; - parameter [15:0] TX_CFG1_LANE2 = 16'h0F00; - parameter [15:0] TX_CFG1_LANE3 = 16'h0F00; - parameter [15:0] TX_CFG2_LANE0 = 16'h0081; - parameter [15:0] TX_CFG2_LANE1 = 16'h0081; - parameter [15:0] TX_CFG2_LANE2 = 16'h0081; - parameter [15:0] TX_CFG2_LANE3 = 16'h0081; - parameter [15:0] TX_CLK_SEL0_LANE0 = 16'h2121; - parameter [15:0] TX_CLK_SEL0_LANE1 = 16'h2121; - parameter [15:0] TX_CLK_SEL0_LANE2 = 16'h2121; - parameter [15:0] TX_CLK_SEL0_LANE3 = 16'h2121; - parameter [15:0] TX_CLK_SEL1_LANE0 = 16'h2121; - parameter [15:0] TX_CLK_SEL1_LANE1 = 16'h2121; - parameter [15:0] TX_CLK_SEL1_LANE2 = 16'h2121; - parameter [15:0] TX_CLK_SEL1_LANE3 = 16'h2121; - parameter [15:0] TX_DISABLE_LANE0 = 16'h0000; - parameter [15:0] TX_DISABLE_LANE1 = 16'h0000; - parameter [15:0] TX_DISABLE_LANE2 = 16'h0000; - parameter [15:0] TX_DISABLE_LANE3 = 16'h0000; - parameter integer TX_FABRIC_WIDTH0 = 6466; - parameter integer TX_FABRIC_WIDTH1 = 6466; - parameter integer TX_FABRIC_WIDTH2 = 6466; - parameter integer TX_FABRIC_WIDTH3 = 6466; - parameter [15:0] TX_P0P0S_CTRL = 16'h060C; - parameter [15:0] TX_P1P2_CTRL = 16'h0C39; - parameter [15:0] TX_PREEMPH_LANE0 = 16'h00A1; - parameter [15:0] TX_PREEMPH_LANE1 = 16'h00A1; - parameter [15:0] TX_PREEMPH_LANE2 = 16'h00A1; - parameter [15:0] TX_PREEMPH_LANE3 = 16'h00A1; - parameter [15:0] TX_PWR_RATE_OVRD_LANE0 = 16'h0060; - parameter [15:0] TX_PWR_RATE_OVRD_LANE1 = 16'h0060; - parameter [15:0] TX_PWR_RATE_OVRD_LANE2 = 16'h0060; - parameter [15:0] TX_PWR_RATE_OVRD_LANE3 = 16'h0060; - output DRDY; - output GTHINITDONE; - output MGMTPCSRDACK; - output RXCTRLACK0; - output RXCTRLACK1; - output RXCTRLACK2; - output RXCTRLACK3; - output RXDATATAP0; - output RXDATATAP1; - output RXDATATAP2; - output RXDATATAP3; - output RXPCSCLKSMPL0; - output RXPCSCLKSMPL1; - output RXPCSCLKSMPL2; - output RXPCSCLKSMPL3; - output RXUSERCLKOUT0; - output RXUSERCLKOUT1; - output RXUSERCLKOUT2; - output RXUSERCLKOUT3; - output TSTPATH; - output TSTREFCLKFAB; - output TSTREFCLKOUT; - output TXCTRLACK0; - output TXCTRLACK1; - output TXCTRLACK2; - output TXCTRLACK3; - output TXDATATAP10; - output TXDATATAP11; - output TXDATATAP12; - output TXDATATAP13; - output TXDATATAP20; - output TXDATATAP21; - output TXDATATAP22; - output TXDATATAP23; - output TXN0; - output TXN1; - output TXN2; - output TXN3; - output TXP0; - output TXP1; - output TXP2; - output TXP3; - output TXPCSCLKSMPL0; - output TXPCSCLKSMPL1; - output TXPCSCLKSMPL2; - output TXPCSCLKSMPL3; - output TXUSERCLKOUT0; - output TXUSERCLKOUT1; - output TXUSERCLKOUT2; - output TXUSERCLKOUT3; - output [15:0] DRPDO; - output [15:0] MGMTPCSRDDATA; - output [63:0] RXDATA0; - output [63:0] RXDATA1; - output [63:0] RXDATA2; - output [63:0] RXDATA3; - output [7:0] RXCODEERR0; - output [7:0] RXCODEERR1; - output [7:0] RXCODEERR2; - output [7:0] RXCODEERR3; - output [7:0] RXCTRL0; - output [7:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [7:0] RXDISPERR0; - output [7:0] RXDISPERR1; - output [7:0] RXDISPERR2; - output [7:0] RXDISPERR3; - output [7:0] RXVALID0; - output [7:0] RXVALID1; - output [7:0] RXVALID2; - output [7:0] RXVALID3; - input DCLK; - input DEN; - input DFETRAINCTRL0; - input DFETRAINCTRL1; - input DFETRAINCTRL2; - input DFETRAINCTRL3; - input DISABLEDRP; - input DWE; - input GTHINIT; - input GTHRESET; - input GTHX2LANE01; - input GTHX2LANE23; - input GTHX4LANE; - input MGMTPCSREGRD; - input MGMTPCSREGWR; - input POWERDOWN0; - input POWERDOWN1; - input POWERDOWN2; - input POWERDOWN3; - input REFCLK; - input RXBUFRESET0; - input RXBUFRESET1; - input RXBUFRESET2; - input RXBUFRESET3; - input RXENCOMMADET0; - input RXENCOMMADET1; - input RXENCOMMADET2; - input RXENCOMMADET3; - input RXN0; - input RXN1; - input RXN2; - input RXN3; - input RXP0; - input RXP1; - input RXP2; - input RXP3; - input RXPOLARITY0; - input RXPOLARITY1; - input RXPOLARITY2; - input RXPOLARITY3; - input RXSLIP0; - input RXSLIP1; - input RXSLIP2; - input RXSLIP3; - input RXUSERCLKIN0; - input RXUSERCLKIN1; - input RXUSERCLKIN2; - input RXUSERCLKIN3; - input TXBUFRESET0; - input TXBUFRESET1; - input TXBUFRESET2; - input TXBUFRESET3; - input TXDEEMPH0; - input TXDEEMPH1; - input TXDEEMPH2; - input TXDEEMPH3; - input TXUSERCLKIN0; - input TXUSERCLKIN1; - input TXUSERCLKIN2; - input TXUSERCLKIN3; - input [15:0] DADDR; - input [15:0] DI; - input [15:0] MGMTPCSREGADDR; - input [15:0] MGMTPCSWRDATA; - input [1:0] RXPOWERDOWN0; - input [1:0] RXPOWERDOWN1; - input [1:0] RXPOWERDOWN2; - input [1:0] RXPOWERDOWN3; - input [1:0] RXRATE0; - input [1:0] RXRATE1; - input [1:0] RXRATE2; - input [1:0] RXRATE3; - input [1:0] TXPOWERDOWN0; - input [1:0] TXPOWERDOWN1; - input [1:0] TXPOWERDOWN2; - input [1:0] TXPOWERDOWN3; - input [1:0] TXRATE0; - input [1:0] TXRATE1; - input [1:0] TXRATE2; - input [1:0] TXRATE3; - input [2:0] PLLREFCLKSEL; - input [2:0] SAMPLERATE0; - input [2:0] SAMPLERATE1; - input [2:0] SAMPLERATE2; - input [2:0] SAMPLERATE3; - input [2:0] TXMARGIN0; - input [2:0] TXMARGIN1; - input [2:0] TXMARGIN2; - input [2:0] TXMARGIN3; - input [3:0] MGMTPCSLANESEL; - input [4:0] MGMTPCSMMDADDR; - input [5:0] PLLPCSCLKDIV; - input [63:0] TXDATA0; - input [63:0] TXDATA1; - input [63:0] TXDATA2; - input [63:0] TXDATA3; - input [7:0] TXCTRL0; - input [7:0] TXCTRL1; - input [7:0] TXCTRL2; - input [7:0] TXCTRL3; - input [7:0] TXDATAMSB0; - input [7:0] TXDATAMSB1; - input [7:0] TXDATAMSB2; - input [7:0] TXDATAMSB3; -endmodule - -module GTXE1 (...); - parameter AC_CAP_DIS = "TRUE"; - parameter integer ALIGN_COMMA_WORD = 1; - parameter [1:0] BGTEST_CFG = 2'b00; - parameter [16:0] BIAS_CFG = 17'h00000; - parameter [4:0] CDR_PH_ADJ_TIME = 5'b10100; - parameter integer CHAN_BOND_1_MAX_SKEW = 7; - parameter integer CHAN_BOND_2_MAX_SKEW = 1; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0001001010; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0110111100; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100111100; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0110111100; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100111100; - parameter [4:0] CHAN_BOND_SEQ_2_CFG = 5'b00000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 1; - parameter CLK_CORRECT_USE = "TRUE"; - parameter integer CLK_COR_ADJ_LEN = 1; - parameter integer CLK_COR_DET_LEN = 1; - parameter CLK_COR_INSERT_IDLE_FLAG = "FALSE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter [1:0] CM_TRIM = 2'b01; - parameter [9:0] COMMA_10B_ENABLE = 10'b1111111111; - parameter COMMA_DOUBLE = "FALSE"; - parameter [3:0] COM_BURST_VAL = 4'b1111; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [4:0] DFE_CAL_TIME = 5'b01100; - parameter [7:0] DFE_CFG = 8'b00011011; - parameter [2:0] GEARBOX_ENDEC = 3'b000; - parameter GEN_RXUSRCLK = "TRUE"; - parameter GEN_TXUSRCLK = "TRUE"; - parameter GTX_CFG_PWRUP = "TRUE"; - parameter [9:0] MCOMMA_10B_VALUE = 10'b1010000011; - parameter MCOMMA_DETECT = "TRUE"; - parameter [2:0] OOBDETECT_THRESHOLD = 3'b011; - parameter PCI_EXPRESS_MODE = "FALSE"; - parameter [9:0] PCOMMA_10B_VALUE = 10'b0101111100; - parameter PCOMMA_DETECT = "TRUE"; - parameter PMA_CAS_CLK_EN = "FALSE"; - parameter [26:0] PMA_CDR_SCAN = 27'h640404C; - parameter [75:0] PMA_CFG = 76'h0040000040000000003; - parameter [6:0] PMA_RXSYNC_CFG = 7'h00; - parameter [24:0] PMA_RX_CFG = 25'h05CE048; - parameter [19:0] PMA_TX_CFG = 20'h00082; - parameter [9:0] POWER_SAVE = 10'b0000110100; - parameter RCV_TERM_GND = "FALSE"; - parameter RCV_TERM_VTTRX = "TRUE"; - parameter RXGEARBOX_USE = "FALSE"; - parameter [23:0] RXPLL_COM_CFG = 24'h21680A; - parameter [7:0] RXPLL_CP_CFG = 8'h00; - parameter integer RXPLL_DIVSEL45_FB = 5; - parameter integer RXPLL_DIVSEL_FB = 2; - parameter integer RXPLL_DIVSEL_OUT = 1; - parameter integer RXPLL_DIVSEL_REF = 1; - parameter [2:0] RXPLL_LKDET_CFG = 3'b111; - parameter [0:0] RXPRBSERR_LOOPBACK = 1'b0; - parameter RXRECCLK_CTRL = "RXRECCLKPCS"; - parameter [9:0] RXRECCLK_DLY = 10'b0000000000; - parameter [15:0] RXUSRCLK_DLY = 16'h0000; - parameter RX_BUFFER_USE = "TRUE"; - parameter integer RX_CLK25_DIVIDER = 6; - parameter integer RX_DATA_WIDTH = 20; - parameter RX_DECODE_SEQ_MATCH = "TRUE"; - parameter [3:0] RX_DLYALIGN_CTRINC = 4'b0100; - parameter [4:0] RX_DLYALIGN_EDGESET = 5'b00110; - parameter [3:0] RX_DLYALIGN_LPFINC = 4'b0111; - parameter [2:0] RX_DLYALIGN_MONSEL = 3'b000; - parameter [7:0] RX_DLYALIGN_OVRDSETTING = 8'b00000000; - parameter RX_EN_IDLE_HOLD_CDR = "FALSE"; - parameter RX_EN_IDLE_HOLD_DFE = "TRUE"; - parameter RX_EN_IDLE_RESET_BUF = "TRUE"; - parameter RX_EN_IDLE_RESET_FR = "TRUE"; - parameter RX_EN_IDLE_RESET_PH = "TRUE"; - parameter RX_EN_MODE_RESET_BUF = "TRUE"; - parameter RX_EN_RATE_RESET_BUF = "TRUE"; - parameter RX_EN_REALIGN_RESET_BUF = "FALSE"; - parameter RX_EN_REALIGN_RESET_BUF2 = "FALSE"; - parameter [7:0] RX_EYE_OFFSET = 8'h4C; - parameter [1:0] RX_EYE_SCANMODE = 2'b00; - parameter RX_FIFO_ADDR_MODE = "FULL"; - parameter [3:0] RX_IDLE_HI_CNT = 4'b1000; - parameter [3:0] RX_IDLE_LO_CNT = 4'b0000; - parameter RX_LOSS_OF_SYNC_FSM = "FALSE"; - parameter integer RX_LOS_INVALID_INCR = 1; - parameter integer RX_LOS_THRESHOLD = 4; - parameter RX_OVERSAMPLE_MODE = "FALSE"; - parameter integer RX_SLIDE_AUTO_WAIT = 5; - parameter RX_SLIDE_MODE = "OFF"; - parameter RX_XCLK_SEL = "RXREC"; - parameter integer SAS_MAX_COMSAS = 52; - parameter integer SAS_MIN_COMSAS = 40; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter [2:0] SATA_IDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 7; - parameter integer SATA_MAX_INIT = 22; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter integer SIM_GTXRESET_SPEEDUP = 1; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter [2:0] SIM_RXREFCLK_SOURCE = 3'b000; - parameter [2:0] SIM_TXREFCLK_SOURCE = 3'b000; - parameter SIM_TX_ELEC_IDLE_LEVEL = "X"; - parameter SIM_VERSION = "2.0"; - parameter [4:0] TERMINATION_CTRL = 5'b10100; - parameter TERMINATION_OVRD = "FALSE"; - parameter [11:0] TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] TRANS_TIME_NON_P2 = 8'h19; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [9:0] TRANS_TIME_TO_P2 = 10'h064; - parameter [31:0] TST_ATTR = 32'h00000000; - parameter TXDRIVE_LOOPBACK_HIZ = "FALSE"; - parameter TXDRIVE_LOOPBACK_PD = "FALSE"; - parameter TXGEARBOX_USE = "FALSE"; - parameter TXOUTCLK_CTRL = "TXOUTCLKPCS"; - parameter [9:0] TXOUTCLK_DLY = 10'b0000000000; - parameter [23:0] TXPLL_COM_CFG = 24'h21680A; - parameter [7:0] TXPLL_CP_CFG = 8'h00; - parameter integer TXPLL_DIVSEL45_FB = 5; - parameter integer TXPLL_DIVSEL_FB = 2; - parameter integer TXPLL_DIVSEL_OUT = 1; - parameter integer TXPLL_DIVSEL_REF = 1; - parameter [2:0] TXPLL_LKDET_CFG = 3'b111; - parameter [1:0] TXPLL_SATA = 2'b00; - parameter TX_BUFFER_USE = "TRUE"; - parameter [5:0] TX_BYTECLK_CFG = 6'h00; - parameter integer TX_CLK25_DIVIDER = 6; - parameter TX_CLK_SOURCE = "RXPLL"; - parameter integer TX_DATA_WIDTH = 20; - parameter [4:0] TX_DEEMPH_0 = 5'b11010; - parameter [4:0] TX_DEEMPH_1 = 5'b10000; - parameter [13:0] TX_DETECT_RX_CFG = 14'h1832; - parameter [3:0] TX_DLYALIGN_CTRINC = 4'b0100; - parameter [3:0] TX_DLYALIGN_LPFINC = 4'b0110; - parameter [2:0] TX_DLYALIGN_MONSEL = 3'b000; - parameter [7:0] TX_DLYALIGN_OVRDSETTING = 8'b10000000; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter TX_EN_RATE_RESET_BUF = "TRUE"; - parameter [2:0] TX_IDLE_ASSERT_DELAY = 3'b100; - parameter [2:0] TX_IDLE_DEASSERT_DELAY = 3'b010; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter TX_OVERSAMPLE_MODE = "FALSE"; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [1:0] TX_TDCC_CFG = 2'b11; - parameter [5:0] TX_USRCLK_CFG = 6'h00; - parameter TX_XCLK_SEL = "TXUSR"; - output COMFINISH; - output COMINITDET; - output COMSASDET; - output COMWAKEDET; - output DRDY; - output PHYSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output RXCOMMADET; - output RXDATAVALID; - output RXELECIDLE; - output RXHEADERVALID; - output RXOVERSAMPLEERR; - output RXPLLLKDET; - output RXPRBSERR; - output RXRATEDONE; - output RXRECCLK; - output RXRECCLKPCS; - output RXRESETDONE; - output RXSTARTOFSEQ; - output RXVALID; - output TXGEARBOXREADY; - output TXN; - output TXOUTCLK; - output TXOUTCLKPCS; - output TXP; - output TXPLLLKDET; - output TXRATEDONE; - output TXRESETDONE; - output [15:0] DRPDO; - output [1:0] MGTREFCLKFAB; - output [1:0] RXLOSSOFSYNC; - output [1:0] TXBUFSTATUS; - output [2:0] DFESENSCAL; - output [2:0] RXBUFSTATUS; - output [2:0] RXCLKCORCNT; - output [2:0] RXHEADER; - output [2:0] RXSTATUS; - output [31:0] RXDATA; - output [3:0] DFETAP3MONITOR; - output [3:0] DFETAP4MONITOR; - output [3:0] RXCHARISCOMMA; - output [3:0] RXCHARISK; - output [3:0] RXCHBONDO; - output [3:0] RXDISPERR; - output [3:0] RXNOTINTABLE; - output [3:0] RXRUNDISP; - output [3:0] TXKERR; - output [3:0] TXRUNDISP; - output [4:0] DFEEYEDACMON; - output [4:0] DFETAP1MONITOR; - output [4:0] DFETAP2MONITOR; - output [5:0] DFECLKDLYADJMON; - output [7:0] RXDLYALIGNMONITOR; - output [7:0] TXDLYALIGNMONITOR; - output [9:0] TSTOUT; - input DCLK; - input DEN; - input DFEDLYOVRD; - input DFETAPOVRD; - input DWE; - input GATERXELECIDLE; - input GREFCLKRX; - input GREFCLKTX; - input GTXRXRESET; - input GTXTXRESET; - input IGNORESIGDET; - input PERFCLKRX; - input PERFCLKTX; - input PLLRXRESET; - input PLLTXRESET; - input PRBSCNTRESET; - input RXBUFRESET; - input RXCDRRESET; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETUSE; - input RXDEC8B10BUSE; - input RXDLYALIGNDISABLE; - input RXDLYALIGNMONENB; - input RXDLYALIGNOVERRIDE; - input RXDLYALIGNRESET; - input RXDLYALIGNSWPPRECURB; - input RXDLYALIGNUPDSW; - input RXENCHANSYNC; - input RXENMCOMMAALIGN; - input RXENPCOMMAALIGN; - input RXENPMAPHASEALIGN; - input RXENSAMPLEALIGN; - input RXGEARBOXSLIP; - input RXN; - input RXP; - input RXPLLLKDETEN; - input RXPLLPOWERDOWN; - input RXPMASETPHASE; - input RXPOLARITY; - input RXRESET; - input RXSLIDE; - input RXUSRCLK2; - input RXUSRCLK; - input TSTCLK0; - input TSTCLK1; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input TXDEEMPH; - input TXDETECTRX; - input TXDLYALIGNDISABLE; - input TXDLYALIGNMONENB; - input TXDLYALIGNOVERRIDE; - input TXDLYALIGNRESET; - input TXDLYALIGNUPDSW; - input TXELECIDLE; - input TXENC8B10BUSE; - input TXENPMAPHASEALIGN; - input TXINHIBIT; - input TXPDOWNASYNCH; - input TXPLLLKDETEN; - input TXPLLPOWERDOWN; - input TXPMASETPHASE; - input TXPOLARITY; - input TXPRBSFORCEERR; - input TXRESET; - input TXSTARTSEQ; - input TXSWING; - input TXUSRCLK2; - input TXUSRCLK; - input USRCODEERR; - input [12:0] GTXTEST; - input [15:0] DI; - input [19:0] TSTIN; - input [1:0] MGTREFCLKRX; - input [1:0] MGTREFCLKTX; - input [1:0] NORTHREFCLKRX; - input [1:0] NORTHREFCLKTX; - input [1:0] RXPOWERDOWN; - input [1:0] RXRATE; - input [1:0] SOUTHREFCLKRX; - input [1:0] SOUTHREFCLKTX; - input [1:0] TXPOWERDOWN; - input [1:0] TXRATE; - input [2:0] LOOPBACK; - input [2:0] RXCHBONDLEVEL; - input [2:0] RXENPRBSTST; - input [2:0] RXPLLREFSELDY; - input [2:0] TXBUFDIFFCTRL; - input [2:0] TXENPRBSTST; - input [2:0] TXHEADER; - input [2:0] TXMARGIN; - input [2:0] TXPLLREFSELDY; - input [31:0] TXDATA; - input [3:0] DFETAP3; - input [3:0] DFETAP4; - input [3:0] RXCHBONDI; - input [3:0] TXBYPASS8B10B; - input [3:0] TXCHARDISPMODE; - input [3:0] TXCHARDISPVAL; - input [3:0] TXCHARISK; - input [3:0] TXDIFFCTRL; - input [3:0] TXPREEMPHASIS; - input [4:0] DFETAP1; - input [4:0] DFETAP2; - input [4:0] TXPOSTEMPHASIS; - input [5:0] DFECLKDLYADJ; - input [6:0] TXSEQUENCE; - input [7:0] DADDR; - input [9:0] RXEQMIX; -endmodule - -module IBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IFD_DELAY_VALUE = "AUTO"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_GTHE1 (...); - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFGDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFGDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -(* keep *) -module IDELAYCTRL (...); - parameter SIM_DEVICE = "7SERIES"; - output RDY; - (* clkbuf_sink *) - input REFCLK; - input RST; -endmodule - -module IOBUF (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input T; -endmodule - -module IOBUFDS (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - inout IOB; - input I; - input T; -endmodule - -module IODELAYE1 (...); - parameter CINVCTRL_SEL = "FALSE"; - parameter DELAY_SRC = "I"; - parameter HIGH_PERFORMANCE_MODE = "FALSE"; - parameter IDELAY_TYPE = "DEFAULT"; - parameter integer IDELAY_VALUE = 0; - parameter ODELAY_TYPE = "FIXED"; - parameter integer ODELAY_VALUE = 0; - parameter real REFCLK_FREQUENCY = 200.0; - parameter SIGNAL_PATTERN = "DATA"; - output [4:0] CNTVALUEOUT; - output DATAOUT; - (* clkbuf_sink *) - input C; - input CE; - input CINVCTRL; - input CLKIN; - input [4:0] CNTVALUEIN; - input DATAIN; - input IDATAIN; - input INC; - input ODATAIN; - input RST; - input T; -endmodule - -module ISERDESE1 (...); - parameter DATA_RATE = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter DYN_CLKDIV_INV_EN = "FALSE"; - parameter DYN_CLK_INV_EN = "FALSE"; - parameter [0:0] INIT_Q1 = 1'b0; - parameter [0:0] INIT_Q2 = 1'b0; - parameter [0:0] INIT_Q3 = 1'b0; - parameter [0:0] INIT_Q4 = 1'b0; - parameter INTERFACE_TYPE = "MEMORY"; - parameter integer NUM_CE = 2; - parameter IOBDELAY = "NONE"; - parameter OFB_USED = "FALSE"; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_Q1 = 1'b0; - parameter [0:0] SRVAL_Q2 = 1'b0; - parameter [0:0] SRVAL_Q3 = 1'b0; - parameter [0:0] SRVAL_Q4 = 1'b0; - output O; - output Q1; - output Q2; - output Q3; - output Q4; - output Q5; - output Q6; - output SHIFTOUT1; - output SHIFTOUT2; - input BITSLIP; - input CE1; - input CE2; - (* clkbuf_sink *) - input CLK; - (* clkbuf_sink *) - input CLKB; - (* clkbuf_sink *) - input CLKDIV; - input D; - input DDLY; - input DYNCLKDIVSEL; - input DYNCLKSEL; - (* clkbuf_sink *) - input OCLK; - input OFB; - input RST; - input SHIFTIN1; - input SHIFTIN2; -endmodule - -module KEEPER (...); - inout O; -endmodule - -module OBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; -endmodule - -module OBUFT (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter integer DRIVE = 12; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - input I; - input T; -endmodule - -module OBUFTDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; - input T; -endmodule - -module OSERDESE1 (...); - parameter DATA_RATE_OQ = "DDR"; - parameter DATA_RATE_TQ = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter integer DDR3_DATA = 1; - parameter [0:0] INIT_OQ = 1'b0; - parameter [0:0] INIT_TQ = 1'b0; - parameter INTERFACE_TYPE = "DEFAULT"; - parameter integer ODELAY_USED = 0; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_OQ = 1'b0; - parameter [0:0] SRVAL_TQ = 1'b0; - parameter integer TRISTATE_WIDTH = 4; - output OCBEXTEND; - output OFB; - output OQ; - output SHIFTOUT1; - output SHIFTOUT2; - output TFB; - output TQ; - (* clkbuf_sink *) - input CLK; - (* clkbuf_sink *) - input CLKDIV; - input CLKPERF; - input CLKPERFDELAY; - input D1; - input D2; - input D3; - input D4; - input D5; - input D6; - input OCE; - input ODV; - input RST; - input SHIFTIN1; - input SHIFTIN2; - input T1; - input T2; - input T3; - input T4; - input TCE; - input WC; -endmodule - -module PULLDOWN (...); - output O; -endmodule - -module PULLUP (...); - output O; -endmodule - -module TEMAC_SINGLE (...); - parameter EMAC_1000BASEX_ENABLE = "FALSE"; - parameter EMAC_ADDRFILTER_ENABLE = "FALSE"; - parameter EMAC_BYTEPHY = "FALSE"; - parameter EMAC_CTRLLENCHECK_DISABLE = "FALSE"; - parameter [0:7] EMAC_DCRBASEADDR = 8'h00; - parameter EMAC_GTLOOPBACK = "FALSE"; - parameter EMAC_HOST_ENABLE = "FALSE"; - parameter [8:0] EMAC_LINKTIMERVAL = 9'h000; - parameter EMAC_LTCHECK_DISABLE = "FALSE"; - parameter EMAC_MDIO_ENABLE = "FALSE"; - parameter EMAC_MDIO_IGNORE_PHYADZERO = "FALSE"; - parameter [47:0] EMAC_PAUSEADDR = 48'h000000000000; - parameter EMAC_PHYINITAUTONEG_ENABLE = "FALSE"; - parameter EMAC_PHYISOLATE = "FALSE"; - parameter EMAC_PHYLOOPBACKMSB = "FALSE"; - parameter EMAC_PHYPOWERDOWN = "FALSE"; - parameter EMAC_PHYRESET = "FALSE"; - parameter EMAC_RGMII_ENABLE = "FALSE"; - parameter EMAC_RX16BITCLIENT_ENABLE = "FALSE"; - parameter EMAC_RXFLOWCTRL_ENABLE = "FALSE"; - parameter EMAC_RXHALFDUPLEX = "FALSE"; - parameter EMAC_RXINBANDFCS_ENABLE = "FALSE"; - parameter EMAC_RXJUMBOFRAME_ENABLE = "FALSE"; - parameter EMAC_RXRESET = "FALSE"; - parameter EMAC_RXVLAN_ENABLE = "FALSE"; - parameter EMAC_RX_ENABLE = "TRUE"; - parameter EMAC_SGMII_ENABLE = "FALSE"; - parameter EMAC_SPEED_LSB = "FALSE"; - parameter EMAC_SPEED_MSB = "FALSE"; - parameter EMAC_TX16BITCLIENT_ENABLE = "FALSE"; - parameter EMAC_TXFLOWCTRL_ENABLE = "FALSE"; - parameter EMAC_TXHALFDUPLEX = "FALSE"; - parameter EMAC_TXIFGADJUST_ENABLE = "FALSE"; - parameter EMAC_TXINBANDFCS_ENABLE = "FALSE"; - parameter EMAC_TXJUMBOFRAME_ENABLE = "FALSE"; - parameter EMAC_TXRESET = "FALSE"; - parameter EMAC_TXVLAN_ENABLE = "FALSE"; - parameter EMAC_TX_ENABLE = "TRUE"; - parameter [47:0] EMAC_UNICASTADDR = 48'h000000000000; - parameter EMAC_UNIDIRECTION_ENABLE = "FALSE"; - parameter EMAC_USECLKEN = "FALSE"; - parameter SIM_VERSION = "1.0"; - output DCRHOSTDONEIR; - output EMACCLIENTANINTERRUPT; - output EMACCLIENTRXBADFRAME; - output EMACCLIENTRXCLIENTCLKOUT; - output EMACCLIENTRXDVLD; - output EMACCLIENTRXDVLDMSW; - output EMACCLIENTRXFRAMEDROP; - output EMACCLIENTRXGOODFRAME; - output EMACCLIENTRXSTATSBYTEVLD; - output EMACCLIENTRXSTATSVLD; - output EMACCLIENTTXACK; - output EMACCLIENTTXCLIENTCLKOUT; - output EMACCLIENTTXCOLLISION; - output EMACCLIENTTXRETRANSMIT; - output EMACCLIENTTXSTATS; - output EMACCLIENTTXSTATSBYTEVLD; - output EMACCLIENTTXSTATSVLD; - output EMACDCRACK; - output EMACPHYENCOMMAALIGN; - output EMACPHYLOOPBACKMSB; - output EMACPHYMCLKOUT; - output EMACPHYMDOUT; - output EMACPHYMDTRI; - output EMACPHYMGTRXRESET; - output EMACPHYMGTTXRESET; - output EMACPHYPOWERDOWN; - output EMACPHYSYNCACQSTATUS; - output EMACPHYTXCHARDISPMODE; - output EMACPHYTXCHARDISPVAL; - output EMACPHYTXCHARISK; - output EMACPHYTXCLK; - output EMACPHYTXEN; - output EMACPHYTXER; - output EMACPHYTXGMIIMIICLKOUT; - output EMACSPEEDIS10100; - output HOSTMIIMRDY; - output [0:31] EMACDCRDBUS; - output [15:0] EMACCLIENTRXD; - output [31:0] HOSTRDDATA; - output [6:0] EMACCLIENTRXSTATS; - output [7:0] EMACPHYTXD; - input CLIENTEMACDCMLOCKED; - input CLIENTEMACPAUSEREQ; - input CLIENTEMACRXCLIENTCLKIN; - input CLIENTEMACTXCLIENTCLKIN; - input CLIENTEMACTXDVLD; - input CLIENTEMACTXDVLDMSW; - input CLIENTEMACTXFIRSTBYTE; - input CLIENTEMACTXUNDERRUN; - input DCREMACCLK; - input DCREMACENABLE; - input DCREMACREAD; - input DCREMACWRITE; - input HOSTCLK; - input HOSTMIIMSEL; - input HOSTREQ; - input PHYEMACCOL; - input PHYEMACCRS; - input PHYEMACGTXCLK; - input PHYEMACMCLKIN; - input PHYEMACMDIN; - input PHYEMACMIITXCLK; - input PHYEMACRXCHARISCOMMA; - input PHYEMACRXCHARISK; - input PHYEMACRXCLK; - input PHYEMACRXDISPERR; - input PHYEMACRXDV; - input PHYEMACRXER; - input PHYEMACRXNOTINTABLE; - input PHYEMACRXRUNDISP; - input PHYEMACSIGNALDET; - input PHYEMACTXBUFERR; - input PHYEMACTXGMIIMIICLKIN; - input RESET; - input [0:31] DCREMACDBUS; - input [0:9] DCREMACABUS; - input [15:0] CLIENTEMACPAUSEVAL; - input [15:0] CLIENTEMACTXD; - input [1:0] HOSTOPCODE; - input [1:0] PHYEMACRXBUFSTATUS; - input [2:0] PHYEMACRXCLKCORCNT; - input [31:0] HOSTWRDATA; - input [4:0] PHYEMACPHYAD; - input [7:0] CLIENTEMACTXIFGDELAY; - input [7:0] PHYEMACRXD; - input [9:0] HOSTADDR; -endmodule - -module FIFO18E1 (...); - parameter ALMOST_EMPTY_OFFSET = 13'h0080; - parameter ALMOST_FULL_OFFSET = 13'h0080; - parameter integer DATA_WIDTH = 4; - parameter integer DO_REG = 1; - parameter EN_SYN = "FALSE"; - parameter FIFO_MODE = "FIFO18"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter INIT = 36'h0; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL = 36'h0; - parameter IS_RDCLK_INVERTED = 1'b0; - parameter IS_RDEN_INVERTED = 1'b0; - parameter IS_RSTREG_INVERTED = 1'b0; - parameter IS_RST_INVERTED = 1'b0; - parameter IS_WRCLK_INVERTED = 1'b0; - parameter IS_WREN_INVERTED = 1'b0; - output ALMOSTEMPTY; - output ALMOSTFULL; - output [31:0] DO; - output [3:0] DOP; - output EMPTY; - output FULL; - output [11:0] RDCOUNT; - output RDERR; - output [11:0] WRCOUNT; - output WRERR; - input [31:0] DI; - input [3:0] DIP; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module FIFO36E1 (...); - parameter ALMOST_EMPTY_OFFSET = 13'h0080; - parameter ALMOST_FULL_OFFSET = 13'h0080; - parameter integer DATA_WIDTH = 4; - parameter integer DO_REG = 1; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter EN_SYN = "FALSE"; - parameter FIFO_MODE = "FIFO36"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter INIT = 72'h0; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL = 72'h0; - parameter IS_RDCLK_INVERTED = 1'b0; - parameter IS_RDEN_INVERTED = 1'b0; - parameter IS_RSTREG_INVERTED = 1'b0; - parameter IS_RST_INVERTED = 1'b0; - parameter IS_WRCLK_INVERTED = 1'b0; - parameter IS_WREN_INVERTED = 1'b0; - output ALMOSTEMPTY; - output ALMOSTFULL; - output DBITERR; - output [63:0] DO; - output [7:0] DOP; - output [7:0] ECCPARITY; - output EMPTY; - output FULL; - output [12:0] RDCOUNT; - output RDERR; - output SBITERR; - output [12:0] WRCOUNT; - output WRERR; - input [63:0] DI; - input [7:0] DIP; - input INJECTDBITERR; - input INJECTSBITERR; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module RAM128X1S (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM256X1S (...); - parameter [255:0] INIT = 256'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input [7:0] A; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [1:0] DOA; - output [1:0] DOB; - output [1:0] DOC; - output [1:0] DOD; - input [4:0] ADDRA; - input [4:0] ADDRB; - input [4:0] ADDRC; - input [4:0] ADDRD; - input [1:0] DIA; - input [1:0] DIB; - input [1:0] DIC; - input [1:0] DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S_1 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X2S (...); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input A4; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DOA; - output DOB; - output DOC; - output DOD; - input [5:0] ADDRA; - input [5:0] ADDRB; - input [5:0] ADDRC; - input [5:0] ADDRD; - input DIA; - input DIB; - input DIC; - input DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S_1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X2S (...); - parameter [63:0] INIT_00 = 64'h0000000000000000; - parameter [63:0] INIT_01 = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module ROM128X1 (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; -endmodule - -module ROM256X1 (...); - parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input A7; -endmodule - -module ROM32X1 (...); - parameter [31:0] INIT = 32'h00000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; -endmodule - -module ROM64X1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; -endmodule - -module IDDR (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT_Q1 = 1'b0; - parameter INIT_Q2 = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q1; - output Q2; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - input R; - input S; -endmodule - -module IDDR_2CLK (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT_Q1 = 1'b0; - parameter INIT_Q2 = 1'b0; - parameter [0:0] IS_CB_INVERTED = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - output Q1; - output Q2; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* clkbuf_sink *) - (* invertible_pin = "IS_CB_INVERTED" *) - input CB; - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - input R; - input S; -endmodule - -module ODDR (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D1_INVERTED = 1'b0; - parameter [0:0] IS_D2_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - (* invertible_pin = "IS_D1_INVERTED" *) - input D1; - (* invertible_pin = "IS_D2_INVERTED" *) - input D2; - input R; - input S; -endmodule - -module CFGLUT5 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - output CDO; - output O5; - output O6; - input I4; - input I3; - input I2; - input I1; - input I0; - input CDI; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; -endmodule - diff --git a/techlibs/xilinx/xc7_brams_bb.v b/techlibs/xilinx/xc7_brams_bb.v deleted file mode 100644 index c374f26b9..000000000 --- a/techlibs/xilinx/xc7_brams_bb.v +++ /dev/null @@ -1,349 +0,0 @@ -// Max delays from https://github.com/SymbiFlow/prjxray-db/blob/f8e0364116b2983ac72a3dc8c509ea1cc79e2e3d/artix7/timings/BRAM_L.sdf#L138-L147 - -module RAMB18E1 ( - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK, - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN, - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN, - input REGCEAREGCE, - input REGCEB, - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM, - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB, - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG, - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB, - - input [13:0] ADDRARDADDR, - input [13:0] ADDRBWRADDR, - input [15:0] DIADI, - input [15:0] DIBDI, - input [1:0] DIPADIP, - input [1:0] DIPBDIP, - input [1:0] WEA, - input [3:0] WEBWE, - - (* abc9_arrival=2454 *) - output [15:0] DOADO, - (* abc9_arrival=2454 *) - output [15:0] DOBDO, - (* abc9_arrival=2454 *) - output [1:0] DOPADOP, - (* abc9_arrival=2454 *) - output [1:0] DOPBDOP -); - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - parameter IS_CLKARDCLK_INVERTED = 1'b0; - parameter IS_CLKBWRCLK_INVERTED = 1'b0; - parameter IS_ENARDEN_INVERTED = 1'b0; - parameter IS_ENBWREN_INVERTED = 1'b0; - parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter IS_RSTRAMB_INVERTED = 1'b0; - parameter IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter IS_RSTREGB_INVERTED = 1'b0; - - parameter RAM_MODE = "TDP"; - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - - parameter SIM_DEVICE = "VIRTEX6"; -endmodule - -module RAMB36E1 ( - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK, - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK, - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN, - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN, - input REGCEAREGCE, - input REGCEB, - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM, - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB, - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG, - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB, - - input [15:0] ADDRARDADDR, - input [15:0] ADDRBWRADDR, - input [31:0] DIADI, - input [31:0] DIBDI, - input [3:0] DIPADIP, - input [3:0] DIPBDIP, - input [3:0] WEA, - input [7:0] WEBWE, - - (* abc9_arrival=2454 *) - output [31:0] DOADO, - (* abc9_arrival=2454 *) - output [31:0] DOBDO, - (* abc9_arrival=2454 *) - output [3:0] DOPADOP, - (* abc9_arrival=2454 *) - output [3:0] DOPBDOP -); - parameter INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - parameter INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - - parameter IS_CLKARDCLK_INVERTED = 1'b0; - parameter IS_CLKBWRCLK_INVERTED = 1'b0; - parameter IS_ENARDEN_INVERTED = 1'b0; - parameter IS_ENBWREN_INVERTED = 1'b0; - parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter IS_RSTRAMB_INVERTED = 1'b0; - parameter IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter IS_RSTREGB_INVERTED = 1'b0; - - parameter RAM_MODE = "TDP"; - parameter integer DOA_REG = 0; - parameter integer DOB_REG = 0; - - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - - parameter WRITE_MODE_A = "WRITE_FIRST"; - parameter WRITE_MODE_B = "WRITE_FIRST"; - - parameter SIM_DEVICE = "VIRTEX6"; -endmodule diff --git a/techlibs/xilinx/xc7_cells_xtra.v b/techlibs/xilinx/xc7_cells_xtra.v deleted file mode 100644 index 10eea4a5f..000000000 --- a/techlibs/xilinx/xc7_cells_xtra.v +++ /dev/null @@ -1,5717 +0,0 @@ -// Created by cells_xtra.py from Xilinx models - -module GTHE2_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [19:0] ADAPT_CFG0 = 20'h00C10; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [41:0] CFOK_CFG = 42'h24800040E80; - parameter [5:0] CFOK_CFG2 = 6'b100000; - parameter [5:0] CFOK_CFG3 = 6'b100000; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 1; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 1; - parameter [28:0] CPLL_CFG = 29'h00BC07DC; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 5; - parameter [23:0] CPLL_INIT_CFG = 24'h00001E; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [23:0] DMONITOR_CFG = 24'h000A00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "TRUE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; - parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; - parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; - parameter [8:0] ES_VERT_OFFSET = 9'b000000000; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [2:0] GEARBOX_MODE = 3'b000; - parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; - parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; - parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; - parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; - parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; - parameter [0:0] LOOPBACK_CFG = 1'b0; - parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; - parameter PCS_PCIE_EN = "FALSE"; - parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [31:0] PMA_RSV = 32'b00000000000000000000000010000000; - parameter [31:0] PMA_RSV2 = 32'b00011100000000000000000000001010; - parameter [1:0] PMA_RSV3 = 2'b00; - parameter [14:0] PMA_RSV4 = 15'b000000000001000; - parameter [3:0] PMA_RSV5 = 4'b0000; - parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 61; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [82:0] RXCDR_CFG = 83'h0002007FE2000C208001A; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDLY_CFG = 16'h001F; - parameter [8:0] RXDLY_LCFG = 9'h030; - parameter [15:0] RXDLY_TAP_CFG = 16'h0000; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [13:0] RXLPM_HF_CFG = 14'b00001000000000; - parameter [17:0] RXLPM_LF_CFG = 18'b001001000000000000; - parameter [6:0] RXOOB_CFG = 7'b0000110; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; - parameter integer RXOUT_DIV = 2; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [23:0] RXPHDLY_CFG = 24'h084020; - parameter [23:0] RXPH_CFG = 24'hC00002; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] RXPI_CFG0 = 2'b00; - parameter [1:0] RXPI_CFG1 = 2'b00; - parameter [1:0] RXPI_CFG2 = 2'b00; - parameter [1:0] RXPI_CFG3 = 2'b00; - parameter [0:0] RXPI_CFG4 = 1'b0; - parameter [0:0] RXPI_CFG5 = 1'b0; - parameter [2:0] RXPI_CFG6 = 3'b100; - parameter [4:0] RXPMARESET_TIME = 5'b00011; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [23:0] RX_BIAS_CFG = 24'b000011000000000000010000; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter integer RX_CLK25_DIV = 7; - parameter [0:0] RX_CLKMUX_PD = 1'b1; - parameter [1:0] RX_CM_SEL = 2'b11; - parameter [3:0] RX_CM_TRIM = 4'b0100; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; - parameter [0:0] RX_DFELPM_CFG1 = 1'b0; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; - parameter [2:0] RX_DFE_AGC_CFG1 = 3'b010; - parameter [3:0] RX_DFE_AGC_CFG2 = 4'b0000; - parameter [0:0] RX_DFE_AGC_OVRDEN = 1'b1; - parameter [22:0] RX_DFE_GAIN_CFG = 23'h0020C0; - parameter [11:0] RX_DFE_H2_CFG = 12'b000000000000; - parameter [11:0] RX_DFE_H3_CFG = 12'b000001000000; - parameter [10:0] RX_DFE_H4_CFG = 11'b00011100000; - parameter [10:0] RX_DFE_H5_CFG = 11'b00011100000; - parameter [10:0] RX_DFE_H6_CFG = 11'b00000100000; - parameter [10:0] RX_DFE_H7_CFG = 11'b00000100000; - parameter [32:0] RX_DFE_KL_CFG = 33'b000000000000000000000001100010000; - parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; - parameter [3:0] RX_DFE_KL_LPM_KH_CFG2 = 4'b0010; - parameter [0:0] RX_DFE_KL_LPM_KH_OVRDEN = 1'b1; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b10; - parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; - parameter [3:0] RX_DFE_KL_LPM_KL_CFG2 = 4'b0010; - parameter [0:0] RX_DFE_KL_LPM_KL_OVRDEN = 1'b1; - parameter [15:0] RX_DFE_LPM_CFG = 16'h0080; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter [53:0] RX_DFE_ST_CFG = 54'h00E100000C003F; - parameter [16:0] RX_DFE_UT_CFG = 17'b00011100000000000; - parameter [16:0] RX_DFE_VP_CFG = 17'b00011101010100011; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter integer RX_INT_DATAWIDTH = 0; - parameter [12:0] RX_OS_CFG = 13'b0000010000000; - parameter integer RX_SIG_VALID_DLY = 10; - parameter RX_XCLK_SEL = "RXREC"; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; - parameter SIM_VERSION = "1.1"; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [31:0] TST_RSV = 32'h00000000; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; - parameter [8:0] TXDLY_LCFG = 9'h030; - parameter [15:0] TXDLY_TAP_CFG = 16'h0000; - parameter TXGEARBOX_EN = "FALSE"; - parameter [0:0] TXOOB_CFG = 1'b0; - parameter integer TXOUT_DIV = 2; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [23:0] TXPHDLY_CFG = 24'h084020; - parameter [15:0] TXPH_CFG = 16'h0780; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b0; - parameter [2:0] TXPI_CFG5 = 3'b100; - parameter [0:0] TXPI_GREY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 7; - parameter [0:0] TX_CLKMUX_PD = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter integer TX_INT_DATAWIDTH = 0; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h1832; - parameter [16:0] TX_RXDETECT_PRECHARGE_TIME = 17'h00000; - parameter [2:0] TX_RXDETECT_REF = 3'b100; - parameter TX_XCLK_SEL = "TXUSR"; - parameter [0:0] UCODEER_CLR = 1'b0; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output DRPRDY; - output EYESCANDATAERROR; - output GTHTXN; - output GTHTXP; - output GTREFCLKMONITOR; - output PHYSTATUS; - output RSOSINTDONE; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output RXDFESLIDETAPSTARTED; - output RXDFESLIDETAPSTROBEDONE; - output RXDFESLIDETAPSTROBESTARTED; - output RXDFESTADAPTDONE; - output RXDLYSRESETDONE; - output RXELECIDLE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPMARESETDONE; - output RXPRBSERR; - output RXQPISENN; - output RXQPISENP; - output RXRATEDONE; - output RXRESETDONE; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output TXCOMFINISH; - output TXDLYSRESETDONE; - output TXGEARBOXREADY; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXQPISENN; - output TXQPISENP; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - output [14:0] DMONITOROUT; - output [15:0] DRPDO; - output [15:0] PCSRSVDOUT; - output [1:0] RXCLKCORCNT; - output [1:0] RXDATAVALID; - output [1:0] RXHEADERVALID; - output [1:0] RXSTARTOFSEQ; - output [1:0] TXBUFSTATUS; - output [2:0] RXBUFSTATUS; - output [2:0] RXSTATUS; - output [4:0] RXCHBONDO; - output [4:0] RXPHMONITOR; - output [4:0] RXPHSLIPMONITOR; - output [5:0] RXHEADER; - output [63:0] RXDATA; - output [6:0] RXMONITOROUT; - output [7:0] RXCHARISCOMMA; - output [7:0] RXCHARISK; - output [7:0] RXDISPERR; - output [7:0] RXNOTINTABLE; - input CFGRESET; - (* invertible_pin = "IS_CLKRSVD0_INVERTED" *) - input CLKRSVD0; - (* invertible_pin = "IS_CLKRSVD1_INVERTED" *) - input CLKRSVD1; - (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *) - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input CPLLRESET; - input DMONFIFORESET; - (* invertible_pin = "IS_DMONITORCLK_INVERTED" *) - input DMONITORCLK; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) - input GTGREFCLK; - input GTHRXN; - input GTHRXP; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTRESETSEL; - input GTRXRESET; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input QPLLCLK; - input QPLLREFCLK; - input RESETOVRD; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETEN; - input RXDDIEN; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input RXDFECM1EN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFESLIDETAPADAPTEN; - input RXDFESLIDETAPHOLD; - input RXDFESLIDETAPINITOVRDEN; - input RXDFESLIDETAPONLYADAPTEN; - input RXDFESLIDETAPOVRDEN; - input RXDFESLIDETAPSTROBE; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEVSEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input RXGEARBOXSLIP; - input RXLPMEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXMCOMMAALIGNEN; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTNTRLEN; - input RXOSINTOVRDEN; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; - input RXOSOVRDEN; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input RXQPIEN; - input RXRATEMODE; - input RXSLIDE; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input RXUSERRDY; - (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) - input RXUSRCLK2; - (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) - input RXUSRCLK; - input SETERRSTATUS; - (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *) - input SIGVALIDCLK; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input TXDEEMPH; - input TXDETECTRX; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input TXINHIBIT; - input TXPCSRESET; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input TXPISOPD; - input TXPMARESET; - input TXPOLARITY; - input TXPOSTCURSORINV; - input TXPRBSFORCEERR; - input TXPRECURSORINV; - input TXQPIBIASEN; - input TXQPISTRONGPDOWN; - input TXQPIWEAKPUP; - input TXRATEMODE; - input TXSTARTSEQ; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input TXUSERRDY; - (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) - input TXUSRCLK2; - (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) - input TXUSRCLK; - input [13:0] RXADAPTSELTEST; - input [15:0] DRPDI; - input [15:0] GTRSVD; - input [15:0] PCSRSVDIN; - input [19:0] TSTIN; - input [1:0] RXELECIDLEMODE; - input [1:0] RXMONITORSEL; - input [1:0] RXPD; - input [1:0] RXSYSCLKSEL; - input [1:0] TXPD; - input [1:0] TXSYSCLKSEL; - input [2:0] CPLLREFCLKSEL; - input [2:0] LOOPBACK; - input [2:0] RXCHBONDLEVEL; - input [2:0] RXOUTCLKSEL; - input [2:0] RXPRBSSEL; - input [2:0] RXRATE; - input [2:0] TXBUFDIFFCTRL; - input [2:0] TXHEADER; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input [2:0] TXPRBSSEL; - input [2:0] TXRATE; - input [3:0] RXOSINTCFG; - input [3:0] RXOSINTID0; - input [3:0] TXDIFFCTRL; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN; - input [4:0] RXCHBONDI; - input [4:0] RXDFEAGCTRL; - input [4:0] RXDFESLIDETAP; - input [4:0] TXPIPPMSTEPSIZE; - input [4:0] TXPOSTCURSOR; - input [4:0] TXPRECURSOR; - input [5:0] RXDFESLIDETAPID; - input [63:0] TXDATA; - input [6:0] TXMAINCURSOR; - input [6:0] TXSEQUENCE; - input [7:0] TX8B10BBYPASS; - input [7:0] TXCHARDISPMODE; - input [7:0] TXCHARDISPVAL; - input [7:0] TXCHARISK; - input [8:0] DRPADDR; -endmodule - -module GTHE2_COMMON (...); - parameter [63:0] BIAS_CFG = 64'h0000040000001000; - parameter [31:0] COMMON_CFG = 32'h0000001C; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; - parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; - parameter [26:0] QPLL_CFG = 27'h0480181; - parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; - parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; - parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; - parameter [9:0] QPLL_CP = 10'b0000011111; - parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; - parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; - parameter [9:0] QPLL_FBDIV = 10'b0000000000; - parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; - parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; - parameter [23:0] QPLL_INIT_CFG = 24'h000006; - parameter [15:0] QPLL_LOCK_CFG = 16'h01E8; - parameter [3:0] QPLL_LPF = 4'b1111; - parameter integer QPLL_REFCLK_DIV = 2; - parameter [0:0] QPLL_RP_COMP = 1'b0; - parameter [1:0] QPLL_VTRL_RESET = 2'b00; - parameter [1:0] RCAL_CFG = 2'b00; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_VERSION = "1.1"; - output DRPRDY; - output QPLLFBCLKLOST; - output QPLLLOCK; - output QPLLOUTCLK; - output QPLLOUTREFCLK; - output QPLLREFCLKLOST; - output REFCLKOUTMONITOR; - output [15:0] DRPDO; - output [15:0] PMARSVDOUT; - output [7:0] QPLLDMONITOR; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input BGRCALOVRDENB; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *) - input QPLLLOCKDETCLK; - input QPLLLOCKEN; - input QPLLOUTRESET; - input QPLLPD; - input QPLLRESET; - input RCALENB; - input [15:0] DRPDI; - input [15:0] QPLLRSVD1; - input [2:0] QPLLREFCLKSEL; - input [4:0] BGRCALOVRD; - input [4:0] QPLLRSVD2; - input [7:0] DRPADDR; - input [7:0] PMARSVD; -endmodule - -module GTPE2_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [19:0] ADAPT_CFG0 = 20'b00000000000000000000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [42:0] CFOK_CFG = 43'b1001001000000000000000001000000111010000000; - parameter [6:0] CFOK_CFG2 = 7'b0100000; - parameter [6:0] CFOK_CFG3 = 7'b0100000; - parameter [0:0] CFOK_CFG4 = 1'b0; - parameter [1:0] CFOK_CFG5 = 2'b00; - parameter [3:0] CFOK_CFG6 = 4'b0000; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 1; - parameter [0:0] CLK_COMMON_SWING = 1'b0; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 1; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [23:0] DMONITOR_CFG = 24'h000A00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h010; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; - parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; - parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; - parameter [8:0] ES_VERT_OFFSET = 9'b000000000; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [2:0] GEARBOX_MODE = 3'b000; - parameter [0:0] IS_CLKRSVD0_INVERTED = 1'b0; - parameter [0:0] IS_CLKRSVD1_INVERTED = 1'b0; - parameter [0:0] IS_DMONITORCLK_INVERTED = 1'b0; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; - parameter [0:0] IS_SIGVALIDCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; - parameter [0:0] LOOPBACK_CFG = 1'b0; - parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; - parameter PCS_PCIE_EN = "FALSE"; - parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [0:0] PMA_LOOPBACK_CFG = 1'b0; - parameter [31:0] PMA_RSV = 32'h00000333; - parameter [31:0] PMA_RSV2 = 32'h00002050; - parameter [1:0] PMA_RSV3 = 2'b00; - parameter [3:0] PMA_RSV4 = 4'b0000; - parameter [0:0] PMA_RSV5 = 1'b0; - parameter [0:0] PMA_RSV6 = 1'b0; - parameter [0:0] PMA_RSV7 = 1'b0; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 61; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [82:0] RXCDR_CFG = 83'h0000107FE406001041010; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [5:0] RXCDR_LOCK_CFG = 6'b001001; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXDLY_CFG = 16'h0010; - parameter [8:0] RXDLY_LCFG = 9'h020; - parameter [15:0] RXDLY_TAP_CFG = 16'h0000; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [6:0] RXLPMRESET_TIME = 7'b0001111; - parameter [0:0] RXLPM_BIAS_STARTUP_DISABLE = 1'b0; - parameter [3:0] RXLPM_CFG = 4'b0110; - parameter [0:0] RXLPM_CFG1 = 1'b0; - parameter [0:0] RXLPM_CM_CFG = 1'b0; - parameter [8:0] RXLPM_GC_CFG = 9'b111100010; - parameter [2:0] RXLPM_GC_CFG2 = 3'b001; - parameter [13:0] RXLPM_HF_CFG = 14'b00001111110000; - parameter [4:0] RXLPM_HF_CFG2 = 5'b01010; - parameter [3:0] RXLPM_HF_CFG3 = 4'b0000; - parameter [0:0] RXLPM_HOLD_DURING_EIDLE = 1'b0; - parameter [0:0] RXLPM_INCM_CFG = 1'b0; - parameter [0:0] RXLPM_IPCM_CFG = 1'b0; - parameter [17:0] RXLPM_LF_CFG = 18'b000000001111110000; - parameter [4:0] RXLPM_LF_CFG2 = 5'b01010; - parameter [2:0] RXLPM_OSINT_CFG = 3'b100; - parameter [6:0] RXOOB_CFG = 7'b0000110; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter [4:0] RXOSCALRESET_TIMEOUT = 5'b00000; - parameter integer RXOUT_DIV = 2; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [23:0] RXPHDLY_CFG = 24'h084000; - parameter [23:0] RXPH_CFG = 24'hC00002; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [2:0] RXPI_CFG0 = 3'b000; - parameter [0:0] RXPI_CFG1 = 1'b0; - parameter [0:0] RXPI_CFG2 = 1'b0; - parameter [4:0] RXPMARESET_TIME = 5'b00011; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [15:0] RX_BIAS_CFG = 16'b0000111100110011; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter integer RX_CLK25_DIV = 7; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [1:0] RX_CM_SEL = 2'b11; - parameter [3:0] RX_CM_TRIM = 4'b0100; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter [13:0] RX_DEBUG_CFG = 14'b00000000000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [12:0] RX_OS_CFG = 13'b0001111110000; - parameter integer RX_SIG_VALID_DLY = 10; - parameter RX_XCLK_SEL = "RXREC"; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SATA_PLL_CFG = "VCO_3000MHZ"; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; - parameter SIM_VERSION = "1.0"; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [31:0] TST_RSV = 32'h00000000; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h0010; - parameter [8:0] TXDLY_LCFG = 9'h020; - parameter [15:0] TXDLY_TAP_CFG = 16'h0000; - parameter TXGEARBOX_EN = "FALSE"; - parameter [0:0] TXOOB_CFG = 1'b0; - parameter integer TXOUT_DIV = 2; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [23:0] TXPHDLY_CFG = 24'h084000; - parameter [15:0] TXPH_CFG = 16'h0400; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b0; - parameter [2:0] TXPI_CFG5 = 3'b000; - parameter [0:0] TXPI_GREY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 7; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [0:0] TX_PREDRIVER_MODE = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h1832; - parameter [2:0] TX_RXDETECT_REF = 3'b100; - parameter TX_XCLK_SEL = "TXUSR"; - parameter [0:0] UCODEER_CLR = 1'b0; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - output DRPRDY; - output EYESCANDATAERROR; - output GTPTXN; - output GTPTXP; - output PHYSTATUS; - output PMARSVDOUT0; - output PMARSVDOUT1; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output RXDLYSRESETDONE; - output RXELECIDLE; - output RXHEADERVALID; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPMARESETDONE; - output RXPRBSERR; - output RXRATEDONE; - output RXRESETDONE; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output TXCOMFINISH; - output TXDLYSRESETDONE; - output TXGEARBOXREADY; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - output [14:0] DMONITOROUT; - output [15:0] DRPDO; - output [15:0] PCSRSVDOUT; - output [1:0] RXCLKCORCNT; - output [1:0] RXDATAVALID; - output [1:0] RXSTARTOFSEQ; - output [1:0] TXBUFSTATUS; - output [2:0] RXBUFSTATUS; - output [2:0] RXHEADER; - output [2:0] RXSTATUS; - output [31:0] RXDATA; - output [3:0] RXCHARISCOMMA; - output [3:0] RXCHARISK; - output [3:0] RXCHBONDO; - output [3:0] RXDISPERR; - output [3:0] RXNOTINTABLE; - output [4:0] RXPHMONITOR; - output [4:0] RXPHSLIPMONITOR; - input CFGRESET; - (* invertible_pin = "IS_CLKRSVD0_INVERTED" *) - input CLKRSVD0; - (* invertible_pin = "IS_CLKRSVD1_INVERTED" *) - input CLKRSVD1; - input DMONFIFORESET; - (* invertible_pin = "IS_DMONITORCLK_INVERTED" *) - input DMONITORCLK; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - input GTPRXN; - input GTPRXP; - input GTRESETSEL; - input GTRXRESET; - input GTTXRESET; - input PLL0CLK; - input PLL0REFCLK; - input PLL1CLK; - input PLL1REFCLK; - input PMARSVDIN0; - input PMARSVDIN1; - input PMARSVDIN2; - input PMARSVDIN3; - input PMARSVDIN4; - input RESETOVRD; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETEN; - input RXDDIEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input RXGEARBOXSLIP; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFOVRDEN; - input RXLPMOSINTNTRLEN; - input RXLPMRESET; - input RXMCOMMAALIGNEN; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTNTRLEN; - input RXOSINTOVRDEN; - input RXOSINTPD; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; - input RXOSOVRDEN; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input RXRATEMODE; - input RXSLIDE; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input RXUSERRDY; - (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) - input RXUSRCLK2; - (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) - input RXUSRCLK; - input SETERRSTATUS; - (* invertible_pin = "IS_SIGVALIDCLK_INVERTED" *) - input SIGVALIDCLK; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input TXDEEMPH; - input TXDETECTRX; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input TXINHIBIT; - input TXPCSRESET; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input TXPISOPD; - input TXPMARESET; - input TXPOLARITY; - input TXPOSTCURSORINV; - input TXPRBSFORCEERR; - input TXPRECURSORINV; - input TXRATEMODE; - input TXSTARTSEQ; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input TXUSERRDY; - (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) - input TXUSRCLK2; - (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) - input TXUSRCLK; - input [13:0] RXADAPTSELTEST; - input [15:0] DRPDI; - input [15:0] GTRSVD; - input [15:0] PCSRSVDIN; - input [19:0] TSTIN; - input [1:0] RXELECIDLEMODE; - input [1:0] RXPD; - input [1:0] RXSYSCLKSEL; - input [1:0] TXPD; - input [1:0] TXSYSCLKSEL; - input [2:0] LOOPBACK; - input [2:0] RXCHBONDLEVEL; - input [2:0] RXOUTCLKSEL; - input [2:0] RXPRBSSEL; - input [2:0] RXRATE; - input [2:0] TXBUFDIFFCTRL; - input [2:0] TXHEADER; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input [2:0] TXPRBSSEL; - input [2:0] TXRATE; - input [31:0] TXDATA; - input [3:0] RXCHBONDI; - input [3:0] RXOSINTCFG; - input [3:0] RXOSINTID0; - input [3:0] TX8B10BBYPASS; - input [3:0] TXCHARDISPMODE; - input [3:0] TXCHARDISPVAL; - input [3:0] TXCHARISK; - input [3:0] TXDIFFCTRL; - input [4:0] TXPIPPMSTEPSIZE; - input [4:0] TXPOSTCURSOR; - input [4:0] TXPRECURSOR; - input [6:0] TXMAINCURSOR; - input [6:0] TXSEQUENCE; - input [8:0] DRPADDR; -endmodule - -module GTPE2_COMMON (...); - parameter [63:0] BIAS_CFG = 64'h0000000000000000; - parameter [31:0] COMMON_CFG = 32'h00000000; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK0_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK1_INVERTED = 1'b0; - parameter [0:0] IS_PLL0LOCKDETCLK_INVERTED = 1'b0; - parameter [0:0] IS_PLL1LOCKDETCLK_INVERTED = 1'b0; - parameter [26:0] PLL0_CFG = 27'h01F03DC; - parameter [0:0] PLL0_DMON_CFG = 1'b0; - parameter integer PLL0_FBDIV = 4; - parameter integer PLL0_FBDIV_45 = 5; - parameter [23:0] PLL0_INIT_CFG = 24'h00001E; - parameter [8:0] PLL0_LOCK_CFG = 9'h1E8; - parameter integer PLL0_REFCLK_DIV = 1; - parameter [26:0] PLL1_CFG = 27'h01F03DC; - parameter [0:0] PLL1_DMON_CFG = 1'b0; - parameter integer PLL1_FBDIV = 4; - parameter integer PLL1_FBDIV_45 = 5; - parameter [23:0] PLL1_INIT_CFG = 24'h00001E; - parameter [8:0] PLL1_LOCK_CFG = 9'h1E8; - parameter integer PLL1_REFCLK_DIV = 1; - parameter [7:0] PLL_CLKOUT_CFG = 8'b00000000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [2:0] SIM_PLL0REFCLK_SEL = 3'b001; - parameter [2:0] SIM_PLL1REFCLK_SEL = 3'b001; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_VERSION = "1.0"; - output DRPRDY; - output PLL0FBCLKLOST; - output PLL0LOCK; - output PLL0OUTCLK; - output PLL0OUTREFCLK; - output PLL0REFCLKLOST; - output PLL1FBCLKLOST; - output PLL1LOCK; - output PLL1OUTCLK; - output PLL1OUTREFCLK; - output PLL1REFCLKLOST; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [15:0] DRPDO; - output [15:0] PMARSVDOUT; - output [7:0] DMONITOROUT; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input BGRCALOVRDENB; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - input GTEASTREFCLK0; - input GTEASTREFCLK1; - (* invertible_pin = "IS_GTGREFCLK0_INVERTED" *) - input GTGREFCLK0; - (* invertible_pin = "IS_GTGREFCLK1_INVERTED" *) - input GTGREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTWESTREFCLK0; - input GTWESTREFCLK1; - (* invertible_pin = "IS_PLL0LOCKDETCLK_INVERTED" *) - input PLL0LOCKDETCLK; - input PLL0LOCKEN; - input PLL0PD; - input PLL0RESET; - (* invertible_pin = "IS_PLL1LOCKDETCLK_INVERTED" *) - input PLL1LOCKDETCLK; - input PLL1LOCKEN; - input PLL1PD; - input PLL1RESET; - input RCALENB; - input [15:0] DRPDI; - input [15:0] PLLRSVD1; - input [2:0] PLL0REFCLKSEL; - input [2:0] PLL1REFCLKSEL; - input [4:0] BGRCALOVRD; - input [4:0] PLLRSVD2; - input [7:0] DRPADDR; - input [7:0] PMARSVD; -endmodule - -module GTXE2_CHANNEL (...); - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 1; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 1; - parameter [23:0] CPLL_CFG = 24'hB007D8; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 5; - parameter [23:0] CPLL_INIT_CFG = 24'h00001E; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [23:0] DMONITOR_CFG = 24'h000A00; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [79:0] ES_QUALIFIER = 80'h00000000000000000000; - parameter [79:0] ES_QUAL_MASK = 80'h00000000000000000000; - parameter [79:0] ES_SDATA_MASK = 80'h00000000000000000000; - parameter [8:0] ES_VERT_OFFSET = 9'b000000000; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [2:0] GEARBOX_MODE = 3'b000; - parameter [0:0] IS_CPLLLOCKDETCLK_INVERTED = 1'b0; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_RXUSRCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXPHDLYTSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK2_INVERTED = 1'b0; - parameter [0:0] IS_TXUSRCLK_INVERTED = 1'b0; - parameter [1:0] OUTREFCLK_SEL_INV = 2'b11; - parameter PCS_PCIE_EN = "FALSE"; - parameter [47:0] PCS_RSVD_ATTR = 48'h000000000000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [31:0] PMA_RSV = 32'h00000000; - parameter [15:0] PMA_RSV2 = 16'h2050; - parameter [1:0] PMA_RSV3 = 2'b00; - parameter [31:0] PMA_RSV4 = 32'h00000000; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 61; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [71:0] RXCDR_CFG = 72'h0B000023FF20400020; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [5:0] RXCDR_LOCK_CFG = 6'b010101; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDLY_CFG = 16'h001F; - parameter [8:0] RXDLY_LCFG = 9'h030; - parameter [15:0] RXDLY_TAP_CFG = 16'h0000; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [13:0] RXLPM_HF_CFG = 14'b00000011110000; - parameter [13:0] RXLPM_LF_CFG = 14'b00000011110000; - parameter [6:0] RXOOB_CFG = 7'b0000110; - parameter integer RXOUT_DIV = 2; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [23:0] RXPHDLY_CFG = 24'h084020; - parameter [23:0] RXPH_CFG = 24'h000000; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [4:0] RXPMARESET_TIME = 5'b00011; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [11:0] RX_BIAS_CFG = 12'b000000000000; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter integer RX_CLK25_DIV = 7; - parameter [0:0] RX_CLKMUX_PD = 1'b1; - parameter [1:0] RX_CM_SEL = 2'b11; - parameter [2:0] RX_CM_TRIM = 3'b100; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter [11:0] RX_DEBUG_CFG = 12'b000000000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [22:0] RX_DFE_GAIN_CFG = 23'h180E0F; - parameter [11:0] RX_DFE_H2_CFG = 12'b000111100000; - parameter [11:0] RX_DFE_H3_CFG = 12'b000111100000; - parameter [10:0] RX_DFE_H4_CFG = 11'b00011110000; - parameter [10:0] RX_DFE_H5_CFG = 11'b00011110000; - parameter [12:0] RX_DFE_KL_CFG = 13'b0001111110000; - parameter [31:0] RX_DFE_KL_CFG2 = 32'h3008E56A; - parameter [15:0] RX_DFE_LPM_CFG = 16'h0904; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter [16:0] RX_DFE_UT_CFG = 17'b00111111000000000; - parameter [16:0] RX_DFE_VP_CFG = 17'b00011111100000000; - parameter [12:0] RX_DFE_XYD_CFG = 13'b0000000010000; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter integer RX_INT_DATAWIDTH = 0; - parameter [12:0] RX_OS_CFG = 13'b0001111110000; - parameter integer RX_SIG_VALID_DLY = 10; - parameter RX_XCLK_SEL = "RXREC"; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter [2:0] SIM_CPLLREFCLK_SEL = 3'b001; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "X"; - parameter SIM_VERSION = "4.0"; - parameter [4:0] TERM_RCAL_CFG = 5'b10000; - parameter [0:0] TERM_RCAL_OVRD = 1'b0; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [31:0] TST_RSV = 32'h00000000; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; - parameter [8:0] TXDLY_LCFG = 9'h030; - parameter [15:0] TXDLY_TAP_CFG = 16'h0000; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 2; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [23:0] TXPHDLY_CFG = 24'h084020; - parameter [15:0] TXPH_CFG = 16'h0780; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter integer TX_CLK25_DIV = 7; - parameter [0:0] TX_CLKMUX_PD = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [4:0] TX_DEEMPH0 = 5'b00000; - parameter [4:0] TX_DEEMPH1 = 5'b00000; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter integer TX_INT_DATAWIDTH = 0; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [0:0] TX_PREDRIVER_MODE = 1'b0; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h1832; - parameter [2:0] TX_RXDETECT_REF = 3'b100; - parameter TX_XCLK_SEL = "TXUSR"; - parameter [0:0] UCODEER_CLR = 1'b0; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output DRPRDY; - output EYESCANDATAERROR; - output GTREFCLKMONITOR; - output GTXTXN; - output GTXTXP; - output PHYSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output RXHEADERVALID; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPRBSERR; - output RXQPISENN; - output RXQPISENP; - output RXRATEDONE; - output RXRESETDONE; - output RXSTARTOFSEQ; - output RXVALID; - output TXCOMFINISH; - output TXDLYSRESETDONE; - output TXGEARBOXREADY; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXQPISENN; - output TXQPISENP; - output TXRATEDONE; - output TXRESETDONE; - output [15:0] DRPDO; - output [15:0] PCSRSVDOUT; - output [1:0] RXCLKCORCNT; - output [1:0] TXBUFSTATUS; - output [2:0] RXBUFSTATUS; - output [2:0] RXHEADER; - output [2:0] RXSTATUS; - output [4:0] RXCHBONDO; - output [4:0] RXPHMONITOR; - output [4:0] RXPHSLIPMONITOR; - output [63:0] RXDATA; - output [6:0] RXMONITOROUT; - output [7:0] DMONITOROUT; - output [7:0] RXCHARISCOMMA; - output [7:0] RXCHARISK; - output [7:0] RXDISPERR; - output [7:0] RXNOTINTABLE; - output [9:0] TSTOUT; - input CFGRESET; - (* invertible_pin = "IS_CPLLLOCKDETCLK_INVERTED" *) - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input CPLLRESET; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTRESETSEL; - input GTRXRESET; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input GTXRXN; - input GTXRXP; - input QPLLCLK; - input QPLLREFCLK; - input RESETOVRD; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETEN; - input RXDDIEN; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input RXDFECM1EN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEVSEN; - input RXDFEXYDEN; - input RXDFEXYDHOLD; - input RXDFEXYDOVRDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input RXGEARBOXSLIP; - input RXLPMEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXMCOMMAALIGNEN; - input RXOOBRESET; - input RXOSHOLD; - input RXOSOVRDEN; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input RXQPIEN; - input RXSLIDE; - input RXUSERRDY; - (* invertible_pin = "IS_RXUSRCLK2_INVERTED" *) - input RXUSRCLK2; - (* invertible_pin = "IS_RXUSRCLK_INVERTED" *) - input RXUSRCLK; - input SETERRSTATUS; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input TXDEEMPH; - input TXDETECTRX; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input TXINHIBIT; - input TXPCSRESET; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - (* invertible_pin = "IS_TXPHDLYTSTCLK_INVERTED" *) - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPISOPD; - input TXPMARESET; - input TXPOLARITY; - input TXPOSTCURSORINV; - input TXPRBSFORCEERR; - input TXPRECURSORINV; - input TXQPIBIASEN; - input TXQPISTRONGPDOWN; - input TXQPIWEAKPUP; - input TXSTARTSEQ; - input TXSWING; - input TXUSERRDY; - (* invertible_pin = "IS_TXUSRCLK2_INVERTED" *) - input TXUSRCLK2; - (* invertible_pin = "IS_TXUSRCLK_INVERTED" *) - input TXUSRCLK; - input [15:0] DRPDI; - input [15:0] GTRSVD; - input [15:0] PCSRSVDIN; - input [19:0] TSTIN; - input [1:0] RXELECIDLEMODE; - input [1:0] RXMONITORSEL; - input [1:0] RXPD; - input [1:0] RXSYSCLKSEL; - input [1:0] TXPD; - input [1:0] TXSYSCLKSEL; - input [2:0] CPLLREFCLKSEL; - input [2:0] LOOPBACK; - input [2:0] RXCHBONDLEVEL; - input [2:0] RXOUTCLKSEL; - input [2:0] RXPRBSSEL; - input [2:0] RXRATE; - input [2:0] TXBUFDIFFCTRL; - input [2:0] TXHEADER; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input [2:0] TXPRBSSEL; - input [2:0] TXRATE; - input [3:0] CLKRSVD; - input [3:0] TXDIFFCTRL; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN2; - input [4:0] PMARSVDIN; - input [4:0] RXCHBONDI; - input [4:0] TXPOSTCURSOR; - input [4:0] TXPRECURSOR; - input [63:0] TXDATA; - input [6:0] TXMAINCURSOR; - input [6:0] TXSEQUENCE; - input [7:0] TX8B10BBYPASS; - input [7:0] TXCHARDISPMODE; - input [7:0] TXCHARDISPVAL; - input [7:0] TXCHARISK; - input [8:0] DRPADDR; -endmodule - -module GTXE2_COMMON (...); - parameter [63:0] BIAS_CFG = 64'h0000040000001000; - parameter [31:0] COMMON_CFG = 32'h00000000; - parameter [0:0] IS_DRPCLK_INVERTED = 1'b0; - parameter [0:0] IS_GTGREFCLK_INVERTED = 1'b0; - parameter [0:0] IS_QPLLLOCKDETCLK_INVERTED = 1'b0; - parameter [26:0] QPLL_CFG = 27'h0680181; - parameter [3:0] QPLL_CLKOUT_CFG = 4'b0000; - parameter [5:0] QPLL_COARSE_FREQ_OVRD = 6'b010000; - parameter [0:0] QPLL_COARSE_FREQ_OVRD_EN = 1'b0; - parameter [9:0] QPLL_CP = 10'b0000011111; - parameter [0:0] QPLL_CP_MONITOR_EN = 1'b0; - parameter [0:0] QPLL_DMONITOR_SEL = 1'b0; - parameter [9:0] QPLL_FBDIV = 10'b0000000000; - parameter [0:0] QPLL_FBDIV_MONITOR_EN = 1'b0; - parameter [0:0] QPLL_FBDIV_RATIO = 1'b0; - parameter [23:0] QPLL_INIT_CFG = 24'h000006; - parameter [15:0] QPLL_LOCK_CFG = 16'h21E8; - parameter [3:0] QPLL_LPF = 4'b1111; - parameter integer QPLL_REFCLK_DIV = 2; - parameter [2:0] SIM_QPLLREFCLK_SEL = 3'b001; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_VERSION = "4.0"; - output DRPRDY; - output QPLLFBCLKLOST; - output QPLLLOCK; - output QPLLOUTCLK; - output QPLLOUTREFCLK; - output QPLLREFCLKLOST; - output REFCLKOUTMONITOR; - output [15:0] DRPDO; - output [7:0] QPLLDMONITOR; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - (* invertible_pin = "IS_DRPCLK_INVERTED" *) - input DRPCLK; - input DRPEN; - input DRPWE; - (* invertible_pin = "IS_GTGREFCLK_INVERTED" *) - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - (* invertible_pin = "IS_QPLLLOCKDETCLK_INVERTED" *) - input QPLLLOCKDETCLK; - input QPLLLOCKEN; - input QPLLOUTRESET; - input QPLLPD; - input QPLLRESET; - input RCALENB; - input [15:0] DRPDI; - input [15:0] QPLLRSVD1; - input [2:0] QPLLREFCLKSEL; - input [4:0] BGRCALOVRD; - input [4:0] QPLLRSVD2; - input [7:0] DRPADDR; - input [7:0] PMARSVD; -endmodule - -module PCIE_2_1 (...); - parameter [11:0] AER_BASE_PTR = 12'h140; - parameter AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [15:0] AER_CAP_ID = 16'h0001; - parameter AER_CAP_MULTIHEADER = "FALSE"; - parameter [11:0] AER_CAP_NEXTPTR = 12'h178; - parameter AER_CAP_ON = "FALSE"; - parameter [23:0] AER_CAP_OPTIONAL_ERR_SUPPORT = 24'h000000; - parameter AER_CAP_PERMIT_ROOTERR_UPDATE = "TRUE"; - parameter [3:0] AER_CAP_VERSION = 4'h2; - parameter ALLOW_X8_GEN2 = "FALSE"; - parameter [31:0] BAR0 = 32'hFFFFFF00; - parameter [31:0] BAR1 = 32'hFFFF0000; - parameter [31:0] BAR2 = 32'hFFFF000C; - parameter [31:0] BAR3 = 32'hFFFFFFFF; - parameter [31:0] BAR4 = 32'h00000000; - parameter [31:0] BAR5 = 32'h00000000; - parameter [7:0] CAPABILITIES_PTR = 8'h40; - parameter [31:0] CARDBUS_CIS_POINTER = 32'h00000000; - parameter integer CFG_ECRC_ERR_CPLSTAT = 0; - parameter [23:0] CLASS_CODE = 24'h000000; - parameter CMD_INTX_IMPLEMENTED = "TRUE"; - parameter CPL_TIMEOUT_DISABLE_SUPPORTED = "FALSE"; - parameter [3:0] CPL_TIMEOUT_RANGES_SUPPORTED = 4'h0; - parameter [6:0] CRM_MODULE_RSTS = 7'h00; - parameter DEV_CAP2_ARI_FORWARDING_SUPPORTED = "FALSE"; - parameter DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED = "FALSE"; - parameter DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED = "FALSE"; - parameter DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED = "FALSE"; - parameter DEV_CAP2_CAS128_COMPLETER_SUPPORTED = "FALSE"; - parameter DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED = "FALSE"; - parameter DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED = "FALSE"; - parameter DEV_CAP2_LTR_MECHANISM_SUPPORTED = "FALSE"; - parameter [1:0] DEV_CAP2_MAX_ENDEND_TLP_PREFIXES = 2'h0; - parameter DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING = "FALSE"; - parameter [1:0] DEV_CAP2_TPH_COMPLETER_SUPPORTED = 2'h0; - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE = "TRUE"; - parameter DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE = "TRUE"; - parameter integer DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "FALSE"; - parameter integer DEV_CAP_MAX_PAYLOAD_SUPPORTED = 2; - parameter integer DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT = 0; - parameter DEV_CAP_ROLE_BASED_ERROR = "TRUE"; - parameter integer DEV_CAP_RSVD_14_12 = 0; - parameter integer DEV_CAP_RSVD_17_16 = 0; - parameter integer DEV_CAP_RSVD_31_29 = 0; - parameter DEV_CONTROL_AUX_POWER_SUPPORTED = "FALSE"; - parameter DEV_CONTROL_EXT_TAG_DEFAULT = "FALSE"; - parameter DISABLE_ASPM_L1_TIMER = "FALSE"; - parameter DISABLE_BAR_FILTERING = "FALSE"; - parameter DISABLE_ERR_MSG = "FALSE"; - parameter DISABLE_ID_CHECK = "FALSE"; - parameter DISABLE_LANE_REVERSAL = "FALSE"; - parameter DISABLE_LOCKED_FILTER = "FALSE"; - parameter DISABLE_PPM_FILTER = "FALSE"; - parameter DISABLE_RX_POISONED_RESP = "FALSE"; - parameter DISABLE_RX_TC_FILTER = "FALSE"; - parameter DISABLE_SCRAMBLING = "FALSE"; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter [11:0] DSN_BASE_PTR = 12'h100; - parameter [15:0] DSN_CAP_ID = 16'h0003; - parameter [11:0] DSN_CAP_NEXTPTR = 12'h10C; - parameter DSN_CAP_ON = "TRUE"; - parameter [3:0] DSN_CAP_VERSION = 4'h1; - parameter [10:0] ENABLE_MSG_ROUTE = 11'h000; - parameter ENABLE_RX_TD_ECRC_TRIM = "FALSE"; - parameter ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED = "FALSE"; - parameter ENTER_RVRY_EI_L0 = "TRUE"; - parameter EXIT_LOOPBACK_ON_EI = "TRUE"; - parameter [31:0] EXPANSION_ROM = 32'hFFFFF001; - parameter [5:0] EXT_CFG_CAP_PTR = 6'h3F; - parameter [9:0] EXT_CFG_XP_CAP_PTR = 10'h3FF; - parameter [7:0] HEADER_TYPE = 8'h00; - parameter [4:0] INFER_EI = 5'h00; - parameter [7:0] INTERRUPT_PIN = 8'h01; - parameter INTERRUPT_STAT_AUTO = "TRUE"; - parameter IS_SWITCH = "FALSE"; - parameter [9:0] LAST_CONFIG_DWORD = 10'h3FF; - parameter LINK_CAP_ASPM_OPTIONALITY = "TRUE"; - parameter integer LINK_CAP_ASPM_SUPPORT = 1; - parameter LINK_CAP_CLOCK_POWER_MANAGEMENT = "FALSE"; - parameter LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP = "FALSE"; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP = "FALSE"; - parameter [3:0] LINK_CAP_MAX_LINK_SPEED = 4'h1; - parameter [5:0] LINK_CAP_MAX_LINK_WIDTH = 6'h08; - parameter integer LINK_CAP_RSVD_23 = 0; - parameter LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE = "FALSE"; - parameter integer LINK_CONTROL_RCB = 0; - parameter LINK_CTRL2_DEEMPHASIS = "FALSE"; - parameter LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE = "FALSE"; - parameter [3:0] LINK_CTRL2_TARGET_LINK_SPEED = 4'h2; - parameter LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [14:0] LL_ACK_TIMEOUT = 15'h0000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter [14:0] LL_REPLAY_TIMEOUT = 15'h0000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter [5:0] LTSSM_MAX_LINK_WIDTH = 6'h01; - parameter MPS_FORCE = "FALSE"; - parameter [7:0] MSIX_BASE_PTR = 8'h9C; - parameter [7:0] MSIX_CAP_ID = 8'h11; - parameter [7:0] MSIX_CAP_NEXTPTR = 8'h00; - parameter MSIX_CAP_ON = "FALSE"; - parameter integer MSIX_CAP_PBA_BIR = 0; - parameter [28:0] MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] MSI_BASE_PTR = 8'h48; - parameter MSI_CAP_64_BIT_ADDR_CAPABLE = "TRUE"; - parameter [7:0] MSI_CAP_ID = 8'h05; - parameter integer MSI_CAP_MULTIMSGCAP = 0; - parameter integer MSI_CAP_MULTIMSG_EXTENSION = 0; - parameter [7:0] MSI_CAP_NEXTPTR = 8'h60; - parameter MSI_CAP_ON = "FALSE"; - parameter MSI_CAP_PER_VECTOR_MASKING_CAPABLE = "TRUE"; - parameter integer N_FTS_COMCLK_GEN1 = 255; - parameter integer N_FTS_COMCLK_GEN2 = 255; - parameter integer N_FTS_GEN1 = 255; - parameter integer N_FTS_GEN2 = 255; - parameter [7:0] PCIE_BASE_PTR = 8'h60; - parameter [7:0] PCIE_CAP_CAPABILITY_ID = 8'h10; - parameter [3:0] PCIE_CAP_CAPABILITY_VERSION = 4'h2; - parameter [3:0] PCIE_CAP_DEVICE_PORT_TYPE = 4'h0; - parameter [7:0] PCIE_CAP_NEXTPTR = 8'h9C; - parameter PCIE_CAP_ON = "TRUE"; - parameter integer PCIE_CAP_RSVD_15_14 = 0; - parameter PCIE_CAP_SLOT_IMPLEMENTED = "FALSE"; - parameter integer PCIE_REVISION = 2; - parameter integer PL_AUTO_CONFIG = 0; - parameter PL_FAST_TRAIN = "FALSE"; - parameter [14:0] PM_ASPML0S_TIMEOUT = 15'h0000; - parameter PM_ASPML0S_TIMEOUT_EN = "FALSE"; - parameter integer PM_ASPML0S_TIMEOUT_FUNC = 0; - parameter PM_ASPM_FASTEXIT = "FALSE"; - parameter [7:0] PM_BASE_PTR = 8'h40; - parameter integer PM_CAP_AUXCURRENT = 0; - parameter PM_CAP_D1SUPPORT = "TRUE"; - parameter PM_CAP_D2SUPPORT = "TRUE"; - parameter PM_CAP_DSI = "FALSE"; - parameter [7:0] PM_CAP_ID = 8'h01; - parameter [7:0] PM_CAP_NEXTPTR = 8'h48; - parameter PM_CAP_ON = "TRUE"; - parameter [4:0] PM_CAP_PMESUPPORT = 5'h0F; - parameter PM_CAP_PME_CLOCK = "FALSE"; - parameter integer PM_CAP_RSVD_04 = 0; - parameter integer PM_CAP_VERSION = 3; - parameter PM_CSR_B2B3 = "FALSE"; - parameter PM_CSR_BPCCEN = "FALSE"; - parameter PM_CSR_NOSOFTRST = "TRUE"; - parameter [7:0] PM_DATA0 = 8'h01; - parameter [7:0] PM_DATA1 = 8'h01; - parameter [7:0] PM_DATA2 = 8'h01; - parameter [7:0] PM_DATA3 = 8'h01; - parameter [7:0] PM_DATA4 = 8'h01; - parameter [7:0] PM_DATA5 = 8'h01; - parameter [7:0] PM_DATA6 = 8'h01; - parameter [7:0] PM_DATA7 = 8'h01; - parameter [1:0] PM_DATA_SCALE0 = 2'h1; - parameter [1:0] PM_DATA_SCALE1 = 2'h1; - parameter [1:0] PM_DATA_SCALE2 = 2'h1; - parameter [1:0] PM_DATA_SCALE3 = 2'h1; - parameter [1:0] PM_DATA_SCALE4 = 2'h1; - parameter [1:0] PM_DATA_SCALE5 = 2'h1; - parameter [1:0] PM_DATA_SCALE6 = 2'h1; - parameter [1:0] PM_DATA_SCALE7 = 2'h1; - parameter PM_MF = "FALSE"; - parameter [11:0] RBAR_BASE_PTR = 12'h178; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR0 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR1 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR2 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR3 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR4 = 5'h00; - parameter [4:0] RBAR_CAP_CONTROL_ENCODEDBAR5 = 5'h00; - parameter [15:0] RBAR_CAP_ID = 16'h0015; - parameter [2:0] RBAR_CAP_INDEX0 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX1 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX2 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX3 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX4 = 3'h0; - parameter [2:0] RBAR_CAP_INDEX5 = 3'h0; - parameter [11:0] RBAR_CAP_NEXTPTR = 12'h000; - parameter RBAR_CAP_ON = "FALSE"; - parameter [31:0] RBAR_CAP_SUP0 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP1 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP2 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP3 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP4 = 32'h00000000; - parameter [31:0] RBAR_CAP_SUP5 = 32'h00000000; - parameter [3:0] RBAR_CAP_VERSION = 4'h1; - parameter [2:0] RBAR_NUM = 3'h1; - parameter integer RECRC_CHK = 0; - parameter RECRC_CHK_TRIM = "FALSE"; - parameter ROOT_CAP_CRS_SW_VISIBILITY = "FALSE"; - parameter [1:0] RP_AUTO_SPD = 2'h1; - parameter [4:0] RP_AUTO_SPD_LOOPCNT = 5'h1F; - parameter SELECT_DLL_IF = "FALSE"; - parameter SIM_VERSION = "1.0"; - parameter SLOT_CAP_ATT_BUTTON_PRESENT = "FALSE"; - parameter SLOT_CAP_ATT_INDICATOR_PRESENT = "FALSE"; - parameter SLOT_CAP_ELEC_INTERLOCK_PRESENT = "FALSE"; - parameter SLOT_CAP_HOTPLUG_CAPABLE = "FALSE"; - parameter SLOT_CAP_HOTPLUG_SURPRISE = "FALSE"; - parameter SLOT_CAP_MRL_SENSOR_PRESENT = "FALSE"; - parameter SLOT_CAP_NO_CMD_COMPLETED_SUPPORT = "FALSE"; - parameter [12:0] SLOT_CAP_PHYSICAL_SLOT_NUM = 13'h0000; - parameter SLOT_CAP_POWER_CONTROLLER_PRESENT = "FALSE"; - parameter SLOT_CAP_POWER_INDICATOR_PRESENT = "FALSE"; - parameter integer SLOT_CAP_SLOT_POWER_LIMIT_SCALE = 0; - parameter [7:0] SLOT_CAP_SLOT_POWER_LIMIT_VALUE = 8'h00; - parameter integer SPARE_BIT0 = 0; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter integer SPARE_BIT3 = 0; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter SSL_MESSAGE_AUTO = "FALSE"; - parameter TECRC_EP_INV = "FALSE"; - parameter TL_RBYPASS = "FALSE"; - parameter integer TL_RX_RAM_RADDR_LATENCY = 0; - parameter integer TL_RX_RAM_RDATA_LATENCY = 2; - parameter integer TL_RX_RAM_WRITE_LATENCY = 0; - parameter TL_TFC_DISABLE = "FALSE"; - parameter TL_TX_CHECKS_DISABLE = "FALSE"; - parameter integer TL_TX_RAM_RADDR_LATENCY = 0; - parameter integer TL_TX_RAM_RDATA_LATENCY = 2; - parameter integer TL_TX_RAM_WRITE_LATENCY = 0; - parameter TRN_DW = "FALSE"; - parameter TRN_NP_FC = "FALSE"; - parameter UPCONFIG_CAPABLE = "TRUE"; - parameter UPSTREAM_FACING = "TRUE"; - parameter UR_ATOMIC = "TRUE"; - parameter UR_CFG1 = "TRUE"; - parameter UR_INV_REQ = "TRUE"; - parameter UR_PRS_RESPONSE = "TRUE"; - parameter USER_CLK2_DIV2 = "FALSE"; - parameter integer USER_CLK_FREQ = 3; - parameter USE_RID_PINS = "FALSE"; - parameter VC0_CPL_INFINITE = "TRUE"; - parameter [12:0] VC0_RX_RAM_LIMIT = 13'h03FF; - parameter integer VC0_TOTAL_CREDITS_CD = 127; - parameter integer VC0_TOTAL_CREDITS_CH = 31; - parameter integer VC0_TOTAL_CREDITS_NPD = 24; - parameter integer VC0_TOTAL_CREDITS_NPH = 12; - parameter integer VC0_TOTAL_CREDITS_PD = 288; - parameter integer VC0_TOTAL_CREDITS_PH = 32; - parameter integer VC0_TX_LASTPACKET = 31; - parameter [11:0] VC_BASE_PTR = 12'h10C; - parameter [15:0] VC_CAP_ID = 16'h0002; - parameter [11:0] VC_CAP_NEXTPTR = 12'h000; - parameter VC_CAP_ON = "FALSE"; - parameter VC_CAP_REJECT_SNOOP_TRANSACTIONS = "FALSE"; - parameter [3:0] VC_CAP_VERSION = 4'h1; - parameter [11:0] VSEC_BASE_PTR = 12'h128; - parameter [15:0] VSEC_CAP_HDR_ID = 16'h1234; - parameter [11:0] VSEC_CAP_HDR_LENGTH = 12'h018; - parameter [3:0] VSEC_CAP_HDR_REVISION = 4'h1; - parameter [15:0] VSEC_CAP_ID = 16'h000B; - parameter VSEC_CAP_IS_LINK_VISIBLE = "TRUE"; - parameter [11:0] VSEC_CAP_NEXTPTR = 12'h140; - parameter VSEC_CAP_ON = "FALSE"; - parameter [3:0] VSEC_CAP_VERSION = 4'h1; - output CFGAERECRCCHECKEN; - output CFGAERECRCGENEN; - output CFGAERROOTERRCORRERRRECEIVED; - output CFGAERROOTERRCORRERRREPORTINGEN; - output CFGAERROOTERRFATALERRRECEIVED; - output CFGAERROOTERRFATALERRREPORTINGEN; - output CFGAERROOTERRNONFATALERRRECEIVED; - output CFGAERROOTERRNONFATALERRREPORTINGEN; - output CFGBRIDGESERREN; - output CFGCOMMANDBUSMASTERENABLE; - output CFGCOMMANDINTERRUPTDISABLE; - output CFGCOMMANDIOENABLE; - output CFGCOMMANDMEMENABLE; - output CFGCOMMANDSERREN; - output CFGDEVCONTROL2ARIFORWARDEN; - output CFGDEVCONTROL2ATOMICEGRESSBLOCK; - output CFGDEVCONTROL2ATOMICREQUESTEREN; - output CFGDEVCONTROL2CPLTIMEOUTDIS; - output CFGDEVCONTROL2IDOCPLEN; - output CFGDEVCONTROL2IDOREQEN; - output CFGDEVCONTROL2LTREN; - output CFGDEVCONTROL2TLPPREFIXBLOCK; - output CFGDEVCONTROLAUXPOWEREN; - output CFGDEVCONTROLCORRERRREPORTINGEN; - output CFGDEVCONTROLENABLERO; - output CFGDEVCONTROLEXTTAGEN; - output CFGDEVCONTROLFATALERRREPORTINGEN; - output CFGDEVCONTROLNONFATALREPORTINGEN; - output CFGDEVCONTROLNOSNOOPEN; - output CFGDEVCONTROLPHANTOMEN; - output CFGDEVCONTROLURERRREPORTINGEN; - output CFGDEVSTATUSCORRERRDETECTED; - output CFGDEVSTATUSFATALERRDETECTED; - output CFGDEVSTATUSNONFATALERRDETECTED; - output CFGDEVSTATUSURDETECTED; - output CFGERRAERHEADERLOGSETN; - output CFGERRCPLRDYN; - output CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIXENABLE; - output CFGINTERRUPTMSIXFM; - output CFGINTERRUPTRDYN; - output CFGLINKCONTROLAUTOBANDWIDTHINTEN; - output CFGLINKCONTROLBANDWIDTHINTEN; - output CFGLINKCONTROLCLOCKPMEN; - output CFGLINKCONTROLCOMMONCLOCK; - output CFGLINKCONTROLEXTENDEDSYNC; - output CFGLINKCONTROLHWAUTOWIDTHDIS; - output CFGLINKCONTROLLINKDISABLE; - output CFGLINKCONTROLRCB; - output CFGLINKCONTROLRETRAINLINK; - output CFGLINKSTATUSAUTOBANDWIDTHSTATUS; - output CFGLINKSTATUSBANDWIDTHSTATUS; - output CFGLINKSTATUSDLLACTIVE; - output CFGLINKSTATUSLINKTRAINING; - output CFGMGMTRDWRDONEN; - output CFGMSGRECEIVED; - output CFGMSGRECEIVEDASSERTINTA; - output CFGMSGRECEIVEDASSERTINTB; - output CFGMSGRECEIVEDASSERTINTC; - output CFGMSGRECEIVEDASSERTINTD; - output CFGMSGRECEIVEDDEASSERTINTA; - output CFGMSGRECEIVEDDEASSERTINTB; - output CFGMSGRECEIVEDDEASSERTINTC; - output CFGMSGRECEIVEDDEASSERTINTD; - output CFGMSGRECEIVEDERRCOR; - output CFGMSGRECEIVEDERRFATAL; - output CFGMSGRECEIVEDERRNONFATAL; - output CFGMSGRECEIVEDPMASNAK; - output CFGMSGRECEIVEDPMETO; - output CFGMSGRECEIVEDPMETOACK; - output CFGMSGRECEIVEDPMPME; - output CFGMSGRECEIVEDSETSLOTPOWERLIMIT; - output CFGMSGRECEIVEDUNLOCK; - output CFGPMCSRPMEEN; - output CFGPMCSRPMESTATUS; - output CFGPMRCVASREQL1N; - output CFGPMRCVENTERL1N; - output CFGPMRCVENTERL23N; - output CFGPMRCVREQACKN; - output CFGROOTCONTROLPMEINTEN; - output CFGROOTCONTROLSYSERRCORRERREN; - output CFGROOTCONTROLSYSERRFATALERREN; - output CFGROOTCONTROLSYSERRNONFATALERREN; - output CFGSLOTCONTROLELECTROMECHILCTLPULSE; - output CFGTRANSACTION; - output CFGTRANSACTIONTYPE; - output DBGSCLRA; - output DBGSCLRB; - output DBGSCLRC; - output DBGSCLRD; - output DBGSCLRE; - output DBGSCLRF; - output DBGSCLRG; - output DBGSCLRH; - output DBGSCLRI; - output DBGSCLRJ; - output DBGSCLRK; - output DRPRDY; - output LL2BADDLLPERR; - output LL2BADTLPERR; - output LL2PROTOCOLERR; - output LL2RECEIVERERR; - output LL2REPLAYROERR; - output LL2REPLAYTOERR; - output LL2SUSPENDOK; - output LL2TFCINIT1SEQ; - output LL2TFCINIT2SEQ; - output LL2TXIDLE; - output LNKCLKEN; - output MIMRXREN; - output MIMRXWEN; - output MIMTXREN; - output MIMTXWEN; - output PIPERX0POLARITY; - output PIPERX1POLARITY; - output PIPERX2POLARITY; - output PIPERX3POLARITY; - output PIPERX4POLARITY; - output PIPERX5POLARITY; - output PIPERX6POLARITY; - output PIPERX7POLARITY; - output PIPETX0COMPLIANCE; - output PIPETX0ELECIDLE; - output PIPETX1COMPLIANCE; - output PIPETX1ELECIDLE; - output PIPETX2COMPLIANCE; - output PIPETX2ELECIDLE; - output PIPETX3COMPLIANCE; - output PIPETX3ELECIDLE; - output PIPETX4COMPLIANCE; - output PIPETX4ELECIDLE; - output PIPETX5COMPLIANCE; - output PIPETX5ELECIDLE; - output PIPETX6COMPLIANCE; - output PIPETX6ELECIDLE; - output PIPETX7COMPLIANCE; - output PIPETX7ELECIDLE; - output PIPETXDEEMPH; - output PIPETXRATE; - output PIPETXRCVRDET; - output PIPETXRESET; - output PL2L0REQ; - output PL2LINKUP; - output PL2RECEIVERERR; - output PL2RECOVERY; - output PL2RXELECIDLE; - output PL2SUSPENDOK; - output PLDIRECTEDCHANGEDONE; - output PLLINKGEN2CAP; - output PLLINKPARTNERGEN2SUPPORTED; - output PLLINKUPCFGCAP; - output PLPHYLNKUPN; - output PLRECEIVEDHOTRST; - output PLSELLNKRATE; - output RECEIVEDFUNCLVLRSTN; - output TL2ASPMSUSPENDCREDITCHECKOK; - output TL2ASPMSUSPENDREQ; - output TL2ERRFCPE; - output TL2ERRMALFORMED; - output TL2ERRRXOVERFLOW; - output TL2PPMSUSPENDOK; - output TRNLNKUP; - output TRNRECRCERR; - output TRNREOF; - output TRNRERRFWD; - output TRNRSOF; - output TRNRSRCDSC; - output TRNRSRCRDY; - output TRNTCFGREQ; - output TRNTDLLPDSTRDY; - output TRNTERRDROP; - output USERRSTN; - output [11:0] DBGVECC; - output [11:0] PLDBGVEC; - output [11:0] TRNFCCPLD; - output [11:0] TRNFCNPD; - output [11:0] TRNFCPD; - output [127:0] TRNRD; - output [12:0] MIMRXRADDR; - output [12:0] MIMRXWADDR; - output [12:0] MIMTXRADDR; - output [12:0] MIMTXWADDR; - output [15:0] CFGMSGDATA; - output [15:0] DRPDO; - output [15:0] PIPETX0DATA; - output [15:0] PIPETX1DATA; - output [15:0] PIPETX2DATA; - output [15:0] PIPETX3DATA; - output [15:0] PIPETX4DATA; - output [15:0] PIPETX5DATA; - output [15:0] PIPETX6DATA; - output [15:0] PIPETX7DATA; - output [1:0] CFGLINKCONTROLASPMCONTROL; - output [1:0] CFGLINKSTATUSCURRENTSPEED; - output [1:0] CFGPMCSRPOWERSTATE; - output [1:0] PIPETX0CHARISK; - output [1:0] PIPETX0POWERDOWN; - output [1:0] PIPETX1CHARISK; - output [1:0] PIPETX1POWERDOWN; - output [1:0] PIPETX2CHARISK; - output [1:0] PIPETX2POWERDOWN; - output [1:0] PIPETX3CHARISK; - output [1:0] PIPETX3POWERDOWN; - output [1:0] PIPETX4CHARISK; - output [1:0] PIPETX4POWERDOWN; - output [1:0] PIPETX5CHARISK; - output [1:0] PIPETX5POWERDOWN; - output [1:0] PIPETX6CHARISK; - output [1:0] PIPETX6POWERDOWN; - output [1:0] PIPETX7CHARISK; - output [1:0] PIPETX7POWERDOWN; - output [1:0] PL2RXPMSTATE; - output [1:0] PLLANEREVERSALMODE; - output [1:0] PLRXPMSTATE; - output [1:0] PLSELLNKWIDTH; - output [1:0] TRNRDLLPSRCRDY; - output [1:0] TRNRREM; - output [2:0] CFGDEVCONTROLMAXPAYLOAD; - output [2:0] CFGDEVCONTROLMAXREADREQ; - output [2:0] CFGINTERRUPTMMENABLE; - output [2:0] CFGPCIELINKSTATE; - output [2:0] PIPETXMARGIN; - output [2:0] PLINITIALLINKWIDTH; - output [2:0] PLTXPMSTATE; - output [31:0] CFGMGMTDO; - output [3:0] CFGDEVCONTROL2CPLTIMEOUTVAL; - output [3:0] CFGLINKSTATUSNEGOTIATEDWIDTH; - output [3:0] TRNTDSTRDY; - output [4:0] LL2LINKSTATUS; - output [5:0] PLLTSSMSTATE; - output [5:0] TRNTBUFAV; - output [63:0] DBGVECA; - output [63:0] DBGVECB; - output [63:0] TL2ERRHDR; - output [63:0] TRNRDLLPDATA; - output [67:0] MIMRXWDATA; - output [68:0] MIMTXWDATA; - output [6:0] CFGTRANSACTIONADDR; - output [6:0] CFGVCTCVCMAP; - output [7:0] CFGINTERRUPTDO; - output [7:0] TRNFCCPLH; - output [7:0] TRNFCNPH; - output [7:0] TRNFCPH; - output [7:0] TRNRBARHIT; - input CFGERRACSN; - input CFGERRATOMICEGRESSBLOCKEDN; - input CFGERRCORN; - input CFGERRCPLABORTN; - input CFGERRCPLTIMEOUTN; - input CFGERRCPLUNEXPECTN; - input CFGERRECRCN; - input CFGERRINTERNALCORN; - input CFGERRINTERNALUNCORN; - input CFGERRLOCKEDN; - input CFGERRMALFORMEDN; - input CFGERRMCBLOCKEDN; - input CFGERRNORECOVERYN; - input CFGERRPOISONEDN; - input CFGERRPOSTEDN; - input CFGERRURN; - input CFGFORCECOMMONCLOCKOFF; - input CFGFORCEEXTENDEDSYNCON; - input CFGINTERRUPTASSERTN; - input CFGINTERRUPTN; - input CFGINTERRUPTSTATN; - input CFGMGMTRDENN; - input CFGMGMTWRENN; - input CFGMGMTWRREADONLYN; - input CFGMGMTWRRW1CASRWN; - input CFGPMFORCESTATEENN; - input CFGPMHALTASPML0SN; - input CFGPMHALTASPML1N; - input CFGPMSENDPMETON; - input CFGPMTURNOFFOKN; - input CFGPMWAKEN; - input CFGTRNPENDINGN; - input CMRSTN; - input CMSTICKYRSTN; - input DBGSUBMODE; - input DLRSTN; - input DRPCLK; - input DRPEN; - input DRPWE; - input FUNCLVLRSTN; - input LL2SENDASREQL1; - input LL2SENDENTERL1; - input LL2SENDENTERL23; - input LL2SENDPMACK; - input LL2SUSPENDNOW; - input LL2TLPRCV; - input PIPECLK; - input PIPERX0CHANISALIGNED; - input PIPERX0ELECIDLE; - input PIPERX0PHYSTATUS; - input PIPERX0VALID; - input PIPERX1CHANISALIGNED; - input PIPERX1ELECIDLE; - input PIPERX1PHYSTATUS; - input PIPERX1VALID; - input PIPERX2CHANISALIGNED; - input PIPERX2ELECIDLE; - input PIPERX2PHYSTATUS; - input PIPERX2VALID; - input PIPERX3CHANISALIGNED; - input PIPERX3ELECIDLE; - input PIPERX3PHYSTATUS; - input PIPERX3VALID; - input PIPERX4CHANISALIGNED; - input PIPERX4ELECIDLE; - input PIPERX4PHYSTATUS; - input PIPERX4VALID; - input PIPERX5CHANISALIGNED; - input PIPERX5ELECIDLE; - input PIPERX5PHYSTATUS; - input PIPERX5VALID; - input PIPERX6CHANISALIGNED; - input PIPERX6ELECIDLE; - input PIPERX6PHYSTATUS; - input PIPERX6VALID; - input PIPERX7CHANISALIGNED; - input PIPERX7ELECIDLE; - input PIPERX7PHYSTATUS; - input PIPERX7VALID; - input PLDIRECTEDLINKAUTON; - input PLDIRECTEDLINKSPEED; - input PLDIRECTEDLTSSMNEWVLD; - input PLDIRECTEDLTSSMSTALL; - input PLDOWNSTREAMDEEMPHSOURCE; - input PLRSTN; - input PLTRANSMITHOTRST; - input PLUPSTREAMPREFERDEEMPH; - input SYSRSTN; - input TL2ASPMSUSPENDCREDITCHECK; - input TL2PPMSUSPENDREQ; - input TLRSTN; - input TRNRDSTRDY; - input TRNRFCPRET; - input TRNRNPOK; - input TRNRNPREQ; - input TRNTCFGGNT; - input TRNTDLLPSRCRDY; - input TRNTECRCGEN; - input TRNTEOF; - input TRNTERRFWD; - input TRNTSOF; - input TRNTSRCDSC; - input TRNTSRCRDY; - input TRNTSTR; - input USERCLK2; - input USERCLK; - input [127:0] CFGERRAERHEADERLOG; - input [127:0] TRNTD; - input [15:0] CFGDEVID; - input [15:0] CFGSUBSYSID; - input [15:0] CFGSUBSYSVENDID; - input [15:0] CFGVENDID; - input [15:0] DRPDI; - input [15:0] PIPERX0DATA; - input [15:0] PIPERX1DATA; - input [15:0] PIPERX2DATA; - input [15:0] PIPERX3DATA; - input [15:0] PIPERX4DATA; - input [15:0] PIPERX5DATA; - input [15:0] PIPERX6DATA; - input [15:0] PIPERX7DATA; - input [1:0] CFGPMFORCESTATE; - input [1:0] DBGMODE; - input [1:0] PIPERX0CHARISK; - input [1:0] PIPERX1CHARISK; - input [1:0] PIPERX2CHARISK; - input [1:0] PIPERX3CHARISK; - input [1:0] PIPERX4CHARISK; - input [1:0] PIPERX5CHARISK; - input [1:0] PIPERX6CHARISK; - input [1:0] PIPERX7CHARISK; - input [1:0] PLDIRECTEDLINKCHANGE; - input [1:0] PLDIRECTEDLINKWIDTH; - input [1:0] TRNTREM; - input [2:0] CFGDSFUNCTIONNUMBER; - input [2:0] CFGFORCEMPS; - input [2:0] PIPERX0STATUS; - input [2:0] PIPERX1STATUS; - input [2:0] PIPERX2STATUS; - input [2:0] PIPERX3STATUS; - input [2:0] PIPERX4STATUS; - input [2:0] PIPERX5STATUS; - input [2:0] PIPERX6STATUS; - input [2:0] PIPERX7STATUS; - input [2:0] PLDBGMODE; - input [2:0] TRNFCSEL; - input [31:0] CFGMGMTDI; - input [31:0] TRNTDLLPDATA; - input [3:0] CFGMGMTBYTEENN; - input [47:0] CFGERRTLPCPLHEADER; - input [4:0] CFGAERINTERRUPTMSGNUM; - input [4:0] CFGDSDEVICENUMBER; - input [4:0] CFGPCIECAPINTERRUPTMSGNUM; - input [4:0] PL2DIRECTEDLSTATE; - input [5:0] PLDIRECTEDLTSSMNEW; - input [63:0] CFGDSN; - input [67:0] MIMRXRDATA; - input [68:0] MIMTXRDATA; - input [7:0] CFGDSBUSNUMBER; - input [7:0] CFGINTERRUPTDI; - input [7:0] CFGPORTNUMBER; - input [7:0] CFGREVID; - input [8:0] DRPADDR; - input [9:0] CFGMGMTDWADDR; -endmodule - -module PCIE_3_0 (...); - parameter ARI_CAP_ENABLE = "FALSE"; - parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; - parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; - parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; - parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; - parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; - parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; - parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; - parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1; - parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE"; - parameter [8:0] LL_ACK_TIMEOUT = 9'h000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; - parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; - parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; - parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; - parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; - parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; - parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; - parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [3:0] PF0_ARI_CAP_VER = 4'h1; - parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_BAR1_CONTROL = 3'h0; - parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR3_CONTROL = 3'h0; - parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR5_CONTROL = 3'h0; - parameter [7:0] PF0_BIST_REGISTER = 8'h00; - parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF0_CLASS_CODE = 24'h000000; - parameter [15:0] PF0_DEVICE_ID = 16'h0000; - parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; - parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; - parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; - parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; - parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; - parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF0_DPA_CAP_VER = 4'h1; - parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; - parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; - parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; - parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; - parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_LTR_CAP_VER = 4'h1; - parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; - parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; - parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF0_PB_CAP_VER = 4'h1; - parameter [7:0] PF0_PM_CAP_ID = 8'h01; - parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; - parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; - parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; - parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; - parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; - parameter PF0_RBAR_CAP_ENABLE = "FALSE"; - parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0; - parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0; - parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0; - parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF0_RBAR_NUM = 3'h1; - parameter [7:0] PF0_REVISION_ID = 8'h00; - parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; - parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF0_TPHR_CAP_ENABLE = "FALSE"; - parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; - parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_VC_CAP_VER = 4'h1; - parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_BAR1_CONTROL = 3'h0; - parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR3_CONTROL = 3'h0; - parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR5_CONTROL = 3'h0; - parameter [7:0] PF1_BIST_REGISTER = 8'h00; - parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF1_CLASS_CODE = 24'h000000; - parameter [15:0] PF1_DEVICE_ID = 16'h0000; - parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF1_DPA_CAP_VER = 4'h1; - parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; - parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; - parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF1_PB_CAP_VER = 4'h1; - parameter [7:0] PF1_PM_CAP_ID = 8'h01; - parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; - parameter PF1_RBAR_CAP_ENABLE = "FALSE"; - parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0; - parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0; - parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0; - parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF1_RBAR_NUM = 3'h1; - parameter [7:0] PF1_REVISION_ID = 8'h00; - parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; - parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF1_TPHR_CAP_ENABLE = "FALSE"; - parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; - parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; - parameter PL_DISABLE_SCRAMBLING = "FALSE"; - parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; - parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; - parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; - parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; - parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; - parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; - parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; - parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; - parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; - parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; - parameter integer PL_N_FTS_COMCLK_GEN1 = 255; - parameter integer PL_N_FTS_COMCLK_GEN2 = 255; - parameter integer PL_N_FTS_COMCLK_GEN3 = 255; - parameter integer PL_N_FTS_GEN1 = 255; - parameter integer PL_N_FTS_GEN2 = 255; - parameter integer PL_N_FTS_GEN3 = 255; - parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; - parameter PL_UPSTREAM_FACING = "TRUE"; - parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; - parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; - parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; - parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; - parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; - parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; - parameter SIM_VERSION = "1.0"; - parameter integer SPARE_BIT0 = 0; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter integer SPARE_BIT3 = 0; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter SRIOV_CAP_ENABLE = "FALSE"; - parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; - parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000; - parameter [11:0] TL_CREDITS_CD = 12'h3E0; - parameter [7:0] TL_CREDITS_CH = 8'h20; - parameter [11:0] TL_CREDITS_NPD = 12'h028; - parameter [7:0] TL_CREDITS_NPH = 8'h20; - parameter [11:0] TL_CREDITS_PD = 12'h198; - parameter [7:0] TL_CREDITS_PH = 8'h20; - parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; - parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter TL_LEGACY_MODE_ENABLE = "FALSE"; - parameter TL_PF_ENABLE_REG = "FALSE"; - parameter TL_TAG_MGMT_ENABLE = "TRUE"; - parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; - parameter integer VF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF0_PM_CAP_ID = 8'h01; - parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; - parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF0_TPHR_CAP_ENABLE = "FALSE"; - parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF1_PM_CAP_ID = 8'h01; - parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; - parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF1_TPHR_CAP_ENABLE = "FALSE"; - parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF2_PM_CAP_ID = 8'h01; - parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; - parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF2_TPHR_CAP_ENABLE = "FALSE"; - parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF3_PM_CAP_ID = 8'h01; - parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; - parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF3_TPHR_CAP_ENABLE = "FALSE"; - parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF4_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF4_PM_CAP_ID = 8'h01; - parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; - parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF4_TPHR_CAP_ENABLE = "FALSE"; - parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF5_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF5_PM_CAP_ID = 8'h01; - parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; - parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF5_TPHR_CAP_ENABLE = "FALSE"; - parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; - output CFGERRCOROUT; - output CFGERRFATALOUT; - output CFGERRNONFATALOUT; - output CFGEXTREADRECEIVED; - output CFGEXTWRITERECEIVED; - output CFGHOTRESETOUT; - output CFGINPUTUPDATEDONE; - output CFGINTERRUPTAOUTPUT; - output CFGINTERRUPTBOUTPUT; - output CFGINTERRUPTCOUTPUT; - output CFGINTERRUPTDOUTPUT; - output CFGINTERRUPTMSIFAIL; - output CFGINTERRUPTMSIMASKUPDATE; - output CFGINTERRUPTMSISENT; - output CFGINTERRUPTMSIXFAIL; - output CFGINTERRUPTMSIXSENT; - output CFGINTERRUPTSENT; - output CFGLOCALERROR; - output CFGLTRENABLE; - output CFGMCUPDATEDONE; - output CFGMGMTREADWRITEDONE; - output CFGMSGRECEIVED; - output CFGMSGTRANSMITDONE; - output CFGPERFUNCTIONUPDATEDONE; - output CFGPHYLINKDOWN; - output CFGPLSTATUSCHANGE; - output CFGPOWERSTATECHANGEINTERRUPT; - output CFGTPHSTTREADENABLE; - output CFGTPHSTTWRITEENABLE; - output DRPRDY; - output MAXISCQTLAST; - output MAXISCQTVALID; - output MAXISRCTLAST; - output MAXISRCTVALID; - output PCIERQSEQNUMVLD; - output PCIERQTAGVLD; - output PIPERX0POLARITY; - output PIPERX1POLARITY; - output PIPERX2POLARITY; - output PIPERX3POLARITY; - output PIPERX4POLARITY; - output PIPERX5POLARITY; - output PIPERX6POLARITY; - output PIPERX7POLARITY; - output PIPETX0COMPLIANCE; - output PIPETX0DATAVALID; - output PIPETX0ELECIDLE; - output PIPETX0STARTBLOCK; - output PIPETX1COMPLIANCE; - output PIPETX1DATAVALID; - output PIPETX1ELECIDLE; - output PIPETX1STARTBLOCK; - output PIPETX2COMPLIANCE; - output PIPETX2DATAVALID; - output PIPETX2ELECIDLE; - output PIPETX2STARTBLOCK; - output PIPETX3COMPLIANCE; - output PIPETX3DATAVALID; - output PIPETX3ELECIDLE; - output PIPETX3STARTBLOCK; - output PIPETX4COMPLIANCE; - output PIPETX4DATAVALID; - output PIPETX4ELECIDLE; - output PIPETX4STARTBLOCK; - output PIPETX5COMPLIANCE; - output PIPETX5DATAVALID; - output PIPETX5ELECIDLE; - output PIPETX5STARTBLOCK; - output PIPETX6COMPLIANCE; - output PIPETX6DATAVALID; - output PIPETX6ELECIDLE; - output PIPETX6STARTBLOCK; - output PIPETX7COMPLIANCE; - output PIPETX7DATAVALID; - output PIPETX7ELECIDLE; - output PIPETX7STARTBLOCK; - output PIPETXDEEMPH; - output PIPETXRCVRDET; - output PIPETXRESET; - output PIPETXSWING; - output PLEQINPROGRESS; - output [11:0] CFGFCCPLD; - output [11:0] CFGFCNPD; - output [11:0] CFGFCPD; - output [11:0] CFGVFSTATUS; - output [143:0] MIREPLAYRAMWRITEDATA; - output [143:0] MIREQUESTRAMWRITEDATA; - output [15:0] CFGPERFUNCSTATUSDATA; - output [15:0] DBGDATAOUT; - output [15:0] DRPDO; - output [17:0] CFGVFPOWERSTATE; - output [17:0] CFGVFTPHSTMODE; - output [1:0] CFGDPASUBSTATECHANGE; - output [1:0] CFGFLRINPROCESS; - output [1:0] CFGINTERRUPTMSIENABLE; - output [1:0] CFGINTERRUPTMSIXENABLE; - output [1:0] CFGINTERRUPTMSIXMASK; - output [1:0] CFGLINKPOWERSTATE; - output [1:0] CFGOBFFENABLE; - output [1:0] CFGPHYLINKSTATUS; - output [1:0] CFGRCBSTATUS; - output [1:0] CFGTPHREQUESTERENABLE; - output [1:0] MIREPLAYRAMREADENABLE; - output [1:0] MIREPLAYRAMWRITEENABLE; - output [1:0] PCIERQTAGAV; - output [1:0] PCIETFCNPDAV; - output [1:0] PCIETFCNPHAV; - output [1:0] PIPERX0EQCONTROL; - output [1:0] PIPERX1EQCONTROL; - output [1:0] PIPERX2EQCONTROL; - output [1:0] PIPERX3EQCONTROL; - output [1:0] PIPERX4EQCONTROL; - output [1:0] PIPERX5EQCONTROL; - output [1:0] PIPERX6EQCONTROL; - output [1:0] PIPERX7EQCONTROL; - output [1:0] PIPETX0CHARISK; - output [1:0] PIPETX0EQCONTROL; - output [1:0] PIPETX0POWERDOWN; - output [1:0] PIPETX0SYNCHEADER; - output [1:0] PIPETX1CHARISK; - output [1:0] PIPETX1EQCONTROL; - output [1:0] PIPETX1POWERDOWN; - output [1:0] PIPETX1SYNCHEADER; - output [1:0] PIPETX2CHARISK; - output [1:0] PIPETX2EQCONTROL; - output [1:0] PIPETX2POWERDOWN; - output [1:0] PIPETX2SYNCHEADER; - output [1:0] PIPETX3CHARISK; - output [1:0] PIPETX3EQCONTROL; - output [1:0] PIPETX3POWERDOWN; - output [1:0] PIPETX3SYNCHEADER; - output [1:0] PIPETX4CHARISK; - output [1:0] PIPETX4EQCONTROL; - output [1:0] PIPETX4POWERDOWN; - output [1:0] PIPETX4SYNCHEADER; - output [1:0] PIPETX5CHARISK; - output [1:0] PIPETX5EQCONTROL; - output [1:0] PIPETX5POWERDOWN; - output [1:0] PIPETX5SYNCHEADER; - output [1:0] PIPETX6CHARISK; - output [1:0] PIPETX6EQCONTROL; - output [1:0] PIPETX6POWERDOWN; - output [1:0] PIPETX6SYNCHEADER; - output [1:0] PIPETX7CHARISK; - output [1:0] PIPETX7EQCONTROL; - output [1:0] PIPETX7POWERDOWN; - output [1:0] PIPETX7SYNCHEADER; - output [1:0] PIPETXRATE; - output [1:0] PLEQPHASE; - output [255:0] MAXISCQTDATA; - output [255:0] MAXISRCTDATA; - output [2:0] CFGCURRENTSPEED; - output [2:0] CFGMAXPAYLOAD; - output [2:0] CFGMAXREADREQ; - output [2:0] CFGTPHFUNCTIONNUM; - output [2:0] PIPERX0EQPRESET; - output [2:0] PIPERX1EQPRESET; - output [2:0] PIPERX2EQPRESET; - output [2:0] PIPERX3EQPRESET; - output [2:0] PIPERX4EQPRESET; - output [2:0] PIPERX5EQPRESET; - output [2:0] PIPERX6EQPRESET; - output [2:0] PIPERX7EQPRESET; - output [2:0] PIPETXMARGIN; - output [31:0] CFGEXTWRITEDATA; - output [31:0] CFGINTERRUPTMSIDATA; - output [31:0] CFGMGMTREADDATA; - output [31:0] CFGTPHSTTWRITEDATA; - output [31:0] PIPETX0DATA; - output [31:0] PIPETX1DATA; - output [31:0] PIPETX2DATA; - output [31:0] PIPETX3DATA; - output [31:0] PIPETX4DATA; - output [31:0] PIPETX5DATA; - output [31:0] PIPETX6DATA; - output [31:0] PIPETX7DATA; - output [3:0] CFGEXTWRITEBYTEENABLE; - output [3:0] CFGNEGOTIATEDWIDTH; - output [3:0] CFGTPHSTTWRITEBYTEVALID; - output [3:0] MICOMPLETIONRAMREADENABLEL; - output [3:0] MICOMPLETIONRAMREADENABLEU; - output [3:0] MICOMPLETIONRAMWRITEENABLEL; - output [3:0] MICOMPLETIONRAMWRITEENABLEU; - output [3:0] MIREQUESTRAMREADENABLE; - output [3:0] MIREQUESTRAMWRITEENABLE; - output [3:0] PCIERQSEQNUM; - output [3:0] PIPERX0EQLPTXPRESET; - output [3:0] PIPERX1EQLPTXPRESET; - output [3:0] PIPERX2EQLPTXPRESET; - output [3:0] PIPERX3EQLPTXPRESET; - output [3:0] PIPERX4EQLPTXPRESET; - output [3:0] PIPERX5EQLPTXPRESET; - output [3:0] PIPERX6EQLPTXPRESET; - output [3:0] PIPERX7EQLPTXPRESET; - output [3:0] PIPETX0EQPRESET; - output [3:0] PIPETX1EQPRESET; - output [3:0] PIPETX2EQPRESET; - output [3:0] PIPETX3EQPRESET; - output [3:0] PIPETX4EQPRESET; - output [3:0] PIPETX5EQPRESET; - output [3:0] PIPETX6EQPRESET; - output [3:0] PIPETX7EQPRESET; - output [3:0] SAXISCCTREADY; - output [3:0] SAXISRQTREADY; - output [4:0] CFGMSGRECEIVEDTYPE; - output [4:0] CFGTPHSTTADDRESS; - output [5:0] CFGFUNCTIONPOWERSTATE; - output [5:0] CFGINTERRUPTMSIMMENABLE; - output [5:0] CFGINTERRUPTMSIVFENABLE; - output [5:0] CFGINTERRUPTMSIXVFENABLE; - output [5:0] CFGINTERRUPTMSIXVFMASK; - output [5:0] CFGLTSSMSTATE; - output [5:0] CFGTPHSTMODE; - output [5:0] CFGVFFLRINPROCESS; - output [5:0] CFGVFTPHREQUESTERENABLE; - output [5:0] PCIECQNPREQCOUNT; - output [5:0] PCIERQTAG; - output [5:0] PIPERX0EQLPLFFS; - output [5:0] PIPERX1EQLPLFFS; - output [5:0] PIPERX2EQLPLFFS; - output [5:0] PIPERX3EQLPLFFS; - output [5:0] PIPERX4EQLPLFFS; - output [5:0] PIPERX5EQLPLFFS; - output [5:0] PIPERX6EQLPLFFS; - output [5:0] PIPERX7EQLPLFFS; - output [5:0] PIPETX0EQDEEMPH; - output [5:0] PIPETX1EQDEEMPH; - output [5:0] PIPETX2EQDEEMPH; - output [5:0] PIPETX3EQDEEMPH; - output [5:0] PIPETX4EQDEEMPH; - output [5:0] PIPETX5EQDEEMPH; - output [5:0] PIPETX6EQDEEMPH; - output [5:0] PIPETX7EQDEEMPH; - output [71:0] MICOMPLETIONRAMWRITEDATAL; - output [71:0] MICOMPLETIONRAMWRITEDATAU; - output [74:0] MAXISRCTUSER; - output [7:0] CFGEXTFUNCTIONNUMBER; - output [7:0] CFGFCCPLH; - output [7:0] CFGFCNPH; - output [7:0] CFGFCPH; - output [7:0] CFGFUNCTIONSTATUS; - output [7:0] CFGMSGRECEIVEDDATA; - output [7:0] MAXISCQTKEEP; - output [7:0] MAXISRCTKEEP; - output [7:0] PLGEN3PCSRXSLIDE; - output [84:0] MAXISCQTUSER; - output [8:0] MIREPLAYRAMADDRESS; - output [8:0] MIREQUESTRAMREADADDRESSA; - output [8:0] MIREQUESTRAMREADADDRESSB; - output [8:0] MIREQUESTRAMWRITEADDRESSA; - output [8:0] MIREQUESTRAMWRITEADDRESSB; - output [9:0] CFGEXTREGISTERNUMBER; - output [9:0] MICOMPLETIONRAMREADADDRESSAL; - output [9:0] MICOMPLETIONRAMREADADDRESSAU; - output [9:0] MICOMPLETIONRAMREADADDRESSBL; - output [9:0] MICOMPLETIONRAMREADADDRESSBU; - output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; - output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; - output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; - output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; - input CFGCONFIGSPACEENABLE; - input CFGERRCORIN; - input CFGERRUNCORIN; - input CFGEXTREADDATAVALID; - input CFGHOTRESETIN; - input CFGINPUTUPDATEREQUEST; - input CFGINTERRUPTMSITPHPRESENT; - input CFGINTERRUPTMSIXINT; - input CFGLINKTRAININGENABLE; - input CFGMCUPDATEREQUEST; - input CFGMGMTREAD; - input CFGMGMTTYPE1CFGREGACCESS; - input CFGMGMTWRITE; - input CFGMSGTRANSMIT; - input CFGPERFUNCTIONOUTPUTREQUEST; - input CFGPOWERSTATECHANGEACK; - input CFGREQPMTRANSITIONL23READY; - input CFGTPHSTTREADDATAVALID; - input CORECLK; - input CORECLKMICOMPLETIONRAML; - input CORECLKMICOMPLETIONRAMU; - input CORECLKMIREPLAYRAM; - input CORECLKMIREQUESTRAM; - input DRPCLK; - input DRPEN; - input DRPWE; - input MGMTRESETN; - input MGMTSTICKYRESETN; - input PCIECQNPREQ; - input PIPECLK; - input PIPERESETN; - input PIPERX0DATAVALID; - input PIPERX0ELECIDLE; - input PIPERX0EQDONE; - input PIPERX0EQLPADAPTDONE; - input PIPERX0EQLPLFFSSEL; - input PIPERX0PHYSTATUS; - input PIPERX0STARTBLOCK; - input PIPERX0VALID; - input PIPERX1DATAVALID; - input PIPERX1ELECIDLE; - input PIPERX1EQDONE; - input PIPERX1EQLPADAPTDONE; - input PIPERX1EQLPLFFSSEL; - input PIPERX1PHYSTATUS; - input PIPERX1STARTBLOCK; - input PIPERX1VALID; - input PIPERX2DATAVALID; - input PIPERX2ELECIDLE; - input PIPERX2EQDONE; - input PIPERX2EQLPADAPTDONE; - input PIPERX2EQLPLFFSSEL; - input PIPERX2PHYSTATUS; - input PIPERX2STARTBLOCK; - input PIPERX2VALID; - input PIPERX3DATAVALID; - input PIPERX3ELECIDLE; - input PIPERX3EQDONE; - input PIPERX3EQLPADAPTDONE; - input PIPERX3EQLPLFFSSEL; - input PIPERX3PHYSTATUS; - input PIPERX3STARTBLOCK; - input PIPERX3VALID; - input PIPERX4DATAVALID; - input PIPERX4ELECIDLE; - input PIPERX4EQDONE; - input PIPERX4EQLPADAPTDONE; - input PIPERX4EQLPLFFSSEL; - input PIPERX4PHYSTATUS; - input PIPERX4STARTBLOCK; - input PIPERX4VALID; - input PIPERX5DATAVALID; - input PIPERX5ELECIDLE; - input PIPERX5EQDONE; - input PIPERX5EQLPADAPTDONE; - input PIPERX5EQLPLFFSSEL; - input PIPERX5PHYSTATUS; - input PIPERX5STARTBLOCK; - input PIPERX5VALID; - input PIPERX6DATAVALID; - input PIPERX6ELECIDLE; - input PIPERX6EQDONE; - input PIPERX6EQLPADAPTDONE; - input PIPERX6EQLPLFFSSEL; - input PIPERX6PHYSTATUS; - input PIPERX6STARTBLOCK; - input PIPERX6VALID; - input PIPERX7DATAVALID; - input PIPERX7ELECIDLE; - input PIPERX7EQDONE; - input PIPERX7EQLPADAPTDONE; - input PIPERX7EQLPLFFSSEL; - input PIPERX7PHYSTATUS; - input PIPERX7STARTBLOCK; - input PIPERX7VALID; - input PIPETX0EQDONE; - input PIPETX1EQDONE; - input PIPETX2EQDONE; - input PIPETX3EQDONE; - input PIPETX4EQDONE; - input PIPETX5EQDONE; - input PIPETX6EQDONE; - input PIPETX7EQDONE; - input PLDISABLESCRAMBLER; - input PLEQRESETEIEOSCOUNT; - input PLGEN3PCSDISABLE; - input RECCLK; - input RESETN; - input SAXISCCTLAST; - input SAXISCCTVALID; - input SAXISRQTLAST; - input SAXISRQTVALID; - input USERCLK; - input [10:0] DRPADDR; - input [143:0] MICOMPLETIONRAMREADDATA; - input [143:0] MIREPLAYRAMREADDATA; - input [143:0] MIREQUESTRAMREADDATA; - input [15:0] CFGDEVID; - input [15:0] CFGSUBSYSID; - input [15:0] CFGSUBSYSVENDID; - input [15:0] CFGVENDID; - input [15:0] DRPDI; - input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; - input [17:0] PIPETX0EQCOEFF; - input [17:0] PIPETX1EQCOEFF; - input [17:0] PIPETX2EQCOEFF; - input [17:0] PIPETX3EQCOEFF; - input [17:0] PIPETX4EQCOEFF; - input [17:0] PIPETX5EQCOEFF; - input [17:0] PIPETX6EQCOEFF; - input [17:0] PIPETX7EQCOEFF; - input [18:0] CFGMGMTADDR; - input [1:0] CFGFLRDONE; - input [1:0] CFGINTERRUPTMSITPHTYPE; - input [1:0] CFGINTERRUPTPENDING; - input [1:0] PIPERX0CHARISK; - input [1:0] PIPERX0SYNCHEADER; - input [1:0] PIPERX1CHARISK; - input [1:0] PIPERX1SYNCHEADER; - input [1:0] PIPERX2CHARISK; - input [1:0] PIPERX2SYNCHEADER; - input [1:0] PIPERX3CHARISK; - input [1:0] PIPERX3SYNCHEADER; - input [1:0] PIPERX4CHARISK; - input [1:0] PIPERX4SYNCHEADER; - input [1:0] PIPERX5CHARISK; - input [1:0] PIPERX5SYNCHEADER; - input [1:0] PIPERX6CHARISK; - input [1:0] PIPERX6SYNCHEADER; - input [1:0] PIPERX7CHARISK; - input [1:0] PIPERX7SYNCHEADER; - input [21:0] MAXISCQTREADY; - input [21:0] MAXISRCTREADY; - input [255:0] SAXISCCTDATA; - input [255:0] SAXISRQTDATA; - input [2:0] CFGDSFUNCTIONNUMBER; - input [2:0] CFGFCSEL; - input [2:0] CFGINTERRUPTMSIATTR; - input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER; - input [2:0] CFGMSGTRANSMITTYPE; - input [2:0] CFGPERFUNCSTATUSCONTROL; - input [2:0] CFGPERFUNCTIONNUMBER; - input [2:0] PIPERX0STATUS; - input [2:0] PIPERX1STATUS; - input [2:0] PIPERX2STATUS; - input [2:0] PIPERX3STATUS; - input [2:0] PIPERX4STATUS; - input [2:0] PIPERX5STATUS; - input [2:0] PIPERX6STATUS; - input [2:0] PIPERX7STATUS; - input [31:0] CFGEXTREADDATA; - input [31:0] CFGINTERRUPTMSIINT; - input [31:0] CFGINTERRUPTMSIXDATA; - input [31:0] CFGMGMTWRITEDATA; - input [31:0] CFGMSGTRANSMITDATA; - input [31:0] CFGTPHSTTREADDATA; - input [31:0] PIPERX0DATA; - input [31:0] PIPERX1DATA; - input [31:0] PIPERX2DATA; - input [31:0] PIPERX3DATA; - input [31:0] PIPERX4DATA; - input [31:0] PIPERX5DATA; - input [31:0] PIPERX6DATA; - input [31:0] PIPERX7DATA; - input [32:0] SAXISCCTUSER; - input [3:0] CFGINTERRUPTINT; - input [3:0] CFGINTERRUPTMSISELECT; - input [3:0] CFGMGMTBYTEENABLE; - input [4:0] CFGDSDEVICENUMBER; - input [59:0] SAXISRQTUSER; - input [5:0] CFGVFFLRDONE; - input [5:0] PIPEEQFS; - input [5:0] PIPEEQLF; - input [63:0] CFGDSN; - input [63:0] CFGINTERRUPTMSIPENDINGSTATUS; - input [63:0] CFGINTERRUPTMSIXADDRESS; - input [7:0] CFGDSBUSNUMBER; - input [7:0] CFGDSPORTNUMBER; - input [7:0] CFGREVID; - input [7:0] PLGEN3PCSRXSYNCDONE; - input [7:0] SAXISCCTKEEP; - input [7:0] SAXISRQTKEEP; - input [8:0] CFGINTERRUPTMSITPHSTTAG; -endmodule - -module XADC (...); - parameter [15:0] INIT_40 = 16'h0; - parameter [15:0] INIT_41 = 16'h0; - parameter [15:0] INIT_42 = 16'h0800; - parameter [15:0] INIT_43 = 16'h0; - parameter [15:0] INIT_44 = 16'h0; - parameter [15:0] INIT_45 = 16'h0; - parameter [15:0] INIT_46 = 16'h0; - parameter [15:0] INIT_47 = 16'h0; - parameter [15:0] INIT_48 = 16'h0; - parameter [15:0] INIT_49 = 16'h0; - parameter [15:0] INIT_4A = 16'h0; - parameter [15:0] INIT_4B = 16'h0; - parameter [15:0] INIT_4C = 16'h0; - parameter [15:0] INIT_4D = 16'h0; - parameter [15:0] INIT_4E = 16'h0; - parameter [15:0] INIT_4F = 16'h0; - parameter [15:0] INIT_50 = 16'h0; - parameter [15:0] INIT_51 = 16'h0; - parameter [15:0] INIT_52 = 16'h0; - parameter [15:0] INIT_53 = 16'h0; - parameter [15:0] INIT_54 = 16'h0; - parameter [15:0] INIT_55 = 16'h0; - parameter [15:0] INIT_56 = 16'h0; - parameter [15:0] INIT_57 = 16'h0; - parameter [15:0] INIT_58 = 16'h0; - parameter [15:0] INIT_59 = 16'h0; - parameter [15:0] INIT_5A = 16'h0; - parameter [15:0] INIT_5B = 16'h0; - parameter [15:0] INIT_5C = 16'h0; - parameter [15:0] INIT_5D = 16'h0; - parameter [15:0] INIT_5E = 16'h0; - parameter [15:0] INIT_5F = 16'h0; - parameter IS_CONVSTCLK_INVERTED = 1'b0; - parameter IS_DCLK_INVERTED = 1'b0; - parameter SIM_DEVICE = "7SERIES"; - parameter SIM_MONITOR_FILE = "design.txt"; - output BUSY; - output DRDY; - output EOC; - output EOS; - output JTAGBUSY; - output JTAGLOCKED; - output JTAGMODIFIED; - output OT; - output [15:0] DO; - output [7:0] ALM; - output [4:0] CHANNEL; - output [4:0] MUXADDR; - input CONVST; - (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) - input CONVSTCLK; - (* invertible_pin = "IS_DCLK_INVERTED" *) - input DCLK; - input DEN; - input DWE; - input RESET; - input VN; - input VP; - input [15:0] DI; - input [15:0] VAUXN; - input [15:0] VAUXP; - input [6:0] DADDR; -endmodule - -module BUFGCE (...); - parameter CE_TYPE = "SYNC"; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_I_INVERTED = 1'b0; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_I_INVERTED" *) - input I; -endmodule - -module BUFGCE_1 (...); - (* clkbuf_driver *) - output O; - input CE; - input I; -endmodule - -module BUFGMUX (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_1 (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_CTRL (...); - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFH (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFIO (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFMR (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFMRCE (...); - parameter CE_TYPE = "SYNC"; - parameter integer INIT_OUT = 0; - parameter [0:0] IS_CE_INVERTED = 1'b0; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - input I; -endmodule - -module BUFR (...); - parameter BUFR_DIVIDE = "BYPASS"; - parameter SIM_DEVICE = "7SERIES"; - (* clkbuf_driver *) - output O; - input CE; - input CLR; - input I; -endmodule - -module MMCME2_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; - parameter COMPENSATION = "ZHOLD"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PSEN_INVERTED = 1'b0; - parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter SS_EN = "FALSE"; - parameter SS_MODE = "CENTER_HIGH"; - parameter integer SS_MOD_PERIOD = 10000; - parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output [15:0] DO; - output DRDY; - output LOCKED; - output PSDONE; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input PSCLK; - (* invertible_pin = "IS_PSEN_INVERTED" *) - input PSEN; - (* invertible_pin = "IS_PSINCDEC_INVERTED" *) - input PSINCDEC; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME2_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - input CLKFBIN; - input CLKIN1; - input PWRDWN; - input RST; -endmodule - -module PLLE2_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter COMPENSATION = "ZHOLD"; - parameter STARTUP_WAIT = "FALSE"; - parameter integer CLKOUT0_DIVIDE = 1; - parameter integer CLKOUT1_DIVIDE = 1; - parameter integer CLKOUT2_DIVIDE = 1; - parameter integer CLKOUT3_DIVIDE = 1; - parameter integer CLKOUT4_DIVIDE = 1; - parameter integer CLKOUT5_DIVIDE = 1; - parameter integer DIVCLK_DIVIDE = 1; - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter real VCOCLK_FREQ_MAX = 2133.000; - parameter real VCOCLK_FREQ_MIN = 800.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 19.000; - parameter real CLKPFD_FREQ_MAX = 550.0; - parameter real CLKPFD_FREQ_MIN = 19.0; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output DRDY; - output LOCKED; - output [15:0] DO; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input DCLK; - input DEN; - input DWE; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input [15:0] DI; - input [6:0] DADDR; -endmodule - -module PLLE2_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output LOCKED; - input CLKFBIN; - input CLKIN1; - input PWRDWN; - input RST; -endmodule - -(* keep *) -module BSCANE2 (...); - parameter DISABLE_JTAG = "FALSE"; - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output RUNTEST; - output SEL; - output SHIFT; - output TCK; - output TDI; - output TMS; - output UPDATE; - input TDO; -endmodule - -(* keep *) -module CAPTUREE2 (...); - parameter ONESHOT = "TRUE"; - input CAP; - input CLK; -endmodule - -module DNA_PORT (...); - parameter [56:0] SIM_DNA_VALUE = 57'h0; - output DOUT; - input CLK; - input DIN; - input READ; - input SHIFT; -endmodule - -module EFUSE_USR (...); - parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; - output [31:0] EFUSEUSR; -endmodule - -module FRAME_ECCE2 (...); - parameter FARSRC = "EFAR"; - parameter FRAME_RBT_IN_FILENAME = "NONE"; - output CRCERROR; - output ECCERROR; - output ECCERRORSINGLE; - output SYNDROMEVALID; - output [12:0] SYNDROME; - output [25:0] FAR; - output [4:0] SYNBIT; - output [6:0] SYNWORD; -endmodule - -(* keep *) -module ICAPE2 (...); - parameter [31:0] DEVICE_ID = 32'h04244093; - parameter ICAP_WIDTH = "X32"; - parameter SIM_CFG_FILE_NAME = "NONE"; - output [31:0] O; - input CLK; - input CSIB; - input RDWRB; - input [31:0] I; -endmodule - -(* keep *) -module STARTUPE2 (...); - parameter PROG_USR = "FALSE"; - parameter real SIM_CCLK_FREQ = 0.0; - output CFGCLK; - output CFGMCLK; - output EOS; - output PREQ; - input CLK; - input GSR; - input GTS; - input KEYCLEARB; - input PACK; - input USRCCLKO; - input USRCCLKTS; - input USRDONEO; - input USRDONETS; -endmodule - -module USR_ACCESSE2 (...); - output CFGCLK; - output DATAVALID; - output [31:0] DATA; -endmodule - -(* keep *) -module DCIRESET (...); - output LOCKED; - input RST; -endmodule - -module IBUF_IBUFDISABLE (...); - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - input IBUFDISABLE; -endmodule - -module IBUF_INTERMDISABLE (...); - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IFD_DELAY_VALUE = "AUTO"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_DIFF_OUT_IBUFDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; -endmodule - -module IBUFDS_DIFF_OUT_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUFDS_GTE2 (...); - parameter CLKCM_CFG = "TRUE"; - parameter CLKRCV_TRST = "TRUE"; - parameter CLKSWING_CFG = "TRUE"; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_IBUFDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; -endmodule - -module IBUFDS_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUFGDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFGDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -(* keep *) -module IDELAYCTRL (...); - parameter SIM_DEVICE = "7SERIES"; - output RDY; - (* clkbuf_sink *) - input REFCLK; - input RST; -endmodule - -module IDELAYE2 (...); - parameter CINVCTRL_SEL = "FALSE"; - parameter DELAY_SRC = "IDATAIN"; - parameter HIGH_PERFORMANCE_MODE = "FALSE"; - parameter IDELAY_TYPE = "FIXED"; - parameter integer IDELAY_VALUE = 0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_DATAIN_INVERTED = 1'b0; - parameter [0:0] IS_IDATAIN_INVERTED = 1'b0; - parameter PIPE_SEL = "FALSE"; - parameter real REFCLK_FREQUENCY = 200.0; - parameter SIGNAL_PATTERN = "DATA"; - parameter integer SIM_DELAY_D = 0; - output [4:0] CNTVALUEOUT; - output DATAOUT; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - input CINVCTRL; - input [4:0] CNTVALUEIN; - (* invertible_pin = "IS_DATAIN_INVERTED" *) - input DATAIN; - (* invertible_pin = "IS_IDATAIN_INVERTED" *) - input IDATAIN; - input INC; - input LD; - input LDPIPEEN; - input REGRST; -endmodule - -module IN_FIFO (...); - parameter integer ALMOST_EMPTY_VALUE = 1; - parameter integer ALMOST_FULL_VALUE = 1; - parameter ARRAY_MODE = "ARRAY_MODE_4_X_8"; - parameter SYNCHRONOUS_MODE = "FALSE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output EMPTY; - output FULL; - output [7:0] Q0; - output [7:0] Q1; - output [7:0] Q2; - output [7:0] Q3; - output [7:0] Q4; - output [7:0] Q5; - output [7:0] Q6; - output [7:0] Q7; - output [7:0] Q8; - output [7:0] Q9; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RESET; - (* clkbuf_sink *) - input WRCLK; - input WREN; - input [3:0] D0; - input [3:0] D1; - input [3:0] D2; - input [3:0] D3; - input [3:0] D4; - input [3:0] D7; - input [3:0] D8; - input [3:0] D9; - input [7:0] D5; - input [7:0] D6; -endmodule - -module IOBUF (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input T; -endmodule - -module IOBUF_DCIEN (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input T; -endmodule - -module IOBUF_INTERMDISABLE (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input T; -endmodule - -module IOBUFDS (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - inout IOB; - input I; - input T; -endmodule - -module IOBUFDS_DCIEN (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input T; -endmodule - -module IOBUFDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input TM; - input TS; -endmodule - -module IOBUFDS_DIFF_OUT_DCIEN (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input TM; - input TS; -endmodule - -module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input TM; - input TS; -endmodule - -module IOBUFDS_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input T; -endmodule - -module ISERDESE2 (...); - parameter DATA_RATE = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter DYN_CLKDIV_INV_EN = "FALSE"; - parameter DYN_CLK_INV_EN = "FALSE"; - parameter [0:0] INIT_Q1 = 1'b0; - parameter [0:0] INIT_Q2 = 1'b0; - parameter [0:0] INIT_Q3 = 1'b0; - parameter [0:0] INIT_Q4 = 1'b0; - parameter INTERFACE_TYPE = "MEMORY"; - parameter IOBDELAY = "NONE"; - parameter [0:0] IS_CLKB_INVERTED = 1'b0; - parameter [0:0] IS_CLKDIVP_INVERTED = 1'b0; - parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter [0:0] IS_OCLKB_INVERTED = 1'b0; - parameter [0:0] IS_OCLK_INVERTED = 1'b0; - parameter integer NUM_CE = 2; - parameter OFB_USED = "FALSE"; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_Q1 = 1'b0; - parameter [0:0] SRVAL_Q2 = 1'b0; - parameter [0:0] SRVAL_Q3 = 1'b0; - parameter [0:0] SRVAL_Q4 = 1'b0; - output O; - output Q1; - output Q2; - output Q3; - output Q4; - output Q5; - output Q6; - output Q7; - output Q8; - output SHIFTOUT1; - output SHIFTOUT2; - input BITSLIP; - input CE1; - input CE2; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKB_INVERTED" *) - input CLKB; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKDIV_INVERTED" *) - input CLKDIV; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKDIVP_INVERTED" *) - input CLKDIVP; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - input DDLY; - input DYNCLKDIVSEL; - input DYNCLKSEL; - (* clkbuf_sink *) - (* invertible_pin = "IS_OCLK_INVERTED" *) - input OCLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_OCLKB_INVERTED" *) - input OCLKB; - input OFB; - input RST; - input SHIFTIN1; - input SHIFTIN2; -endmodule - -module KEEPER (...); - inout O; -endmodule - -module OBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; -endmodule - -module OBUFT (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter integer DRIVE = 12; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - input I; - input T; -endmodule - -module OBUFTDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; - input T; -endmodule - -module ODELAYE2 (...); - parameter CINVCTRL_SEL = "FALSE"; - parameter DELAY_SRC = "ODATAIN"; - parameter HIGH_PERFORMANCE_MODE = "FALSE"; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_ODATAIN_INVERTED = 1'b0; - parameter ODELAY_TYPE = "FIXED"; - parameter integer ODELAY_VALUE = 0; - parameter PIPE_SEL = "FALSE"; - parameter real REFCLK_FREQUENCY = 200.0; - parameter SIGNAL_PATTERN = "DATA"; - parameter integer SIM_DELAY_D = 0; - output [4:0] CNTVALUEOUT; - output DATAOUT; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - input CINVCTRL; - input CLKIN; - input [4:0] CNTVALUEIN; - input INC; - input LD; - input LDPIPEEN; - (* invertible_pin = "IS_ODATAIN_INVERTED" *) - input ODATAIN; - input REGRST; -endmodule - -module OSERDESE2 (...); - parameter DATA_RATE_OQ = "DDR"; - parameter DATA_RATE_TQ = "DDR"; - parameter integer DATA_WIDTH = 4; - parameter [0:0] INIT_OQ = 1'b0; - parameter [0:0] INIT_TQ = 1'b0; - parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_D1_INVERTED = 1'b0; - parameter [0:0] IS_D2_INVERTED = 1'b0; - parameter [0:0] IS_D3_INVERTED = 1'b0; - parameter [0:0] IS_D4_INVERTED = 1'b0; - parameter [0:0] IS_D5_INVERTED = 1'b0; - parameter [0:0] IS_D6_INVERTED = 1'b0; - parameter [0:0] IS_D7_INVERTED = 1'b0; - parameter [0:0] IS_D8_INVERTED = 1'b0; - parameter [0:0] IS_T1_INVERTED = 1'b0; - parameter [0:0] IS_T2_INVERTED = 1'b0; - parameter [0:0] IS_T3_INVERTED = 1'b0; - parameter [0:0] IS_T4_INVERTED = 1'b0; - parameter SERDES_MODE = "MASTER"; - parameter [0:0] SRVAL_OQ = 1'b0; - parameter [0:0] SRVAL_TQ = 1'b0; - parameter TBYTE_CTL = "FALSE"; - parameter TBYTE_SRC = "FALSE"; - parameter integer TRISTATE_WIDTH = 4; - output OFB; - output OQ; - output SHIFTOUT1; - output SHIFTOUT2; - output TBYTEOUT; - output TFB; - output TQ; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKDIV_INVERTED" *) - input CLKDIV; - (* invertible_pin = "IS_D1_INVERTED" *) - input D1; - (* invertible_pin = "IS_D2_INVERTED" *) - input D2; - (* invertible_pin = "IS_D3_INVERTED" *) - input D3; - (* invertible_pin = "IS_D4_INVERTED" *) - input D4; - (* invertible_pin = "IS_D5_INVERTED" *) - input D5; - (* invertible_pin = "IS_D6_INVERTED" *) - input D6; - (* invertible_pin = "IS_D7_INVERTED" *) - input D7; - (* invertible_pin = "IS_D8_INVERTED" *) - input D8; - input OCE; - input RST; - input SHIFTIN1; - input SHIFTIN2; - (* invertible_pin = "IS_T1_INVERTED" *) - input T1; - (* invertible_pin = "IS_T2_INVERTED" *) - input T2; - (* invertible_pin = "IS_T3_INVERTED" *) - input T3; - (* invertible_pin = "IS_T4_INVERTED" *) - input T4; - input TBYTEIN; - input TCE; -endmodule - -module OUT_FIFO (...); - parameter integer ALMOST_EMPTY_VALUE = 1; - parameter integer ALMOST_FULL_VALUE = 1; - parameter ARRAY_MODE = "ARRAY_MODE_8_X_4"; - parameter OUTPUT_DISABLE = "FALSE"; - parameter SYNCHRONOUS_MODE = "FALSE"; - output ALMOSTEMPTY; - output ALMOSTFULL; - output EMPTY; - output FULL; - output [3:0] Q0; - output [3:0] Q1; - output [3:0] Q2; - output [3:0] Q3; - output [3:0] Q4; - output [3:0] Q7; - output [3:0] Q8; - output [3:0] Q9; - output [7:0] Q5; - output [7:0] Q6; - (* clkbuf_sink *) - input RDCLK; - input RDEN; - input RESET; - (* clkbuf_sink *) - input WRCLK; - input WREN; - input [7:0] D0; - input [7:0] D1; - input [7:0] D2; - input [7:0] D3; - input [7:0] D4; - input [7:0] D5; - input [7:0] D6; - input [7:0] D7; - input [7:0] D8; - input [7:0] D9; -endmodule - -module PHASER_IN (...); - parameter integer CLKOUT_DIV = 4; - parameter DQS_BIAS_MODE = "FALSE"; - parameter EN_ISERDES_RST = "FALSE"; - parameter integer FINE_DELAY = 0; - parameter FREQ_REF_DIV = "NONE"; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real MEMREFCLK_PERIOD = 0.000; - parameter OUTPUT_CLK_SRC = "PHASE_REF"; - parameter real PHASEREFCLK_PERIOD = 0.000; - parameter real REFCLK_PERIOD = 0.000; - parameter integer SEL_CLK_OFFSET = 5; - parameter SYNC_IN_DIV_RST = "FALSE"; - output FINEOVERFLOW; - output ICLK; - output ICLKDIV; - output ISERDESRST; - output RCLK; - output [5:0] COUNTERREADVAL; - input COUNTERLOADEN; - input COUNTERREADEN; - input DIVIDERST; - input EDGEADV; - input FINEENABLE; - input FINEINC; - input FREQREFCLK; - input MEMREFCLK; - input PHASEREFCLK; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input SYNCIN; - input SYSCLK; - input [1:0] RANKSEL; - input [5:0] COUNTERLOADVAL; -endmodule - -module PHASER_IN_PHY (...); - parameter BURST_MODE = "FALSE"; - parameter integer CLKOUT_DIV = 4; - parameter [0:0] DQS_AUTO_RECAL = 1'b1; - parameter DQS_BIAS_MODE = "FALSE"; - parameter [2:0] DQS_FIND_PATTERN = 3'b001; - parameter integer FINE_DELAY = 0; - parameter FREQ_REF_DIV = "NONE"; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real MEMREFCLK_PERIOD = 0.000; - parameter OUTPUT_CLK_SRC = "PHASE_REF"; - parameter real PHASEREFCLK_PERIOD = 0.000; - parameter real REFCLK_PERIOD = 0.000; - parameter integer SEL_CLK_OFFSET = 5; - parameter SYNC_IN_DIV_RST = "FALSE"; - parameter WR_CYCLES = "FALSE"; - output DQSFOUND; - output DQSOUTOFRANGE; - output FINEOVERFLOW; - output ICLK; - output ICLKDIV; - output ISERDESRST; - output PHASELOCKED; - output RCLK; - output WRENABLE; - output [5:0] COUNTERREADVAL; - input BURSTPENDINGPHY; - input COUNTERLOADEN; - input COUNTERREADEN; - input FINEENABLE; - input FINEINC; - input FREQREFCLK; - input MEMREFCLK; - input PHASEREFCLK; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input RSTDQSFIND; - input SYNCIN; - input SYSCLK; - input [1:0] ENCALIBPHY; - input [1:0] RANKSELPHY; - input [5:0] COUNTERLOADVAL; -endmodule - -module PHASER_OUT (...); - parameter integer CLKOUT_DIV = 4; - parameter COARSE_BYPASS = "FALSE"; - parameter integer COARSE_DELAY = 0; - parameter EN_OSERDES_RST = "FALSE"; - parameter integer FINE_DELAY = 0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real MEMREFCLK_PERIOD = 0.000; - parameter OCLKDELAY_INV = "FALSE"; - parameter integer OCLK_DELAY = 0; - parameter OUTPUT_CLK_SRC = "PHASE_REF"; - parameter real PHASEREFCLK_PERIOD = 0.000; - parameter [2:0] PO = 3'b000; - parameter real REFCLK_PERIOD = 0.000; - parameter SYNC_IN_DIV_RST = "FALSE"; - output COARSEOVERFLOW; - output FINEOVERFLOW; - output OCLK; - output OCLKDELAYED; - output OCLKDIV; - output OSERDESRST; - output [8:0] COUNTERREADVAL; - input COARSEENABLE; - input COARSEINC; - input COUNTERLOADEN; - input COUNTERREADEN; - input DIVIDERST; - input EDGEADV; - input FINEENABLE; - input FINEINC; - input FREQREFCLK; - input MEMREFCLK; - input PHASEREFCLK; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input SELFINEOCLKDELAY; - input SYNCIN; - input SYSCLK; - input [8:0] COUNTERLOADVAL; -endmodule - -module PHASER_OUT_PHY (...); - parameter integer CLKOUT_DIV = 4; - parameter COARSE_BYPASS = "FALSE"; - parameter integer COARSE_DELAY = 0; - parameter DATA_CTL_N = "FALSE"; - parameter DATA_RD_CYCLES = "FALSE"; - parameter integer FINE_DELAY = 0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real MEMREFCLK_PERIOD = 0.000; - parameter OCLKDELAY_INV = "FALSE"; - parameter integer OCLK_DELAY = 0; - parameter OUTPUT_CLK_SRC = "PHASE_REF"; - parameter real PHASEREFCLK_PERIOD = 0.000; - parameter [2:0] PO = 3'b000; - parameter real REFCLK_PERIOD = 0.000; - parameter SYNC_IN_DIV_RST = "FALSE"; - output COARSEOVERFLOW; - output FINEOVERFLOW; - output OCLK; - output OCLKDELAYED; - output OCLKDIV; - output OSERDESRST; - output RDENABLE; - output [1:0] CTSBUS; - output [1:0] DQSBUS; - output [1:0] DTSBUS; - output [8:0] COUNTERREADVAL; - input BURSTPENDINGPHY; - input COARSEENABLE; - input COARSEINC; - input COUNTERLOADEN; - input COUNTERREADEN; - input FINEENABLE; - input FINEINC; - input FREQREFCLK; - input MEMREFCLK; - input PHASEREFCLK; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input SELFINEOCLKDELAY; - input SYNCIN; - input SYSCLK; - input [1:0] ENCALIBPHY; - input [8:0] COUNTERLOADVAL; -endmodule - -module PHASER_REF (...); - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - output LOCKED; - input CLKIN; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PHY_CONTROL (...); - parameter integer AO_TOGGLE = 0; - parameter [3:0] AO_WRLVL_EN = 4'b0000; - parameter BURST_MODE = "FALSE"; - parameter integer CLK_RATIO = 1; - parameter integer CMD_OFFSET = 0; - parameter integer CO_DURATION = 0; - parameter DATA_CTL_A_N = "FALSE"; - parameter DATA_CTL_B_N = "FALSE"; - parameter DATA_CTL_C_N = "FALSE"; - parameter DATA_CTL_D_N = "FALSE"; - parameter DISABLE_SEQ_MATCH = "TRUE"; - parameter integer DI_DURATION = 0; - parameter integer DO_DURATION = 0; - parameter integer EVENTS_DELAY = 63; - parameter integer FOUR_WINDOW_CLOCKS = 63; - parameter MULTI_REGION = "FALSE"; - parameter PHY_COUNT_ENABLE = "FALSE"; - parameter integer RD_CMD_OFFSET_0 = 0; - parameter integer RD_CMD_OFFSET_1 = 00; - parameter integer RD_CMD_OFFSET_2 = 0; - parameter integer RD_CMD_OFFSET_3 = 0; - parameter integer RD_DURATION_0 = 0; - parameter integer RD_DURATION_1 = 0; - parameter integer RD_DURATION_2 = 0; - parameter integer RD_DURATION_3 = 0; - parameter SYNC_MODE = "FALSE"; - parameter integer WR_CMD_OFFSET_0 = 0; - parameter integer WR_CMD_OFFSET_1 = 0; - parameter integer WR_CMD_OFFSET_2 = 0; - parameter integer WR_CMD_OFFSET_3 = 0; - parameter integer WR_DURATION_0 = 0; - parameter integer WR_DURATION_1 = 0; - parameter integer WR_DURATION_2 = 0; - parameter integer WR_DURATION_3 = 0; - output PHYCTLALMOSTFULL; - output PHYCTLEMPTY; - output PHYCTLFULL; - output PHYCTLREADY; - output [1:0] INRANKA; - output [1:0] INRANKB; - output [1:0] INRANKC; - output [1:0] INRANKD; - output [1:0] PCENABLECALIB; - output [3:0] AUXOUTPUT; - output [3:0] INBURSTPENDING; - output [3:0] OUTBURSTPENDING; - input MEMREFCLK; - input PHYCLK; - input PHYCTLMSTREMPTY; - input PHYCTLWRENABLE; - input PLLLOCK; - input READCALIBENABLE; - input REFDLLLOCK; - input RESET; - input SYNCIN; - input WRITECALIBENABLE; - input [31:0] PHYCTLWD; -endmodule - -module PULLDOWN (...); - output O; -endmodule - -module PULLUP (...); - output O; -endmodule - -module FIFO18E1 (...); - parameter ALMOST_EMPTY_OFFSET = 13'h0080; - parameter ALMOST_FULL_OFFSET = 13'h0080; - parameter integer DATA_WIDTH = 4; - parameter integer DO_REG = 1; - parameter EN_SYN = "FALSE"; - parameter FIFO_MODE = "FIFO18"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter INIT = 36'h0; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL = 36'h0; - parameter IS_RDCLK_INVERTED = 1'b0; - parameter IS_RDEN_INVERTED = 1'b0; - parameter IS_RSTREG_INVERTED = 1'b0; - parameter IS_RST_INVERTED = 1'b0; - parameter IS_WRCLK_INVERTED = 1'b0; - parameter IS_WREN_INVERTED = 1'b0; - output ALMOSTEMPTY; - output ALMOSTFULL; - output [31:0] DO; - output [3:0] DOP; - output EMPTY; - output FULL; - output [11:0] RDCOUNT; - output RDERR; - output [11:0] WRCOUNT; - output WRERR; - input [31:0] DI; - input [3:0] DIP; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module FIFO36E1 (...); - parameter ALMOST_EMPTY_OFFSET = 13'h0080; - parameter ALMOST_FULL_OFFSET = 13'h0080; - parameter integer DATA_WIDTH = 4; - parameter integer DO_REG = 1; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter EN_SYN = "FALSE"; - parameter FIFO_MODE = "FIFO36"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter INIT = 72'h0; - parameter SIM_DEVICE = "VIRTEX6"; - parameter SRVAL = 72'h0; - parameter IS_RDCLK_INVERTED = 1'b0; - parameter IS_RDEN_INVERTED = 1'b0; - parameter IS_RSTREG_INVERTED = 1'b0; - parameter IS_RST_INVERTED = 1'b0; - parameter IS_WRCLK_INVERTED = 1'b0; - parameter IS_WREN_INVERTED = 1'b0; - output ALMOSTEMPTY; - output ALMOSTFULL; - output DBITERR; - output [63:0] DO; - output [7:0] DOP; - output [7:0] ECCPARITY; - output EMPTY; - output FULL; - output [12:0] RDCOUNT; - output RDERR; - output SBITERR; - output [12:0] WRCOUNT; - output WRERR; - input [63:0] DI; - input [7:0] DIP; - input INJECTDBITERR; - input INJECTSBITERR; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module RAM128X1S (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM256X1S (...); - parameter [255:0] INIT = 256'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input [7:0] A; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [1:0] DOA; - output [1:0] DOB; - output [1:0] DOC; - output [1:0] DOD; - input [4:0] ADDRA; - input [4:0] ADDRB; - input [4:0] ADDRC; - input [4:0] ADDRD; - input [1:0] DIA; - input [1:0] DIB; - input [1:0] DIC; - input [1:0] DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S_1 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X2S (...); - parameter [31:0] INIT_00 = 32'h00000000; - parameter [31:0] INIT_01 = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input A4; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DOA; - output DOB; - output DOC; - output DOD; - input [5:0] ADDRA; - input [5:0] ADDRB; - input [5:0] ADDRC; - input [5:0] ADDRD; - input DIA; - input DIB; - input DIC; - input DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S_1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X2S (...); - parameter [63:0] INIT_00 = 64'h0000000000000000; - parameter [63:0] INIT_01 = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O0; - output O1; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D0; - input D1; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module ROM128X1 (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; -endmodule - -module ROM256X1 (...); - parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input A7; -endmodule - -module ROM32X1 (...); - parameter [31:0] INIT = 32'h00000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; -endmodule - -module ROM64X1 (...); - parameter [63:0] INIT = 64'h0000000000000000; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; -endmodule - -module IDDR (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT_Q1 = 1'b0; - parameter INIT_Q2 = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q1; - output Q2; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - input R; - input S; -endmodule - -module IDDR_2CLK (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT_Q1 = 1'b0; - parameter INIT_Q2 = 1'b0; - parameter [0:0] IS_CB_INVERTED = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - output Q1; - output Q2; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* clkbuf_sink *) - (* invertible_pin = "IS_CB_INVERTED" *) - input CB; - input CE; - (* invertible_pin = "IS_D_INVERTED" *) - input D; - input R; - input S; -endmodule - -module ODDR (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter INIT = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D1_INVERTED = 1'b0; - parameter [0:0] IS_D2_INVERTED = 1'b0; - parameter SRTYPE = "SYNC"; - parameter MSGON = "TRUE"; - parameter XON = "TRUE"; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - input CE; - (* invertible_pin = "IS_D1_INVERTED" *) - input D1; - (* invertible_pin = "IS_D2_INVERTED" *) - input D2; - input R; - input S; -endmodule - -module CFGLUT5 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - output CDO; - output O5; - output O6; - input I4; - input I3; - input I2; - input I1; - input I0; - input CDI; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; -endmodule - -(* keep *) -module PS7 (...); - output DMA0DAVALID; - output DMA0DRREADY; - output DMA0RSTN; - output DMA1DAVALID; - output DMA1DRREADY; - output DMA1RSTN; - output DMA2DAVALID; - output DMA2DRREADY; - output DMA2RSTN; - output DMA3DAVALID; - output DMA3DRREADY; - output DMA3RSTN; - output EMIOCAN0PHYTX; - output EMIOCAN1PHYTX; - output EMIOENET0GMIITXEN; - output EMIOENET0GMIITXER; - output EMIOENET0MDIOMDC; - output EMIOENET0MDIOO; - output EMIOENET0MDIOTN; - output EMIOENET0PTPDELAYREQRX; - output EMIOENET0PTPDELAYREQTX; - output EMIOENET0PTPPDELAYREQRX; - output EMIOENET0PTPPDELAYREQTX; - output EMIOENET0PTPPDELAYRESPRX; - output EMIOENET0PTPPDELAYRESPTX; - output EMIOENET0PTPSYNCFRAMERX; - output EMIOENET0PTPSYNCFRAMETX; - output EMIOENET0SOFRX; - output EMIOENET0SOFTX; - output EMIOENET1GMIITXEN; - output EMIOENET1GMIITXER; - output EMIOENET1MDIOMDC; - output EMIOENET1MDIOO; - output EMIOENET1MDIOTN; - output EMIOENET1PTPDELAYREQRX; - output EMIOENET1PTPDELAYREQTX; - output EMIOENET1PTPPDELAYREQRX; - output EMIOENET1PTPPDELAYREQTX; - output EMIOENET1PTPPDELAYRESPRX; - output EMIOENET1PTPPDELAYRESPTX; - output EMIOENET1PTPSYNCFRAMERX; - output EMIOENET1PTPSYNCFRAMETX; - output EMIOENET1SOFRX; - output EMIOENET1SOFTX; - output EMIOI2C0SCLO; - output EMIOI2C0SCLTN; - output EMIOI2C0SDAO; - output EMIOI2C0SDATN; - output EMIOI2C1SCLO; - output EMIOI2C1SCLTN; - output EMIOI2C1SDAO; - output EMIOI2C1SDATN; - output EMIOPJTAGTDO; - output EMIOPJTAGTDTN; - output EMIOSDIO0BUSPOW; - output EMIOSDIO0CLK; - output EMIOSDIO0CMDO; - output EMIOSDIO0CMDTN; - output EMIOSDIO0LED; - output EMIOSDIO1BUSPOW; - output EMIOSDIO1CLK; - output EMIOSDIO1CMDO; - output EMIOSDIO1CMDTN; - output EMIOSDIO1LED; - output EMIOSPI0MO; - output EMIOSPI0MOTN; - output EMIOSPI0SCLKO; - output EMIOSPI0SCLKTN; - output EMIOSPI0SO; - output EMIOSPI0SSNTN; - output EMIOSPI0STN; - output EMIOSPI1MO; - output EMIOSPI1MOTN; - output EMIOSPI1SCLKO; - output EMIOSPI1SCLKTN; - output EMIOSPI1SO; - output EMIOSPI1SSNTN; - output EMIOSPI1STN; - output EMIOTRACECTL; - output EMIOUART0DTRN; - output EMIOUART0RTSN; - output EMIOUART0TX; - output EMIOUART1DTRN; - output EMIOUART1RTSN; - output EMIOUART1TX; - output EMIOUSB0VBUSPWRSELECT; - output EMIOUSB1VBUSPWRSELECT; - output EMIOWDTRSTO; - output EVENTEVENTO; - output MAXIGP0ARESETN; - output MAXIGP0ARVALID; - output MAXIGP0AWVALID; - output MAXIGP0BREADY; - output MAXIGP0RREADY; - output MAXIGP0WLAST; - output MAXIGP0WVALID; - output MAXIGP1ARESETN; - output MAXIGP1ARVALID; - output MAXIGP1AWVALID; - output MAXIGP1BREADY; - output MAXIGP1RREADY; - output MAXIGP1WLAST; - output MAXIGP1WVALID; - output SAXIACPARESETN; - output SAXIACPARREADY; - output SAXIACPAWREADY; - output SAXIACPBVALID; - output SAXIACPRLAST; - output SAXIACPRVALID; - output SAXIACPWREADY; - output SAXIGP0ARESETN; - output SAXIGP0ARREADY; - output SAXIGP0AWREADY; - output SAXIGP0BVALID; - output SAXIGP0RLAST; - output SAXIGP0RVALID; - output SAXIGP0WREADY; - output SAXIGP1ARESETN; - output SAXIGP1ARREADY; - output SAXIGP1AWREADY; - output SAXIGP1BVALID; - output SAXIGP1RLAST; - output SAXIGP1RVALID; - output SAXIGP1WREADY; - output SAXIHP0ARESETN; - output SAXIHP0ARREADY; - output SAXIHP0AWREADY; - output SAXIHP0BVALID; - output SAXIHP0RLAST; - output SAXIHP0RVALID; - output SAXIHP0WREADY; - output SAXIHP1ARESETN; - output SAXIHP1ARREADY; - output SAXIHP1AWREADY; - output SAXIHP1BVALID; - output SAXIHP1RLAST; - output SAXIHP1RVALID; - output SAXIHP1WREADY; - output SAXIHP2ARESETN; - output SAXIHP2ARREADY; - output SAXIHP2AWREADY; - output SAXIHP2BVALID; - output SAXIHP2RLAST; - output SAXIHP2RVALID; - output SAXIHP2WREADY; - output SAXIHP3ARESETN; - output SAXIHP3ARREADY; - output SAXIHP3AWREADY; - output SAXIHP3BVALID; - output SAXIHP3RLAST; - output SAXIHP3RVALID; - output SAXIHP3WREADY; - output [11:0] MAXIGP0ARID; - output [11:0] MAXIGP0AWID; - output [11:0] MAXIGP0WID; - output [11:0] MAXIGP1ARID; - output [11:0] MAXIGP1AWID; - output [11:0] MAXIGP1WID; - output [1:0] DMA0DATYPE; - output [1:0] DMA1DATYPE; - output [1:0] DMA2DATYPE; - output [1:0] DMA3DATYPE; - output [1:0] EMIOUSB0PORTINDCTL; - output [1:0] EMIOUSB1PORTINDCTL; - output [1:0] EVENTSTANDBYWFE; - output [1:0] EVENTSTANDBYWFI; - output [1:0] MAXIGP0ARBURST; - output [1:0] MAXIGP0ARLOCK; - output [1:0] MAXIGP0ARSIZE; - output [1:0] MAXIGP0AWBURST; - output [1:0] MAXIGP0AWLOCK; - output [1:0] MAXIGP0AWSIZE; - output [1:0] MAXIGP1ARBURST; - output [1:0] MAXIGP1ARLOCK; - output [1:0] MAXIGP1ARSIZE; - output [1:0] MAXIGP1AWBURST; - output [1:0] MAXIGP1AWLOCK; - output [1:0] MAXIGP1AWSIZE; - output [1:0] SAXIACPBRESP; - output [1:0] SAXIACPRRESP; - output [1:0] SAXIGP0BRESP; - output [1:0] SAXIGP0RRESP; - output [1:0] SAXIGP1BRESP; - output [1:0] SAXIGP1RRESP; - output [1:0] SAXIHP0BRESP; - output [1:0] SAXIHP0RRESP; - output [1:0] SAXIHP1BRESP; - output [1:0] SAXIHP1RRESP; - output [1:0] SAXIHP2BRESP; - output [1:0] SAXIHP2RRESP; - output [1:0] SAXIHP3BRESP; - output [1:0] SAXIHP3RRESP; - output [28:0] IRQP2F; - output [2:0] EMIOSDIO0BUSVOLT; - output [2:0] EMIOSDIO1BUSVOLT; - output [2:0] EMIOSPI0SSON; - output [2:0] EMIOSPI1SSON; - output [2:0] EMIOTTC0WAVEO; - output [2:0] EMIOTTC1WAVEO; - output [2:0] MAXIGP0ARPROT; - output [2:0] MAXIGP0AWPROT; - output [2:0] MAXIGP1ARPROT; - output [2:0] MAXIGP1AWPROT; - output [2:0] SAXIACPBID; - output [2:0] SAXIACPRID; - output [2:0] SAXIHP0RACOUNT; - output [2:0] SAXIHP1RACOUNT; - output [2:0] SAXIHP2RACOUNT; - output [2:0] SAXIHP3RACOUNT; - output [31:0] EMIOTRACEDATA; - output [31:0] FTMTP2FDEBUG; - output [31:0] MAXIGP0ARADDR; - output [31:0] MAXIGP0AWADDR; - output [31:0] MAXIGP0WDATA; - output [31:0] MAXIGP1ARADDR; - output [31:0] MAXIGP1AWADDR; - output [31:0] MAXIGP1WDATA; - output [31:0] SAXIGP0RDATA; - output [31:0] SAXIGP1RDATA; - output [3:0] EMIOSDIO0DATAO; - output [3:0] EMIOSDIO0DATATN; - output [3:0] EMIOSDIO1DATAO; - output [3:0] EMIOSDIO1DATATN; - output [3:0] FCLKCLK; - output [3:0] FCLKRESETN; - output [3:0] FTMTF2PTRIGACK; - output [3:0] FTMTP2FTRIG; - output [3:0] MAXIGP0ARCACHE; - output [3:0] MAXIGP0ARLEN; - output [3:0] MAXIGP0ARQOS; - output [3:0] MAXIGP0AWCACHE; - output [3:0] MAXIGP0AWLEN; - output [3:0] MAXIGP0AWQOS; - output [3:0] MAXIGP0WSTRB; - output [3:0] MAXIGP1ARCACHE; - output [3:0] MAXIGP1ARLEN; - output [3:0] MAXIGP1ARQOS; - output [3:0] MAXIGP1AWCACHE; - output [3:0] MAXIGP1AWLEN; - output [3:0] MAXIGP1AWQOS; - output [3:0] MAXIGP1WSTRB; - output [5:0] SAXIGP0BID; - output [5:0] SAXIGP0RID; - output [5:0] SAXIGP1BID; - output [5:0] SAXIGP1RID; - output [5:0] SAXIHP0BID; - output [5:0] SAXIHP0RID; - output [5:0] SAXIHP0WACOUNT; - output [5:0] SAXIHP1BID; - output [5:0] SAXIHP1RID; - output [5:0] SAXIHP1WACOUNT; - output [5:0] SAXIHP2BID; - output [5:0] SAXIHP2RID; - output [5:0] SAXIHP2WACOUNT; - output [5:0] SAXIHP3BID; - output [5:0] SAXIHP3RID; - output [5:0] SAXIHP3WACOUNT; - output [63:0] EMIOGPIOO; - output [63:0] EMIOGPIOTN; - output [63:0] SAXIACPRDATA; - output [63:0] SAXIHP0RDATA; - output [63:0] SAXIHP1RDATA; - output [63:0] SAXIHP2RDATA; - output [63:0] SAXIHP3RDATA; - output [7:0] EMIOENET0GMIITXD; - output [7:0] EMIOENET1GMIITXD; - output [7:0] SAXIHP0RCOUNT; - output [7:0] SAXIHP0WCOUNT; - output [7:0] SAXIHP1RCOUNT; - output [7:0] SAXIHP1WCOUNT; - output [7:0] SAXIHP2RCOUNT; - output [7:0] SAXIHP2WCOUNT; - output [7:0] SAXIHP3RCOUNT; - output [7:0] SAXIHP3WCOUNT; - inout DDRCASB; - inout DDRCKE; - inout DDRCKN; - inout DDRCKP; - inout DDRCSB; - inout DDRDRSTB; - inout DDRODT; - inout DDRRASB; - inout DDRVRN; - inout DDRVRP; - inout DDRWEB; - inout PSCLK; - inout PSPORB; - inout PSSRSTB; - inout [14:0] DDRA; - inout [2:0] DDRBA; - inout [31:0] DDRDQ; - inout [3:0] DDRDM; - inout [3:0] DDRDQSN; - inout [3:0] DDRDQSP; - inout [53:0] MIO; - input DMA0ACLK; - input DMA0DAREADY; - input DMA0DRLAST; - input DMA0DRVALID; - input DMA1ACLK; - input DMA1DAREADY; - input DMA1DRLAST; - input DMA1DRVALID; - input DMA2ACLK; - input DMA2DAREADY; - input DMA2DRLAST; - input DMA2DRVALID; - input DMA3ACLK; - input DMA3DAREADY; - input DMA3DRLAST; - input DMA3DRVALID; - input EMIOCAN0PHYRX; - input EMIOCAN1PHYRX; - input EMIOENET0EXTINTIN; - input EMIOENET0GMIICOL; - input EMIOENET0GMIICRS; - input EMIOENET0GMIIRXCLK; - input EMIOENET0GMIIRXDV; - input EMIOENET0GMIIRXER; - input EMIOENET0GMIITXCLK; - input EMIOENET0MDIOI; - input EMIOENET1EXTINTIN; - input EMIOENET1GMIICOL; - input EMIOENET1GMIICRS; - input EMIOENET1GMIIRXCLK; - input EMIOENET1GMIIRXDV; - input EMIOENET1GMIIRXER; - input EMIOENET1GMIITXCLK; - input EMIOENET1MDIOI; - input EMIOI2C0SCLI; - input EMIOI2C0SDAI; - input EMIOI2C1SCLI; - input EMIOI2C1SDAI; - input EMIOPJTAGTCK; - input EMIOPJTAGTDI; - input EMIOPJTAGTMS; - input EMIOSDIO0CDN; - input EMIOSDIO0CLKFB; - input EMIOSDIO0CMDI; - input EMIOSDIO0WP; - input EMIOSDIO1CDN; - input EMIOSDIO1CLKFB; - input EMIOSDIO1CMDI; - input EMIOSDIO1WP; - input EMIOSPI0MI; - input EMIOSPI0SCLKI; - input EMIOSPI0SI; - input EMIOSPI0SSIN; - input EMIOSPI1MI; - input EMIOSPI1SCLKI; - input EMIOSPI1SI; - input EMIOSPI1SSIN; - input EMIOSRAMINTIN; - input EMIOTRACECLK; - input EMIOUART0CTSN; - input EMIOUART0DCDN; - input EMIOUART0DSRN; - input EMIOUART0RIN; - input EMIOUART0RX; - input EMIOUART1CTSN; - input EMIOUART1DCDN; - input EMIOUART1DSRN; - input EMIOUART1RIN; - input EMIOUART1RX; - input EMIOUSB0VBUSPWRFAULT; - input EMIOUSB1VBUSPWRFAULT; - input EMIOWDTCLKI; - input EVENTEVENTI; - input FPGAIDLEN; - input FTMDTRACEINCLOCK; - input FTMDTRACEINVALID; - input MAXIGP0ACLK; - input MAXIGP0ARREADY; - input MAXIGP0AWREADY; - input MAXIGP0BVALID; - input MAXIGP0RLAST; - input MAXIGP0RVALID; - input MAXIGP0WREADY; - input MAXIGP1ACLK; - input MAXIGP1ARREADY; - input MAXIGP1AWREADY; - input MAXIGP1BVALID; - input MAXIGP1RLAST; - input MAXIGP1RVALID; - input MAXIGP1WREADY; - input SAXIACPACLK; - input SAXIACPARVALID; - input SAXIACPAWVALID; - input SAXIACPBREADY; - input SAXIACPRREADY; - input SAXIACPWLAST; - input SAXIACPWVALID; - input SAXIGP0ACLK; - input SAXIGP0ARVALID; - input SAXIGP0AWVALID; - input SAXIGP0BREADY; - input SAXIGP0RREADY; - input SAXIGP0WLAST; - input SAXIGP0WVALID; - input SAXIGP1ACLK; - input SAXIGP1ARVALID; - input SAXIGP1AWVALID; - input SAXIGP1BREADY; - input SAXIGP1RREADY; - input SAXIGP1WLAST; - input SAXIGP1WVALID; - input SAXIHP0ACLK; - input SAXIHP0ARVALID; - input SAXIHP0AWVALID; - input SAXIHP0BREADY; - input SAXIHP0RDISSUECAP1EN; - input SAXIHP0RREADY; - input SAXIHP0WLAST; - input SAXIHP0WRISSUECAP1EN; - input SAXIHP0WVALID; - input SAXIHP1ACLK; - input SAXIHP1ARVALID; - input SAXIHP1AWVALID; - input SAXIHP1BREADY; - input SAXIHP1RDISSUECAP1EN; - input SAXIHP1RREADY; - input SAXIHP1WLAST; - input SAXIHP1WRISSUECAP1EN; - input SAXIHP1WVALID; - input SAXIHP2ACLK; - input SAXIHP2ARVALID; - input SAXIHP2AWVALID; - input SAXIHP2BREADY; - input SAXIHP2RDISSUECAP1EN; - input SAXIHP2RREADY; - input SAXIHP2WLAST; - input SAXIHP2WRISSUECAP1EN; - input SAXIHP2WVALID; - input SAXIHP3ACLK; - input SAXIHP3ARVALID; - input SAXIHP3AWVALID; - input SAXIHP3BREADY; - input SAXIHP3RDISSUECAP1EN; - input SAXIHP3RREADY; - input SAXIHP3WLAST; - input SAXIHP3WRISSUECAP1EN; - input SAXIHP3WVALID; - input [11:0] MAXIGP0BID; - input [11:0] MAXIGP0RID; - input [11:0] MAXIGP1BID; - input [11:0] MAXIGP1RID; - input [19:0] IRQF2P; - input [1:0] DMA0DRTYPE; - input [1:0] DMA1DRTYPE; - input [1:0] DMA2DRTYPE; - input [1:0] DMA3DRTYPE; - input [1:0] MAXIGP0BRESP; - input [1:0] MAXIGP0RRESP; - input [1:0] MAXIGP1BRESP; - input [1:0] MAXIGP1RRESP; - input [1:0] SAXIACPARBURST; - input [1:0] SAXIACPARLOCK; - input [1:0] SAXIACPARSIZE; - input [1:0] SAXIACPAWBURST; - input [1:0] SAXIACPAWLOCK; - input [1:0] SAXIACPAWSIZE; - input [1:0] SAXIGP0ARBURST; - input [1:0] SAXIGP0ARLOCK; - input [1:0] SAXIGP0ARSIZE; - input [1:0] SAXIGP0AWBURST; - input [1:0] SAXIGP0AWLOCK; - input [1:0] SAXIGP0AWSIZE; - input [1:0] SAXIGP1ARBURST; - input [1:0] SAXIGP1ARLOCK; - input [1:0] SAXIGP1ARSIZE; - input [1:0] SAXIGP1AWBURST; - input [1:0] SAXIGP1AWLOCK; - input [1:0] SAXIGP1AWSIZE; - input [1:0] SAXIHP0ARBURST; - input [1:0] SAXIHP0ARLOCK; - input [1:0] SAXIHP0ARSIZE; - input [1:0] SAXIHP0AWBURST; - input [1:0] SAXIHP0AWLOCK; - input [1:0] SAXIHP0AWSIZE; - input [1:0] SAXIHP1ARBURST; - input [1:0] SAXIHP1ARLOCK; - input [1:0] SAXIHP1ARSIZE; - input [1:0] SAXIHP1AWBURST; - input [1:0] SAXIHP1AWLOCK; - input [1:0] SAXIHP1AWSIZE; - input [1:0] SAXIHP2ARBURST; - input [1:0] SAXIHP2ARLOCK; - input [1:0] SAXIHP2ARSIZE; - input [1:0] SAXIHP2AWBURST; - input [1:0] SAXIHP2AWLOCK; - input [1:0] SAXIHP2AWSIZE; - input [1:0] SAXIHP3ARBURST; - input [1:0] SAXIHP3ARLOCK; - input [1:0] SAXIHP3ARSIZE; - input [1:0] SAXIHP3AWBURST; - input [1:0] SAXIHP3AWLOCK; - input [1:0] SAXIHP3AWSIZE; - input [2:0] EMIOTTC0CLKI; - input [2:0] EMIOTTC1CLKI; - input [2:0] SAXIACPARID; - input [2:0] SAXIACPARPROT; - input [2:0] SAXIACPAWID; - input [2:0] SAXIACPAWPROT; - input [2:0] SAXIACPWID; - input [2:0] SAXIGP0ARPROT; - input [2:0] SAXIGP0AWPROT; - input [2:0] SAXIGP1ARPROT; - input [2:0] SAXIGP1AWPROT; - input [2:0] SAXIHP0ARPROT; - input [2:0] SAXIHP0AWPROT; - input [2:0] SAXIHP1ARPROT; - input [2:0] SAXIHP1AWPROT; - input [2:0] SAXIHP2ARPROT; - input [2:0] SAXIHP2AWPROT; - input [2:0] SAXIHP3ARPROT; - input [2:0] SAXIHP3AWPROT; - input [31:0] FTMDTRACEINDATA; - input [31:0] FTMTF2PDEBUG; - input [31:0] MAXIGP0RDATA; - input [31:0] MAXIGP1RDATA; - input [31:0] SAXIACPARADDR; - input [31:0] SAXIACPAWADDR; - input [31:0] SAXIGP0ARADDR; - input [31:0] SAXIGP0AWADDR; - input [31:0] SAXIGP0WDATA; - input [31:0] SAXIGP1ARADDR; - input [31:0] SAXIGP1AWADDR; - input [31:0] SAXIGP1WDATA; - input [31:0] SAXIHP0ARADDR; - input [31:0] SAXIHP0AWADDR; - input [31:0] SAXIHP1ARADDR; - input [31:0] SAXIHP1AWADDR; - input [31:0] SAXIHP2ARADDR; - input [31:0] SAXIHP2AWADDR; - input [31:0] SAXIHP3ARADDR; - input [31:0] SAXIHP3AWADDR; - input [3:0] DDRARB; - input [3:0] EMIOSDIO0DATAI; - input [3:0] EMIOSDIO1DATAI; - input [3:0] FCLKCLKTRIGN; - input [3:0] FTMDTRACEINATID; - input [3:0] FTMTF2PTRIG; - input [3:0] FTMTP2FTRIGACK; - input [3:0] SAXIACPARCACHE; - input [3:0] SAXIACPARLEN; - input [3:0] SAXIACPARQOS; - input [3:0] SAXIACPAWCACHE; - input [3:0] SAXIACPAWLEN; - input [3:0] SAXIACPAWQOS; - input [3:0] SAXIGP0ARCACHE; - input [3:0] SAXIGP0ARLEN; - input [3:0] SAXIGP0ARQOS; - input [3:0] SAXIGP0AWCACHE; - input [3:0] SAXIGP0AWLEN; - input [3:0] SAXIGP0AWQOS; - input [3:0] SAXIGP0WSTRB; - input [3:0] SAXIGP1ARCACHE; - input [3:0] SAXIGP1ARLEN; - input [3:0] SAXIGP1ARQOS; - input [3:0] SAXIGP1AWCACHE; - input [3:0] SAXIGP1AWLEN; - input [3:0] SAXIGP1AWQOS; - input [3:0] SAXIGP1WSTRB; - input [3:0] SAXIHP0ARCACHE; - input [3:0] SAXIHP0ARLEN; - input [3:0] SAXIHP0ARQOS; - input [3:0] SAXIHP0AWCACHE; - input [3:0] SAXIHP0AWLEN; - input [3:0] SAXIHP0AWQOS; - input [3:0] SAXIHP1ARCACHE; - input [3:0] SAXIHP1ARLEN; - input [3:0] SAXIHP1ARQOS; - input [3:0] SAXIHP1AWCACHE; - input [3:0] SAXIHP1AWLEN; - input [3:0] SAXIHP1AWQOS; - input [3:0] SAXIHP2ARCACHE; - input [3:0] SAXIHP2ARLEN; - input [3:0] SAXIHP2ARQOS; - input [3:0] SAXIHP2AWCACHE; - input [3:0] SAXIHP2AWLEN; - input [3:0] SAXIHP2AWQOS; - input [3:0] SAXIHP3ARCACHE; - input [3:0] SAXIHP3ARLEN; - input [3:0] SAXIHP3ARQOS; - input [3:0] SAXIHP3AWCACHE; - input [3:0] SAXIHP3AWLEN; - input [3:0] SAXIHP3AWQOS; - input [4:0] SAXIACPARUSER; - input [4:0] SAXIACPAWUSER; - input [5:0] SAXIGP0ARID; - input [5:0] SAXIGP0AWID; - input [5:0] SAXIGP0WID; - input [5:0] SAXIGP1ARID; - input [5:0] SAXIGP1AWID; - input [5:0] SAXIGP1WID; - input [5:0] SAXIHP0ARID; - input [5:0] SAXIHP0AWID; - input [5:0] SAXIHP0WID; - input [5:0] SAXIHP1ARID; - input [5:0] SAXIHP1AWID; - input [5:0] SAXIHP1WID; - input [5:0] SAXIHP2ARID; - input [5:0] SAXIHP2AWID; - input [5:0] SAXIHP2WID; - input [5:0] SAXIHP3ARID; - input [5:0] SAXIHP3AWID; - input [5:0] SAXIHP3WID; - input [63:0] EMIOGPIOI; - input [63:0] SAXIACPWDATA; - input [63:0] SAXIHP0WDATA; - input [63:0] SAXIHP1WDATA; - input [63:0] SAXIHP2WDATA; - input [63:0] SAXIHP3WDATA; - input [7:0] EMIOENET0GMIIRXD; - input [7:0] EMIOENET1GMIIRXD; - input [7:0] SAXIACPWSTRB; - input [7:0] SAXIHP0WSTRB; - input [7:0] SAXIHP1WSTRB; - input [7:0] SAXIHP2WSTRB; - input [7:0] SAXIHP3WSTRB; -endmodule - diff --git a/techlibs/xilinx/xcu_brams_bb.v b/techlibs/xilinx/xcu_brams_bb.v deleted file mode 100644 index cc70ce371..000000000 --- a/techlibs/xilinx/xcu_brams_bb.v +++ /dev/null @@ -1,405 +0,0 @@ -module RAMB18E2 (...); - parameter CASCADE_ORDER_A = "NONE"; - parameter CASCADE_ORDER_B = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter integer DOA_REG = 1; - parameter integer DOB_REG = 1; - parameter ENADDRENA = "FALSE"; - parameter ENADDRENB = "FALSE"; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [17:0] INIT_A = 18'h00000; - parameter [17:0] INIT_B = 18'h00000; - parameter INIT_FILE = "NONE"; - parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; - parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; - parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; - parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; - parameter RDADDRCHANGEA = "FALSE"; - parameter RDADDRCHANGEB = "FALSE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [17:0] SRVAL_A = 18'h00000; - parameter [17:0] SRVAL_B = 18'h00000; - parameter WRITE_MODE_A = "NO_CHANGE"; - parameter WRITE_MODE_B = "NO_CHANGE"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output [15:0] CASDOUTA; - output [15:0] CASDOUTB; - output [1:0] CASDOUTPA; - output [1:0] CASDOUTPB; - output [15:0] DOUTADOUT; - output [15:0] DOUTBDOUT; - output [1:0] DOUTPADOUTP; - output [1:0] DOUTPBDOUTP; - input [13:0] ADDRARDADDR; - input [13:0] ADDRBWRADDR; - input ADDRENA; - input ADDRENB; - input CASDIMUXA; - input CASDIMUXB; - input [15:0] CASDINA; - input [15:0] CASDINB; - input [1:0] CASDINPA; - input [1:0] CASDINPB; - input CASDOMUXA; - input CASDOMUXB; - input CASDOMUXEN_A; - input CASDOMUXEN_B; - input CASOREGIMUXA; - input CASOREGIMUXB; - input CASOREGIMUXEN_A; - input CASOREGIMUXEN_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK; - input [15:0] DINADIN; - input [15:0] DINBDIN; - input [1:0] DINPADINP; - input [1:0] DINPBDINP; - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN; - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN; - input REGCEAREGCE; - input REGCEB; - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM; - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB; - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG; - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB; - input SLEEP; - input [1:0] WEA; - input [3:0] WEBWE; -endmodule - -module RAMB36E2 (...); - parameter CASCADE_ORDER_A = "NONE"; - parameter CASCADE_ORDER_B = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter integer DOA_REG = 1; - parameter integer DOB_REG = 1; - parameter ENADDRENA = "FALSE"; - parameter ENADDRENB = "FALSE"; - parameter EN_ECC_PIPE = "FALSE"; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter [255:0] INITP_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INITP_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_40 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_41 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_42 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_43 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_44 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_45 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_46 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_47 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_48 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_49 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_4F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_50 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_51 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_52 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_53 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_54 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_55 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_56 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_57 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_58 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_59 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_5F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_60 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_61 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_62 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_63 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_64 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_65 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_66 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_67 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_68 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_69 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_6F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_70 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_71 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_72 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_73 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_74 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_75 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_76 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_77 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_78 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_79 = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7A = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7B = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7C = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7D = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7E = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [255:0] INIT_7F = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [35:0] INIT_A = 36'h000000000; - parameter [35:0] INIT_B = 36'h000000000; - parameter INIT_FILE = "NONE"; - parameter [0:0] IS_CLKARDCLK_INVERTED = 1'b0; - parameter [0:0] IS_CLKBWRCLK_INVERTED = 1'b0; - parameter [0:0] IS_ENARDEN_INVERTED = 1'b0; - parameter [0:0] IS_ENBWREN_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMARSTRAM_INVERTED = 1'b0; - parameter [0:0] IS_RSTRAMB_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGARSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RSTREGB_INVERTED = 1'b0; - parameter RDADDRCHANGEA = "FALSE"; - parameter RDADDRCHANGEB = "FALSE"; - parameter integer READ_WIDTH_A = 0; - parameter integer READ_WIDTH_B = 0; - parameter RSTREG_PRIORITY_A = "RSTREG"; - parameter RSTREG_PRIORITY_B = "RSTREG"; - parameter SIM_COLLISION_CHECK = "ALL"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [35:0] SRVAL_A = 36'h000000000; - parameter [35:0] SRVAL_B = 36'h000000000; - parameter WRITE_MODE_A = "NO_CHANGE"; - parameter WRITE_MODE_B = "NO_CHANGE"; - parameter integer WRITE_WIDTH_A = 0; - parameter integer WRITE_WIDTH_B = 0; - output [31:0] CASDOUTA; - output [31:0] CASDOUTB; - output [3:0] CASDOUTPA; - output [3:0] CASDOUTPB; - output CASOUTDBITERR; - output CASOUTSBITERR; - output DBITERR; - output [31:0] DOUTADOUT; - output [31:0] DOUTBDOUT; - output [3:0] DOUTPADOUTP; - output [3:0] DOUTPBDOUTP; - output [7:0] ECCPARITY; - output [8:0] RDADDRECC; - output SBITERR; - input [14:0] ADDRARDADDR; - input [14:0] ADDRBWRADDR; - input ADDRENA; - input ADDRENB; - input CASDIMUXA; - input CASDIMUXB; - input [31:0] CASDINA; - input [31:0] CASDINB; - input [3:0] CASDINPA; - input [3:0] CASDINPB; - input CASDOMUXA; - input CASDOMUXB; - input CASDOMUXEN_A; - input CASDOMUXEN_B; - input CASINDBITERR; - input CASINSBITERR; - input CASOREGIMUXA; - input CASOREGIMUXB; - input CASOREGIMUXEN_A; - input CASOREGIMUXEN_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKARDCLK_INVERTED" *) - input CLKARDCLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKBWRCLK_INVERTED" *) - input CLKBWRCLK; - input [31:0] DINADIN; - input [31:0] DINBDIN; - input [3:0] DINPADINP; - input [3:0] DINPBDINP; - input ECCPIPECE; - (* invertible_pin = "IS_ENARDEN_INVERTED" *) - input ENARDEN; - (* invertible_pin = "IS_ENBWREN_INVERTED" *) - input ENBWREN; - input INJECTDBITERR; - input INJECTSBITERR; - input REGCEAREGCE; - input REGCEB; - (* invertible_pin = "IS_RSTRAMARSTRAM_INVERTED" *) - input RSTRAMARSTRAM; - (* invertible_pin = "IS_RSTRAMB_INVERTED" *) - input RSTRAMB; - (* invertible_pin = "IS_RSTREGARSTREG_INVERTED" *) - input RSTREGARSTREG; - (* invertible_pin = "IS_RSTREGB_INVERTED" *) - input RSTREGB; - input SLEEP; - input [3:0] WEA; - input [7:0] WEBWE; -endmodule diff --git a/techlibs/xilinx/xcu_cells_xtra.v b/techlibs/xilinx/xcu_cells_xtra.v deleted file mode 100644 index 3c83e0ef1..000000000 --- a/techlibs/xilinx/xcu_cells_xtra.v +++ /dev/null @@ -1,11612 +0,0 @@ -// Created by cells_xtra.py from Xilinx models - -module CMAC (...); - parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; - parameter CTL_RX_CHECK_ACK = "TRUE"; - parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; - parameter CTL_RX_CHECK_SFD = "FALSE"; - parameter CTL_RX_DELETE_FCS = "TRUE"; - parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808; - parameter CTL_RX_FORWARD_CONTROL = "FALSE"; - parameter CTL_RX_IGNORE_FCS = "FALSE"; - parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580; - parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40; - parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001; - parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF; - parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF; - parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000; - parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000; - parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001; - parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001; - parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000; - parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000; - parameter CTL_RX_PROCESS_LFI = "FALSE"; - parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF; - parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00; - parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100; - parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600; - parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00; - parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; - parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; - parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500; - parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; - parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; - parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800; - parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500; - parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; - parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700; - parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; - parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600; - parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; - parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; - parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900; - parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900; - parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400; - parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; - parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001; - parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001; - parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808; - parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808; - parameter CTL_TX_FCS_INS_ENABLE = "TRUE"; - parameter CTL_TX_IGNORE_FCS = "FALSE"; - parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001; - parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001; - parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE"; - parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1; - parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000; - parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000; - parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF; - parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00; - parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100; - parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600; - parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00; - parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; - parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; - parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500; - parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; - parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; - parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800; - parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500; - parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; - parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700; - parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; - parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600; - parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; - parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; - parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900; - parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900; - parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400; - parameter SIM_VERSION = "2.0"; - parameter TEST_MODE_PIN_CHAR = "FALSE"; - output [15:0] DRP_DO; - output DRP_RDY; - output [127:0] RX_DATAOUT0; - output [127:0] RX_DATAOUT1; - output [127:0] RX_DATAOUT2; - output [127:0] RX_DATAOUT3; - output RX_ENAOUT0; - output RX_ENAOUT1; - output RX_ENAOUT2; - output RX_ENAOUT3; - output RX_EOPOUT0; - output RX_EOPOUT1; - output RX_EOPOUT2; - output RX_EOPOUT3; - output RX_ERROUT0; - output RX_ERROUT1; - output RX_ERROUT2; - output RX_ERROUT3; - output [6:0] RX_LANE_ALIGNER_FILL_0; - output [6:0] RX_LANE_ALIGNER_FILL_1; - output [6:0] RX_LANE_ALIGNER_FILL_10; - output [6:0] RX_LANE_ALIGNER_FILL_11; - output [6:0] RX_LANE_ALIGNER_FILL_12; - output [6:0] RX_LANE_ALIGNER_FILL_13; - output [6:0] RX_LANE_ALIGNER_FILL_14; - output [6:0] RX_LANE_ALIGNER_FILL_15; - output [6:0] RX_LANE_ALIGNER_FILL_16; - output [6:0] RX_LANE_ALIGNER_FILL_17; - output [6:0] RX_LANE_ALIGNER_FILL_18; - output [6:0] RX_LANE_ALIGNER_FILL_19; - output [6:0] RX_LANE_ALIGNER_FILL_2; - output [6:0] RX_LANE_ALIGNER_FILL_3; - output [6:0] RX_LANE_ALIGNER_FILL_4; - output [6:0] RX_LANE_ALIGNER_FILL_5; - output [6:0] RX_LANE_ALIGNER_FILL_6; - output [6:0] RX_LANE_ALIGNER_FILL_7; - output [6:0] RX_LANE_ALIGNER_FILL_8; - output [6:0] RX_LANE_ALIGNER_FILL_9; - output [3:0] RX_MTYOUT0; - output [3:0] RX_MTYOUT1; - output [3:0] RX_MTYOUT2; - output [3:0] RX_MTYOUT3; - output [4:0] RX_PTP_PCSLANE_OUT; - output [79:0] RX_PTP_TSTAMP_OUT; - output RX_SOPOUT0; - output RX_SOPOUT1; - output RX_SOPOUT2; - output RX_SOPOUT3; - output STAT_RX_ALIGNED; - output STAT_RX_ALIGNED_ERR; - output [6:0] STAT_RX_BAD_CODE; - output [3:0] STAT_RX_BAD_FCS; - output STAT_RX_BAD_PREAMBLE; - output STAT_RX_BAD_SFD; - output STAT_RX_BIP_ERR_0; - output STAT_RX_BIP_ERR_1; - output STAT_RX_BIP_ERR_10; - output STAT_RX_BIP_ERR_11; - output STAT_RX_BIP_ERR_12; - output STAT_RX_BIP_ERR_13; - output STAT_RX_BIP_ERR_14; - output STAT_RX_BIP_ERR_15; - output STAT_RX_BIP_ERR_16; - output STAT_RX_BIP_ERR_17; - output STAT_RX_BIP_ERR_18; - output STAT_RX_BIP_ERR_19; - output STAT_RX_BIP_ERR_2; - output STAT_RX_BIP_ERR_3; - output STAT_RX_BIP_ERR_4; - output STAT_RX_BIP_ERR_5; - output STAT_RX_BIP_ERR_6; - output STAT_RX_BIP_ERR_7; - output STAT_RX_BIP_ERR_8; - output STAT_RX_BIP_ERR_9; - output [19:0] STAT_RX_BLOCK_LOCK; - output STAT_RX_BROADCAST; - output [3:0] STAT_RX_FRAGMENT; - output [3:0] STAT_RX_FRAMING_ERR_0; - output [3:0] STAT_RX_FRAMING_ERR_1; - output [3:0] STAT_RX_FRAMING_ERR_10; - output [3:0] STAT_RX_FRAMING_ERR_11; - output [3:0] STAT_RX_FRAMING_ERR_12; - output [3:0] STAT_RX_FRAMING_ERR_13; - output [3:0] STAT_RX_FRAMING_ERR_14; - output [3:0] STAT_RX_FRAMING_ERR_15; - output [3:0] STAT_RX_FRAMING_ERR_16; - output [3:0] STAT_RX_FRAMING_ERR_17; - output [3:0] STAT_RX_FRAMING_ERR_18; - output [3:0] STAT_RX_FRAMING_ERR_19; - output [3:0] STAT_RX_FRAMING_ERR_2; - output [3:0] STAT_RX_FRAMING_ERR_3; - output [3:0] STAT_RX_FRAMING_ERR_4; - output [3:0] STAT_RX_FRAMING_ERR_5; - output [3:0] STAT_RX_FRAMING_ERR_6; - output [3:0] STAT_RX_FRAMING_ERR_7; - output [3:0] STAT_RX_FRAMING_ERR_8; - output [3:0] STAT_RX_FRAMING_ERR_9; - output STAT_RX_FRAMING_ERR_VALID_0; - output STAT_RX_FRAMING_ERR_VALID_1; - output STAT_RX_FRAMING_ERR_VALID_10; - output STAT_RX_FRAMING_ERR_VALID_11; - output STAT_RX_FRAMING_ERR_VALID_12; - output STAT_RX_FRAMING_ERR_VALID_13; - output STAT_RX_FRAMING_ERR_VALID_14; - output STAT_RX_FRAMING_ERR_VALID_15; - output STAT_RX_FRAMING_ERR_VALID_16; - output STAT_RX_FRAMING_ERR_VALID_17; - output STAT_RX_FRAMING_ERR_VALID_18; - output STAT_RX_FRAMING_ERR_VALID_19; - output STAT_RX_FRAMING_ERR_VALID_2; - output STAT_RX_FRAMING_ERR_VALID_3; - output STAT_RX_FRAMING_ERR_VALID_4; - output STAT_RX_FRAMING_ERR_VALID_5; - output STAT_RX_FRAMING_ERR_VALID_6; - output STAT_RX_FRAMING_ERR_VALID_7; - output STAT_RX_FRAMING_ERR_VALID_8; - output STAT_RX_FRAMING_ERR_VALID_9; - output STAT_RX_GOT_SIGNAL_OS; - output STAT_RX_HI_BER; - output STAT_RX_INRANGEERR; - output STAT_RX_INTERNAL_LOCAL_FAULT; - output STAT_RX_JABBER; - output [7:0] STAT_RX_LANE0_VLM_BIP7; - output STAT_RX_LANE0_VLM_BIP7_VALID; - output STAT_RX_LOCAL_FAULT; - output [19:0] STAT_RX_MF_ERR; - output [19:0] STAT_RX_MF_LEN_ERR; - output [19:0] STAT_RX_MF_REPEAT_ERR; - output STAT_RX_MISALIGNED; - output STAT_RX_MULTICAST; - output STAT_RX_OVERSIZE; - output STAT_RX_PACKET_1024_1518_BYTES; - output STAT_RX_PACKET_128_255_BYTES; - output STAT_RX_PACKET_1519_1522_BYTES; - output STAT_RX_PACKET_1523_1548_BYTES; - output STAT_RX_PACKET_1549_2047_BYTES; - output STAT_RX_PACKET_2048_4095_BYTES; - output STAT_RX_PACKET_256_511_BYTES; - output STAT_RX_PACKET_4096_8191_BYTES; - output STAT_RX_PACKET_512_1023_BYTES; - output STAT_RX_PACKET_64_BYTES; - output STAT_RX_PACKET_65_127_BYTES; - output STAT_RX_PACKET_8192_9215_BYTES; - output STAT_RX_PACKET_BAD_FCS; - output STAT_RX_PACKET_LARGE; - output [3:0] STAT_RX_PACKET_SMALL; - output STAT_RX_PAUSE; - output [15:0] STAT_RX_PAUSE_QUANTA0; - output [15:0] STAT_RX_PAUSE_QUANTA1; - output [15:0] STAT_RX_PAUSE_QUANTA2; - output [15:0] STAT_RX_PAUSE_QUANTA3; - output [15:0] STAT_RX_PAUSE_QUANTA4; - output [15:0] STAT_RX_PAUSE_QUANTA5; - output [15:0] STAT_RX_PAUSE_QUANTA6; - output [15:0] STAT_RX_PAUSE_QUANTA7; - output [15:0] STAT_RX_PAUSE_QUANTA8; - output [8:0] STAT_RX_PAUSE_REQ; - output [8:0] STAT_RX_PAUSE_VALID; - output STAT_RX_RECEIVED_LOCAL_FAULT; - output STAT_RX_REMOTE_FAULT; - output STAT_RX_STATUS; - output [3:0] STAT_RX_STOMPED_FCS; - output [19:0] STAT_RX_SYNCED; - output [19:0] STAT_RX_SYNCED_ERR; - output [2:0] STAT_RX_TEST_PATTERN_MISMATCH; - output STAT_RX_TOOLONG; - output [7:0] STAT_RX_TOTAL_BYTES; - output [13:0] STAT_RX_TOTAL_GOOD_BYTES; - output STAT_RX_TOTAL_GOOD_PACKETS; - output [3:0] STAT_RX_TOTAL_PACKETS; - output STAT_RX_TRUNCATED; - output [3:0] STAT_RX_UNDERSIZE; - output STAT_RX_UNICAST; - output STAT_RX_USER_PAUSE; - output STAT_RX_VLAN; - output [19:0] STAT_RX_VL_DEMUXED; - output [4:0] STAT_RX_VL_NUMBER_0; - output [4:0] STAT_RX_VL_NUMBER_1; - output [4:0] STAT_RX_VL_NUMBER_10; - output [4:0] STAT_RX_VL_NUMBER_11; - output [4:0] STAT_RX_VL_NUMBER_12; - output [4:0] STAT_RX_VL_NUMBER_13; - output [4:0] STAT_RX_VL_NUMBER_14; - output [4:0] STAT_RX_VL_NUMBER_15; - output [4:0] STAT_RX_VL_NUMBER_16; - output [4:0] STAT_RX_VL_NUMBER_17; - output [4:0] STAT_RX_VL_NUMBER_18; - output [4:0] STAT_RX_VL_NUMBER_19; - output [4:0] STAT_RX_VL_NUMBER_2; - output [4:0] STAT_RX_VL_NUMBER_3; - output [4:0] STAT_RX_VL_NUMBER_4; - output [4:0] STAT_RX_VL_NUMBER_5; - output [4:0] STAT_RX_VL_NUMBER_6; - output [4:0] STAT_RX_VL_NUMBER_7; - output [4:0] STAT_RX_VL_NUMBER_8; - output [4:0] STAT_RX_VL_NUMBER_9; - output STAT_TX_BAD_FCS; - output STAT_TX_BROADCAST; - output STAT_TX_FRAME_ERROR; - output STAT_TX_LOCAL_FAULT; - output STAT_TX_MULTICAST; - output STAT_TX_PACKET_1024_1518_BYTES; - output STAT_TX_PACKET_128_255_BYTES; - output STAT_TX_PACKET_1519_1522_BYTES; - output STAT_TX_PACKET_1523_1548_BYTES; - output STAT_TX_PACKET_1549_2047_BYTES; - output STAT_TX_PACKET_2048_4095_BYTES; - output STAT_TX_PACKET_256_511_BYTES; - output STAT_TX_PACKET_4096_8191_BYTES; - output STAT_TX_PACKET_512_1023_BYTES; - output STAT_TX_PACKET_64_BYTES; - output STAT_TX_PACKET_65_127_BYTES; - output STAT_TX_PACKET_8192_9215_BYTES; - output STAT_TX_PACKET_LARGE; - output STAT_TX_PACKET_SMALL; - output STAT_TX_PAUSE; - output [8:0] STAT_TX_PAUSE_VALID; - output STAT_TX_PTP_FIFO_READ_ERROR; - output STAT_TX_PTP_FIFO_WRITE_ERROR; - output [6:0] STAT_TX_TOTAL_BYTES; - output [13:0] STAT_TX_TOTAL_GOOD_BYTES; - output STAT_TX_TOTAL_GOOD_PACKETS; - output STAT_TX_TOTAL_PACKETS; - output STAT_TX_UNICAST; - output STAT_TX_USER_PAUSE; - output STAT_TX_VLAN; - output TX_OVFOUT; - output [4:0] TX_PTP_PCSLANE_OUT; - output [79:0] TX_PTP_TSTAMP_OUT; - output [15:0] TX_PTP_TSTAMP_TAG_OUT; - output TX_PTP_TSTAMP_VALID_OUT; - output TX_RDYOUT; - output [15:0] TX_SERDES_ALT_DATA0; - output [15:0] TX_SERDES_ALT_DATA1; - output [15:0] TX_SERDES_ALT_DATA2; - output [15:0] TX_SERDES_ALT_DATA3; - output [63:0] TX_SERDES_DATA0; - output [63:0] TX_SERDES_DATA1; - output [63:0] TX_SERDES_DATA2; - output [63:0] TX_SERDES_DATA3; - output [31:0] TX_SERDES_DATA4; - output [31:0] TX_SERDES_DATA5; - output [31:0] TX_SERDES_DATA6; - output [31:0] TX_SERDES_DATA7; - output [31:0] TX_SERDES_DATA8; - output [31:0] TX_SERDES_DATA9; - output TX_UNFOUT; - input CTL_CAUI4_MODE; - input CTL_RX_CHECK_ETYPE_GCP; - input CTL_RX_CHECK_ETYPE_GPP; - input CTL_RX_CHECK_ETYPE_PCP; - input CTL_RX_CHECK_ETYPE_PPP; - input CTL_RX_CHECK_MCAST_GCP; - input CTL_RX_CHECK_MCAST_GPP; - input CTL_RX_CHECK_MCAST_PCP; - input CTL_RX_CHECK_MCAST_PPP; - input CTL_RX_CHECK_OPCODE_GCP; - input CTL_RX_CHECK_OPCODE_GPP; - input CTL_RX_CHECK_OPCODE_PCP; - input CTL_RX_CHECK_OPCODE_PPP; - input CTL_RX_CHECK_SA_GCP; - input CTL_RX_CHECK_SA_GPP; - input CTL_RX_CHECK_SA_PCP; - input CTL_RX_CHECK_SA_PPP; - input CTL_RX_CHECK_UCAST_GCP; - input CTL_RX_CHECK_UCAST_GPP; - input CTL_RX_CHECK_UCAST_PCP; - input CTL_RX_CHECK_UCAST_PPP; - input CTL_RX_ENABLE; - input CTL_RX_ENABLE_GCP; - input CTL_RX_ENABLE_GPP; - input CTL_RX_ENABLE_PCP; - input CTL_RX_ENABLE_PPP; - input CTL_RX_FORCE_RESYNC; - input [8:0] CTL_RX_PAUSE_ACK; - input [8:0] CTL_RX_PAUSE_ENABLE; - input [79:0] CTL_RX_SYSTEMTIMERIN; - input CTL_RX_TEST_PATTERN; - input CTL_TX_ENABLE; - input CTL_TX_LANE0_VLM_BIP7_OVERRIDE; - input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; - input [8:0] CTL_TX_PAUSE_ENABLE; - input [15:0] CTL_TX_PAUSE_QUANTA0; - input [15:0] CTL_TX_PAUSE_QUANTA1; - input [15:0] CTL_TX_PAUSE_QUANTA2; - input [15:0] CTL_TX_PAUSE_QUANTA3; - input [15:0] CTL_TX_PAUSE_QUANTA4; - input [15:0] CTL_TX_PAUSE_QUANTA5; - input [15:0] CTL_TX_PAUSE_QUANTA6; - input [15:0] CTL_TX_PAUSE_QUANTA7; - input [15:0] CTL_TX_PAUSE_QUANTA8; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8; - input [8:0] CTL_TX_PAUSE_REQ; - input CTL_TX_PTP_VLANE_ADJUST_MODE; - input CTL_TX_RESEND_PAUSE; - input CTL_TX_SEND_IDLE; - input CTL_TX_SEND_RFI; - input [79:0] CTL_TX_SYSTEMTIMERIN; - input CTL_TX_TEST_PATTERN; - input [9:0] DRP_ADDR; - input DRP_CLK; - input [15:0] DRP_DI; - input DRP_EN; - input DRP_WE; - input RX_CLK; - input RX_RESET; - input [15:0] RX_SERDES_ALT_DATA0; - input [15:0] RX_SERDES_ALT_DATA1; - input [15:0] RX_SERDES_ALT_DATA2; - input [15:0] RX_SERDES_ALT_DATA3; - input [9:0] RX_SERDES_CLK; - input [63:0] RX_SERDES_DATA0; - input [63:0] RX_SERDES_DATA1; - input [63:0] RX_SERDES_DATA2; - input [63:0] RX_SERDES_DATA3; - input [31:0] RX_SERDES_DATA4; - input [31:0] RX_SERDES_DATA5; - input [31:0] RX_SERDES_DATA6; - input [31:0] RX_SERDES_DATA7; - input [31:0] RX_SERDES_DATA8; - input [31:0] RX_SERDES_DATA9; - input [9:0] RX_SERDES_RESET; - input TX_CLK; - input [127:0] TX_DATAIN0; - input [127:0] TX_DATAIN1; - input [127:0] TX_DATAIN2; - input [127:0] TX_DATAIN3; - input TX_ENAIN0; - input TX_ENAIN1; - input TX_ENAIN2; - input TX_ENAIN3; - input TX_EOPIN0; - input TX_EOPIN1; - input TX_EOPIN2; - input TX_EOPIN3; - input TX_ERRIN0; - input TX_ERRIN1; - input TX_ERRIN2; - input TX_ERRIN3; - input [3:0] TX_MTYIN0; - input [3:0] TX_MTYIN1; - input [3:0] TX_MTYIN2; - input [3:0] TX_MTYIN3; - input [1:0] TX_PTP_1588OP_IN; - input [15:0] TX_PTP_CHKSUM_OFFSET_IN; - input [63:0] TX_PTP_RXTSTAMP_IN; - input [15:0] TX_PTP_TAG_FIELD_IN; - input [15:0] TX_PTP_TSTAMP_OFFSET_IN; - input TX_PTP_UPD_CHKSUM_IN; - input TX_RESET; - input TX_SOPIN0; - input TX_SOPIN1; - input TX_SOPIN2; - input TX_SOPIN3; -endmodule - -module CMACE4 (...); - parameter CTL_PTP_TRANSPCLK_MODE = "FALSE"; - parameter CTL_RX_CHECK_ACK = "TRUE"; - parameter CTL_RX_CHECK_PREAMBLE = "FALSE"; - parameter CTL_RX_CHECK_SFD = "FALSE"; - parameter CTL_RX_DELETE_FCS = "TRUE"; - parameter [15:0] CTL_RX_ETYPE_GCP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_GPP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_PCP = 16'h8808; - parameter [15:0] CTL_RX_ETYPE_PPP = 16'h8808; - parameter CTL_RX_FORWARD_CONTROL = "FALSE"; - parameter CTL_RX_IGNORE_FCS = "FALSE"; - parameter [14:0] CTL_RX_MAX_PACKET_LEN = 15'h2580; - parameter [7:0] CTL_RX_MIN_PACKET_LEN = 8'h40; - parameter [15:0] CTL_RX_OPCODE_GPP = 16'h0001; - parameter [15:0] CTL_RX_OPCODE_MAX_GCP = 16'hFFFF; - parameter [15:0] CTL_RX_OPCODE_MAX_PCP = 16'hFFFF; - parameter [15:0] CTL_RX_OPCODE_MIN_GCP = 16'h0000; - parameter [15:0] CTL_RX_OPCODE_MIN_PCP = 16'h0000; - parameter [15:0] CTL_RX_OPCODE_PPP = 16'h0001; - parameter [47:0] CTL_RX_PAUSE_DA_MCAST = 48'h0180C2000001; - parameter [47:0] CTL_RX_PAUSE_DA_UCAST = 48'h000000000000; - parameter [47:0] CTL_RX_PAUSE_SA = 48'h000000000000; - parameter CTL_RX_PROCESS_LFI = "FALSE"; - parameter [8:0] CTL_RX_RSFEC_AM_THRESHOLD = 9'h046; - parameter [1:0] CTL_RX_RSFEC_FILL_ADJUST = 2'h0; - parameter [15:0] CTL_RX_VL_LENGTH_MINUS1 = 16'h3FFF; - parameter [63:0] CTL_RX_VL_MARKER_ID0 = 64'hC16821003E97DE00; - parameter [63:0] CTL_RX_VL_MARKER_ID1 = 64'h9D718E00628E7100; - parameter [63:0] CTL_RX_VL_MARKER_ID10 = 64'hFD6C990002936600; - parameter [63:0] CTL_RX_VL_MARKER_ID11 = 64'hB9915500466EAA00; - parameter [63:0] CTL_RX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; - parameter [63:0] CTL_RX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; - parameter [63:0] CTL_RX_VL_MARKER_ID14 = 64'h83C7CA007C383500; - parameter [63:0] CTL_RX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; - parameter [63:0] CTL_RX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; - parameter [63:0] CTL_RX_VL_MARKER_ID17 = 64'hADD6B70052294800; - parameter [63:0] CTL_RX_VL_MARKER_ID18 = 64'h5F662A00A099D500; - parameter [63:0] CTL_RX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; - parameter [63:0] CTL_RX_VL_MARKER_ID2 = 64'h594BE800A6B41700; - parameter [63:0] CTL_RX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; - parameter [63:0] CTL_RX_VL_MARKER_ID4 = 64'hF50709000AF8F600; - parameter [63:0] CTL_RX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; - parameter [63:0] CTL_RX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; - parameter [63:0] CTL_RX_VL_MARKER_ID7 = 64'h7B45660084BA9900; - parameter [63:0] CTL_RX_VL_MARKER_ID8 = 64'hA02476005FDB8900; - parameter [63:0] CTL_RX_VL_MARKER_ID9 = 64'h68C9FB0097360400; - parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; - parameter CTL_TX_CUSTOM_PREAMBLE_ENABLE = "FALSE"; - parameter [47:0] CTL_TX_DA_GPP = 48'h0180C2000001; - parameter [47:0] CTL_TX_DA_PPP = 48'h0180C2000001; - parameter [15:0] CTL_TX_ETHERTYPE_GPP = 16'h8808; - parameter [15:0] CTL_TX_ETHERTYPE_PPP = 16'h8808; - parameter CTL_TX_FCS_INS_ENABLE = "TRUE"; - parameter CTL_TX_IGNORE_FCS = "FALSE"; - parameter [3:0] CTL_TX_IPG_VALUE = 4'hC; - parameter [15:0] CTL_TX_OPCODE_GPP = 16'h0001; - parameter [15:0] CTL_TX_OPCODE_PPP = 16'h0001; - parameter CTL_TX_PTP_1STEP_ENABLE = "FALSE"; - parameter [10:0] CTL_TX_PTP_LATENCY_ADJUST = 11'h2C1; - parameter [47:0] CTL_TX_SA_GPP = 48'h000000000000; - parameter [47:0] CTL_TX_SA_PPP = 48'h000000000000; - parameter [15:0] CTL_TX_VL_LENGTH_MINUS1 = 16'h3FFF; - parameter [63:0] CTL_TX_VL_MARKER_ID0 = 64'hC16821003E97DE00; - parameter [63:0] CTL_TX_VL_MARKER_ID1 = 64'h9D718E00628E7100; - parameter [63:0] CTL_TX_VL_MARKER_ID10 = 64'hFD6C990002936600; - parameter [63:0] CTL_TX_VL_MARKER_ID11 = 64'hB9915500466EAA00; - parameter [63:0] CTL_TX_VL_MARKER_ID12 = 64'h5CB9B200A3464D00; - parameter [63:0] CTL_TX_VL_MARKER_ID13 = 64'h1AF8BD00E5074200; - parameter [63:0] CTL_TX_VL_MARKER_ID14 = 64'h83C7CA007C383500; - parameter [63:0] CTL_TX_VL_MARKER_ID15 = 64'h3536CD00CAC93200; - parameter [63:0] CTL_TX_VL_MARKER_ID16 = 64'hC4314C003BCEB300; - parameter [63:0] CTL_TX_VL_MARKER_ID17 = 64'hADD6B70052294800; - parameter [63:0] CTL_TX_VL_MARKER_ID18 = 64'h5F662A00A099D500; - parameter [63:0] CTL_TX_VL_MARKER_ID19 = 64'hC0F0E5003F0F1A00; - parameter [63:0] CTL_TX_VL_MARKER_ID2 = 64'h594BE800A6B41700; - parameter [63:0] CTL_TX_VL_MARKER_ID3 = 64'h4D957B00B26A8400; - parameter [63:0] CTL_TX_VL_MARKER_ID4 = 64'hF50709000AF8F600; - parameter [63:0] CTL_TX_VL_MARKER_ID5 = 64'hDD14C20022EB3D00; - parameter [63:0] CTL_TX_VL_MARKER_ID6 = 64'h9A4A260065B5D900; - parameter [63:0] CTL_TX_VL_MARKER_ID7 = 64'h7B45660084BA9900; - parameter [63:0] CTL_TX_VL_MARKER_ID8 = 64'hA02476005FDB8900; - parameter [63:0] CTL_TX_VL_MARKER_ID9 = 64'h68C9FB0097360400; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter TEST_MODE_PIN_CHAR = "FALSE"; - output [15:0] DRP_DO; - output DRP_RDY; - output [329:0] RSFEC_BYPASS_RX_DOUT; - output RSFEC_BYPASS_RX_DOUT_CW_START; - output RSFEC_BYPASS_RX_DOUT_VALID; - output [329:0] RSFEC_BYPASS_TX_DOUT; - output RSFEC_BYPASS_TX_DOUT_CW_START; - output RSFEC_BYPASS_TX_DOUT_VALID; - output [127:0] RX_DATAOUT0; - output [127:0] RX_DATAOUT1; - output [127:0] RX_DATAOUT2; - output [127:0] RX_DATAOUT3; - output RX_ENAOUT0; - output RX_ENAOUT1; - output RX_ENAOUT2; - output RX_ENAOUT3; - output RX_EOPOUT0; - output RX_EOPOUT1; - output RX_EOPOUT2; - output RX_EOPOUT3; - output RX_ERROUT0; - output RX_ERROUT1; - output RX_ERROUT2; - output RX_ERROUT3; - output [6:0] RX_LANE_ALIGNER_FILL_0; - output [6:0] RX_LANE_ALIGNER_FILL_1; - output [6:0] RX_LANE_ALIGNER_FILL_10; - output [6:0] RX_LANE_ALIGNER_FILL_11; - output [6:0] RX_LANE_ALIGNER_FILL_12; - output [6:0] RX_LANE_ALIGNER_FILL_13; - output [6:0] RX_LANE_ALIGNER_FILL_14; - output [6:0] RX_LANE_ALIGNER_FILL_15; - output [6:0] RX_LANE_ALIGNER_FILL_16; - output [6:0] RX_LANE_ALIGNER_FILL_17; - output [6:0] RX_LANE_ALIGNER_FILL_18; - output [6:0] RX_LANE_ALIGNER_FILL_19; - output [6:0] RX_LANE_ALIGNER_FILL_2; - output [6:0] RX_LANE_ALIGNER_FILL_3; - output [6:0] RX_LANE_ALIGNER_FILL_4; - output [6:0] RX_LANE_ALIGNER_FILL_5; - output [6:0] RX_LANE_ALIGNER_FILL_6; - output [6:0] RX_LANE_ALIGNER_FILL_7; - output [6:0] RX_LANE_ALIGNER_FILL_8; - output [6:0] RX_LANE_ALIGNER_FILL_9; - output [3:0] RX_MTYOUT0; - output [3:0] RX_MTYOUT1; - output [3:0] RX_MTYOUT2; - output [3:0] RX_MTYOUT3; - output [7:0] RX_OTN_BIP8_0; - output [7:0] RX_OTN_BIP8_1; - output [7:0] RX_OTN_BIP8_2; - output [7:0] RX_OTN_BIP8_3; - output [7:0] RX_OTN_BIP8_4; - output [65:0] RX_OTN_DATA_0; - output [65:0] RX_OTN_DATA_1; - output [65:0] RX_OTN_DATA_2; - output [65:0] RX_OTN_DATA_3; - output [65:0] RX_OTN_DATA_4; - output RX_OTN_ENA; - output RX_OTN_LANE0; - output RX_OTN_VLMARKER; - output [55:0] RX_PREOUT; - output [4:0] RX_PTP_PCSLANE_OUT; - output [79:0] RX_PTP_TSTAMP_OUT; - output RX_SOPOUT0; - output RX_SOPOUT1; - output RX_SOPOUT2; - output RX_SOPOUT3; - output STAT_RX_ALIGNED; - output STAT_RX_ALIGNED_ERR; - output [2:0] STAT_RX_BAD_CODE; - output [2:0] STAT_RX_BAD_FCS; - output STAT_RX_BAD_PREAMBLE; - output STAT_RX_BAD_SFD; - output STAT_RX_BIP_ERR_0; - output STAT_RX_BIP_ERR_1; - output STAT_RX_BIP_ERR_10; - output STAT_RX_BIP_ERR_11; - output STAT_RX_BIP_ERR_12; - output STAT_RX_BIP_ERR_13; - output STAT_RX_BIP_ERR_14; - output STAT_RX_BIP_ERR_15; - output STAT_RX_BIP_ERR_16; - output STAT_RX_BIP_ERR_17; - output STAT_RX_BIP_ERR_18; - output STAT_RX_BIP_ERR_19; - output STAT_RX_BIP_ERR_2; - output STAT_RX_BIP_ERR_3; - output STAT_RX_BIP_ERR_4; - output STAT_RX_BIP_ERR_5; - output STAT_RX_BIP_ERR_6; - output STAT_RX_BIP_ERR_7; - output STAT_RX_BIP_ERR_8; - output STAT_RX_BIP_ERR_9; - output [19:0] STAT_RX_BLOCK_LOCK; - output STAT_RX_BROADCAST; - output [2:0] STAT_RX_FRAGMENT; - output [1:0] STAT_RX_FRAMING_ERR_0; - output [1:0] STAT_RX_FRAMING_ERR_1; - output [1:0] STAT_RX_FRAMING_ERR_10; - output [1:0] STAT_RX_FRAMING_ERR_11; - output [1:0] STAT_RX_FRAMING_ERR_12; - output [1:0] STAT_RX_FRAMING_ERR_13; - output [1:0] STAT_RX_FRAMING_ERR_14; - output [1:0] STAT_RX_FRAMING_ERR_15; - output [1:0] STAT_RX_FRAMING_ERR_16; - output [1:0] STAT_RX_FRAMING_ERR_17; - output [1:0] STAT_RX_FRAMING_ERR_18; - output [1:0] STAT_RX_FRAMING_ERR_19; - output [1:0] STAT_RX_FRAMING_ERR_2; - output [1:0] STAT_RX_FRAMING_ERR_3; - output [1:0] STAT_RX_FRAMING_ERR_4; - output [1:0] STAT_RX_FRAMING_ERR_5; - output [1:0] STAT_RX_FRAMING_ERR_6; - output [1:0] STAT_RX_FRAMING_ERR_7; - output [1:0] STAT_RX_FRAMING_ERR_8; - output [1:0] STAT_RX_FRAMING_ERR_9; - output STAT_RX_FRAMING_ERR_VALID_0; - output STAT_RX_FRAMING_ERR_VALID_1; - output STAT_RX_FRAMING_ERR_VALID_10; - output STAT_RX_FRAMING_ERR_VALID_11; - output STAT_RX_FRAMING_ERR_VALID_12; - output STAT_RX_FRAMING_ERR_VALID_13; - output STAT_RX_FRAMING_ERR_VALID_14; - output STAT_RX_FRAMING_ERR_VALID_15; - output STAT_RX_FRAMING_ERR_VALID_16; - output STAT_RX_FRAMING_ERR_VALID_17; - output STAT_RX_FRAMING_ERR_VALID_18; - output STAT_RX_FRAMING_ERR_VALID_19; - output STAT_RX_FRAMING_ERR_VALID_2; - output STAT_RX_FRAMING_ERR_VALID_3; - output STAT_RX_FRAMING_ERR_VALID_4; - output STAT_RX_FRAMING_ERR_VALID_5; - output STAT_RX_FRAMING_ERR_VALID_6; - output STAT_RX_FRAMING_ERR_VALID_7; - output STAT_RX_FRAMING_ERR_VALID_8; - output STAT_RX_FRAMING_ERR_VALID_9; - output STAT_RX_GOT_SIGNAL_OS; - output STAT_RX_HI_BER; - output STAT_RX_INRANGEERR; - output STAT_RX_INTERNAL_LOCAL_FAULT; - output STAT_RX_JABBER; - output [7:0] STAT_RX_LANE0_VLM_BIP7; - output STAT_RX_LANE0_VLM_BIP7_VALID; - output STAT_RX_LOCAL_FAULT; - output [19:0] STAT_RX_MF_ERR; - output [19:0] STAT_RX_MF_LEN_ERR; - output [19:0] STAT_RX_MF_REPEAT_ERR; - output STAT_RX_MISALIGNED; - output STAT_RX_MULTICAST; - output STAT_RX_OVERSIZE; - output STAT_RX_PACKET_1024_1518_BYTES; - output STAT_RX_PACKET_128_255_BYTES; - output STAT_RX_PACKET_1519_1522_BYTES; - output STAT_RX_PACKET_1523_1548_BYTES; - output STAT_RX_PACKET_1549_2047_BYTES; - output STAT_RX_PACKET_2048_4095_BYTES; - output STAT_RX_PACKET_256_511_BYTES; - output STAT_RX_PACKET_4096_8191_BYTES; - output STAT_RX_PACKET_512_1023_BYTES; - output STAT_RX_PACKET_64_BYTES; - output STAT_RX_PACKET_65_127_BYTES; - output STAT_RX_PACKET_8192_9215_BYTES; - output STAT_RX_PACKET_BAD_FCS; - output STAT_RX_PACKET_LARGE; - output [2:0] STAT_RX_PACKET_SMALL; - output STAT_RX_PAUSE; - output [15:0] STAT_RX_PAUSE_QUANTA0; - output [15:0] STAT_RX_PAUSE_QUANTA1; - output [15:0] STAT_RX_PAUSE_QUANTA2; - output [15:0] STAT_RX_PAUSE_QUANTA3; - output [15:0] STAT_RX_PAUSE_QUANTA4; - output [15:0] STAT_RX_PAUSE_QUANTA5; - output [15:0] STAT_RX_PAUSE_QUANTA6; - output [15:0] STAT_RX_PAUSE_QUANTA7; - output [15:0] STAT_RX_PAUSE_QUANTA8; - output [8:0] STAT_RX_PAUSE_REQ; - output [8:0] STAT_RX_PAUSE_VALID; - output STAT_RX_RECEIVED_LOCAL_FAULT; - output STAT_RX_REMOTE_FAULT; - output STAT_RX_RSFEC_AM_LOCK0; - output STAT_RX_RSFEC_AM_LOCK1; - output STAT_RX_RSFEC_AM_LOCK2; - output STAT_RX_RSFEC_AM_LOCK3; - output STAT_RX_RSFEC_CORRECTED_CW_INC; - output STAT_RX_RSFEC_CW_INC; - output [2:0] STAT_RX_RSFEC_ERR_COUNT0_INC; - output [2:0] STAT_RX_RSFEC_ERR_COUNT1_INC; - output [2:0] STAT_RX_RSFEC_ERR_COUNT2_INC; - output [2:0] STAT_RX_RSFEC_ERR_COUNT3_INC; - output STAT_RX_RSFEC_HI_SER; - output STAT_RX_RSFEC_LANE_ALIGNMENT_STATUS; - output [13:0] STAT_RX_RSFEC_LANE_FILL_0; - output [13:0] STAT_RX_RSFEC_LANE_FILL_1; - output [13:0] STAT_RX_RSFEC_LANE_FILL_2; - output [13:0] STAT_RX_RSFEC_LANE_FILL_3; - output [7:0] STAT_RX_RSFEC_LANE_MAPPING; - output [31:0] STAT_RX_RSFEC_RSVD; - output STAT_RX_RSFEC_UNCORRECTED_CW_INC; - output STAT_RX_STATUS; - output [2:0] STAT_RX_STOMPED_FCS; - output [19:0] STAT_RX_SYNCED; - output [19:0] STAT_RX_SYNCED_ERR; - output [2:0] STAT_RX_TEST_PATTERN_MISMATCH; - output STAT_RX_TOOLONG; - output [6:0] STAT_RX_TOTAL_BYTES; - output [13:0] STAT_RX_TOTAL_GOOD_BYTES; - output STAT_RX_TOTAL_GOOD_PACKETS; - output [2:0] STAT_RX_TOTAL_PACKETS; - output STAT_RX_TRUNCATED; - output [2:0] STAT_RX_UNDERSIZE; - output STAT_RX_UNICAST; - output STAT_RX_USER_PAUSE; - output STAT_RX_VLAN; - output [19:0] STAT_RX_VL_DEMUXED; - output [4:0] STAT_RX_VL_NUMBER_0; - output [4:0] STAT_RX_VL_NUMBER_1; - output [4:0] STAT_RX_VL_NUMBER_10; - output [4:0] STAT_RX_VL_NUMBER_11; - output [4:0] STAT_RX_VL_NUMBER_12; - output [4:0] STAT_RX_VL_NUMBER_13; - output [4:0] STAT_RX_VL_NUMBER_14; - output [4:0] STAT_RX_VL_NUMBER_15; - output [4:0] STAT_RX_VL_NUMBER_16; - output [4:0] STAT_RX_VL_NUMBER_17; - output [4:0] STAT_RX_VL_NUMBER_18; - output [4:0] STAT_RX_VL_NUMBER_19; - output [4:0] STAT_RX_VL_NUMBER_2; - output [4:0] STAT_RX_VL_NUMBER_3; - output [4:0] STAT_RX_VL_NUMBER_4; - output [4:0] STAT_RX_VL_NUMBER_5; - output [4:0] STAT_RX_VL_NUMBER_6; - output [4:0] STAT_RX_VL_NUMBER_7; - output [4:0] STAT_RX_VL_NUMBER_8; - output [4:0] STAT_RX_VL_NUMBER_9; - output STAT_TX_BAD_FCS; - output STAT_TX_BROADCAST; - output STAT_TX_FRAME_ERROR; - output STAT_TX_LOCAL_FAULT; - output STAT_TX_MULTICAST; - output STAT_TX_PACKET_1024_1518_BYTES; - output STAT_TX_PACKET_128_255_BYTES; - output STAT_TX_PACKET_1519_1522_BYTES; - output STAT_TX_PACKET_1523_1548_BYTES; - output STAT_TX_PACKET_1549_2047_BYTES; - output STAT_TX_PACKET_2048_4095_BYTES; - output STAT_TX_PACKET_256_511_BYTES; - output STAT_TX_PACKET_4096_8191_BYTES; - output STAT_TX_PACKET_512_1023_BYTES; - output STAT_TX_PACKET_64_BYTES; - output STAT_TX_PACKET_65_127_BYTES; - output STAT_TX_PACKET_8192_9215_BYTES; - output STAT_TX_PACKET_LARGE; - output STAT_TX_PACKET_SMALL; - output STAT_TX_PAUSE; - output [8:0] STAT_TX_PAUSE_VALID; - output STAT_TX_PTP_FIFO_READ_ERROR; - output STAT_TX_PTP_FIFO_WRITE_ERROR; - output [5:0] STAT_TX_TOTAL_BYTES; - output [13:0] STAT_TX_TOTAL_GOOD_BYTES; - output STAT_TX_TOTAL_GOOD_PACKETS; - output STAT_TX_TOTAL_PACKETS; - output STAT_TX_UNICAST; - output STAT_TX_USER_PAUSE; - output STAT_TX_VLAN; - output TX_OVFOUT; - output [4:0] TX_PTP_PCSLANE_OUT; - output [79:0] TX_PTP_TSTAMP_OUT; - output [15:0] TX_PTP_TSTAMP_TAG_OUT; - output TX_PTP_TSTAMP_VALID_OUT; - output TX_RDYOUT; - output [15:0] TX_SERDES_ALT_DATA0; - output [15:0] TX_SERDES_ALT_DATA1; - output [15:0] TX_SERDES_ALT_DATA2; - output [15:0] TX_SERDES_ALT_DATA3; - output [63:0] TX_SERDES_DATA0; - output [63:0] TX_SERDES_DATA1; - output [63:0] TX_SERDES_DATA2; - output [63:0] TX_SERDES_DATA3; - output [31:0] TX_SERDES_DATA4; - output [31:0] TX_SERDES_DATA5; - output [31:0] TX_SERDES_DATA6; - output [31:0] TX_SERDES_DATA7; - output [31:0] TX_SERDES_DATA8; - output [31:0] TX_SERDES_DATA9; - output TX_UNFOUT; - input CTL_CAUI4_MODE; - input CTL_RSFEC_ENABLE_TRANSCODER_BYPASS_MODE; - input CTL_RSFEC_IEEE_ERROR_INDICATION_MODE; - input CTL_RX_CHECK_ETYPE_GCP; - input CTL_RX_CHECK_ETYPE_GPP; - input CTL_RX_CHECK_ETYPE_PCP; - input CTL_RX_CHECK_ETYPE_PPP; - input CTL_RX_CHECK_MCAST_GCP; - input CTL_RX_CHECK_MCAST_GPP; - input CTL_RX_CHECK_MCAST_PCP; - input CTL_RX_CHECK_MCAST_PPP; - input CTL_RX_CHECK_OPCODE_GCP; - input CTL_RX_CHECK_OPCODE_GPP; - input CTL_RX_CHECK_OPCODE_PCP; - input CTL_RX_CHECK_OPCODE_PPP; - input CTL_RX_CHECK_SA_GCP; - input CTL_RX_CHECK_SA_GPP; - input CTL_RX_CHECK_SA_PCP; - input CTL_RX_CHECK_SA_PPP; - input CTL_RX_CHECK_UCAST_GCP; - input CTL_RX_CHECK_UCAST_GPP; - input CTL_RX_CHECK_UCAST_PCP; - input CTL_RX_CHECK_UCAST_PPP; - input CTL_RX_ENABLE; - input CTL_RX_ENABLE_GCP; - input CTL_RX_ENABLE_GPP; - input CTL_RX_ENABLE_PCP; - input CTL_RX_ENABLE_PPP; - input CTL_RX_FORCE_RESYNC; - input [8:0] CTL_RX_PAUSE_ACK; - input [8:0] CTL_RX_PAUSE_ENABLE; - input CTL_RX_RSFEC_ENABLE; - input CTL_RX_RSFEC_ENABLE_CORRECTION; - input CTL_RX_RSFEC_ENABLE_INDICATION; - input [79:0] CTL_RX_SYSTEMTIMERIN; - input CTL_RX_TEST_PATTERN; - input CTL_TX_ENABLE; - input CTL_TX_LANE0_VLM_BIP7_OVERRIDE; - input [7:0] CTL_TX_LANE0_VLM_BIP7_OVERRIDE_VALUE; - input [8:0] CTL_TX_PAUSE_ENABLE; - input [15:0] CTL_TX_PAUSE_QUANTA0; - input [15:0] CTL_TX_PAUSE_QUANTA1; - input [15:0] CTL_TX_PAUSE_QUANTA2; - input [15:0] CTL_TX_PAUSE_QUANTA3; - input [15:0] CTL_TX_PAUSE_QUANTA4; - input [15:0] CTL_TX_PAUSE_QUANTA5; - input [15:0] CTL_TX_PAUSE_QUANTA6; - input [15:0] CTL_TX_PAUSE_QUANTA7; - input [15:0] CTL_TX_PAUSE_QUANTA8; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER0; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER1; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER2; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER3; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER4; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER5; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER6; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER7; - input [15:0] CTL_TX_PAUSE_REFRESH_TIMER8; - input [8:0] CTL_TX_PAUSE_REQ; - input CTL_TX_PTP_VLANE_ADJUST_MODE; - input CTL_TX_RESEND_PAUSE; - input CTL_TX_RSFEC_ENABLE; - input CTL_TX_SEND_IDLE; - input CTL_TX_SEND_LFI; - input CTL_TX_SEND_RFI; - input [79:0] CTL_TX_SYSTEMTIMERIN; - input CTL_TX_TEST_PATTERN; - input [9:0] DRP_ADDR; - input DRP_CLK; - input [15:0] DRP_DI; - input DRP_EN; - input DRP_WE; - input [329:0] RSFEC_BYPASS_RX_DIN; - input RSFEC_BYPASS_RX_DIN_CW_START; - input [329:0] RSFEC_BYPASS_TX_DIN; - input RSFEC_BYPASS_TX_DIN_CW_START; - input RX_CLK; - input RX_RESET; - input [15:0] RX_SERDES_ALT_DATA0; - input [15:0] RX_SERDES_ALT_DATA1; - input [15:0] RX_SERDES_ALT_DATA2; - input [15:0] RX_SERDES_ALT_DATA3; - input [9:0] RX_SERDES_CLK; - input [63:0] RX_SERDES_DATA0; - input [63:0] RX_SERDES_DATA1; - input [63:0] RX_SERDES_DATA2; - input [63:0] RX_SERDES_DATA3; - input [31:0] RX_SERDES_DATA4; - input [31:0] RX_SERDES_DATA5; - input [31:0] RX_SERDES_DATA6; - input [31:0] RX_SERDES_DATA7; - input [31:0] RX_SERDES_DATA8; - input [31:0] RX_SERDES_DATA9; - input [9:0] RX_SERDES_RESET; - input TX_CLK; - input [127:0] TX_DATAIN0; - input [127:0] TX_DATAIN1; - input [127:0] TX_DATAIN2; - input [127:0] TX_DATAIN3; - input TX_ENAIN0; - input TX_ENAIN1; - input TX_ENAIN2; - input TX_ENAIN3; - input TX_EOPIN0; - input TX_EOPIN1; - input TX_EOPIN2; - input TX_EOPIN3; - input TX_ERRIN0; - input TX_ERRIN1; - input TX_ERRIN2; - input TX_ERRIN3; - input [3:0] TX_MTYIN0; - input [3:0] TX_MTYIN1; - input [3:0] TX_MTYIN2; - input [3:0] TX_MTYIN3; - input [55:0] TX_PREIN; - input [1:0] TX_PTP_1588OP_IN; - input [15:0] TX_PTP_CHKSUM_OFFSET_IN; - input [63:0] TX_PTP_RXTSTAMP_IN; - input [15:0] TX_PTP_TAG_FIELD_IN; - input [15:0] TX_PTP_TSTAMP_OFFSET_IN; - input TX_PTP_UPD_CHKSUM_IN; - input TX_RESET; - input TX_SOPIN0; - input TX_SOPIN1; - input TX_SOPIN2; - input TX_SOPIN3; -endmodule - -module GTHE3_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [15:0] ADAPT_CFG0 = 16'hF800; - parameter [15:0] ADAPT_CFG1 = 16'h0000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [0:0] A_TXPROGDIVRESET = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h20F8; - parameter [15:0] CPLL_CFG1 = 16'hA494; - parameter [15:0] CPLL_CFG2 = 16'hF001; - parameter [5:0] CPLL_CFG3 = 6'h00; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 4; - parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [7:0] CPLL_INIT_CFG1 = 8'h00; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter [1:0] DDI_CTRL = 2'b00; - parameter integer DDI_REALIGN_WAIT = 15; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DFE_D_X_REL_POS = 1'b0; - parameter [0:0] DFE_VCM_COMP_EN = 1'b0; - parameter [9:0] DMONITOR_CFG0 = 10'h000; - parameter [7:0] DMONITOR_CFG1 = 8'h00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [15:0] ES_QUALIFIER0 = 16'h0000; - parameter [15:0] ES_QUALIFIER1 = 16'h0000; - parameter [15:0] ES_QUALIFIER2 = 16'h0000; - parameter [15:0] ES_QUALIFIER3 = 16'h0000; - parameter [15:0] ES_QUALIFIER4 = 16'h0000; - parameter [15:0] ES_QUAL_MASK0 = 16'h0000; - parameter [15:0] ES_QUAL_MASK1 = 16'h0000; - parameter [15:0] ES_QUAL_MASK2 = 16'h0000; - parameter [15:0] ES_QUAL_MASK3 = 16'h0000; - parameter [15:0] ES_QUAL_MASK4 = 16'h0000; - parameter [15:0] ES_SDATA_MASK0 = 16'h0000; - parameter [15:0] ES_SDATA_MASK1 = 16'h0000; - parameter [15:0] ES_SDATA_MASK2 = 16'h0000; - parameter [15:0] ES_SDATA_MASK3 = 16'h0000; - parameter [15:0] ES_SDATA_MASK4 = 16'h0000; - parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; - parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] GM_BIAS_SELECT = 1'b0; - parameter [0:0] LOCAL_MASTER = 1'b0; - parameter [1:0] OOBDIVCTL = 2'b00; - parameter [0:0] OOB_PWRUP = 1'b0; - parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; - parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; - parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; - parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; - parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; - parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; - parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; - parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; - parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; - parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; - parameter PCS_PCIE_EN = "FALSE"; - parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; - parameter [2:0] PCS_RSVD1 = 3'b000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; - parameter [15:0] PMA_RSV1 = 16'h0000; - parameter [2:0] PROCESS_PAR = 3'b010; - parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 0; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0000; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG1 = 16'h0080; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG2 = 16'h07E6; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG3 = 16'h0000; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG4 = 16'h0000; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG5 = 16'h0000; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h5080; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h07E0; - parameter [15:0] RXCDR_LOCK_CFG2 = 16'h7C42; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXCFOK_CFG0 = 16'h4000; - parameter [15:0] RXCFOK_CFG1 = 16'h0060; - parameter [15:0] RXCFOK_CFG2 = 16'h000E; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; - parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0032; - parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0000; - parameter [15:0] RXDFE_CFG0 = 16'h0A00; - parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG1 = 16'h7840; - parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H3_CFG0 = 16'h4000; - parameter [15:0] RXDFE_H3_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H4_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H5_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H5_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H6_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H6_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H7_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H7_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H8_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H8_CFG1 = 16'h0000; - parameter [15:0] RXDFE_H9_CFG0 = 16'h2000; - parameter [15:0] RXDFE_H9_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HA_CFG0 = 16'h2000; - parameter [15:0] RXDFE_HA_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HB_CFG0 = 16'h2000; - parameter [15:0] RXDFE_HB_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG1 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG0 = 16'h8000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG0 = 16'h8000; - parameter [15:0] RXDFE_UT_CFG1 = 16'h0003; - parameter [15:0] RXDFE_VP_CFG0 = 16'hAA00; - parameter [15:0] RXDFE_VP_CFG1 = 16'h0033; - parameter [15:0] RXDLY_CFG = 16'h001F; - parameter [15:0] RXDLY_LCFG = 16'h0030; - parameter RXELECIDLE_CFG = "Sigcfg_4"; - parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h0000; - parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; - parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h8000; - parameter [15:0] RXLPM_OS_CFG1 = 16'h0002; - parameter [8:0] RXOOB_CFG = 9'b000000110; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter integer RXOUT_DIV = 4; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [15:0] RXPHBEACON_CFG = 16'h0000; - parameter [15:0] RXPHDLY_CFG = 16'h2020; - parameter [15:0] RXPHSAMP_CFG = 16'h2100; - parameter [15:0] RXPHSLIP_CFG = 16'h6622; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] RXPI_CFG0 = 2'b00; - parameter [1:0] RXPI_CFG1 = 2'b00; - parameter [1:0] RXPI_CFG2 = 2'b00; - parameter [1:0] RXPI_CFG3 = 2'b00; - parameter [0:0] RXPI_CFG4 = 1'b0; - parameter [0:0] RXPI_CFG5 = 1'b1; - parameter [2:0] RXPI_CFG6 = 3'b000; - parameter [0:0] RXPI_LPM = 1'b0; - parameter [0:0] RXPI_VREFSEL = 1'b0; - parameter RXPMACLK_SEL = "DATA"; - parameter [4:0] RXPMARESET_TIME = 5'b00001; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h0AD4; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; - parameter integer RX_CLK25_DIV = 8; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; - parameter [3:0] RX_CM_BUF_CFG = 4'b1010; - parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter [1:0] RX_CM_SEL = 2'b11; - parameter [3:0] RX_CM_TRIM = 4'b0100; - parameter [7:0] RX_CTLE3_LPF = 8'b00000000; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [3:0] RX_DFELPM_CFG0 = 4'b0110; - parameter [0:0] RX_DFELPM_CFG1 = 1'b0; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; - parameter [2:0] RX_DFE_AGC_CFG1 = 3'b100; - parameter [1:0] RX_DFE_KL_LPM_KH_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KH_CFG1 = 3'b010; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [4:0] RX_DIVRESET_TIME = 5'b00001; - parameter [0:0] RX_EN_HI_LR = 1'b0; - parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; - parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; - parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; - parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; - parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; - parameter integer RX_INT_DATAWIDTH = 1; - parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter real RX_PROGDIV_CFG = 4.0; - parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; - parameter integer RX_SIG_VALID_DLY = 11; - parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; - parameter [1:0] RX_SUM_RES_CTRL = 2'b00; - parameter [3:0] RX_SUM_VCMTUNE = 4'b0000; - parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; - parameter [2:0] RX_SUM_VREF_TUNE = 3'b000; - parameter [1:0] RX_TUNE_AFE_OS = 2'b00; - parameter [0:0] RX_WIDEMODE_CDR = 1'b0; - parameter RX_XCLK_SEL = "RXDES"; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_MODE = "FAST"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; - parameter integer SIM_VERSION = 2; - parameter [1:0] TAPDLY_SET_TX = 2'h0; - parameter [3:0] TEMPERATUR_PAR = 4'b0010; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [7:0] TST_RSV0 = 8'h00; - parameter [7:0] TST_RSV1 = 8'h00; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; - parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter [3:0] TXDRVBIAS_N = 4'b1010; - parameter [3:0] TXDRVBIAS_P = 4'b1100; - parameter TXFIFO_ADDR_CFG = "LOW"; - parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 4; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h2020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0001; - parameter [15:0] TXPH_CFG = 16'h0980; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b1; - parameter [2:0] TXPI_CFG5 = 3'b000; - parameter [0:0] TXPI_GRAY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter [0:0] TXPI_LPM = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [0:0] TXPI_VREFSEL = 1'b0; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 8; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DCD_CFG = 6'b000010; - parameter [0:0] TX_DCD_EN = 1'b0; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [4:0] TX_DIVRESET_TIME = 5'b00001; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_EML_PHI_TUNE = 1'b0; - parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; - parameter integer TX_INT_DATAWIDTH = 1; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [2:0] TX_MODE_SEL = 3'b000; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter TX_PROGCLK_SEL = "POSTPI"; - parameter real TX_PROGDIV_CFG = 4.0; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter [2:0] TX_RXDETECT_REF = 3'b100; - parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; - parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; - parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - parameter [1:0] WB_MODE = 2'b00; - output [2:0] BUFGTCE; - output [2:0] BUFGTCEMASK; - output [8:0] BUFGTDIV; - output [2:0] BUFGTRESET; - output [2:0] BUFGTRSTMASK; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output [16:0] DMONITOROUT; - output [15:0] DRPDO; - output DRPRDY; - output EYESCANDATAERROR; - output GTHTXN; - output GTHTXP; - output GTPOWERGOOD; - output GTREFCLKMONITOR; - output PCIERATEGEN3; - output PCIERATEIDLE; - output [1:0] PCIERATEQPLLPD; - output [1:0] PCIERATEQPLLRESET; - output PCIESYNCTXSYNCDONE; - output PCIEUSERGEN3RDY; - output PCIEUSERPHYSTATUSRST; - output PCIEUSERRATESTART; - output [11:0] PCSRSVDOUT; - output PHYSTATUS; - output [7:0] PINRSRVDAS; - output RESETEXCEPTION; - output [2:0] RXBUFSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCDRPHDONE; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output [4:0] RXCHBONDO; - output [1:0] RXCLKCORCNT; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output [15:0] RXCTRL0; - output [15:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [127:0] RXDATA; - output [7:0] RXDATAEXTENDRSVD; - output [1:0] RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output [5:0] RXHEADER; - output [1:0] RXHEADERVALID; - output [6:0] RXMONITOROUT; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPHALIGNERR; - output RXPMARESETDONE; - output RXPRBSERR; - output RXPRBSLOCKED; - output RXPRGDIVRESETDONE; - output RXQPISENN; - output RXQPISENP; - output RXRATEDONE; - output RXRECCLKOUT; - output RXRESETDONE; - output RXSLIDERDY; - output RXSLIPDONE; - output RXSLIPOUTCLKRDY; - output RXSLIPPMARDY; - output [1:0] RXSTARTOFSEQ; - output [2:0] RXSTATUS; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output [1:0] TXBUFSTATUS; - output TXCOMFINISH; - output TXDLYSRESETDONE; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXPRGDIVRESETDONE; - output TXQPISENN; - output TXQPISENP; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - input CFGRESET; - input CLKRSVD0; - input CLKRSVD1; - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input [2:0] CPLLREFCLKSEL; - input CPLLRESET; - input DMONFIFORESET; - input DMONITORCLK; - input [8:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input EVODDPHICALDONE; - input EVODDPHICALSTART; - input EVODDPHIDRDEN; - input EVODDPHIDWREN; - input EVODDPHIXRDEN; - input EVODDPHIXWREN; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - input GTGREFCLK; - input GTHRXN; - input GTHRXP; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTRESETSEL; - input [15:0] GTRSVD; - input GTRXRESET; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input [2:0] LOOPBACK; - input LPBKRXTXSEREN; - input LPBKTXRXSEREN; - input PCIEEQRXEQADAPTDONE; - input PCIERSTIDLE; - input PCIERSTTXSYNCSTART; - input PCIEUSERRATEDONE; - input [15:0] PCSRSVDIN; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN; - input QPLL0CLK; - input QPLL0REFCLK; - input QPLL1CLK; - input QPLL1REFCLK; - input RESETOVRD; - input RSTCLKENTX; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input [4:0] RXCHBONDI; - input [2:0] RXCHBONDLEVEL; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCOMMADETEN; - input [1:0] RXDFEAGCCTRL; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP10HOLD; - input RXDFETAP10OVRDEN; - input RXDFETAP11HOLD; - input RXDFETAP11OVRDEN; - input RXDFETAP12HOLD; - input RXDFETAP12OVRDEN; - input RXDFETAP13HOLD; - input RXDFETAP13OVRDEN; - input RXDFETAP14HOLD; - input RXDFETAP14OVRDEN; - input RXDFETAP15HOLD; - input RXDFETAP15OVRDEN; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFETAP8HOLD; - input RXDFETAP8OVRDEN; - input RXDFETAP9HOLD; - input RXDFETAP9OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEVSEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input [1:0] RXELECIDLEMODE; - input RXGEARBOXSLIP; - input RXLATCLK; - input RXLPMEN; - input RXLPMGCHOLD; - input RXLPMGCOVRDEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXLPMOSHOLD; - input RXLPMOSOVRDEN; - input RXMCOMMAALIGNEN; - input [1:0] RXMONITORSEL; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input [3:0] RXOSINTCFG; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTOVRDEN; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; - input RXOSOVRDEN; - input [2:0] RXOUTCLKSEL; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input [1:0] RXPD; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input [1:0] RXPLLCLKSEL; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input [3:0] RXPRBSSEL; - input RXPROGDIVRESET; - input RXQPIEN; - input [2:0] RXRATE; - input RXRATEMODE; - input RXSLIDE; - input RXSLIPOUTCLK; - input RXSLIPPMA; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input [1:0] RXSYSCLKSEL; - input RXUSERRDY; - input RXUSRCLK; - input RXUSRCLK2; - input SIGVALIDCLK; - input [19:0] TSTIN; - input [7:0] TX8B10BBYPASS; - input TX8B10BEN; - input [2:0] TXBUFDIFFCTRL; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input [15:0] TXCTRL0; - input [15:0] TXCTRL1; - input [7:0] TXCTRL2; - input [127:0] TXDATA; - input [7:0] TXDATAEXTENDRSVD; - input TXDEEMPH; - input TXDETECTRX; - input [3:0] TXDIFFCTRL; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input [5:0] TXHEADER; - input TXINHIBIT; - input TXLATCLK; - input [6:0] TXMAINCURSOR; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input TXPCSRESET; - input [1:0] TXPD; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input [4:0] TXPIPPMSTEPSIZE; - input TXPISOPD; - input [1:0] TXPLLCLKSEL; - input TXPMARESET; - input TXPOLARITY; - input [4:0] TXPOSTCURSOR; - input TXPOSTCURSORINV; - input TXPRBSFORCEERR; - input [3:0] TXPRBSSEL; - input [4:0] TXPRECURSOR; - input TXPRECURSORINV; - input TXPROGDIVRESET; - input TXQPIBIASEN; - input TXQPISTRONGPDOWN; - input TXQPIWEAKPUP; - input [2:0] TXRATE; - input TXRATEMODE; - input [6:0] TXSEQUENCE; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input [1:0] TXSYSCLKSEL; - input TXUSERRDY; - input TXUSRCLK; - input TXUSRCLK2; -endmodule - -module GTHE3_COMMON (...); - parameter [15:0] BIAS_CFG0 = 16'h0000; - parameter [15:0] BIAS_CFG1 = 16'h0000; - parameter [15:0] BIAS_CFG2 = 16'h0000; - parameter [15:0] BIAS_CFG3 = 16'h0000; - parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; - parameter [15:0] COMMON_CFG0 = 16'h0000; - parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0004; - parameter [15:0] QPLL0_CFG0 = 16'h3018; - parameter [15:0] QPLL0_CFG1 = 16'h0000; - parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0000; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0000; - parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0009; - parameter [9:0] QPLL0_CP = 10'b0000011111; - parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; - parameter integer QPLL0_FBDIV = 66; - parameter integer QPLL0_FBDIV_G3 = 80; - parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h01E8; - parameter [9:0] QPLL0_LPF = 10'b1111111111; - parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter integer QPLL0_REFCLK_DIV = 2; - parameter [15:0] QPLL0_SDM_CFG0 = 16'b0000000000000000; - parameter [15:0] QPLL0_SDM_CFG1 = 16'b0000000000000000; - parameter [15:0] QPLL0_SDM_CFG2 = 16'b0000000000000000; - parameter [15:0] QPLL1_CFG0 = 16'h3018; - parameter [15:0] QPLL1_CFG1 = 16'h0000; - parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0000; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0000; - parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0009; - parameter [9:0] QPLL1_CP = 10'b0000011111; - parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; - parameter integer QPLL1_FBDIV = 66; - parameter integer QPLL1_FBDIV_G3 = 80; - parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1111111111; - parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter integer QPLL1_REFCLK_DIV = 2; - parameter [15:0] QPLL1_SDM_CFG0 = 16'b0000000000000000; - parameter [15:0] QPLL1_SDM_CFG1 = 16'b0000000000000000; - parameter [15:0] QPLL1_SDM_CFG2 = 16'b0000000000000000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [15:0] RSVD_ATTR2 = 16'h0000; - parameter [15:0] RSVD_ATTR3 = 16'h0000; - parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; - parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_EN = 1'b1; - parameter [0:0] SARC_SEL = 1'b0; - parameter [15:0] SDM0DATA1_0 = 16'b0000000000000000; - parameter [8:0] SDM0DATA1_1 = 9'b000000000; - parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; - parameter [0:0] SDM0_DATA_PIN_SEL = 1'b0; - parameter [0:0] SDM0_WIDTH_PIN_SEL = 1'b0; - parameter [15:0] SDM1DATA1_0 = 16'b0000000000000000; - parameter [8:0] SDM1DATA1_1 = 9'b000000000; - parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter [0:0] SDM1_DATA_PIN_SEL = 1'b0; - parameter [0:0] SDM1_WIDTH_PIN_SEL = 1'b0; - parameter SIM_MODE = "FAST"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter integer SIM_VERSION = 2; - output [15:0] DRPDO; - output DRPRDY; - output [7:0] PMARSVDOUT0; - output [7:0] PMARSVDOUT1; - output QPLL0FBCLKLOST; - output QPLL0LOCK; - output QPLL0OUTCLK; - output QPLL0OUTREFCLK; - output QPLL0REFCLKLOST; - output QPLL1FBCLKLOST; - output QPLL1LOCK; - output QPLL1OUTCLK; - output QPLL1OUTREFCLK; - output QPLL1REFCLKLOST; - output [7:0] QPLLDMONITOR0; - output [7:0] QPLLDMONITOR1; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0_SEL; - output [1:0] RXRECCLK1_SEL; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input [8:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input GTGREFCLK0; - input GTGREFCLK1; - input GTNORTHREFCLK00; - input GTNORTHREFCLK01; - input GTNORTHREFCLK10; - input GTNORTHREFCLK11; - input GTREFCLK00; - input GTREFCLK01; - input GTREFCLK10; - input GTREFCLK11; - input GTSOUTHREFCLK00; - input GTSOUTHREFCLK01; - input GTSOUTHREFCLK10; - input GTSOUTHREFCLK11; - input [7:0] PMARSVD0; - input [7:0] PMARSVD1; - input QPLL0CLKRSVD0; - input QPLL0CLKRSVD1; - input QPLL0LOCKDETCLK; - input QPLL0LOCKEN; - input QPLL0PD; - input [2:0] QPLL0REFCLKSEL; - input QPLL0RESET; - input QPLL1CLKRSVD0; - input QPLL1CLKRSVD1; - input QPLL1LOCKDETCLK; - input QPLL1LOCKEN; - input QPLL1PD; - input [2:0] QPLL1REFCLKSEL; - input QPLL1RESET; - input [7:0] QPLLRSVD1; - input [4:0] QPLLRSVD2; - input [4:0] QPLLRSVD3; - input [7:0] QPLLRSVD4; - input RCALENB; -endmodule - -module GTHE4_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [15:0] ADAPT_CFG0 = 16'h9200; - parameter [15:0] ADAPT_CFG1 = 16'h801C; - parameter [15:0] ADAPT_CFG2 = 16'h0000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [0:0] A_RXTERMINATION = 1'b1; - parameter [4:0] A_TXDIFFCTRL = 5'b01100; - parameter [0:0] A_TXPROGDIVRESET = 1'b0; - parameter [0:0] CAPBYPASS_FORCE = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter [0:0] CFOK_PWRSVE_EN = 1'b1; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter [15:0] CH_HSPMUX = 16'h2424; - parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; - parameter [15:0] CKCAL_RSVD0 = 16'h4000; - parameter [15:0] CKCAL_RSVD1 = 16'h0000; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h01FA; - parameter [15:0] CPLL_CFG1 = 16'h24A9; - parameter [15:0] CPLL_CFG2 = 16'h6807; - parameter [15:0] CPLL_CFG3 = 16'h0000; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 4; - parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; - parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; - parameter [1:0] DDI_CTRL = 2'b00; - parameter integer DDI_REALIGN_WAIT = 15; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DELAY_ELEC = 1'b0; - parameter [9:0] DMONITOR_CFG0 = 10'h000; - parameter [7:0] DMONITOR_CFG1 = 8'h00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h800; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [15:0] ES_QUALIFIER0 = 16'h0000; - parameter [15:0] ES_QUALIFIER1 = 16'h0000; - parameter [15:0] ES_QUALIFIER2 = 16'h0000; - parameter [15:0] ES_QUALIFIER3 = 16'h0000; - parameter [15:0] ES_QUALIFIER4 = 16'h0000; - parameter [15:0] ES_QUALIFIER5 = 16'h0000; - parameter [15:0] ES_QUALIFIER6 = 16'h0000; - parameter [15:0] ES_QUALIFIER7 = 16'h0000; - parameter [15:0] ES_QUALIFIER8 = 16'h0000; - parameter [15:0] ES_QUALIFIER9 = 16'h0000; - parameter [15:0] ES_QUAL_MASK0 = 16'h0000; - parameter [15:0] ES_QUAL_MASK1 = 16'h0000; - parameter [15:0] ES_QUAL_MASK2 = 16'h0000; - parameter [15:0] ES_QUAL_MASK3 = 16'h0000; - parameter [15:0] ES_QUAL_MASK4 = 16'h0000; - parameter [15:0] ES_QUAL_MASK5 = 16'h0000; - parameter [15:0] ES_QUAL_MASK6 = 16'h0000; - parameter [15:0] ES_QUAL_MASK7 = 16'h0000; - parameter [15:0] ES_QUAL_MASK8 = 16'h0000; - parameter [15:0] ES_QUAL_MASK9 = 16'h0000; - parameter [15:0] ES_SDATA_MASK0 = 16'h0000; - parameter [15:0] ES_SDATA_MASK1 = 16'h0000; - parameter [15:0] ES_SDATA_MASK2 = 16'h0000; - parameter [15:0] ES_SDATA_MASK3 = 16'h0000; - parameter [15:0] ES_SDATA_MASK4 = 16'h0000; - parameter [15:0] ES_SDATA_MASK5 = 16'h0000; - parameter [15:0] ES_SDATA_MASK6 = 16'h0000; - parameter [15:0] ES_SDATA_MASK7 = 16'h0000; - parameter [15:0] ES_SDATA_MASK8 = 16'h0000; - parameter [15:0] ES_SDATA_MASK9 = 16'h0000; - parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; - parameter [0:0] LOCAL_MASTER = 1'b0; - parameter [2:0] LPBK_BIAS_CTRL = 3'b000; - parameter [0:0] LPBK_EN_RCAL_B = 1'b0; - parameter [3:0] LPBK_EXT_RCAL = 4'b0000; - parameter [2:0] LPBK_IND_CTRL0 = 3'b000; - parameter [2:0] LPBK_IND_CTRL1 = 3'b000; - parameter [2:0] LPBK_IND_CTRL2 = 3'b000; - parameter [3:0] LPBK_RG_CTRL = 4'b0000; - parameter [1:0] OOBDIVCTL = 2'b00; - parameter [0:0] OOB_PWRUP = 1'b0; - parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; - parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; - parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; - parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; - parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; - parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; - parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; - parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; - parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; - parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; - parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; - parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; - parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; - parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; - parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; - parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; - parameter PCS_PCIE_EN = "FALSE"; - parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter integer PREIQ_FREQ_BST = 0; - parameter [2:0] PROCESS_PAR = 3'b010; - parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; - parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; - parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; - parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 0; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0003; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; - parameter [15:0] RXCDR_CFG1 = 16'h0000; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG2 = 16'h0164; - parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; - parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; - parameter [15:0] RXCDR_CFG3 = 16'h0024; - parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; - parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; - parameter [15:0] RXCDR_CFG4 = 16'h5CF6; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; - parameter [15:0] RXCDR_CFG5 = 16'hB46B; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; - parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXCFOK_CFG0 = 16'h0000; - parameter [15:0] RXCFOK_CFG1 = 16'h0002; - parameter [15:0] RXCFOK_CFG2 = 16'h002D; - parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; - parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; - parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; - parameter [15:0] RXDFE_CFG0 = 16'h4000; - parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; - parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0002; - parameter [0:0] RXDFE_PWR_SAVING = 1'b0; - parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; - parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; - parameter [15:0] RXDLY_CFG = 16'h0010; - parameter [15:0] RXDLY_LCFG = 16'h0030; - parameter RXELECIDLE_CFG = "SIGCFG_4"; - parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h1000; - parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; - parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; - parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; - parameter [8:0] RXOOB_CFG = 9'b000110000; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter integer RXOUT_DIV = 4; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [15:0] RXPHBEACON_CFG = 16'h0000; - parameter [15:0] RXPHDLY_CFG = 16'h2020; - parameter [15:0] RXPHSAMP_CFG = 16'h2100; - parameter [15:0] RXPHSLIP_CFG = 16'h9933; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; - parameter [15:0] RXPI_CFG0 = 16'h0002; - parameter [15:0] RXPI_CFG1 = 16'b0000000000000000; - parameter [0:0] RXPI_LPM = 1'b0; - parameter [1:0] RXPI_SEL_LC = 2'b00; - parameter [1:0] RXPI_STARTCODE = 2'b00; - parameter [0:0] RXPI_VREFSEL = 1'b0; - parameter RXPMACLK_SEL = "DATA"; - parameter [4:0] RXPMARESET_TIME = 5'b00001; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; - parameter integer RX_CLK25_DIV = 8; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; - parameter [3:0] RX_CM_BUF_CFG = 4'b1010; - parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter integer RX_CM_SEL = 3; - parameter integer RX_CM_TRIM = 12; - parameter [7:0] RX_CTLE3_LPF = 8'b00000000; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [2:0] RX_DEGEN_CTRL = 3'b011; - parameter integer RX_DFELPM_CFG0 = 0; - parameter [0:0] RX_DFELPM_CFG1 = 1'b1; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; - parameter integer RX_DFE_AGC_CFG1 = 4; - parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [0:0] RX_DIV2_MODE_B = 1'b0; - parameter [4:0] RX_DIVRESET_TIME = 5'b00001; - parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; - parameter [0:0] RX_EN_HI_LR = 1'b1; - parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; - parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; - parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; - parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; - parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; - parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; - parameter integer RX_INT_DATAWIDTH = 1; - parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] RX_PMA_RSV0 = 16'h0000; - parameter real RX_PROGDIV_CFG = 0.0; - parameter [15:0] RX_PROGDIV_RATE = 16'h0001; - parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; - parameter [0:0] RX_RESLOAD_OVRD = 1'b0; - parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; - parameter integer RX_SIG_VALID_DLY = 11; - parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b1001; - parameter [3:0] RX_SUM_RESLOAD_CTRL = 4'b0000; - parameter [3:0] RX_SUM_VCMTUNE = 4'b1010; - parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; - parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; - parameter [1:0] RX_TUNE_AFE_OS = 2'b00; - parameter [2:0] RX_VREG_CTRL = 3'b101; - parameter [0:0] RX_VREG_PDB = 1'b1; - parameter [1:0] RX_WIDEMODE_CDR = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; - parameter RX_XCLK_SEL = "RXDES"; - parameter [0:0] RX_XMODE_SEL = 1'b0; - parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; - parameter [0:0] SAS_12G_MODE = 1'b0; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SIM_MODE = "FAST"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; - parameter [0:0] SRSTMODE = 1'b0; - parameter [1:0] TAPDLY_SET_TX = 2'h0; - parameter [3:0] TEMPERATURE_PAR = 4'b0010; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [7:0] TST_RSV0 = 8'h00; - parameter [7:0] TST_RSV1 = 8'h00; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h0010; - parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter [3:0] TXDRVBIAS_N = 4'b1010; - parameter TXFIFO_ADDR_CFG = "LOW"; - parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 4; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h6020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0002; - parameter [15:0] TXPH_CFG = 16'h0123; - parameter [15:0] TXPH_CFG2 = 16'h0000; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [15:0] TXPI_CFG = 16'h0000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b1; - parameter [2:0] TXPI_CFG5 = 3'b000; - parameter [0:0] TXPI_GRAY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter [0:0] TXPI_LPM = 1'b0; - parameter [0:0] TXPI_PPM = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [0:0] TXPI_VREFSEL = 1'b0; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 8; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [5:0] TX_DEEMPH2 = 6'b000000; - parameter [5:0] TX_DEEMPH3 = 6'b000000; - parameter [4:0] TX_DIVRESET_TIME = 5'b00001; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter integer TX_DRVMUX_CTRL = 2; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] TX_FIFO_BYP_EN = 1'b0; - parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; - parameter integer TX_INT_DATAWIDTH = 1; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; - parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; - parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; - parameter integer TX_PI_BIASSET = 0; - parameter [1:0] TX_PI_IBIAS_MID = 2'b00; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] TX_PMA_RSV0 = 16'h0008; - parameter integer TX_PREDRV_CTRL = 2; - parameter TX_PROGCLK_SEL = "POSTPI"; - parameter real TX_PROGDIV_CFG = 0.0; - parameter [15:0] TX_PROGDIV_RATE = 16'h0001; - parameter [0:0] TX_QPI_STATUS_EN = 1'b0; - parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter integer TX_RXDETECT_REF = 3; - parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; - parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; - parameter [1:0] TX_SW_MEAS = 2'b00; - parameter [2:0] TX_VREG_CTRL = 3'b000; - parameter [0:0] TX_VREG_PDB = 1'b0; - parameter [1:0] TX_VREG_VREFSEL = 2'b00; - parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; - parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; - parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; - parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; - parameter [0:0] USB_EXT_CNTL = 1'b1; - parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; - parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; - parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; - parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; - parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; - parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; - parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; - parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; - parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; - parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; - parameter [0:0] USB_MODE = 1'b0; - parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; - parameter integer USB_PING_SATA_MAX_INIT = 21; - parameter integer USB_PING_SATA_MIN_INIT = 12; - parameter integer USB_POLL_SATA_MAX_BURST = 8; - parameter integer USB_POLL_SATA_MIN_BURST = 4; - parameter [0:0] USB_RAW_ELEC = 1'b0; - parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; - parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; - parameter integer USB_U1_SATA_MAX_WAKE = 7; - parameter integer USB_U1_SATA_MIN_WAKE = 4; - parameter integer USB_U2_SAS_MAX_COM = 64; - parameter integer USB_U2_SAS_MIN_COM = 36; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - parameter [0:0] Y_ALL_MODE = 1'b0; - output BUFGTCE; - output [2:0] BUFGTCEMASK; - output [8:0] BUFGTDIV; - output BUFGTRESET; - output [2:0] BUFGTRSTMASK; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output [15:0] DMONITOROUT; - output DMONITOROUTCLK; - output [15:0] DRPDO; - output DRPRDY; - output EYESCANDATAERROR; - output GTHTXN; - output GTHTXP; - output GTPOWERGOOD; - output GTREFCLKMONITOR; - output PCIERATEGEN3; - output PCIERATEIDLE; - output [1:0] PCIERATEQPLLPD; - output [1:0] PCIERATEQPLLRESET; - output PCIESYNCTXSYNCDONE; - output PCIEUSERGEN3RDY; - output PCIEUSERPHYSTATUSRST; - output PCIEUSERRATESTART; - output [15:0] PCSRSVDOUT; - output PHYSTATUS; - output [15:0] PINRSRVDAS; - output POWERPRESENT; - output RESETEXCEPTION; - output [2:0] RXBUFSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCDRPHDONE; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output [4:0] RXCHBONDO; - output RXCKCALDONE; - output [1:0] RXCLKCORCNT; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output [15:0] RXCTRL0; - output [15:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [127:0] RXDATA; - output [7:0] RXDATAEXTENDRSVD; - output [1:0] RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output [5:0] RXHEADER; - output [1:0] RXHEADERVALID; - output RXLFPSTRESETDET; - output RXLFPSU2LPEXITDET; - output RXLFPSU3WAKEDET; - output [7:0] RXMONITOROUT; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPHALIGNERR; - output RXPMARESETDONE; - output RXPRBSERR; - output RXPRBSLOCKED; - output RXPRGDIVRESETDONE; - output RXQPISENN; - output RXQPISENP; - output RXRATEDONE; - output RXRECCLKOUT; - output RXRESETDONE; - output RXSLIDERDY; - output RXSLIPDONE; - output RXSLIPOUTCLKRDY; - output RXSLIPPMARDY; - output [1:0] RXSTARTOFSEQ; - output [2:0] RXSTATUS; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output [1:0] TXBUFSTATUS; - output TXCOMFINISH; - output TXDCCDONE; - output TXDLYSRESETDONE; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXPRGDIVRESETDONE; - output TXQPISENN; - output TXQPISENP; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - input CDRSTEPDIR; - input CDRSTEPSQ; - input CDRSTEPSX; - input CFGRESET; - input CLKRSVD0; - input CLKRSVD1; - input CPLLFREQLOCK; - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input [2:0] CPLLREFCLKSEL; - input CPLLRESET; - input DMONFIFORESET; - input DMONITORCLK; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPRST; - input DRPWE; - input EYESCANRESET; - input EYESCANTRIGGER; - input FREQOS; - input GTGREFCLK; - input GTHRXN; - input GTHRXP; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input [15:0] GTRSVD; - input GTRXRESET; - input GTRXRESETSEL; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input GTTXRESETSEL; - input INCPCTRL; - input [2:0] LOOPBACK; - input PCIEEQRXEQADAPTDONE; - input PCIERSTIDLE; - input PCIERSTTXSYNCSTART; - input PCIEUSERRATEDONE; - input [15:0] PCSRSVDIN; - input QPLL0CLK; - input QPLL0FREQLOCK; - input QPLL0REFCLK; - input QPLL1CLK; - input QPLL1FREQLOCK; - input QPLL1REFCLK; - input RESETOVRD; - input RX8B10BEN; - input RXAFECFOKEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCHBONDEN; - input [4:0] RXCHBONDI; - input [2:0] RXCHBONDLEVEL; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCKCALRESET; - input [6:0] RXCKCALSTART; - input RXCOMMADETEN; - input [1:0] RXDFEAGCCTRL; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input [3:0] RXDFECFOKFCNUM; - input RXDFECFOKFEN; - input RXDFECFOKFPULSE; - input RXDFECFOKHOLD; - input RXDFECFOKOVREN; - input RXDFEKHHOLD; - input RXDFEKHOVRDEN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP10HOLD; - input RXDFETAP10OVRDEN; - input RXDFETAP11HOLD; - input RXDFETAP11OVRDEN; - input RXDFETAP12HOLD; - input RXDFETAP12OVRDEN; - input RXDFETAP13HOLD; - input RXDFETAP13OVRDEN; - input RXDFETAP14HOLD; - input RXDFETAP14OVRDEN; - input RXDFETAP15HOLD; - input RXDFETAP15OVRDEN; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFETAP8HOLD; - input RXDFETAP8OVRDEN; - input RXDFETAP9HOLD; - input RXDFETAP9OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input [1:0] RXELECIDLEMODE; - input RXEQTRAINING; - input RXGEARBOXSLIP; - input RXLATCLK; - input RXLPMEN; - input RXLPMGCHOLD; - input RXLPMGCOVRDEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXLPMOSHOLD; - input RXLPMOSOVRDEN; - input RXMCOMMAALIGNEN; - input [1:0] RXMONITORSEL; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input RXOSOVRDEN; - input [2:0] RXOUTCLKSEL; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input [1:0] RXPD; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input [1:0] RXPLLCLKSEL; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input [3:0] RXPRBSSEL; - input RXPROGDIVRESET; - input RXQPIEN; - input [2:0] RXRATE; - input RXRATEMODE; - input RXSLIDE; - input RXSLIPOUTCLK; - input RXSLIPPMA; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input [1:0] RXSYSCLKSEL; - input RXTERMINATION; - input RXUSERRDY; - input RXUSRCLK; - input RXUSRCLK2; - input SIGVALIDCLK; - input [19:0] TSTIN; - input [7:0] TX8B10BBYPASS; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input [15:0] TXCTRL0; - input [15:0] TXCTRL1; - input [7:0] TXCTRL2; - input [127:0] TXDATA; - input [7:0] TXDATAEXTENDRSVD; - input TXDCCFORCESTART; - input TXDCCRESET; - input [1:0] TXDEEMPH; - input TXDETECTRX; - input [4:0] TXDIFFCTRL; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input [5:0] TXHEADER; - input TXINHIBIT; - input TXLATCLK; - input TXLFPSTRESET; - input TXLFPSU2LPEXIT; - input TXLFPSU3WAKE; - input [6:0] TXMAINCURSOR; - input [2:0] TXMARGIN; - input TXMUXDCDEXHOLD; - input TXMUXDCDORWREN; - input TXONESZEROS; - input [2:0] TXOUTCLKSEL; - input TXPCSRESET; - input [1:0] TXPD; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input [4:0] TXPIPPMSTEPSIZE; - input TXPISOPD; - input [1:0] TXPLLCLKSEL; - input TXPMARESET; - input TXPOLARITY; - input [4:0] TXPOSTCURSOR; - input TXPRBSFORCEERR; - input [3:0] TXPRBSSEL; - input [4:0] TXPRECURSOR; - input TXPROGDIVRESET; - input TXQPIBIASEN; - input TXQPIWEAKPUP; - input [2:0] TXRATE; - input TXRATEMODE; - input [6:0] TXSEQUENCE; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input [1:0] TXSYSCLKSEL; - input TXUSERRDY; - input TXUSRCLK; - input TXUSRCLK2; -endmodule - -module GTHE4_COMMON (...); - parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; - parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; - parameter [0:0] AEN_SDM0TOGGLE = 1'b0; - parameter [0:0] AEN_SDM1TOGGLE = 1'b0; - parameter [0:0] A_SDM0TOGGLE = 1'b0; - parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; - parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; - parameter [0:0] A_SDM1TOGGLE = 1'b0; - parameter [15:0] BIAS_CFG0 = 16'h0000; - parameter [15:0] BIAS_CFG1 = 16'h0000; - parameter [15:0] BIAS_CFG2 = 16'h0000; - parameter [15:0] BIAS_CFG3 = 16'h0000; - parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [15:0] BIAS_CFG_RSVD = 16'h0000; - parameter [15:0] COMMON_CFG0 = 16'h0000; - parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0000; - parameter [15:0] PPF0_CFG = 16'h0F00; - parameter [15:0] PPF1_CFG = 16'h0F00; - parameter QPLL0CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL0_CFG0 = 16'h391C; - parameter [15:0] QPLL0_CFG1 = 16'h0000; - parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0F80; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; - parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0002; - parameter [9:0] QPLL0_CP = 10'b0000011111; - parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; - parameter integer QPLL0_FBDIV = 66; - parameter integer QPLL0_FBDIV_G3 = 80; - parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL0_LPF = 10'b1011111111; - parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL0_PCI_EN = 1'b0; - parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL0_REFCLK_DIV = 1; - parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; - parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; - parameter QPLL1CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL1_CFG0 = 16'h691C; - parameter [15:0] QPLL1_CFG1 = 16'h0020; - parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0F80; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; - parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0002; - parameter [9:0] QPLL1_CP = 10'b0000011111; - parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; - parameter integer QPLL1_FBDIV = 66; - parameter integer QPLL1_FBDIV_G3 = 80; - parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1011111111; - parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL1_PCI_EN = 1'b0; - parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL1_REFCLK_DIV = 1; - parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [15:0] RSVD_ATTR2 = 16'h0000; - parameter [15:0] RSVD_ATTR3 = 16'h0000; - parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; - parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_ENB = 1'b0; - parameter [0:0] SARC_SEL = 1'b0; - parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; - parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SIM_MODE = "FAST"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - output [15:0] DRPDO; - output DRPRDY; - output [7:0] PMARSVDOUT0; - output [7:0] PMARSVDOUT1; - output QPLL0FBCLKLOST; - output QPLL0LOCK; - output QPLL0OUTCLK; - output QPLL0OUTREFCLK; - output QPLL0REFCLKLOST; - output QPLL1FBCLKLOST; - output QPLL1LOCK; - output QPLL1OUTCLK; - output QPLL1OUTREFCLK; - output QPLL1REFCLKLOST; - output [7:0] QPLLDMONITOR0; - output [7:0] QPLLDMONITOR1; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0SEL; - output [1:0] RXRECCLK1SEL; - output [3:0] SDM0FINALOUT; - output [14:0] SDM0TESTDATA; - output [3:0] SDM1FINALOUT; - output [14:0] SDM1TESTDATA; - output [9:0] TCONGPO; - output TCONRSVDOUT0; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input [15:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input GTGREFCLK0; - input GTGREFCLK1; - input GTNORTHREFCLK00; - input GTNORTHREFCLK01; - input GTNORTHREFCLK10; - input GTNORTHREFCLK11; - input GTREFCLK00; - input GTREFCLK01; - input GTREFCLK10; - input GTREFCLK11; - input GTSOUTHREFCLK00; - input GTSOUTHREFCLK01; - input GTSOUTHREFCLK10; - input GTSOUTHREFCLK11; - input [2:0] PCIERATEQPLL0; - input [2:0] PCIERATEQPLL1; - input [7:0] PMARSVD0; - input [7:0] PMARSVD1; - input QPLL0CLKRSVD0; - input QPLL0CLKRSVD1; - input [7:0] QPLL0FBDIV; - input QPLL0LOCKDETCLK; - input QPLL0LOCKEN; - input QPLL0PD; - input [2:0] QPLL0REFCLKSEL; - input QPLL0RESET; - input QPLL1CLKRSVD0; - input QPLL1CLKRSVD1; - input [7:0] QPLL1FBDIV; - input QPLL1LOCKDETCLK; - input QPLL1LOCKEN; - input QPLL1PD; - input [2:0] QPLL1REFCLKSEL; - input QPLL1RESET; - input [7:0] QPLLRSVD1; - input [4:0] QPLLRSVD2; - input [4:0] QPLLRSVD3; - input [7:0] QPLLRSVD4; - input RCALENB; - input [24:0] SDM0DATA; - input SDM0RESET; - input SDM0TOGGLE; - input [1:0] SDM0WIDTH; - input [24:0] SDM1DATA; - input SDM1RESET; - input SDM1TOGGLE; - input [1:0] SDM1WIDTH; - input [9:0] TCONGPI; - input TCONPOWERUP; - input [1:0] TCONRESET; - input [1:0] TCONRSVDIN1; -endmodule - -module GTYE3_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [15:0] ADAPT_CFG0 = 16'h9200; - parameter [15:0] ADAPT_CFG1 = 16'h801C; - parameter [15:0] ADAPT_CFG2 = 16'b0000000000000000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] AUTO_BW_SEL_BYPASS = 1'b0; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [4:0] A_TXDIFFCTRL = 5'b01100; - parameter [0:0] A_TXPROGDIVRESET = 1'b0; - parameter [0:0] CAPBYPASS_FORCE = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter [15:0] CH_HSPMUX = 16'h0000; - parameter [15:0] CKCAL1_CFG_0 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_1 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_0 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_1 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; - parameter [15:0] CKCAL_RSVD0 = 16'h0000; - parameter [15:0] CKCAL_RSVD1 = 16'h0000; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h20F8; - parameter [15:0] CPLL_CFG1 = 16'hA494; - parameter [15:0] CPLL_CFG2 = 16'hF001; - parameter [5:0] CPLL_CFG3 = 6'h00; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 4; - parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [7:0] CPLL_INIT_CFG1 = 8'h00; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; - parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; - parameter [1:0] DDI_CTRL = 2'b00; - parameter integer DDI_REALIGN_WAIT = 15; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DFE_D_X_REL_POS = 1'b0; - parameter [0:0] DFE_VCM_COMP_EN = 1'b0; - parameter [9:0] DMONITOR_CFG0 = 10'h000; - parameter [7:0] DMONITOR_CFG1 = 8'h00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h000; - parameter [9:0] ES_PMA_CFG = 10'b0000000000; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [15:0] ES_QUALIFIER0 = 16'h0000; - parameter [15:0] ES_QUALIFIER1 = 16'h0000; - parameter [15:0] ES_QUALIFIER2 = 16'h0000; - parameter [15:0] ES_QUALIFIER3 = 16'h0000; - parameter [15:0] ES_QUALIFIER4 = 16'h0000; - parameter [15:0] ES_QUALIFIER5 = 16'h0000; - parameter [15:0] ES_QUALIFIER6 = 16'h0000; - parameter [15:0] ES_QUALIFIER7 = 16'h0000; - parameter [15:0] ES_QUALIFIER8 = 16'h0000; - parameter [15:0] ES_QUALIFIER9 = 16'h0000; - parameter [15:0] ES_QUAL_MASK0 = 16'h0000; - parameter [15:0] ES_QUAL_MASK1 = 16'h0000; - parameter [15:0] ES_QUAL_MASK2 = 16'h0000; - parameter [15:0] ES_QUAL_MASK3 = 16'h0000; - parameter [15:0] ES_QUAL_MASK4 = 16'h0000; - parameter [15:0] ES_QUAL_MASK5 = 16'h0000; - parameter [15:0] ES_QUAL_MASK6 = 16'h0000; - parameter [15:0] ES_QUAL_MASK7 = 16'h0000; - parameter [15:0] ES_QUAL_MASK8 = 16'h0000; - parameter [15:0] ES_QUAL_MASK9 = 16'h0000; - parameter [15:0] ES_SDATA_MASK0 = 16'h0000; - parameter [15:0] ES_SDATA_MASK1 = 16'h0000; - parameter [15:0] ES_SDATA_MASK2 = 16'h0000; - parameter [15:0] ES_SDATA_MASK3 = 16'h0000; - parameter [15:0] ES_SDATA_MASK4 = 16'h0000; - parameter [15:0] ES_SDATA_MASK5 = 16'h0000; - parameter [15:0] ES_SDATA_MASK6 = 16'h0000; - parameter [15:0] ES_SDATA_MASK7 = 16'h0000; - parameter [15:0] ES_SDATA_MASK8 = 16'h0000; - parameter [15:0] ES_SDATA_MASK9 = 16'h0000; - parameter [10:0] EVODD_PHI_CFG = 11'b00000000000; - parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] GM_BIAS_SELECT = 1'b0; - parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; - parameter [0:0] LOCAL_MASTER = 1'b0; - parameter [15:0] LOOP0_CFG = 16'h0000; - parameter [15:0] LOOP10_CFG = 16'h0000; - parameter [15:0] LOOP11_CFG = 16'h0000; - parameter [15:0] LOOP12_CFG = 16'h0000; - parameter [15:0] LOOP13_CFG = 16'h0000; - parameter [15:0] LOOP1_CFG = 16'h0000; - parameter [15:0] LOOP2_CFG = 16'h0000; - parameter [15:0] LOOP3_CFG = 16'h0000; - parameter [15:0] LOOP4_CFG = 16'h0000; - parameter [15:0] LOOP5_CFG = 16'h0000; - parameter [15:0] LOOP6_CFG = 16'h0000; - parameter [15:0] LOOP7_CFG = 16'h0000; - parameter [15:0] LOOP8_CFG = 16'h0000; - parameter [15:0] LOOP9_CFG = 16'h0000; - parameter [2:0] LPBK_BIAS_CTRL = 3'b000; - parameter [0:0] LPBK_EN_RCAL_B = 1'b0; - parameter [3:0] LPBK_EXT_RCAL = 4'b0000; - parameter [3:0] LPBK_RG_CTRL = 4'b0000; - parameter [1:0] OOBDIVCTL = 2'b00; - parameter [0:0] OOB_PWRUP = 1'b0; - parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; - parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; - parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; - parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; - parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; - parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; - parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; - parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; - parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; - parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; - parameter PCS_PCIE_EN = "FALSE"; - parameter [15:0] PCS_RSVD0 = 16'b0000000000000000; - parameter [2:0] PCS_RSVD1 = 3'b000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter [1:0] PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PLL_SEL_MODE_GEN3 = 2'h0; - parameter [15:0] PMA_RSV0 = 16'h0000; - parameter [15:0] PMA_RSV1 = 16'h0000; - parameter integer PREIQ_FREQ_BST = 0; - parameter [2:0] PROCESS_PAR = 3'b010; - parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RESET_POWERSAVE_DISABLE = 1'b0; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 0; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b00001; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0000; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG1 = 16'h0300; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0300; - parameter [15:0] RXCDR_CFG2 = 16'h0060; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0060; - parameter [15:0] RXCDR_CFG3 = 16'h0000; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG4 = 16'h0002; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h0002; - parameter [15:0] RXCDR_CFG5 = 16'h0000; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h0000; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0001; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [1:0] RXCFOKDONE_SRC = 2'b00; - parameter [15:0] RXCFOK_CFG0 = 16'h3E00; - parameter [15:0] RXCFOK_CFG1 = 16'h0042; - parameter [15:0] RXCFOK_CFG2 = 16'h002D; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; - parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; - parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; - parameter [15:0] RXDFE_CFG0 = 16'h4C00; - parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h1E00; - parameter [15:0] RXDFE_GC_CFG1 = 16'h1900; - parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; - parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0200; - parameter [0:0] RXDFE_PWR_SAVING = 1'b0; - parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; - parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; - parameter [15:0] RXDLY_CFG = 16'h001F; - parameter [15:0] RXDLY_LCFG = 16'h0030; - parameter RXELECIDLE_CFG = "SIGCFG_4"; - parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h0200; - parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; - parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h0400; - parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; - parameter [8:0] RXOOB_CFG = 9'b000000110; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter integer RXOUT_DIV = 4; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [15:0] RXPHBEACON_CFG = 16'h0000; - parameter [15:0] RXPHDLY_CFG = 16'h2020; - parameter [15:0] RXPHSAMP_CFG = 16'h2100; - parameter [15:0] RXPHSLIP_CFG = 16'h9933; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [0:0] RXPI_AUTO_BW_SEL_BYPASS = 1'b0; - parameter [15:0] RXPI_CFG = 16'h0100; - parameter [0:0] RXPI_LPM = 1'b0; - parameter [15:0] RXPI_RSV0 = 16'h0000; - parameter [1:0] RXPI_SEL_LC = 2'b00; - parameter [1:0] RXPI_STARTCODE = 2'b00; - parameter [0:0] RXPI_VREFSEL = 1'b0; - parameter RXPMACLK_SEL = "DATA"; - parameter [4:0] RXPMARESET_TIME = 5'b00001; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h1534; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; - parameter integer RX_CLK25_DIV = 8; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; - parameter [3:0] RX_CM_BUF_CFG = 4'b1010; - parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter integer RX_CM_SEL = 3; - parameter integer RX_CM_TRIM = 10; - parameter [0:0] RX_CTLE1_KHKL = 1'b0; - parameter [0:0] RX_CTLE2_KHKL = 1'b0; - parameter [0:0] RX_CTLE3_AGC = 1'b0; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [2:0] RX_DEGEN_CTRL = 3'b010; - parameter integer RX_DFELPM_CFG0 = 6; - parameter [0:0] RX_DFELPM_CFG1 = 1'b0; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter [1:0] RX_DFE_AGC_CFG0 = 2'b00; - parameter integer RX_DFE_AGC_CFG1 = 4; - parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 2; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter [2:0] RX_DFE_KL_LPM_KL_CFG1 = 3'b010; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [0:0] RX_DIV2_MODE_B = 1'b0; - parameter [4:0] RX_DIVRESET_TIME = 5'b00001; - parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; - parameter [0:0] RX_EN_HI_LR = 1'b0; - parameter [8:0] RX_EXT_RL_CTRL = 9'b000000000; - parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; - parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; - parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b00; - parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; - parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; - parameter integer RX_INT_DATAWIDTH = 1; - parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter real RX_PROGDIV_CFG = 0.0; - parameter [15:0] RX_PROGDIV_RATE = 16'h0001; - parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; - parameter [0:0] RX_RESLOAD_OVRD = 1'b0; - parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; - parameter integer RX_SIG_VALID_DLY = 11; - parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; - parameter [3:0] RX_SUM_VCMTUNE = 4'b1000; - parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; - parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; - parameter [1:0] RX_TUNE_AFE_OS = 2'b00; - parameter [2:0] RX_VREG_CTRL = 3'b101; - parameter [0:0] RX_VREG_PDB = 1'b1; - parameter [1:0] RX_WIDEMODE_CDR = 2'b01; - parameter RX_XCLK_SEL = "RXDES"; - parameter [0:0] RX_XMODE_SEL = 1'b0; - parameter integer SAS_MAX_COM = 64; - parameter integer SAS_MIN_COM = 36; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter integer SATA_MAX_BURST = 8; - parameter integer SATA_MAX_INIT = 21; - parameter integer SATA_MAX_WAKE = 7; - parameter integer SATA_MIN_BURST = 4; - parameter integer SATA_MIN_INIT = 12; - parameter integer SATA_MIN_WAKE = 4; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_MODE = "FAST"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter [0:0] SIM_TX_EIDLE_DRIVE_LEVEL = 1'b0; - parameter integer SIM_VERSION = 2; - parameter [1:0] TAPDLY_SET_TX = 2'h0; - parameter [3:0] TEMPERATURE_PAR = 4'b0010; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [7:0] TST_RSV0 = 8'h00; - parameter [7:0] TST_RSV1 = 8'h00; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h001F; - parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter TXFIFO_ADDR_CFG = "LOW"; - parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 4; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h2020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0001; - parameter [15:0] TXPH_CFG = 16'h0123; - parameter [15:0] TXPH_CFG2 = 16'h0000; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [1:0] TXPI_CFG0 = 2'b00; - parameter [1:0] TXPI_CFG1 = 2'b00; - parameter [1:0] TXPI_CFG2 = 2'b00; - parameter [0:0] TXPI_CFG3 = 1'b0; - parameter [0:0] TXPI_CFG4 = 1'b1; - parameter [2:0] TXPI_CFG5 = 3'b000; - parameter [0:0] TXPI_GRAY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter [0:0] TXPI_LPM = 1'b0; - parameter TXPI_PPMCLK_SEL = "TXUSRCLK2"; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [15:0] TXPI_RSV0 = 16'h0000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [0:0] TXPI_VREFSEL = 1'b0; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 8; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter [0:0] TX_CLKREG_PDB = 1'b0; - parameter [2:0] TX_CLKREG_SET = 3'b000; - parameter integer TX_DATA_WIDTH = 20; - parameter [5:0] TX_DCD_CFG = 6'b000010; - parameter [0:0] TX_DCD_EN = 1'b0; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [4:0] TX_DIVRESET_TIME = 5'b00001; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter integer TX_DRVMUX_CTRL = 2; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_EML_PHI_TUNE = 1'b0; - parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] TX_FIFO_BYP_EN = 1'b0; - parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; - parameter integer TX_INT_DATAWIDTH = 1; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [2:0] TX_MODE_SEL = 3'b000; - parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; - parameter [15:0] TX_PHICAL_CFG1 = 16'h7E00; - parameter [15:0] TX_PHICAL_CFG2 = 16'h0000; - parameter integer TX_PI_BIASSET = 0; - parameter [15:0] TX_PI_CFG0 = 16'h0000; - parameter [15:0] TX_PI_CFG1 = 16'h0000; - parameter [0:0] TX_PI_DIV2_MODE_B = 1'b0; - parameter [0:0] TX_PI_SEL_QPLL0 = 1'b0; - parameter [0:0] TX_PI_SEL_QPLL1 = 1'b0; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter integer TX_PREDRV_CTRL = 2; - parameter TX_PROGCLK_SEL = "POSTPI"; - parameter real TX_PROGDIV_CFG = 0.0; - parameter [15:0] TX_PROGDIV_RATE = 16'h0001; - parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter integer TX_RXDETECT_REF = 4; - parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; - parameter [0:0] TX_SARC_LPBK_ENB = 1'b0; - parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - output [2:0] BUFGTCE; - output [2:0] BUFGTCEMASK; - output [8:0] BUFGTDIV; - output [2:0] BUFGTRESET; - output [2:0] BUFGTRSTMASK; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output [16:0] DMONITOROUT; - output [15:0] DRPDO; - output DRPRDY; - output EYESCANDATAERROR; - output GTPOWERGOOD; - output GTREFCLKMONITOR; - output GTYTXN; - output GTYTXP; - output PCIERATEGEN3; - output PCIERATEIDLE; - output [1:0] PCIERATEQPLLPD; - output [1:0] PCIERATEQPLLRESET; - output PCIESYNCTXSYNCDONE; - output PCIEUSERGEN3RDY; - output PCIEUSERPHYSTATUSRST; - output PCIEUSERRATESTART; - output [15:0] PCSRSVDOUT; - output PHYSTATUS; - output [7:0] PINRSRVDAS; - output RESETEXCEPTION; - output [2:0] RXBUFSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCDRPHDONE; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output [4:0] RXCHBONDO; - output RXCKCALDONE; - output [1:0] RXCLKCORCNT; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output [15:0] RXCTRL0; - output [15:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [127:0] RXDATA; - output [7:0] RXDATAEXTENDRSVD; - output [1:0] RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output [5:0] RXHEADER; - output [1:0] RXHEADERVALID; - output [6:0] RXMONITOROUT; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPHALIGNERR; - output RXPMARESETDONE; - output RXPRBSERR; - output RXPRBSLOCKED; - output RXPRGDIVRESETDONE; - output RXRATEDONE; - output RXRECCLKOUT; - output RXRESETDONE; - output RXSLIDERDY; - output RXSLIPDONE; - output RXSLIPOUTCLKRDY; - output RXSLIPPMARDY; - output [1:0] RXSTARTOFSEQ; - output [2:0] RXSTATUS; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output [1:0] TXBUFSTATUS; - output TXCOMFINISH; - output TXDCCDONE; - output TXDLYSRESETDONE; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXPRGDIVRESETDONE; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - input CDRSTEPDIR; - input CDRSTEPSQ; - input CDRSTEPSX; - input CFGRESET; - input CLKRSVD0; - input CLKRSVD1; - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input [2:0] CPLLREFCLKSEL; - input CPLLRESET; - input DMONFIFORESET; - input DMONITORCLK; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input ELPCALDVORWREN; - input ELPCALPAORWREN; - input EVODDPHICALDONE; - input EVODDPHICALSTART; - input EVODDPHIDRDEN; - input EVODDPHIDWREN; - input EVODDPHIXRDEN; - input EVODDPHIXWREN; - input EYESCANMODE; - input EYESCANRESET; - input EYESCANTRIGGER; - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input GTRESETSEL; - input [15:0] GTRSVD; - input GTRXRESET; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input GTYRXN; - input GTYRXP; - input [2:0] LOOPBACK; - input [15:0] LOOPRSVD; - input LPBKRXTXSEREN; - input LPBKTXRXSEREN; - input PCIEEQRXEQADAPTDONE; - input PCIERSTIDLE; - input PCIERSTTXSYNCSTART; - input PCIEUSERRATEDONE; - input [15:0] PCSRSVDIN; - input [4:0] PCSRSVDIN2; - input [4:0] PMARSVDIN; - input QPLL0CLK; - input QPLL0REFCLK; - input QPLL1CLK; - input QPLL1REFCLK; - input RESETOVRD; - input RSTCLKENTX; - input RX8B10BEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCDRRESETRSV; - input RXCHBONDEN; - input [4:0] RXCHBONDI; - input [2:0] RXCHBONDLEVEL; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCKCALRESET; - input RXCOMMADETEN; - input RXDCCFORCESTART; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP10HOLD; - input RXDFETAP10OVRDEN; - input RXDFETAP11HOLD; - input RXDFETAP11OVRDEN; - input RXDFETAP12HOLD; - input RXDFETAP12OVRDEN; - input RXDFETAP13HOLD; - input RXDFETAP13OVRDEN; - input RXDFETAP14HOLD; - input RXDFETAP14OVRDEN; - input RXDFETAP15HOLD; - input RXDFETAP15OVRDEN; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFETAP8HOLD; - input RXDFETAP8OVRDEN; - input RXDFETAP9HOLD; - input RXDFETAP9OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEVSEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input [1:0] RXELECIDLEMODE; - input RXGEARBOXSLIP; - input RXLATCLK; - input RXLPMEN; - input RXLPMGCHOLD; - input RXLPMGCOVRDEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXLPMOSHOLD; - input RXLPMOSOVRDEN; - input RXMCOMMAALIGNEN; - input [1:0] RXMONITORSEL; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input [3:0] RXOSINTCFG; - input RXOSINTEN; - input RXOSINTHOLD; - input RXOSINTOVRDEN; - input RXOSINTSTROBE; - input RXOSINTTESTOVRDEN; - input RXOSOVRDEN; - input [2:0] RXOUTCLKSEL; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input [1:0] RXPD; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input RXPHOVRDEN; - input [1:0] RXPLLCLKSEL; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input [3:0] RXPRBSSEL; - input RXPROGDIVRESET; - input [2:0] RXRATE; - input RXRATEMODE; - input RXSLIDE; - input RXSLIPOUTCLK; - input RXSLIPPMA; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input [1:0] RXSYSCLKSEL; - input RXUSERRDY; - input RXUSRCLK; - input RXUSRCLK2; - input SIGVALIDCLK; - input [19:0] TSTIN; - input [7:0] TX8B10BBYPASS; - input TX8B10BEN; - input [2:0] TXBUFDIFFCTRL; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input [15:0] TXCTRL0; - input [15:0] TXCTRL1; - input [7:0] TXCTRL2; - input [127:0] TXDATA; - input [7:0] TXDATAEXTENDRSVD; - input TXDCCFORCESTART; - input TXDCCRESET; - input TXDEEMPH; - input TXDETECTRX; - input [4:0] TXDIFFCTRL; - input TXDIFFPD; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input TXELFORCESTART; - input [5:0] TXHEADER; - input TXINHIBIT; - input TXLATCLK; - input [6:0] TXMAINCURSOR; - input [2:0] TXMARGIN; - input [2:0] TXOUTCLKSEL; - input TXPCSRESET; - input [1:0] TXPD; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input [4:0] TXPIPPMSTEPSIZE; - input TXPISOPD; - input [1:0] TXPLLCLKSEL; - input TXPMARESET; - input TXPOLARITY; - input [4:0] TXPOSTCURSOR; - input TXPRBSFORCEERR; - input [3:0] TXPRBSSEL; - input [4:0] TXPRECURSOR; - input TXPROGDIVRESET; - input [2:0] TXRATE; - input TXRATEMODE; - input [6:0] TXSEQUENCE; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input [1:0] TXSYSCLKSEL; - input TXUSERRDY; - input TXUSRCLK; - input TXUSRCLK2; -endmodule - -module GTYE3_COMMON (...); - parameter [15:0] A_SDM1DATA1_0 = 16'b0000000000000000; - parameter [8:0] A_SDM1DATA1_1 = 9'b000000000; - parameter [15:0] BIAS_CFG0 = 16'h0000; - parameter [15:0] BIAS_CFG1 = 16'h0000; - parameter [15:0] BIAS_CFG2 = 16'h0000; - parameter [15:0] BIAS_CFG3 = 16'h0000; - parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [9:0] BIAS_CFG_RSVD = 10'b0000000000; - parameter [15:0] COMMON_CFG0 = 16'h0000; - parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0004; - parameter [15:0] PPF0_CFG = 16'h0FFF; - parameter [15:0] PPF1_CFG = 16'h0FFF; - parameter QPLL0CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL0_CFG0 = 16'h301C; - parameter [15:0] QPLL0_CFG1 = 16'h0000; - parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0780; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0780; - parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0021; - parameter [9:0] QPLL0_CP = 10'b0000011111; - parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; - parameter integer QPLL0_FBDIV = 66; - parameter integer QPLL0_FBDIV_G3 = 80; - parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL0_LPF = 10'b1111111111; - parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter integer QPLL0_REFCLK_DIV = 2; - parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; - parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; - parameter QPLL1CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL1_CFG0 = 16'h301C; - parameter [15:0] QPLL1_CFG1 = 16'h0000; - parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0780; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0780; - parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0021; - parameter [9:0] QPLL1_CP = 10'b0000011111; - parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; - parameter integer QPLL1_FBDIV = 66; - parameter integer QPLL1_FBDIV_G3 = 80; - parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1111111111; - parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter integer QPLL1_REFCLK_DIV = 2; - parameter [15:0] QPLL1_SDM_CFG0 = 16'h0040; - parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [15:0] RSVD_ATTR2 = 16'h0000; - parameter [15:0] RSVD_ATTR3 = 16'h0000; - parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; - parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_EN = 1'b1; - parameter [0:0] SARC_SEL = 1'b0; - parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; - parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter SIM_MODE = "FAST"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter integer SIM_VERSION = 2; - output [15:0] DRPDO; - output DRPRDY; - output [7:0] PMARSVDOUT0; - output [7:0] PMARSVDOUT1; - output QPLL0FBCLKLOST; - output QPLL0LOCK; - output QPLL0OUTCLK; - output QPLL0OUTREFCLK; - output QPLL0REFCLKLOST; - output QPLL1FBCLKLOST; - output QPLL1LOCK; - output QPLL1OUTCLK; - output QPLL1OUTREFCLK; - output QPLL1REFCLKLOST; - output [7:0] QPLLDMONITOR0; - output [7:0] QPLLDMONITOR1; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0_SEL; - output [1:0] RXRECCLK1_SEL; - output [3:0] SDM0FINALOUT; - output [14:0] SDM0TESTDATA; - output [3:0] SDM1FINALOUT; - output [14:0] SDM1TESTDATA; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input GTGREFCLK0; - input GTGREFCLK1; - input GTNORTHREFCLK00; - input GTNORTHREFCLK01; - input GTNORTHREFCLK10; - input GTNORTHREFCLK11; - input GTREFCLK00; - input GTREFCLK01; - input GTREFCLK10; - input GTREFCLK11; - input GTSOUTHREFCLK00; - input GTSOUTHREFCLK01; - input GTSOUTHREFCLK10; - input GTSOUTHREFCLK11; - input [7:0] PMARSVD0; - input [7:0] PMARSVD1; - input QPLL0CLKRSVD0; - input QPLL0LOCKDETCLK; - input QPLL0LOCKEN; - input QPLL0PD; - input [2:0] QPLL0REFCLKSEL; - input QPLL0RESET; - input QPLL1CLKRSVD0; - input QPLL1LOCKDETCLK; - input QPLL1LOCKEN; - input QPLL1PD; - input [2:0] QPLL1REFCLKSEL; - input QPLL1RESET; - input [7:0] QPLLRSVD1; - input [4:0] QPLLRSVD2; - input [4:0] QPLLRSVD3; - input [7:0] QPLLRSVD4; - input RCALENB; - input [24:0] SDM0DATA; - input SDM0RESET; - input [1:0] SDM0WIDTH; - input [24:0] SDM1DATA; - input SDM1RESET; - input [1:0] SDM1WIDTH; -endmodule - -module GTYE4_CHANNEL (...); - parameter [0:0] ACJTAG_DEBUG_MODE = 1'b0; - parameter [0:0] ACJTAG_MODE = 1'b0; - parameter [0:0] ACJTAG_RESET = 1'b0; - parameter [15:0] ADAPT_CFG0 = 16'h9200; - parameter [15:0] ADAPT_CFG1 = 16'h801C; - parameter [15:0] ADAPT_CFG2 = 16'h0000; - parameter ALIGN_COMMA_DOUBLE = "FALSE"; - parameter [9:0] ALIGN_COMMA_ENABLE = 10'b0001111111; - parameter integer ALIGN_COMMA_WORD = 1; - parameter ALIGN_MCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_MCOMMA_VALUE = 10'b1010000011; - parameter ALIGN_PCOMMA_DET = "TRUE"; - parameter [9:0] ALIGN_PCOMMA_VALUE = 10'b0101111100; - parameter [0:0] A_RXOSCALRESET = 1'b0; - parameter [0:0] A_RXPROGDIVRESET = 1'b0; - parameter [0:0] A_RXTERMINATION = 1'b1; - parameter [4:0] A_TXDIFFCTRL = 5'b01100; - parameter [0:0] A_TXPROGDIVRESET = 1'b0; - parameter CBCC_DATA_SOURCE_SEL = "DECODED"; - parameter [0:0] CDR_SWAP_MODE_EN = 1'b0; - parameter [0:0] CFOK_PWRSVE_EN = 1'b1; - parameter CHAN_BOND_KEEP_ALIGN = "FALSE"; - parameter integer CHAN_BOND_MAX_SKEW = 7; - parameter [9:0] CHAN_BOND_SEQ_1_1 = 10'b0101111100; - parameter [9:0] CHAN_BOND_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CHAN_BOND_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CHAN_BOND_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CHAN_BOND_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CHAN_BOND_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CHAN_BOND_SEQ_2_ENABLE = 4'b1111; - parameter CHAN_BOND_SEQ_2_USE = "FALSE"; - parameter integer CHAN_BOND_SEQ_LEN = 2; - parameter [15:0] CH_HSPMUX = 16'h2424; - parameter [15:0] CKCAL1_CFG_0 = 16'b1100000011000000; - parameter [15:0] CKCAL1_CFG_1 = 16'b0101000011000000; - parameter [15:0] CKCAL1_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL1_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_0 = 16'b1100000011000000; - parameter [15:0] CKCAL2_CFG_1 = 16'b1000000011000000; - parameter [15:0] CKCAL2_CFG_2 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_3 = 16'b0000000000000000; - parameter [15:0] CKCAL2_CFG_4 = 16'b0000000000000000; - parameter CLK_CORRECT_USE = "TRUE"; - parameter CLK_COR_KEEP_IDLE = "FALSE"; - parameter integer CLK_COR_MAX_LAT = 20; - parameter integer CLK_COR_MIN_LAT = 18; - parameter CLK_COR_PRECEDENCE = "TRUE"; - parameter integer CLK_COR_REPEAT_WAIT = 0; - parameter [9:0] CLK_COR_SEQ_1_1 = 10'b0100011100; - parameter [9:0] CLK_COR_SEQ_1_2 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_3 = 10'b0000000000; - parameter [9:0] CLK_COR_SEQ_1_4 = 10'b0000000000; - parameter [3:0] CLK_COR_SEQ_1_ENABLE = 4'b1111; - parameter [9:0] CLK_COR_SEQ_2_1 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_2 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_3 = 10'b0100000000; - parameter [9:0] CLK_COR_SEQ_2_4 = 10'b0100000000; - parameter [3:0] CLK_COR_SEQ_2_ENABLE = 4'b1111; - parameter CLK_COR_SEQ_2_USE = "FALSE"; - parameter integer CLK_COR_SEQ_LEN = 2; - parameter [15:0] CPLL_CFG0 = 16'h01FA; - parameter [15:0] CPLL_CFG1 = 16'h24A9; - parameter [15:0] CPLL_CFG2 = 16'h6807; - parameter [15:0] CPLL_CFG3 = 16'h0000; - parameter integer CPLL_FBDIV = 4; - parameter integer CPLL_FBDIV_45 = 4; - parameter [15:0] CPLL_INIT_CFG0 = 16'h001E; - parameter [15:0] CPLL_LOCK_CFG = 16'h01E8; - parameter integer CPLL_REFCLK_DIV = 1; - parameter [2:0] CTLE3_OCAP_EXT_CTRL = 3'b000; - parameter [0:0] CTLE3_OCAP_EXT_EN = 1'b0; - parameter [1:0] DDI_CTRL = 2'b00; - parameter integer DDI_REALIGN_WAIT = 15; - parameter DEC_MCOMMA_DETECT = "TRUE"; - parameter DEC_PCOMMA_DETECT = "TRUE"; - parameter DEC_VALID_COMMA_ONLY = "TRUE"; - parameter [0:0] DELAY_ELEC = 1'b0; - parameter [9:0] DMONITOR_CFG0 = 10'h000; - parameter [7:0] DMONITOR_CFG1 = 8'h00; - parameter [0:0] ES_CLK_PHASE_SEL = 1'b0; - parameter [5:0] ES_CONTROL = 6'b000000; - parameter ES_ERRDET_EN = "FALSE"; - parameter ES_EYE_SCAN_EN = "FALSE"; - parameter [11:0] ES_HORZ_OFFSET = 12'h800; - parameter [4:0] ES_PRESCALE = 5'b00000; - parameter [15:0] ES_QUALIFIER0 = 16'h0000; - parameter [15:0] ES_QUALIFIER1 = 16'h0000; - parameter [15:0] ES_QUALIFIER2 = 16'h0000; - parameter [15:0] ES_QUALIFIER3 = 16'h0000; - parameter [15:0] ES_QUALIFIER4 = 16'h0000; - parameter [15:0] ES_QUALIFIER5 = 16'h0000; - parameter [15:0] ES_QUALIFIER6 = 16'h0000; - parameter [15:0] ES_QUALIFIER7 = 16'h0000; - parameter [15:0] ES_QUALIFIER8 = 16'h0000; - parameter [15:0] ES_QUALIFIER9 = 16'h0000; - parameter [15:0] ES_QUAL_MASK0 = 16'h0000; - parameter [15:0] ES_QUAL_MASK1 = 16'h0000; - parameter [15:0] ES_QUAL_MASK2 = 16'h0000; - parameter [15:0] ES_QUAL_MASK3 = 16'h0000; - parameter [15:0] ES_QUAL_MASK4 = 16'h0000; - parameter [15:0] ES_QUAL_MASK5 = 16'h0000; - parameter [15:0] ES_QUAL_MASK6 = 16'h0000; - parameter [15:0] ES_QUAL_MASK7 = 16'h0000; - parameter [15:0] ES_QUAL_MASK8 = 16'h0000; - parameter [15:0] ES_QUAL_MASK9 = 16'h0000; - parameter [15:0] ES_SDATA_MASK0 = 16'h0000; - parameter [15:0] ES_SDATA_MASK1 = 16'h0000; - parameter [15:0] ES_SDATA_MASK2 = 16'h0000; - parameter [15:0] ES_SDATA_MASK3 = 16'h0000; - parameter [15:0] ES_SDATA_MASK4 = 16'h0000; - parameter [15:0] ES_SDATA_MASK5 = 16'h0000; - parameter [15:0] ES_SDATA_MASK6 = 16'h0000; - parameter [15:0] ES_SDATA_MASK7 = 16'h0000; - parameter [15:0] ES_SDATA_MASK8 = 16'h0000; - parameter [15:0] ES_SDATA_MASK9 = 16'h0000; - parameter integer EYESCAN_VP_RANGE = 0; - parameter [0:0] EYE_SCAN_SWAP_EN = 1'b0; - parameter [3:0] FTS_DESKEW_SEQ_ENABLE = 4'b1111; - parameter [3:0] FTS_LANE_DESKEW_CFG = 4'b1111; - parameter FTS_LANE_DESKEW_EN = "FALSE"; - parameter [4:0] GEARBOX_MODE = 5'b00000; - parameter [0:0] ISCAN_CK_PH_SEL2 = 1'b0; - parameter [0:0] LOCAL_MASTER = 1'b0; - parameter integer LPBK_BIAS_CTRL = 4; - parameter [0:0] LPBK_EN_RCAL_B = 1'b0; - parameter [3:0] LPBK_EXT_RCAL = 4'b0000; - parameter integer LPBK_IND_CTRL0 = 5; - parameter integer LPBK_IND_CTRL1 = 5; - parameter integer LPBK_IND_CTRL2 = 5; - parameter integer LPBK_RG_CTRL = 2; - parameter [1:0] OOBDIVCTL = 2'b00; - parameter [0:0] OOB_PWRUP = 1'b0; - parameter PCI3_AUTO_REALIGN = "FRST_SMPL"; - parameter [0:0] PCI3_PIPE_RX_ELECIDLE = 1'b1; - parameter [1:0] PCI3_RX_ASYNC_EBUF_BYPASS = 2'b00; - parameter [0:0] PCI3_RX_ELECIDLE_EI2_ENABLE = 1'b0; - parameter [5:0] PCI3_RX_ELECIDLE_H2L_COUNT = 6'b000000; - parameter [2:0] PCI3_RX_ELECIDLE_H2L_DISABLE = 3'b000; - parameter [5:0] PCI3_RX_ELECIDLE_HI_COUNT = 6'b000000; - parameter [0:0] PCI3_RX_ELECIDLE_LP4_DISABLE = 1'b0; - parameter [0:0] PCI3_RX_FIFO_DISABLE = 1'b0; - parameter [4:0] PCIE3_CLK_COR_EMPTY_THRSH = 5'b00000; - parameter [5:0] PCIE3_CLK_COR_FULL_THRSH = 6'b010000; - parameter [4:0] PCIE3_CLK_COR_MAX_LAT = 5'b01000; - parameter [4:0] PCIE3_CLK_COR_MIN_LAT = 5'b00100; - parameter [5:0] PCIE3_CLK_COR_THRSH_TIMER = 6'b001000; - parameter PCIE_64B_DYN_CLKSW_DIS = "FALSE"; - parameter [15:0] PCIE_BUFG_DIV_CTRL = 16'h0000; - parameter PCIE_GEN4_64BIT_INT_EN = "FALSE"; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN12 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN3 = 2'h0; - parameter [1:0] PCIE_PLL_SEL_MODE_GEN4 = 2'h0; - parameter [15:0] PCIE_RXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_RXPMA_CFG = 16'h0000; - parameter [15:0] PCIE_TXPCS_CFG_GEN3 = 16'h0000; - parameter [15:0] PCIE_TXPMA_CFG = 16'h0000; - parameter PCS_PCIE_EN = "FALSE"; - parameter [15:0] PCS_RSVD0 = 16'h0000; - parameter [11:0] PD_TRANS_TIME_FROM_P2 = 12'h03C; - parameter [7:0] PD_TRANS_TIME_NONE_P2 = 8'h19; - parameter [7:0] PD_TRANS_TIME_TO_P2 = 8'h64; - parameter integer PREIQ_FREQ_BST = 0; - parameter [0:0] RATE_SW_USE_DRP = 1'b0; - parameter [0:0] RCLK_SIPO_DLY_ENB = 1'b0; - parameter [0:0] RCLK_SIPO_INV_EN = 1'b0; - parameter [2:0] RTX_BUF_CML_CTRL = 3'b010; - parameter [1:0] RTX_BUF_TERM_CTRL = 2'b00; - parameter [4:0] RXBUFRESET_TIME = 5'b00001; - parameter RXBUF_ADDR_MODE = "FULL"; - parameter [3:0] RXBUF_EIDLE_HI_CNT = 4'b1000; - parameter [3:0] RXBUF_EIDLE_LO_CNT = 4'b0000; - parameter RXBUF_EN = "TRUE"; - parameter RXBUF_RESET_ON_CB_CHANGE = "TRUE"; - parameter RXBUF_RESET_ON_COMMAALIGN = "FALSE"; - parameter RXBUF_RESET_ON_EIDLE = "FALSE"; - parameter RXBUF_RESET_ON_RATE_CHANGE = "TRUE"; - parameter integer RXBUF_THRESH_OVFLW = 0; - parameter RXBUF_THRESH_OVRD = "FALSE"; - parameter integer RXBUF_THRESH_UNDFLW = 4; - parameter [4:0] RXCDRFREQRESET_TIME = 5'b10000; - parameter [4:0] RXCDRPHRESET_TIME = 5'b00001; - parameter [15:0] RXCDR_CFG0 = 16'h0003; - parameter [15:0] RXCDR_CFG0_GEN3 = 16'h0003; - parameter [15:0] RXCDR_CFG1 = 16'h0000; - parameter [15:0] RXCDR_CFG1_GEN3 = 16'h0000; - parameter [15:0] RXCDR_CFG2 = 16'h0164; - parameter [9:0] RXCDR_CFG2_GEN2 = 10'h164; - parameter [15:0] RXCDR_CFG2_GEN3 = 16'h0034; - parameter [15:0] RXCDR_CFG2_GEN4 = 16'h0034; - parameter [15:0] RXCDR_CFG3 = 16'h0024; - parameter [5:0] RXCDR_CFG3_GEN2 = 6'h24; - parameter [15:0] RXCDR_CFG3_GEN3 = 16'h0024; - parameter [15:0] RXCDR_CFG3_GEN4 = 16'h0024; - parameter [15:0] RXCDR_CFG4 = 16'h5CF6; - parameter [15:0] RXCDR_CFG4_GEN3 = 16'h5CF6; - parameter [15:0] RXCDR_CFG5 = 16'hB46B; - parameter [15:0] RXCDR_CFG5_GEN3 = 16'h146B; - parameter [0:0] RXCDR_FR_RESET_ON_EIDLE = 1'b0; - parameter [0:0] RXCDR_HOLD_DURING_EIDLE = 1'b0; - parameter [15:0] RXCDR_LOCK_CFG0 = 16'h0040; - parameter [15:0] RXCDR_LOCK_CFG1 = 16'h8000; - parameter [15:0] RXCDR_LOCK_CFG2 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG3 = 16'h0000; - parameter [15:0] RXCDR_LOCK_CFG4 = 16'h0000; - parameter [0:0] RXCDR_PH_RESET_ON_EIDLE = 1'b0; - parameter [15:0] RXCFOK_CFG0 = 16'h0000; - parameter [15:0] RXCFOK_CFG1 = 16'h0002; - parameter [15:0] RXCFOK_CFG2 = 16'h002D; - parameter [15:0] RXCKCAL1_IQ_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_I_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL1_Q_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_DX_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_D_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_S_LOOP_RST_CFG = 16'h0000; - parameter [15:0] RXCKCAL2_X_LOOP_RST_CFG = 16'h0000; - parameter [6:0] RXDFELPMRESET_TIME = 7'b0001111; - parameter [15:0] RXDFELPM_KL_CFG0 = 16'h0000; - parameter [15:0] RXDFELPM_KL_CFG1 = 16'h0022; - parameter [15:0] RXDFELPM_KL_CFG2 = 16'h0100; - parameter [15:0] RXDFE_CFG0 = 16'h4000; - parameter [15:0] RXDFE_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG1 = 16'h0000; - parameter [15:0] RXDFE_GC_CFG2 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H2_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H3_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H3_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H4_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H4_CFG1 = 16'h0003; - parameter [15:0] RXDFE_H5_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H5_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H6_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H6_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H7_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H7_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H8_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H8_CFG1 = 16'h0002; - parameter [15:0] RXDFE_H9_CFG0 = 16'h0000; - parameter [15:0] RXDFE_H9_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HA_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HA_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HB_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HB_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HC_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HC_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HD_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HD_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HE_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HE_CFG1 = 16'h0002; - parameter [15:0] RXDFE_HF_CFG0 = 16'h0000; - parameter [15:0] RXDFE_HF_CFG1 = 16'h0002; - parameter [15:0] RXDFE_KH_CFG0 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG1 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG2 = 16'h0000; - parameter [15:0] RXDFE_KH_CFG3 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG0 = 16'h0000; - parameter [15:0] RXDFE_OS_CFG1 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG0 = 16'h0000; - parameter [15:0] RXDFE_UT_CFG1 = 16'h0002; - parameter [15:0] RXDFE_UT_CFG2 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG0 = 16'h0000; - parameter [15:0] RXDFE_VP_CFG1 = 16'h0022; - parameter [15:0] RXDLY_CFG = 16'h0010; - parameter [15:0] RXDLY_LCFG = 16'h0030; - parameter RXELECIDLE_CFG = "SIGCFG_4"; - parameter integer RXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter RXGEARBOX_EN = "FALSE"; - parameter [4:0] RXISCANRESET_TIME = 5'b00001; - parameter [15:0] RXLPM_CFG = 16'h0000; - parameter [15:0] RXLPM_GC_CFG = 16'h1000; - parameter [15:0] RXLPM_KH_CFG0 = 16'h0000; - parameter [15:0] RXLPM_KH_CFG1 = 16'h0002; - parameter [15:0] RXLPM_OS_CFG0 = 16'h0000; - parameter [15:0] RXLPM_OS_CFG1 = 16'h0000; - parameter [8:0] RXOOB_CFG = 9'b000110000; - parameter RXOOB_CLK_CFG = "PMA"; - parameter [4:0] RXOSCALRESET_TIME = 5'b00011; - parameter integer RXOUT_DIV = 4; - parameter [4:0] RXPCSRESET_TIME = 5'b00001; - parameter [15:0] RXPHBEACON_CFG = 16'h0000; - parameter [15:0] RXPHDLY_CFG = 16'h2020; - parameter [15:0] RXPHSAMP_CFG = 16'h2100; - parameter [15:0] RXPHSLIP_CFG = 16'h9933; - parameter [4:0] RXPH_MONITOR_SEL = 5'b00000; - parameter [15:0] RXPI_CFG0 = 16'h0102; - parameter [15:0] RXPI_CFG1 = 16'b0000000001010100; - parameter RXPMACLK_SEL = "DATA"; - parameter [4:0] RXPMARESET_TIME = 5'b00001; - parameter [0:0] RXPRBS_ERR_LOOPBACK = 1'b0; - parameter integer RXPRBS_LINKACQ_CNT = 15; - parameter [0:0] RXREFCLKDIV2_SEL = 1'b0; - parameter integer RXSLIDE_AUTO_WAIT = 7; - parameter RXSLIDE_MODE = "OFF"; - parameter [0:0] RXSYNC_MULTILANE = 1'b0; - parameter [0:0] RXSYNC_OVRD = 1'b0; - parameter [0:0] RXSYNC_SKIP_DA = 1'b0; - parameter [0:0] RX_AFE_CM_EN = 1'b0; - parameter [15:0] RX_BIAS_CFG0 = 16'h12B0; - parameter [5:0] RX_BUFFER_CFG = 6'b000000; - parameter [0:0] RX_CAPFF_SARC_ENB = 1'b0; - parameter integer RX_CLK25_DIV = 8; - parameter [0:0] RX_CLKMUX_EN = 1'b1; - parameter [4:0] RX_CLK_SLIP_OVRD = 5'b00000; - parameter [3:0] RX_CM_BUF_CFG = 4'b1010; - parameter [0:0] RX_CM_BUF_PD = 1'b0; - parameter integer RX_CM_SEL = 3; - parameter integer RX_CM_TRIM = 12; - parameter [0:0] RX_CTLE_PWR_SAVING = 1'b0; - parameter [3:0] RX_CTLE_RES_CTRL = 4'b0000; - parameter integer RX_DATA_WIDTH = 20; - parameter [5:0] RX_DDI_SEL = 6'b000000; - parameter RX_DEFER_RESET_BUF_EN = "TRUE"; - parameter [2:0] RX_DEGEN_CTRL = 3'b100; - parameter integer RX_DFELPM_CFG0 = 0; - parameter [0:0] RX_DFELPM_CFG1 = 1'b1; - parameter [0:0] RX_DFELPM_KLKH_AGC_STUP_EN = 1'b1; - parameter integer RX_DFE_AGC_CFG1 = 4; - parameter integer RX_DFE_KL_LPM_KH_CFG0 = 1; - parameter integer RX_DFE_KL_LPM_KH_CFG1 = 4; - parameter [1:0] RX_DFE_KL_LPM_KL_CFG0 = 2'b01; - parameter integer RX_DFE_KL_LPM_KL_CFG1 = 4; - parameter [0:0] RX_DFE_LPM_HOLD_DURING_EIDLE = 1'b0; - parameter RX_DISPERR_SEQ_MATCH = "TRUE"; - parameter [4:0] RX_DIVRESET_TIME = 5'b00001; - parameter [0:0] RX_EN_CTLE_RCAL_B = 1'b0; - parameter integer RX_EN_SUM_RCAL_B = 0; - parameter [6:0] RX_EYESCAN_VS_CODE = 7'b0000000; - parameter [0:0] RX_EYESCAN_VS_NEG_DIR = 1'b0; - parameter [1:0] RX_EYESCAN_VS_RANGE = 2'b10; - parameter [0:0] RX_EYESCAN_VS_UT_SIGN = 1'b0; - parameter [0:0] RX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] RX_I2V_FILTER_EN = 1'b1; - parameter integer RX_INT_DATAWIDTH = 1; - parameter [0:0] RX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] RX_PMA_RSV0 = 16'h000F; - parameter real RX_PROGDIV_CFG = 0.0; - parameter [15:0] RX_PROGDIV_RATE = 16'h0001; - parameter [3:0] RX_RESLOAD_CTRL = 4'b0000; - parameter [0:0] RX_RESLOAD_OVRD = 1'b0; - parameter [2:0] RX_SAMPLE_PERIOD = 3'b101; - parameter integer RX_SIG_VALID_DLY = 11; - parameter integer RX_SUM_DEGEN_AVTT_OVERITE = 0; - parameter [0:0] RX_SUM_DFETAPREP_EN = 1'b0; - parameter [3:0] RX_SUM_IREF_TUNE = 4'b0000; - parameter integer RX_SUM_PWR_SAVING = 0; - parameter [3:0] RX_SUM_RES_CTRL = 4'b0000; - parameter [3:0] RX_SUM_VCMTUNE = 4'b0011; - parameter [0:0] RX_SUM_VCM_BIAS_TUNE_EN = 1'b1; - parameter [0:0] RX_SUM_VCM_OVWR = 1'b0; - parameter [2:0] RX_SUM_VREF_TUNE = 3'b100; - parameter [1:0] RX_TUNE_AFE_OS = 2'b00; - parameter [2:0] RX_VREG_CTRL = 3'b010; - parameter [0:0] RX_VREG_PDB = 1'b1; - parameter [1:0] RX_WIDEMODE_CDR = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN3 = 2'b01; - parameter [1:0] RX_WIDEMODE_CDR_GEN4 = 2'b01; - parameter RX_XCLK_SEL = "RXDES"; - parameter [0:0] RX_XMODE_SEL = 1'b0; - parameter [0:0] SAMPLE_CLK_PHASE = 1'b0; - parameter [0:0] SAS_12G_MODE = 1'b0; - parameter [3:0] SATA_BURST_SEQ_LEN = 4'b1111; - parameter [2:0] SATA_BURST_VAL = 3'b100; - parameter SATA_CPLL_CFG = "VCO_3000MHZ"; - parameter [2:0] SATA_EIDLE_VAL = 3'b100; - parameter SHOW_REALIGN_COMMA = "TRUE"; - parameter SIM_MODE = "FAST"; - parameter SIM_RECEIVER_DETECT_PASS = "TRUE"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_TX_EIDLE_DRIVE_LEVEL = "Z"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter [0:0] SRSTMODE = 1'b0; - parameter [1:0] TAPDLY_SET_TX = 2'h0; - parameter [14:0] TERM_RCAL_CFG = 15'b100001000010000; - parameter [2:0] TERM_RCAL_OVRD = 3'b000; - parameter [7:0] TRANS_TIME_RATE = 8'h0E; - parameter [7:0] TST_RSV0 = 8'h00; - parameter [7:0] TST_RSV1 = 8'h00; - parameter TXBUF_EN = "TRUE"; - parameter TXBUF_RESET_ON_RATE_CHANGE = "FALSE"; - parameter [15:0] TXDLY_CFG = 16'h0010; - parameter [15:0] TXDLY_LCFG = 16'h0030; - parameter integer TXDRV_FREQBAND = 0; - parameter [15:0] TXFE_CFG0 = 16'b0000000000000000; - parameter [15:0] TXFE_CFG1 = 16'b0000000000000000; - parameter [15:0] TXFE_CFG2 = 16'b0000000000000000; - parameter [15:0] TXFE_CFG3 = 16'b0000000000000000; - parameter TXFIFO_ADDR_CFG = "LOW"; - parameter integer TXGBOX_FIFO_INIT_RD_ADDR = 4; - parameter TXGEARBOX_EN = "FALSE"; - parameter integer TXOUT_DIV = 4; - parameter [4:0] TXPCSRESET_TIME = 5'b00001; - parameter [15:0] TXPHDLY_CFG0 = 16'h6020; - parameter [15:0] TXPHDLY_CFG1 = 16'h0002; - parameter [15:0] TXPH_CFG = 16'h0123; - parameter [15:0] TXPH_CFG2 = 16'h0000; - parameter [4:0] TXPH_MONITOR_SEL = 5'b00000; - parameter [15:0] TXPI_CFG0 = 16'b0000000100000000; - parameter [15:0] TXPI_CFG1 = 16'b0000000000000000; - parameter [0:0] TXPI_GRAY_SEL = 1'b0; - parameter [0:0] TXPI_INVSTROBE_SEL = 1'b0; - parameter [0:0] TXPI_PPM = 1'b0; - parameter [7:0] TXPI_PPM_CFG = 8'b00000000; - parameter [2:0] TXPI_SYNFREQ_PPM = 3'b000; - parameter [4:0] TXPMARESET_TIME = 5'b00001; - parameter [0:0] TXREFCLKDIV2_SEL = 1'b0; - parameter integer TXSWBST_BST = 1; - parameter integer TXSWBST_EN = 0; - parameter integer TXSWBST_MAG = 6; - parameter [0:0] TXSYNC_MULTILANE = 1'b0; - parameter [0:0] TXSYNC_OVRD = 1'b0; - parameter [0:0] TXSYNC_SKIP_DA = 1'b0; - parameter integer TX_CLK25_DIV = 8; - parameter [0:0] TX_CLKMUX_EN = 1'b1; - parameter integer TX_DATA_WIDTH = 20; - parameter [15:0] TX_DCC_LOOP_RST_CFG = 16'h0000; - parameter [5:0] TX_DEEMPH0 = 6'b000000; - parameter [5:0] TX_DEEMPH1 = 6'b000000; - parameter [5:0] TX_DEEMPH2 = 6'b000000; - parameter [5:0] TX_DEEMPH3 = 6'b000000; - parameter [4:0] TX_DIVRESET_TIME = 5'b00001; - parameter TX_DRIVE_MODE = "DIRECT"; - parameter [2:0] TX_EIDLE_ASSERT_DELAY = 3'b110; - parameter [2:0] TX_EIDLE_DEASSERT_DELAY = 3'b100; - parameter [0:0] TX_FABINT_USRCLK_FLOP = 1'b0; - parameter [0:0] TX_FIFO_BYP_EN = 1'b0; - parameter [0:0] TX_IDLE_DATA_ZERO = 1'b0; - parameter integer TX_INT_DATAWIDTH = 1; - parameter TX_LOOPBACK_DRIVE_HIZ = "FALSE"; - parameter [0:0] TX_MAINCURSOR_SEL = 1'b0; - parameter [6:0] TX_MARGIN_FULL_0 = 7'b1001110; - parameter [6:0] TX_MARGIN_FULL_1 = 7'b1001001; - parameter [6:0] TX_MARGIN_FULL_2 = 7'b1000101; - parameter [6:0] TX_MARGIN_FULL_3 = 7'b1000010; - parameter [6:0] TX_MARGIN_FULL_4 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_0 = 7'b1000110; - parameter [6:0] TX_MARGIN_LOW_1 = 7'b1000100; - parameter [6:0] TX_MARGIN_LOW_2 = 7'b1000010; - parameter [6:0] TX_MARGIN_LOW_3 = 7'b1000000; - parameter [6:0] TX_MARGIN_LOW_4 = 7'b1000000; - parameter [15:0] TX_PHICAL_CFG0 = 16'h0000; - parameter [15:0] TX_PHICAL_CFG1 = 16'h003F; - parameter integer TX_PI_BIASSET = 0; - parameter [0:0] TX_PMADATA_OPT = 1'b0; - parameter [0:0] TX_PMA_POWER_SAVE = 1'b0; - parameter [15:0] TX_PMA_RSV0 = 16'h0000; - parameter [15:0] TX_PMA_RSV1 = 16'h0000; - parameter TX_PROGCLK_SEL = "POSTPI"; - parameter real TX_PROGDIV_CFG = 0.0; - parameter [15:0] TX_PROGDIV_RATE = 16'h0001; - parameter [13:0] TX_RXDETECT_CFG = 14'h0032; - parameter integer TX_RXDETECT_REF = 3; - parameter [2:0] TX_SAMPLE_PERIOD = 3'b101; - parameter [1:0] TX_SW_MEAS = 2'b00; - parameter [2:0] TX_VREG_CTRL = 3'b000; - parameter [0:0] TX_VREG_PDB = 1'b0; - parameter [1:0] TX_VREG_VREFSEL = 2'b00; - parameter TX_XCLK_SEL = "TXOUT"; - parameter [0:0] USB_BOTH_BURST_IDLE = 1'b0; - parameter [6:0] USB_BURSTMAX_U3WAKE = 7'b1111111; - parameter [6:0] USB_BURSTMIN_U3WAKE = 7'b1100011; - parameter [0:0] USB_CLK_COR_EQ_EN = 1'b0; - parameter [0:0] USB_EXT_CNTL = 1'b1; - parameter [9:0] USB_IDLEMAX_POLLING = 10'b1010111011; - parameter [9:0] USB_IDLEMIN_POLLING = 10'b0100101011; - parameter [8:0] USB_LFPSPING_BURST = 9'b000000101; - parameter [8:0] USB_LFPSPOLLING_BURST = 9'b000110001; - parameter [8:0] USB_LFPSPOLLING_IDLE_MS = 9'b000000100; - parameter [8:0] USB_LFPSU1EXIT_BURST = 9'b000011101; - parameter [8:0] USB_LFPSU2LPEXIT_BURST_MS = 9'b001100011; - parameter [8:0] USB_LFPSU3WAKE_BURST_MS = 9'b111110011; - parameter [3:0] USB_LFPS_TPERIOD = 4'b0011; - parameter [0:0] USB_LFPS_TPERIOD_ACCURATE = 1'b1; - parameter [0:0] USB_MODE = 1'b0; - parameter [0:0] USB_PCIE_ERR_REP_DIS = 1'b0; - parameter integer USB_PING_SATA_MAX_INIT = 21; - parameter integer USB_PING_SATA_MIN_INIT = 12; - parameter integer USB_POLL_SATA_MAX_BURST = 8; - parameter integer USB_POLL_SATA_MIN_BURST = 4; - parameter [0:0] USB_RAW_ELEC = 1'b0; - parameter [0:0] USB_RXIDLE_P0_CTRL = 1'b1; - parameter [0:0] USB_TXIDLE_TUNE_ENABLE = 1'b1; - parameter integer USB_U1_SATA_MAX_WAKE = 7; - parameter integer USB_U1_SATA_MIN_WAKE = 4; - parameter integer USB_U2_SAS_MAX_COM = 64; - parameter integer USB_U2_SAS_MIN_COM = 36; - parameter [0:0] USE_PCS_CLK_PHASE_SEL = 1'b0; - parameter [0:0] Y_ALL_MODE = 1'b0; - output BUFGTCE; - output [2:0] BUFGTCEMASK; - output [8:0] BUFGTDIV; - output BUFGTRESET; - output [2:0] BUFGTRSTMASK; - output CPLLFBCLKLOST; - output CPLLLOCK; - output CPLLREFCLKLOST; - output [15:0] DMONITOROUT; - output DMONITOROUTCLK; - output [15:0] DRPDO; - output DRPRDY; - output EYESCANDATAERROR; - output GTPOWERGOOD; - output GTREFCLKMONITOR; - output GTYTXN; - output GTYTXP; - output PCIERATEGEN3; - output PCIERATEIDLE; - output [1:0] PCIERATEQPLLPD; - output [1:0] PCIERATEQPLLRESET; - output PCIESYNCTXSYNCDONE; - output PCIEUSERGEN3RDY; - output PCIEUSERPHYSTATUSRST; - output PCIEUSERRATESTART; - output [15:0] PCSRSVDOUT; - output PHYSTATUS; - output [15:0] PINRSRVDAS; - output POWERPRESENT; - output RESETEXCEPTION; - output [2:0] RXBUFSTATUS; - output RXBYTEISALIGNED; - output RXBYTEREALIGN; - output RXCDRLOCK; - output RXCDRPHDONE; - output RXCHANBONDSEQ; - output RXCHANISALIGNED; - output RXCHANREALIGN; - output [4:0] RXCHBONDO; - output RXCKCALDONE; - output [1:0] RXCLKCORCNT; - output RXCOMINITDET; - output RXCOMMADET; - output RXCOMSASDET; - output RXCOMWAKEDET; - output [15:0] RXCTRL0; - output [15:0] RXCTRL1; - output [7:0] RXCTRL2; - output [7:0] RXCTRL3; - output [127:0] RXDATA; - output [7:0] RXDATAEXTENDRSVD; - output [1:0] RXDATAVALID; - output RXDLYSRESETDONE; - output RXELECIDLE; - output [5:0] RXHEADER; - output [1:0] RXHEADERVALID; - output RXLFPSTRESETDET; - output RXLFPSU2LPEXITDET; - output RXLFPSU3WAKEDET; - output [7:0] RXMONITOROUT; - output RXOSINTDONE; - output RXOSINTSTARTED; - output RXOSINTSTROBEDONE; - output RXOSINTSTROBESTARTED; - output RXOUTCLK; - output RXOUTCLKFABRIC; - output RXOUTCLKPCS; - output RXPHALIGNDONE; - output RXPHALIGNERR; - output RXPMARESETDONE; - output RXPRBSERR; - output RXPRBSLOCKED; - output RXPRGDIVRESETDONE; - output RXRATEDONE; - output RXRECCLKOUT; - output RXRESETDONE; - output RXSLIDERDY; - output RXSLIPDONE; - output RXSLIPOUTCLKRDY; - output RXSLIPPMARDY; - output [1:0] RXSTARTOFSEQ; - output [2:0] RXSTATUS; - output RXSYNCDONE; - output RXSYNCOUT; - output RXVALID; - output [1:0] TXBUFSTATUS; - output TXCOMFINISH; - output TXDCCDONE; - output TXDLYSRESETDONE; - output TXOUTCLK; - output TXOUTCLKFABRIC; - output TXOUTCLKPCS; - output TXPHALIGNDONE; - output TXPHINITDONE; - output TXPMARESETDONE; - output TXPRGDIVRESETDONE; - output TXRATEDONE; - output TXRESETDONE; - output TXSYNCDONE; - output TXSYNCOUT; - input CDRSTEPDIR; - input CDRSTEPSQ; - input CDRSTEPSX; - input CFGRESET; - input CLKRSVD0; - input CLKRSVD1; - input CPLLFREQLOCK; - input CPLLLOCKDETCLK; - input CPLLLOCKEN; - input CPLLPD; - input [2:0] CPLLREFCLKSEL; - input CPLLRESET; - input DMONFIFORESET; - input DMONITORCLK; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPRST; - input DRPWE; - input EYESCANRESET; - input EYESCANTRIGGER; - input FREQOS; - input GTGREFCLK; - input GTNORTHREFCLK0; - input GTNORTHREFCLK1; - input GTREFCLK0; - input GTREFCLK1; - input [15:0] GTRSVD; - input GTRXRESET; - input GTRXRESETSEL; - input GTSOUTHREFCLK0; - input GTSOUTHREFCLK1; - input GTTXRESET; - input GTTXRESETSEL; - input GTYRXN; - input GTYRXP; - input INCPCTRL; - input [2:0] LOOPBACK; - input PCIEEQRXEQADAPTDONE; - input PCIERSTIDLE; - input PCIERSTTXSYNCSTART; - input PCIEUSERRATEDONE; - input [15:0] PCSRSVDIN; - input QPLL0CLK; - input QPLL0FREQLOCK; - input QPLL0REFCLK; - input QPLL1CLK; - input QPLL1FREQLOCK; - input QPLL1REFCLK; - input RESETOVRD; - input RX8B10BEN; - input RXAFECFOKEN; - input RXBUFRESET; - input RXCDRFREQRESET; - input RXCDRHOLD; - input RXCDROVRDEN; - input RXCDRRESET; - input RXCHBONDEN; - input [4:0] RXCHBONDI; - input [2:0] RXCHBONDLEVEL; - input RXCHBONDMASTER; - input RXCHBONDSLAVE; - input RXCKCALRESET; - input [6:0] RXCKCALSTART; - input RXCOMMADETEN; - input RXDFEAGCHOLD; - input RXDFEAGCOVRDEN; - input [3:0] RXDFECFOKFCNUM; - input RXDFECFOKFEN; - input RXDFECFOKFPULSE; - input RXDFECFOKHOLD; - input RXDFECFOKOVREN; - input RXDFEKHHOLD; - input RXDFEKHOVRDEN; - input RXDFELFHOLD; - input RXDFELFOVRDEN; - input RXDFELPMRESET; - input RXDFETAP10HOLD; - input RXDFETAP10OVRDEN; - input RXDFETAP11HOLD; - input RXDFETAP11OVRDEN; - input RXDFETAP12HOLD; - input RXDFETAP12OVRDEN; - input RXDFETAP13HOLD; - input RXDFETAP13OVRDEN; - input RXDFETAP14HOLD; - input RXDFETAP14OVRDEN; - input RXDFETAP15HOLD; - input RXDFETAP15OVRDEN; - input RXDFETAP2HOLD; - input RXDFETAP2OVRDEN; - input RXDFETAP3HOLD; - input RXDFETAP3OVRDEN; - input RXDFETAP4HOLD; - input RXDFETAP4OVRDEN; - input RXDFETAP5HOLD; - input RXDFETAP5OVRDEN; - input RXDFETAP6HOLD; - input RXDFETAP6OVRDEN; - input RXDFETAP7HOLD; - input RXDFETAP7OVRDEN; - input RXDFETAP8HOLD; - input RXDFETAP8OVRDEN; - input RXDFETAP9HOLD; - input RXDFETAP9OVRDEN; - input RXDFEUTHOLD; - input RXDFEUTOVRDEN; - input RXDFEVPHOLD; - input RXDFEVPOVRDEN; - input RXDFEXYDEN; - input RXDLYBYPASS; - input RXDLYEN; - input RXDLYOVRDEN; - input RXDLYSRESET; - input [1:0] RXELECIDLEMODE; - input RXEQTRAINING; - input RXGEARBOXSLIP; - input RXLATCLK; - input RXLPMEN; - input RXLPMGCHOLD; - input RXLPMGCOVRDEN; - input RXLPMHFHOLD; - input RXLPMHFOVRDEN; - input RXLPMLFHOLD; - input RXLPMLFKLOVRDEN; - input RXLPMOSHOLD; - input RXLPMOSOVRDEN; - input RXMCOMMAALIGNEN; - input [1:0] RXMONITORSEL; - input RXOOBRESET; - input RXOSCALRESET; - input RXOSHOLD; - input RXOSOVRDEN; - input [2:0] RXOUTCLKSEL; - input RXPCOMMAALIGNEN; - input RXPCSRESET; - input [1:0] RXPD; - input RXPHALIGN; - input RXPHALIGNEN; - input RXPHDLYPD; - input RXPHDLYRESET; - input [1:0] RXPLLCLKSEL; - input RXPMARESET; - input RXPOLARITY; - input RXPRBSCNTRESET; - input [3:0] RXPRBSSEL; - input RXPROGDIVRESET; - input [2:0] RXRATE; - input RXRATEMODE; - input RXSLIDE; - input RXSLIPOUTCLK; - input RXSLIPPMA; - input RXSYNCALLIN; - input RXSYNCIN; - input RXSYNCMODE; - input [1:0] RXSYSCLKSEL; - input RXTERMINATION; - input RXUSERRDY; - input RXUSRCLK; - input RXUSRCLK2; - input SIGVALIDCLK; - input [19:0] TSTIN; - input [7:0] TX8B10BBYPASS; - input TX8B10BEN; - input TXCOMINIT; - input TXCOMSAS; - input TXCOMWAKE; - input [15:0] TXCTRL0; - input [15:0] TXCTRL1; - input [7:0] TXCTRL2; - input [127:0] TXDATA; - input [7:0] TXDATAEXTENDRSVD; - input TXDCCFORCESTART; - input TXDCCRESET; - input [1:0] TXDEEMPH; - input TXDETECTRX; - input [4:0] TXDIFFCTRL; - input TXDLYBYPASS; - input TXDLYEN; - input TXDLYHOLD; - input TXDLYOVRDEN; - input TXDLYSRESET; - input TXDLYUPDOWN; - input TXELECIDLE; - input [5:0] TXHEADER; - input TXINHIBIT; - input TXLATCLK; - input TXLFPSTRESET; - input TXLFPSU2LPEXIT; - input TXLFPSU3WAKE; - input [6:0] TXMAINCURSOR; - input [2:0] TXMARGIN; - input TXMUXDCDEXHOLD; - input TXMUXDCDORWREN; - input TXONESZEROS; - input [2:0] TXOUTCLKSEL; - input TXPCSRESET; - input [1:0] TXPD; - input TXPDELECIDLEMODE; - input TXPHALIGN; - input TXPHALIGNEN; - input TXPHDLYPD; - input TXPHDLYRESET; - input TXPHDLYTSTCLK; - input TXPHINIT; - input TXPHOVRDEN; - input TXPIPPMEN; - input TXPIPPMOVRDEN; - input TXPIPPMPD; - input TXPIPPMSEL; - input [4:0] TXPIPPMSTEPSIZE; - input TXPISOPD; - input [1:0] TXPLLCLKSEL; - input TXPMARESET; - input TXPOLARITY; - input [4:0] TXPOSTCURSOR; - input TXPRBSFORCEERR; - input [3:0] TXPRBSSEL; - input [4:0] TXPRECURSOR; - input TXPROGDIVRESET; - input [2:0] TXRATE; - input TXRATEMODE; - input [6:0] TXSEQUENCE; - input TXSWING; - input TXSYNCALLIN; - input TXSYNCIN; - input TXSYNCMODE; - input [1:0] TXSYSCLKSEL; - input TXUSERRDY; - input TXUSRCLK; - input TXUSRCLK2; -endmodule - -module GTYE4_COMMON (...); - parameter [0:0] AEN_QPLL0_FBDIV = 1'b1; - parameter [0:0] AEN_QPLL1_FBDIV = 1'b1; - parameter [0:0] AEN_SDM0TOGGLE = 1'b0; - parameter [0:0] AEN_SDM1TOGGLE = 1'b0; - parameter [0:0] A_SDM0TOGGLE = 1'b0; - parameter [8:0] A_SDM1DATA_HIGH = 9'b000000000; - parameter [15:0] A_SDM1DATA_LOW = 16'b0000000000000000; - parameter [0:0] A_SDM1TOGGLE = 1'b0; - parameter [15:0] BIAS_CFG0 = 16'h0000; - parameter [15:0] BIAS_CFG1 = 16'h0000; - parameter [15:0] BIAS_CFG2 = 16'h0000; - parameter [15:0] BIAS_CFG3 = 16'h0000; - parameter [15:0] BIAS_CFG4 = 16'h0000; - parameter [15:0] BIAS_CFG_RSVD = 16'h0000; - parameter [15:0] COMMON_CFG0 = 16'h0000; - parameter [15:0] COMMON_CFG1 = 16'h0000; - parameter [15:0] POR_CFG = 16'h0000; - parameter [15:0] PPF0_CFG = 16'h0F00; - parameter [15:0] PPF1_CFG = 16'h0F00; - parameter QPLL0CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL0_CFG0 = 16'h391C; - parameter [15:0] QPLL0_CFG1 = 16'h0000; - parameter [15:0] QPLL0_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL0_CFG2 = 16'h0F80; - parameter [15:0] QPLL0_CFG2_G3 = 16'h0F80; - parameter [15:0] QPLL0_CFG3 = 16'h0120; - parameter [15:0] QPLL0_CFG4 = 16'h0002; - parameter [9:0] QPLL0_CP = 10'b0000011111; - parameter [9:0] QPLL0_CP_G3 = 10'b0000011111; - parameter integer QPLL0_FBDIV = 66; - parameter integer QPLL0_FBDIV_G3 = 80; - parameter [15:0] QPLL0_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL0_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL0_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL0_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL0_LPF = 10'b1011111111; - parameter [9:0] QPLL0_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL0_PCI_EN = 1'b0; - parameter [0:0] QPLL0_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL0_REFCLK_DIV = 1; - parameter [15:0] QPLL0_SDM_CFG0 = 16'h0040; - parameter [15:0] QPLL0_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL0_SDM_CFG2 = 16'h0000; - parameter QPLL1CLKOUT_RATE = "FULL"; - parameter [15:0] QPLL1_CFG0 = 16'h691C; - parameter [15:0] QPLL1_CFG1 = 16'h0020; - parameter [15:0] QPLL1_CFG1_G3 = 16'h0020; - parameter [15:0] QPLL1_CFG2 = 16'h0F80; - parameter [15:0] QPLL1_CFG2_G3 = 16'h0F80; - parameter [15:0] QPLL1_CFG3 = 16'h0120; - parameter [15:0] QPLL1_CFG4 = 16'h0002; - parameter [9:0] QPLL1_CP = 10'b0000011111; - parameter [9:0] QPLL1_CP_G3 = 10'b0000011111; - parameter integer QPLL1_FBDIV = 66; - parameter integer QPLL1_FBDIV_G3 = 80; - parameter [15:0] QPLL1_INIT_CFG0 = 16'h0000; - parameter [7:0] QPLL1_INIT_CFG1 = 8'h00; - parameter [15:0] QPLL1_LOCK_CFG = 16'h01E8; - parameter [15:0] QPLL1_LOCK_CFG_G3 = 16'h21E8; - parameter [9:0] QPLL1_LPF = 10'b1011111111; - parameter [9:0] QPLL1_LPF_G3 = 10'b1111111111; - parameter [0:0] QPLL1_PCI_EN = 1'b0; - parameter [0:0] QPLL1_RATE_SW_USE_DRP = 1'b0; - parameter integer QPLL1_REFCLK_DIV = 1; - parameter [15:0] QPLL1_SDM_CFG0 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG1 = 16'h0000; - parameter [15:0] QPLL1_SDM_CFG2 = 16'h0000; - parameter [15:0] RSVD_ATTR0 = 16'h0000; - parameter [15:0] RSVD_ATTR1 = 16'h0000; - parameter [15:0] RSVD_ATTR2 = 16'h0000; - parameter [15:0] RSVD_ATTR3 = 16'h0000; - parameter [1:0] RXRECCLKOUT0_SEL = 2'b00; - parameter [1:0] RXRECCLKOUT1_SEL = 2'b00; - parameter [0:0] SARC_ENB = 1'b0; - parameter [0:0] SARC_SEL = 1'b0; - parameter [15:0] SDM0INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM0INITSEED0_1 = 9'b000000000; - parameter [15:0] SDM1INITSEED0_0 = 16'b0000000000000000; - parameter [8:0] SDM1INITSEED0_1 = 9'b000000000; - parameter SIM_MODE = "FAST"; - parameter SIM_RESET_SPEEDUP = "TRUE"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter [15:0] UB_CFG0 = 16'h0000; - parameter [15:0] UB_CFG1 = 16'h0000; - parameter [15:0] UB_CFG2 = 16'h0000; - parameter [15:0] UB_CFG3 = 16'h0000; - parameter [15:0] UB_CFG4 = 16'h0000; - parameter [15:0] UB_CFG5 = 16'h0400; - parameter [15:0] UB_CFG6 = 16'h0000; - output [15:0] DRPDO; - output DRPRDY; - output [7:0] PMARSVDOUT0; - output [7:0] PMARSVDOUT1; - output QPLL0FBCLKLOST; - output QPLL0LOCK; - output QPLL0OUTCLK; - output QPLL0OUTREFCLK; - output QPLL0REFCLKLOST; - output QPLL1FBCLKLOST; - output QPLL1LOCK; - output QPLL1OUTCLK; - output QPLL1OUTREFCLK; - output QPLL1REFCLKLOST; - output [7:0] QPLLDMONITOR0; - output [7:0] QPLLDMONITOR1; - output REFCLKOUTMONITOR0; - output REFCLKOUTMONITOR1; - output [1:0] RXRECCLK0SEL; - output [1:0] RXRECCLK1SEL; - output [3:0] SDM0FINALOUT; - output [14:0] SDM0TESTDATA; - output [3:0] SDM1FINALOUT; - output [14:0] SDM1TESTDATA; - output [15:0] UBDADDR; - output UBDEN; - output [15:0] UBDI; - output UBDWE; - output UBMDMTDO; - output UBRSVDOUT; - output UBTXUART; - input BGBYPASSB; - input BGMONITORENB; - input BGPDB; - input [4:0] BGRCALOVRD; - input BGRCALOVRDENB; - input [15:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input GTGREFCLK0; - input GTGREFCLK1; - input GTNORTHREFCLK00; - input GTNORTHREFCLK01; - input GTNORTHREFCLK10; - input GTNORTHREFCLK11; - input GTREFCLK00; - input GTREFCLK01; - input GTREFCLK10; - input GTREFCLK11; - input GTSOUTHREFCLK00; - input GTSOUTHREFCLK01; - input GTSOUTHREFCLK10; - input GTSOUTHREFCLK11; - input [2:0] PCIERATEQPLL0; - input [2:0] PCIERATEQPLL1; - input [7:0] PMARSVD0; - input [7:0] PMARSVD1; - input QPLL0CLKRSVD0; - input QPLL0CLKRSVD1; - input [7:0] QPLL0FBDIV; - input QPLL0LOCKDETCLK; - input QPLL0LOCKEN; - input QPLL0PD; - input [2:0] QPLL0REFCLKSEL; - input QPLL0RESET; - input QPLL1CLKRSVD0; - input QPLL1CLKRSVD1; - input [7:0] QPLL1FBDIV; - input QPLL1LOCKDETCLK; - input QPLL1LOCKEN; - input QPLL1PD; - input [2:0] QPLL1REFCLKSEL; - input QPLL1RESET; - input [7:0] QPLLRSVD1; - input [4:0] QPLLRSVD2; - input [4:0] QPLLRSVD3; - input [7:0] QPLLRSVD4; - input RCALENB; - input [24:0] SDM0DATA; - input SDM0RESET; - input SDM0TOGGLE; - input [1:0] SDM0WIDTH; - input [24:0] SDM1DATA; - input SDM1RESET; - input SDM1TOGGLE; - input [1:0] SDM1WIDTH; - input UBCFGSTREAMEN; - input [15:0] UBDO; - input UBDRDY; - input UBENABLE; - input [1:0] UBGPI; - input [1:0] UBINTR; - input UBIOLMBRST; - input UBMBRST; - input UBMDMCAPTURE; - input UBMDMDBGRST; - input UBMDMDBGUPDATE; - input [3:0] UBMDMREGEN; - input UBMDMSHIFT; - input UBMDMSYSRST; - input UBMDMTCK; - input UBMDMTDI; -endmodule - -module IBUFDS_GTE3 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; - parameter [1:0] REFCLK_ICNTL_RX = 2'b00; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_GTE4 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [1:0] REFCLK_HROW_CK_SEL = 2'b00; - parameter [1:0] REFCLK_ICNTL_RX = 2'b00; - output O; - output ODIV2; - input CEB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module ILKN (...); - parameter BYPASS = "FALSE"; - parameter [1:0] CTL_RX_BURSTMAX = 2'h3; - parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; - parameter [3:0] CTL_RX_LAST_LANE = 4'hB; - parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF; - parameter CTL_RX_PACKET_MODE = "TRUE"; - parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0; - parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2; - parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0000; - parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0008; - parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000; - parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00; - parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; - parameter [1:0] CTL_TX_BURSTMAX = 2'h3; - parameter [2:0] CTL_TX_BURSTSHORT = 3'h1; - parameter [1:0] CTL_TX_CHAN_EXT = 2'h0; - parameter CTL_TX_DISABLE_SKIPWORD = "TRUE"; - parameter [6:0] CTL_TX_FC_CALLEN = 7'h00; - parameter [3:0] CTL_TX_LAST_LANE = 4'hB; - parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF; - parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800; - parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0; - parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3; - parameter MODE = "TRUE"; - parameter SIM_VERSION = "2.0"; - parameter TEST_MODE_PIN_CHAR = "FALSE"; - output [15:0] DRP_DO; - output DRP_RDY; - output [65:0] RX_BYPASS_DATAOUT00; - output [65:0] RX_BYPASS_DATAOUT01; - output [65:0] RX_BYPASS_DATAOUT02; - output [65:0] RX_BYPASS_DATAOUT03; - output [65:0] RX_BYPASS_DATAOUT04; - output [65:0] RX_BYPASS_DATAOUT05; - output [65:0] RX_BYPASS_DATAOUT06; - output [65:0] RX_BYPASS_DATAOUT07; - output [65:0] RX_BYPASS_DATAOUT08; - output [65:0] RX_BYPASS_DATAOUT09; - output [65:0] RX_BYPASS_DATAOUT10; - output [65:0] RX_BYPASS_DATAOUT11; - output [11:0] RX_BYPASS_ENAOUT; - output [11:0] RX_BYPASS_IS_AVAILOUT; - output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT; - output [11:0] RX_BYPASS_IS_OVERFLOWOUT; - output [11:0] RX_BYPASS_IS_SYNCEDOUT; - output [11:0] RX_BYPASS_IS_SYNCWORDOUT; - output [10:0] RX_CHANOUT0; - output [10:0] RX_CHANOUT1; - output [10:0] RX_CHANOUT2; - output [10:0] RX_CHANOUT3; - output [127:0] RX_DATAOUT0; - output [127:0] RX_DATAOUT1; - output [127:0] RX_DATAOUT2; - output [127:0] RX_DATAOUT3; - output RX_ENAOUT0; - output RX_ENAOUT1; - output RX_ENAOUT2; - output RX_ENAOUT3; - output RX_EOPOUT0; - output RX_EOPOUT1; - output RX_EOPOUT2; - output RX_EOPOUT3; - output RX_ERROUT0; - output RX_ERROUT1; - output RX_ERROUT2; - output RX_ERROUT3; - output [3:0] RX_MTYOUT0; - output [3:0] RX_MTYOUT1; - output [3:0] RX_MTYOUT2; - output [3:0] RX_MTYOUT3; - output RX_OVFOUT; - output RX_SOPOUT0; - output RX_SOPOUT1; - output RX_SOPOUT2; - output RX_SOPOUT3; - output STAT_RX_ALIGNED; - output STAT_RX_ALIGNED_ERR; - output [11:0] STAT_RX_BAD_TYPE_ERR; - output STAT_RX_BURSTMAX_ERR; - output STAT_RX_BURST_ERR; - output STAT_RX_CRC24_ERR; - output [11:0] STAT_RX_CRC32_ERR; - output [11:0] STAT_RX_CRC32_VALID; - output [11:0] STAT_RX_DESCRAM_ERR; - output [11:0] STAT_RX_DIAGWORD_INTFSTAT; - output [11:0] STAT_RX_DIAGWORD_LANESTAT; - output [255:0] STAT_RX_FC_STAT; - output [11:0] STAT_RX_FRAMING_ERR; - output STAT_RX_MEOP_ERR; - output [11:0] STAT_RX_MF_ERR; - output [11:0] STAT_RX_MF_LEN_ERR; - output [11:0] STAT_RX_MF_REPEAT_ERR; - output STAT_RX_MISALIGNED; - output STAT_RX_MSOP_ERR; - output [7:0] STAT_RX_MUBITS; - output STAT_RX_MUBITS_UPDATED; - output STAT_RX_OVERFLOW_ERR; - output STAT_RX_RETRANS_CRC24_ERR; - output STAT_RX_RETRANS_DISC; - output [15:0] STAT_RX_RETRANS_LATENCY; - output STAT_RX_RETRANS_REQ; - output STAT_RX_RETRANS_RETRY_ERR; - output [7:0] STAT_RX_RETRANS_SEQ; - output STAT_RX_RETRANS_SEQ_UPDATED; - output [2:0] STAT_RX_RETRANS_STATE; - output [4:0] STAT_RX_RETRANS_SUBSEQ; - output STAT_RX_RETRANS_WDOG_ERR; - output STAT_RX_RETRANS_WRAP_ERR; - output [11:0] STAT_RX_SYNCED; - output [11:0] STAT_RX_SYNCED_ERR; - output [11:0] STAT_RX_WORD_SYNC; - output STAT_TX_BURST_ERR; - output STAT_TX_ERRINJ_BITERR_DONE; - output STAT_TX_OVERFLOW_ERR; - output STAT_TX_RETRANS_BURST_ERR; - output STAT_TX_RETRANS_BUSY; - output STAT_TX_RETRANS_RAM_PERROUT; - output [8:0] STAT_TX_RETRANS_RAM_RADDR; - output STAT_TX_RETRANS_RAM_RD_B0; - output STAT_TX_RETRANS_RAM_RD_B1; - output STAT_TX_RETRANS_RAM_RD_B2; - output STAT_TX_RETRANS_RAM_RD_B3; - output [1:0] STAT_TX_RETRANS_RAM_RSEL; - output [8:0] STAT_TX_RETRANS_RAM_WADDR; - output [643:0] STAT_TX_RETRANS_RAM_WDATA; - output STAT_TX_RETRANS_RAM_WE_B0; - output STAT_TX_RETRANS_RAM_WE_B1; - output STAT_TX_RETRANS_RAM_WE_B2; - output STAT_TX_RETRANS_RAM_WE_B3; - output STAT_TX_UNDERFLOW_ERR; - output TX_OVFOUT; - output TX_RDYOUT; - output [63:0] TX_SERDES_DATA00; - output [63:0] TX_SERDES_DATA01; - output [63:0] TX_SERDES_DATA02; - output [63:0] TX_SERDES_DATA03; - output [63:0] TX_SERDES_DATA04; - output [63:0] TX_SERDES_DATA05; - output [63:0] TX_SERDES_DATA06; - output [63:0] TX_SERDES_DATA07; - output [63:0] TX_SERDES_DATA08; - output [63:0] TX_SERDES_DATA09; - output [63:0] TX_SERDES_DATA10; - output [63:0] TX_SERDES_DATA11; - input CORE_CLK; - input CTL_RX_FORCE_RESYNC; - input CTL_RX_RETRANS_ACK; - input CTL_RX_RETRANS_ENABLE; - input CTL_RX_RETRANS_ERRIN; - input CTL_RX_RETRANS_FORCE_REQ; - input CTL_RX_RETRANS_RESET; - input CTL_RX_RETRANS_RESET_MODE; - input CTL_TX_DIAGWORD_INTFSTAT; - input [11:0] CTL_TX_DIAGWORD_LANESTAT; - input CTL_TX_ENABLE; - input CTL_TX_ERRINJ_BITERR_GO; - input [3:0] CTL_TX_ERRINJ_BITERR_LANE; - input [255:0] CTL_TX_FC_STAT; - input [7:0] CTL_TX_MUBITS; - input CTL_TX_RETRANS_ENABLE; - input CTL_TX_RETRANS_RAM_PERRIN; - input [643:0] CTL_TX_RETRANS_RAM_RDATA; - input CTL_TX_RETRANS_REQ; - input CTL_TX_RETRANS_REQ_VALID; - input [11:0] CTL_TX_RLIM_DELTA; - input CTL_TX_RLIM_ENABLE; - input [7:0] CTL_TX_RLIM_INTV; - input [11:0] CTL_TX_RLIM_MAX; - input [9:0] DRP_ADDR; - input DRP_CLK; - input [15:0] DRP_DI; - input DRP_EN; - input DRP_WE; - input LBUS_CLK; - input RX_BYPASS_FORCE_REALIGNIN; - input RX_BYPASS_RDIN; - input RX_RESET; - input [11:0] RX_SERDES_CLK; - input [63:0] RX_SERDES_DATA00; - input [63:0] RX_SERDES_DATA01; - input [63:0] RX_SERDES_DATA02; - input [63:0] RX_SERDES_DATA03; - input [63:0] RX_SERDES_DATA04; - input [63:0] RX_SERDES_DATA05; - input [63:0] RX_SERDES_DATA06; - input [63:0] RX_SERDES_DATA07; - input [63:0] RX_SERDES_DATA08; - input [63:0] RX_SERDES_DATA09; - input [63:0] RX_SERDES_DATA10; - input [63:0] RX_SERDES_DATA11; - input [11:0] RX_SERDES_RESET; - input TX_BCTLIN0; - input TX_BCTLIN1; - input TX_BCTLIN2; - input TX_BCTLIN3; - input [11:0] TX_BYPASS_CTRLIN; - input [63:0] TX_BYPASS_DATAIN00; - input [63:0] TX_BYPASS_DATAIN01; - input [63:0] TX_BYPASS_DATAIN02; - input [63:0] TX_BYPASS_DATAIN03; - input [63:0] TX_BYPASS_DATAIN04; - input [63:0] TX_BYPASS_DATAIN05; - input [63:0] TX_BYPASS_DATAIN06; - input [63:0] TX_BYPASS_DATAIN07; - input [63:0] TX_BYPASS_DATAIN08; - input [63:0] TX_BYPASS_DATAIN09; - input [63:0] TX_BYPASS_DATAIN10; - input [63:0] TX_BYPASS_DATAIN11; - input TX_BYPASS_ENAIN; - input [7:0] TX_BYPASS_GEARBOX_SEQIN; - input [3:0] TX_BYPASS_MFRAMER_STATEIN; - input [10:0] TX_CHANIN0; - input [10:0] TX_CHANIN1; - input [10:0] TX_CHANIN2; - input [10:0] TX_CHANIN3; - input [127:0] TX_DATAIN0; - input [127:0] TX_DATAIN1; - input [127:0] TX_DATAIN2; - input [127:0] TX_DATAIN3; - input TX_ENAIN0; - input TX_ENAIN1; - input TX_ENAIN2; - input TX_ENAIN3; - input TX_EOPIN0; - input TX_EOPIN1; - input TX_EOPIN2; - input TX_EOPIN3; - input TX_ERRIN0; - input TX_ERRIN1; - input TX_ERRIN2; - input TX_ERRIN3; - input [3:0] TX_MTYIN0; - input [3:0] TX_MTYIN1; - input [3:0] TX_MTYIN2; - input [3:0] TX_MTYIN3; - input TX_RESET; - input TX_SERDES_REFCLK; - input TX_SERDES_REFCLK_RESET; - input TX_SOPIN0; - input TX_SOPIN1; - input TX_SOPIN2; - input TX_SOPIN3; -endmodule - -module ILKNE4 (...); - parameter BYPASS = "FALSE"; - parameter [1:0] CTL_RX_BURSTMAX = 2'h3; - parameter [1:0] CTL_RX_CHAN_EXT = 2'h0; - parameter [3:0] CTL_RX_LAST_LANE = 4'hB; - parameter [15:0] CTL_RX_MFRAMELEN_MINUS1 = 16'h07FF; - parameter CTL_RX_PACKET_MODE = "FALSE"; - parameter [2:0] CTL_RX_RETRANS_MULT = 3'h0; - parameter [3:0] CTL_RX_RETRANS_RETRY = 4'h2; - parameter [15:0] CTL_RX_RETRANS_TIMER1 = 16'h0009; - parameter [15:0] CTL_RX_RETRANS_TIMER2 = 16'h0000; - parameter [11:0] CTL_RX_RETRANS_WDOG = 12'h000; - parameter [7:0] CTL_RX_RETRANS_WRAP_TIMER = 8'h00; - parameter CTL_TEST_MODE_PIN_CHAR = "FALSE"; - parameter [1:0] CTL_TX_BURSTMAX = 2'h3; - parameter [2:0] CTL_TX_BURSTSHORT = 3'h1; - parameter [1:0] CTL_TX_CHAN_EXT = 2'h0; - parameter CTL_TX_DISABLE_SKIPWORD = "FALSE"; - parameter [3:0] CTL_TX_FC_CALLEN = 4'hF; - parameter [3:0] CTL_TX_LAST_LANE = 4'hB; - parameter [15:0] CTL_TX_MFRAMELEN_MINUS1 = 16'h07FF; - parameter [13:0] CTL_TX_RETRANS_DEPTH = 14'h0800; - parameter [2:0] CTL_TX_RETRANS_MULT = 3'h0; - parameter [1:0] CTL_TX_RETRANS_RAM_BANKS = 2'h3; - parameter MODE = "TRUE"; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter TEST_MODE_PIN_CHAR = "FALSE"; - output [15:0] DRP_DO; - output DRP_RDY; - output [65:0] RX_BYPASS_DATAOUT00; - output [65:0] RX_BYPASS_DATAOUT01; - output [65:0] RX_BYPASS_DATAOUT02; - output [65:0] RX_BYPASS_DATAOUT03; - output [65:0] RX_BYPASS_DATAOUT04; - output [65:0] RX_BYPASS_DATAOUT05; - output [65:0] RX_BYPASS_DATAOUT06; - output [65:0] RX_BYPASS_DATAOUT07; - output [65:0] RX_BYPASS_DATAOUT08; - output [65:0] RX_BYPASS_DATAOUT09; - output [65:0] RX_BYPASS_DATAOUT10; - output [65:0] RX_BYPASS_DATAOUT11; - output [11:0] RX_BYPASS_ENAOUT; - output [11:0] RX_BYPASS_IS_AVAILOUT; - output [11:0] RX_BYPASS_IS_BADLYFRAMEDOUT; - output [11:0] RX_BYPASS_IS_OVERFLOWOUT; - output [11:0] RX_BYPASS_IS_SYNCEDOUT; - output [11:0] RX_BYPASS_IS_SYNCWORDOUT; - output [10:0] RX_CHANOUT0; - output [10:0] RX_CHANOUT1; - output [10:0] RX_CHANOUT2; - output [10:0] RX_CHANOUT3; - output [127:0] RX_DATAOUT0; - output [127:0] RX_DATAOUT1; - output [127:0] RX_DATAOUT2; - output [127:0] RX_DATAOUT3; - output RX_ENAOUT0; - output RX_ENAOUT1; - output RX_ENAOUT2; - output RX_ENAOUT3; - output RX_EOPOUT0; - output RX_EOPOUT1; - output RX_EOPOUT2; - output RX_EOPOUT3; - output RX_ERROUT0; - output RX_ERROUT1; - output RX_ERROUT2; - output RX_ERROUT3; - output [3:0] RX_MTYOUT0; - output [3:0] RX_MTYOUT1; - output [3:0] RX_MTYOUT2; - output [3:0] RX_MTYOUT3; - output RX_OVFOUT; - output RX_SOPOUT0; - output RX_SOPOUT1; - output RX_SOPOUT2; - output RX_SOPOUT3; - output STAT_RX_ALIGNED; - output STAT_RX_ALIGNED_ERR; - output [11:0] STAT_RX_BAD_TYPE_ERR; - output STAT_RX_BURSTMAX_ERR; - output STAT_RX_BURST_ERR; - output STAT_RX_CRC24_ERR; - output [11:0] STAT_RX_CRC32_ERR; - output [11:0] STAT_RX_CRC32_VALID; - output [11:0] STAT_RX_DESCRAM_ERR; - output [11:0] STAT_RX_DIAGWORD_INTFSTAT; - output [11:0] STAT_RX_DIAGWORD_LANESTAT; - output [255:0] STAT_RX_FC_STAT; - output [11:0] STAT_RX_FRAMING_ERR; - output STAT_RX_MEOP_ERR; - output [11:0] STAT_RX_MF_ERR; - output [11:0] STAT_RX_MF_LEN_ERR; - output [11:0] STAT_RX_MF_REPEAT_ERR; - output STAT_RX_MISALIGNED; - output STAT_RX_MSOP_ERR; - output [7:0] STAT_RX_MUBITS; - output STAT_RX_MUBITS_UPDATED; - output STAT_RX_OVERFLOW_ERR; - output STAT_RX_RETRANS_CRC24_ERR; - output STAT_RX_RETRANS_DISC; - output [15:0] STAT_RX_RETRANS_LATENCY; - output STAT_RX_RETRANS_REQ; - output STAT_RX_RETRANS_RETRY_ERR; - output [7:0] STAT_RX_RETRANS_SEQ; - output STAT_RX_RETRANS_SEQ_UPDATED; - output [2:0] STAT_RX_RETRANS_STATE; - output [4:0] STAT_RX_RETRANS_SUBSEQ; - output STAT_RX_RETRANS_WDOG_ERR; - output STAT_RX_RETRANS_WRAP_ERR; - output [11:0] STAT_RX_SYNCED; - output [11:0] STAT_RX_SYNCED_ERR; - output [11:0] STAT_RX_WORD_SYNC; - output STAT_TX_BURST_ERR; - output STAT_TX_ERRINJ_BITERR_DONE; - output STAT_TX_OVERFLOW_ERR; - output STAT_TX_RETRANS_BURST_ERR; - output STAT_TX_RETRANS_BUSY; - output STAT_TX_RETRANS_RAM_PERROUT; - output [8:0] STAT_TX_RETRANS_RAM_RADDR; - output STAT_TX_RETRANS_RAM_RD_B0; - output STAT_TX_RETRANS_RAM_RD_B1; - output STAT_TX_RETRANS_RAM_RD_B2; - output STAT_TX_RETRANS_RAM_RD_B3; - output [1:0] STAT_TX_RETRANS_RAM_RSEL; - output [8:0] STAT_TX_RETRANS_RAM_WADDR; - output [643:0] STAT_TX_RETRANS_RAM_WDATA; - output STAT_TX_RETRANS_RAM_WE_B0; - output STAT_TX_RETRANS_RAM_WE_B1; - output STAT_TX_RETRANS_RAM_WE_B2; - output STAT_TX_RETRANS_RAM_WE_B3; - output STAT_TX_UNDERFLOW_ERR; - output TX_OVFOUT; - output TX_RDYOUT; - output [63:0] TX_SERDES_DATA00; - output [63:0] TX_SERDES_DATA01; - output [63:0] TX_SERDES_DATA02; - output [63:0] TX_SERDES_DATA03; - output [63:0] TX_SERDES_DATA04; - output [63:0] TX_SERDES_DATA05; - output [63:0] TX_SERDES_DATA06; - output [63:0] TX_SERDES_DATA07; - output [63:0] TX_SERDES_DATA08; - output [63:0] TX_SERDES_DATA09; - output [63:0] TX_SERDES_DATA10; - output [63:0] TX_SERDES_DATA11; - input CORE_CLK; - input CTL_RX_FORCE_RESYNC; - input CTL_RX_RETRANS_ACK; - input CTL_RX_RETRANS_ENABLE; - input CTL_RX_RETRANS_ERRIN; - input CTL_RX_RETRANS_FORCE_REQ; - input CTL_RX_RETRANS_RESET; - input CTL_RX_RETRANS_RESET_MODE; - input CTL_TX_DIAGWORD_INTFSTAT; - input [11:0] CTL_TX_DIAGWORD_LANESTAT; - input CTL_TX_ENABLE; - input CTL_TX_ERRINJ_BITERR_GO; - input [3:0] CTL_TX_ERRINJ_BITERR_LANE; - input [255:0] CTL_TX_FC_STAT; - input [7:0] CTL_TX_MUBITS; - input CTL_TX_RETRANS_ENABLE; - input CTL_TX_RETRANS_RAM_PERRIN; - input [643:0] CTL_TX_RETRANS_RAM_RDATA; - input CTL_TX_RETRANS_REQ; - input CTL_TX_RETRANS_REQ_VALID; - input [11:0] CTL_TX_RLIM_DELTA; - input CTL_TX_RLIM_ENABLE; - input [7:0] CTL_TX_RLIM_INTV; - input [11:0] CTL_TX_RLIM_MAX; - input [9:0] DRP_ADDR; - input DRP_CLK; - input [15:0] DRP_DI; - input DRP_EN; - input DRP_WE; - input LBUS_CLK; - input RX_BYPASS_FORCE_REALIGNIN; - input RX_BYPASS_RDIN; - input RX_RESET; - input [11:0] RX_SERDES_CLK; - input [63:0] RX_SERDES_DATA00; - input [63:0] RX_SERDES_DATA01; - input [63:0] RX_SERDES_DATA02; - input [63:0] RX_SERDES_DATA03; - input [63:0] RX_SERDES_DATA04; - input [63:0] RX_SERDES_DATA05; - input [63:0] RX_SERDES_DATA06; - input [63:0] RX_SERDES_DATA07; - input [63:0] RX_SERDES_DATA08; - input [63:0] RX_SERDES_DATA09; - input [63:0] RX_SERDES_DATA10; - input [63:0] RX_SERDES_DATA11; - input [11:0] RX_SERDES_RESET; - input TX_BCTLIN0; - input TX_BCTLIN1; - input TX_BCTLIN2; - input TX_BCTLIN3; - input [11:0] TX_BYPASS_CTRLIN; - input [63:0] TX_BYPASS_DATAIN00; - input [63:0] TX_BYPASS_DATAIN01; - input [63:0] TX_BYPASS_DATAIN02; - input [63:0] TX_BYPASS_DATAIN03; - input [63:0] TX_BYPASS_DATAIN04; - input [63:0] TX_BYPASS_DATAIN05; - input [63:0] TX_BYPASS_DATAIN06; - input [63:0] TX_BYPASS_DATAIN07; - input [63:0] TX_BYPASS_DATAIN08; - input [63:0] TX_BYPASS_DATAIN09; - input [63:0] TX_BYPASS_DATAIN10; - input [63:0] TX_BYPASS_DATAIN11; - input TX_BYPASS_ENAIN; - input [7:0] TX_BYPASS_GEARBOX_SEQIN; - input [3:0] TX_BYPASS_MFRAMER_STATEIN; - input [10:0] TX_CHANIN0; - input [10:0] TX_CHANIN1; - input [10:0] TX_CHANIN2; - input [10:0] TX_CHANIN3; - input [127:0] TX_DATAIN0; - input [127:0] TX_DATAIN1; - input [127:0] TX_DATAIN2; - input [127:0] TX_DATAIN3; - input TX_ENAIN0; - input TX_ENAIN1; - input TX_ENAIN2; - input TX_ENAIN3; - input TX_EOPIN0; - input TX_EOPIN1; - input TX_EOPIN2; - input TX_EOPIN3; - input TX_ERRIN0; - input TX_ERRIN1; - input TX_ERRIN2; - input TX_ERRIN3; - input [3:0] TX_MTYIN0; - input [3:0] TX_MTYIN1; - input [3:0] TX_MTYIN2; - input [3:0] TX_MTYIN3; - input TX_RESET; - input TX_SERDES_REFCLK; - input TX_SERDES_REFCLK_RESET; - input TX_SOPIN0; - input TX_SOPIN1; - input TX_SOPIN2; - input TX_SOPIN3; -endmodule - -module OBUFDS_GTE3 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input I; -endmodule - -module OBUFDS_GTE3_ADV (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input [3:0] I; - input [1:0] RXRECCLK_SEL; -endmodule - -module OBUFDS_GTE4 (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input I; -endmodule - -module OBUFDS_GTE4_ADV (...); - parameter [0:0] REFCLK_EN_TX_PATH = 1'b0; - parameter [4:0] REFCLK_ICNTL_TX = 5'b00000; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input CEB; - input [3:0] I; - input [1:0] RXRECCLK_SEL; -endmodule - -module PCIE40E4 (...); - parameter ARI_CAP_ENABLE = "FALSE"; - parameter AUTO_FLR_RESPONSE = "FALSE"; - parameter [1:0] AXISTEN_IF_CC_ALIGNMENT_MODE = 2'h0; - parameter [23:0] AXISTEN_IF_COMPL_TIMEOUT_REG0 = 24'hBEBC20; - parameter [27:0] AXISTEN_IF_COMPL_TIMEOUT_REG1 = 28'h2FAF080; - parameter [1:0] AXISTEN_IF_CQ_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_CQ_EN_POISONED_MEM_WR = "FALSE"; - parameter AXISTEN_IF_ENABLE_256_TAGS = "FALSE"; - parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; - parameter AXISTEN_IF_ENABLE_INTERNAL_MSIX_TABLE = "FALSE"; - parameter AXISTEN_IF_ENABLE_MESSAGE_RID_CHECK = "TRUE"; - parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; - parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; - parameter AXISTEN_IF_EXT_512 = "FALSE"; - parameter AXISTEN_IF_EXT_512_CC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_CQ_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_RC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_EXT_512_RQ_STRADDLE = "FALSE"; - parameter AXISTEN_IF_LEGACY_MODE_ENABLE = "FALSE"; - parameter AXISTEN_IF_MSIX_FROM_RAM_PIPELINE = "FALSE"; - parameter AXISTEN_IF_MSIX_RX_PARITY_EN = "TRUE"; - parameter AXISTEN_IF_MSIX_TO_RAM_PIPELINE = "FALSE"; - parameter [1:0] AXISTEN_IF_RC_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; - parameter [1:0] AXISTEN_IF_RQ_ALIGNMENT_MODE = 2'h0; - parameter AXISTEN_IF_RX_PARITY_EN = "TRUE"; - parameter AXISTEN_IF_SIM_SHORT_CPL_TIMEOUT = "FALSE"; - parameter AXISTEN_IF_TX_PARITY_EN = "TRUE"; - parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; - parameter CFG_BYPASS_MODE_ENABLE = "FALSE"; - parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; - parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; - parameter [15:0] DEBUG_AXI4ST_SPARE = 16'h0000; - parameter [7:0] DEBUG_AXIST_DISABLE_FEATURE_BIT = 8'h00; - parameter [3:0] DEBUG_CAR_SPARE = 4'h0; - parameter [15:0] DEBUG_CFG_SPARE = 16'h0000; - parameter [15:0] DEBUG_LL_SPARE = 16'h0000; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_DEFRAMER_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_LES_UPDATE_ON_SKP_PARITY_ERROR = "FALSE"; - parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_DYNAMIC_DSKEW_FAIL = "FALSE"; - parameter DEBUG_PL_DISABLE_REC_ENTRY_ON_RX_BUFFER_UNDER_OVER_FLOW = "FALSE"; - parameter DEBUG_PL_DISABLE_SCRAMBLING = "FALSE"; - parameter DEBUG_PL_SIM_RESET_LFSR = "FALSE"; - parameter [15:0] DEBUG_PL_SPARE = 16'h0000; - parameter DEBUG_TL_DISABLE_FC_TIMEOUT = "FALSE"; - parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; - parameter [15:0] DEBUG_TL_SPARE = 16'h0000; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter DSN_CAP_ENABLE = "FALSE"; - parameter EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter HEADER_TYPE_OVERRIDE = "FALSE"; - parameter IS_SWITCH_PORT = "FALSE"; - parameter LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter [8:0] LL_ACK_TIMEOUT = 9'h000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter LL_DISABLE_SCHED_TX_NAK = "FALSE"; - parameter LL_REPLAY_FROM_RAM_PIPELINE = "FALSE"; - parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter LL_REPLAY_TO_RAM_PIPELINE = "FALSE"; - parameter LL_RX_TLP_PARITY_GEN = "TRUE"; - parameter LL_TX_TLP_PARITY_CHK = "TRUE"; - parameter [15:0] LL_USER_SPARE = 16'h0000; - parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h250; - parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; - parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; - parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; - parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; - parameter MCAP_ENABLE = "FALSE"; - parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; - parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; - parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; - parameter [15:0] MCAP_VSEC_ID = 16'h0000; - parameter [11:0] MCAP_VSEC_LEN = 12'h02C; - parameter [3:0] MCAP_VSEC_REV = 4'h0; - parameter PF0_AER_CAP_ECRC_GEN_AND_CHECK_CAPABLE = "FALSE"; - parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [3:0] PF0_ARI_CAP_VER = 4'h1; - parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_BAR1_CONTROL = 3'h0; - parameter [5:0] PF0_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR3_CONTROL = 3'h0; - parameter [5:0] PF0_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR5_CONTROL = 3'h0; - parameter [7:0] PF0_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF0_CLASS_CODE = 24'h000000; - parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; - parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; - parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; - parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; - parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; - parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; - parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; - parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN4 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN4 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN4 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN4 = 7; - parameter [0:0] PF0_LINK_CONTROL_RCB = 1'h0; - parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; - parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; - parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_LTR_CAP_VER = 4'h1; - parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [5:0] PF0_MSIX_VECTOR_COUNT = 6'h04; - parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; - parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF0_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF0_PM_CAP_ID = 8'h01; - parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; - parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; - parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; - parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; - parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; - parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; - parameter PF0_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF0_TPHR_CAP_ENABLE = "FALSE"; - parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; - parameter PF0_VC_CAP_ENABLE = "FALSE"; - parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_VC_CAP_VER = 4'h1; - parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_BAR1_CONTROL = 3'h0; - parameter [5:0] PF1_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR3_CONTROL = 3'h0; - parameter [5:0] PF1_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR5_CONTROL = 3'h0; - parameter [7:0] PF1_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF1_CLASS_CODE = 24'h000000; - parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; - parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF1_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; - parameter PF1_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR0_CONTROL = 3'h4; - parameter [4:0] PF2_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF2_BAR1_CONTROL = 3'h0; - parameter [5:0] PF2_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR3_CONTROL = 3'h0; - parameter [5:0] PF2_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR5_CONTROL = 3'h0; - parameter [7:0] PF2_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF2_CLASS_CODE = 24'h000000; - parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; - parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF2_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; - parameter PF2_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR0_CONTROL = 3'h4; - parameter [4:0] PF3_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF3_BAR1_CONTROL = 3'h0; - parameter [5:0] PF3_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR3_CONTROL = 3'h0; - parameter [5:0] PF3_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR5_CONTROL = 3'h0; - parameter [7:0] PF3_CAPABILITY_POINTER = 8'h80; - parameter [23:0] PF3_CLASS_CODE = 24'h000000; - parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; - parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [7:0] PF3_PCIE_CAP_NEXTPTR = 8'h00; - parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; - parameter PF3_SRIOV_ARI_CAPBL_HIER_PRESERVED = "FALSE"; - parameter [5:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; - parameter [5:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; - parameter [5:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter PL_CFG_STATE_ROBUSTNESS_ENABLE = "TRUE"; - parameter PL_DEEMPH_SOURCE_SELECT = "TRUE"; - parameter PL_DESKEW_ON_SKIP_IN_GEN12 = "FALSE"; - parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; - parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN4 = "FALSE"; - parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; - parameter PL_DISABLE_DC_BALANCE = "FALSE"; - parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter PL_DISABLE_LANE_REVERSAL = "FALSE"; - parameter [1:0] PL_DISABLE_LFSR_UPDATE_ON_SKP = 2'h0; - parameter PL_DISABLE_RETRAIN_ON_EB_ERROR = "FALSE"; - parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; - parameter [15:0] PL_DISABLE_RETRAIN_ON_SPECIFIC_FRAMING_ERROR = 16'h0000; - parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; - parameter [1:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK = 2'h0; - parameter [1:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK = 2'h0; - parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; - parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; - parameter [1:0] PL_EQ_BYPASS_PHASE23 = 2'h0; - parameter [5:0] PL_EQ_DEFAULT_RX_PRESET_HINT = 6'h33; - parameter [7:0] PL_EQ_DEFAULT_TX_PRESET = 8'h44; - parameter PL_EQ_DISABLE_MISMATCH_CHECK = "TRUE"; - parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE0 = 2'h0; - parameter [1:0] PL_EQ_RX_ADAPT_EQ_PHASE1 = 2'h0; - parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; - parameter PL_EQ_TX_8G_EQ_TS2_ENABLE = "FALSE"; - parameter PL_EXIT_LOOPBACK_ON_EI_ENTRY = "TRUE"; - parameter PL_INFER_EI_DISABLE_LPBK_ACTIVE = "TRUE"; - parameter PL_INFER_EI_DISABLE_REC_RC = "FALSE"; - parameter PL_INFER_EI_DISABLE_REC_SPD = "FALSE"; - parameter [31:0] PL_LANE0_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE10_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE11_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE12_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE13_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE14_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE15_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE1_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE2_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE3_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE4_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE5_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE6_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE7_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE8_EQ_CONTROL = 32'h00003F00; - parameter [31:0] PL_LANE9_EQ_CONTROL = 32'h00003F00; - parameter [3:0] PL_LINK_CAP_MAX_LINK_SPEED = 4'h4; - parameter [4:0] PL_LINK_CAP_MAX_LINK_WIDTH = 5'h08; - parameter integer PL_N_FTS = 255; - parameter PL_QUIESCE_GUARANTEE_DISABLE = "FALSE"; - parameter PL_REDO_EQ_SOURCE_SELECT = "TRUE"; - parameter [7:0] PL_REPORT_ALL_PHY_ERRORS = 8'h00; - parameter [1:0] PL_RX_ADAPT_TIMER_CLWS_CLOBBER_TX_TS = 2'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN3 = 4'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_CLWS_GEN4 = 4'h0; - parameter [1:0] PL_RX_ADAPT_TIMER_RRL_CLOBBER_TX_TS = 2'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN3 = 4'h0; - parameter [3:0] PL_RX_ADAPT_TIMER_RRL_GEN4 = 4'h0; - parameter [1:0] PL_RX_L0S_EXIT_TO_RECOVERY = 2'h0; - parameter [1:0] PL_SIM_FAST_LINK_TRAINING = 2'h0; - parameter PL_SRIS_ENABLE = "FALSE"; - parameter [6:0] PL_SRIS_SKPOS_GEN_SPD_VEC = 7'h00; - parameter [6:0] PL_SRIS_SKPOS_REC_SPD_VEC = 7'h00; - parameter PL_UPSTREAM_FACING = "TRUE"; - parameter [15:0] PL_USER_SPARE = 16'h0000; - parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h1500; - parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h003E8; - parameter PM_ENABLE_L23_ENTRY = "FALSE"; - parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; - parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000100; - parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h00000; - parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0100; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; - parameter SIM_VERSION = "1.0"; - parameter SPARE_BIT0 = "FALSE"; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter SPARE_BIT3 = "FALSE"; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter [3:0] SRIOV_CAP_ENABLE = 4'h0; - parameter TL2CFG_IF_PARITY_CHK = "TRUE"; - parameter [1:0] TL_COMPLETION_RAM_NUM_TLPS = 2'h0; - parameter [1:0] TL_COMPLETION_RAM_SIZE = 2'h1; - parameter [11:0] TL_CREDITS_CD = 12'h000; - parameter [7:0] TL_CREDITS_CH = 8'h00; - parameter [11:0] TL_CREDITS_NPD = 12'h004; - parameter [7:0] TL_CREDITS_NPH = 8'h20; - parameter [11:0] TL_CREDITS_PD = 12'h0E0; - parameter [7:0] TL_CREDITS_PH = 8'h20; - parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TIME = 5'h02; - parameter [4:0] TL_FC_UPDATE_MIN_INTERVAL_TLP_COUNT = 5'h08; - parameter [1:0] TL_PF_ENABLE_REG = 2'h0; - parameter [0:0] TL_POSTED_RAM_SIZE = 1'h0; - parameter TL_RX_COMPLETION_FROM_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_COMPLETION_TO_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_COMPLETION_TO_RAM_WRITE_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_FROM_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_TO_RAM_READ_PIPELINE = "FALSE"; - parameter TL_RX_POSTED_TO_RAM_WRITE_PIPELINE = "FALSE"; - parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; - parameter TL_TX_TLP_STRADDLE_ENABLE = "FALSE"; - parameter TL_TX_TLP_TERMINATE_PARITY = "FALSE"; - parameter [15:0] TL_USER_SPARE = 16'h0000; - parameter TPH_FROM_RAM_PIPELINE = "FALSE"; - parameter TPH_TO_RAM_PIPELINE = "FALSE"; - parameter [7:0] VF0_CAPABILITY_POINTER = 8'h80; - parameter [11:0] VFG0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VFG0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG0_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VFG1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG1_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG2_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VFG2_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG2_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [11:0] VFG3_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VFG3_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer VFG3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VFG3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VFG3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VFG3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VFG3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter [7:0] VFG3_PCIE_CAP_NEXTPTR = 8'h00; - parameter [11:0] VFG3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VFG3_TPHR_CAP_ST_MODE_SEL = 3'h0; - output [7:0] AXIUSEROUT; - output [7:0] CFGBUSNUMBER; - output [1:0] CFGCURRENTSPEED; - output CFGERRCOROUT; - output CFGERRFATALOUT; - output CFGERRNONFATALOUT; - output [7:0] CFGEXTFUNCTIONNUMBER; - output CFGEXTREADRECEIVED; - output [9:0] CFGEXTREGISTERNUMBER; - output [3:0] CFGEXTWRITEBYTEENABLE; - output [31:0] CFGEXTWRITEDATA; - output CFGEXTWRITERECEIVED; - output [11:0] CFGFCCPLD; - output [7:0] CFGFCCPLH; - output [11:0] CFGFCNPD; - output [7:0] CFGFCNPH; - output [11:0] CFGFCPD; - output [7:0] CFGFCPH; - output [3:0] CFGFLRINPROCESS; - output [11:0] CFGFUNCTIONPOWERSTATE; - output [15:0] CFGFUNCTIONSTATUS; - output CFGHOTRESETOUT; - output [31:0] CFGINTERRUPTMSIDATA; - output [3:0] CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIFAIL; - output CFGINTERRUPTMSIMASKUPDATE; - output [11:0] CFGINTERRUPTMSIMMENABLE; - output CFGINTERRUPTMSISENT; - output [3:0] CFGINTERRUPTMSIXENABLE; - output [3:0] CFGINTERRUPTMSIXMASK; - output CFGINTERRUPTMSIXVECPENDINGSTATUS; - output CFGINTERRUPTSENT; - output [1:0] CFGLINKPOWERSTATE; - output [4:0] CFGLOCALERROROUT; - output CFGLOCALERRORVALID; - output CFGLTRENABLE; - output [5:0] CFGLTSSMSTATE; - output [1:0] CFGMAXPAYLOAD; - output [2:0] CFGMAXREADREQ; - output [31:0] CFGMGMTREADDATA; - output CFGMGMTREADWRITEDONE; - output CFGMSGRECEIVED; - output [7:0] CFGMSGRECEIVEDDATA; - output [4:0] CFGMSGRECEIVEDTYPE; - output CFGMSGTRANSMITDONE; - output [12:0] CFGMSIXRAMADDRESS; - output CFGMSIXRAMREADENABLE; - output [3:0] CFGMSIXRAMWRITEBYTEENABLE; - output [35:0] CFGMSIXRAMWRITEDATA; - output [2:0] CFGNEGOTIATEDWIDTH; - output [1:0] CFGOBFFENABLE; - output CFGPHYLINKDOWN; - output [1:0] CFGPHYLINKSTATUS; - output CFGPLSTATUSCHANGE; - output CFGPOWERSTATECHANGEINTERRUPT; - output [3:0] CFGRCBSTATUS; - output [1:0] CFGRXPMSTATE; - output [11:0] CFGTPHRAMADDRESS; - output CFGTPHRAMREADENABLE; - output [3:0] CFGTPHRAMWRITEBYTEENABLE; - output [35:0] CFGTPHRAMWRITEDATA; - output [3:0] CFGTPHREQUESTERENABLE; - output [11:0] CFGTPHSTMODE; - output [1:0] CFGTXPMSTATE; - output CONFMCAPDESIGNSWITCH; - output CONFMCAPEOS; - output CONFMCAPINUSEBYPCIE; - output CONFREQREADY; - output [31:0] CONFRESPRDATA; - output CONFRESPVALID; - output [31:0] DBGCTRL0OUT; - output [31:0] DBGCTRL1OUT; - output [255:0] DBGDATA0OUT; - output [255:0] DBGDATA1OUT; - output [15:0] DRPDO; - output DRPRDY; - output [255:0] MAXISCQTDATA; - output [7:0] MAXISCQTKEEP; - output MAXISCQTLAST; - output [87:0] MAXISCQTUSER; - output MAXISCQTVALID; - output [255:0] MAXISRCTDATA; - output [7:0] MAXISRCTKEEP; - output MAXISRCTLAST; - output [74:0] MAXISRCTUSER; - output MAXISRCTVALID; - output [8:0] MIREPLAYRAMADDRESS0; - output [8:0] MIREPLAYRAMADDRESS1; - output MIREPLAYRAMREADENABLE0; - output MIREPLAYRAMREADENABLE1; - output [127:0] MIREPLAYRAMWRITEDATA0; - output [127:0] MIREPLAYRAMWRITEDATA1; - output MIREPLAYRAMWRITEENABLE0; - output MIREPLAYRAMWRITEENABLE1; - output [8:0] MIRXCOMPLETIONRAMREADADDRESS0; - output [8:0] MIRXCOMPLETIONRAMREADADDRESS1; - output [1:0] MIRXCOMPLETIONRAMREADENABLE0; - output [1:0] MIRXCOMPLETIONRAMREADENABLE1; - output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS0; - output [8:0] MIRXCOMPLETIONRAMWRITEADDRESS1; - output [143:0] MIRXCOMPLETIONRAMWRITEDATA0; - output [143:0] MIRXCOMPLETIONRAMWRITEDATA1; - output [1:0] MIRXCOMPLETIONRAMWRITEENABLE0; - output [1:0] MIRXCOMPLETIONRAMWRITEENABLE1; - output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS0; - output [8:0] MIRXPOSTEDREQUESTRAMREADADDRESS1; - output MIRXPOSTEDREQUESTRAMREADENABLE0; - output MIRXPOSTEDREQUESTRAMREADENABLE1; - output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS0; - output [8:0] MIRXPOSTEDREQUESTRAMWRITEADDRESS1; - output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA0; - output [143:0] MIRXPOSTEDREQUESTRAMWRITEDATA1; - output MIRXPOSTEDREQUESTRAMWRITEENABLE0; - output MIRXPOSTEDREQUESTRAMWRITEENABLE1; - output [5:0] PCIECQNPREQCOUNT; - output PCIEPERST0B; - output PCIEPERST1B; - output [5:0] PCIERQSEQNUM0; - output [5:0] PCIERQSEQNUM1; - output PCIERQSEQNUMVLD0; - output PCIERQSEQNUMVLD1; - output [7:0] PCIERQTAG0; - output [7:0] PCIERQTAG1; - output [3:0] PCIERQTAGAV; - output PCIERQTAGVLD0; - output PCIERQTAGVLD1; - output [3:0] PCIETFCNPDAV; - output [3:0] PCIETFCNPHAV; - output [1:0] PIPERX00EQCONTROL; - output PIPERX00POLARITY; - output [1:0] PIPERX01EQCONTROL; - output PIPERX01POLARITY; - output [1:0] PIPERX02EQCONTROL; - output PIPERX02POLARITY; - output [1:0] PIPERX03EQCONTROL; - output PIPERX03POLARITY; - output [1:0] PIPERX04EQCONTROL; - output PIPERX04POLARITY; - output [1:0] PIPERX05EQCONTROL; - output PIPERX05POLARITY; - output [1:0] PIPERX06EQCONTROL; - output PIPERX06POLARITY; - output [1:0] PIPERX07EQCONTROL; - output PIPERX07POLARITY; - output [1:0] PIPERX08EQCONTROL; - output PIPERX08POLARITY; - output [1:0] PIPERX09EQCONTROL; - output PIPERX09POLARITY; - output [1:0] PIPERX10EQCONTROL; - output PIPERX10POLARITY; - output [1:0] PIPERX11EQCONTROL; - output PIPERX11POLARITY; - output [1:0] PIPERX12EQCONTROL; - output PIPERX12POLARITY; - output [1:0] PIPERX13EQCONTROL; - output PIPERX13POLARITY; - output [1:0] PIPERX14EQCONTROL; - output PIPERX14POLARITY; - output [1:0] PIPERX15EQCONTROL; - output PIPERX15POLARITY; - output [5:0] PIPERXEQLPLFFS; - output [3:0] PIPERXEQLPTXPRESET; - output [1:0] PIPETX00CHARISK; - output PIPETX00COMPLIANCE; - output [31:0] PIPETX00DATA; - output PIPETX00DATAVALID; - output PIPETX00ELECIDLE; - output [1:0] PIPETX00EQCONTROL; - output [5:0] PIPETX00EQDEEMPH; - output [1:0] PIPETX00POWERDOWN; - output PIPETX00STARTBLOCK; - output [1:0] PIPETX00SYNCHEADER; - output [1:0] PIPETX01CHARISK; - output PIPETX01COMPLIANCE; - output [31:0] PIPETX01DATA; - output PIPETX01DATAVALID; - output PIPETX01ELECIDLE; - output [1:0] PIPETX01EQCONTROL; - output [5:0] PIPETX01EQDEEMPH; - output [1:0] PIPETX01POWERDOWN; - output PIPETX01STARTBLOCK; - output [1:0] PIPETX01SYNCHEADER; - output [1:0] PIPETX02CHARISK; - output PIPETX02COMPLIANCE; - output [31:0] PIPETX02DATA; - output PIPETX02DATAVALID; - output PIPETX02ELECIDLE; - output [1:0] PIPETX02EQCONTROL; - output [5:0] PIPETX02EQDEEMPH; - output [1:0] PIPETX02POWERDOWN; - output PIPETX02STARTBLOCK; - output [1:0] PIPETX02SYNCHEADER; - output [1:0] PIPETX03CHARISK; - output PIPETX03COMPLIANCE; - output [31:0] PIPETX03DATA; - output PIPETX03DATAVALID; - output PIPETX03ELECIDLE; - output [1:0] PIPETX03EQCONTROL; - output [5:0] PIPETX03EQDEEMPH; - output [1:0] PIPETX03POWERDOWN; - output PIPETX03STARTBLOCK; - output [1:0] PIPETX03SYNCHEADER; - output [1:0] PIPETX04CHARISK; - output PIPETX04COMPLIANCE; - output [31:0] PIPETX04DATA; - output PIPETX04DATAVALID; - output PIPETX04ELECIDLE; - output [1:0] PIPETX04EQCONTROL; - output [5:0] PIPETX04EQDEEMPH; - output [1:0] PIPETX04POWERDOWN; - output PIPETX04STARTBLOCK; - output [1:0] PIPETX04SYNCHEADER; - output [1:0] PIPETX05CHARISK; - output PIPETX05COMPLIANCE; - output [31:0] PIPETX05DATA; - output PIPETX05DATAVALID; - output PIPETX05ELECIDLE; - output [1:0] PIPETX05EQCONTROL; - output [5:0] PIPETX05EQDEEMPH; - output [1:0] PIPETX05POWERDOWN; - output PIPETX05STARTBLOCK; - output [1:0] PIPETX05SYNCHEADER; - output [1:0] PIPETX06CHARISK; - output PIPETX06COMPLIANCE; - output [31:0] PIPETX06DATA; - output PIPETX06DATAVALID; - output PIPETX06ELECIDLE; - output [1:0] PIPETX06EQCONTROL; - output [5:0] PIPETX06EQDEEMPH; - output [1:0] PIPETX06POWERDOWN; - output PIPETX06STARTBLOCK; - output [1:0] PIPETX06SYNCHEADER; - output [1:0] PIPETX07CHARISK; - output PIPETX07COMPLIANCE; - output [31:0] PIPETX07DATA; - output PIPETX07DATAVALID; - output PIPETX07ELECIDLE; - output [1:0] PIPETX07EQCONTROL; - output [5:0] PIPETX07EQDEEMPH; - output [1:0] PIPETX07POWERDOWN; - output PIPETX07STARTBLOCK; - output [1:0] PIPETX07SYNCHEADER; - output [1:0] PIPETX08CHARISK; - output PIPETX08COMPLIANCE; - output [31:0] PIPETX08DATA; - output PIPETX08DATAVALID; - output PIPETX08ELECIDLE; - output [1:0] PIPETX08EQCONTROL; - output [5:0] PIPETX08EQDEEMPH; - output [1:0] PIPETX08POWERDOWN; - output PIPETX08STARTBLOCK; - output [1:0] PIPETX08SYNCHEADER; - output [1:0] PIPETX09CHARISK; - output PIPETX09COMPLIANCE; - output [31:0] PIPETX09DATA; - output PIPETX09DATAVALID; - output PIPETX09ELECIDLE; - output [1:0] PIPETX09EQCONTROL; - output [5:0] PIPETX09EQDEEMPH; - output [1:0] PIPETX09POWERDOWN; - output PIPETX09STARTBLOCK; - output [1:0] PIPETX09SYNCHEADER; - output [1:0] PIPETX10CHARISK; - output PIPETX10COMPLIANCE; - output [31:0] PIPETX10DATA; - output PIPETX10DATAVALID; - output PIPETX10ELECIDLE; - output [1:0] PIPETX10EQCONTROL; - output [5:0] PIPETX10EQDEEMPH; - output [1:0] PIPETX10POWERDOWN; - output PIPETX10STARTBLOCK; - output [1:0] PIPETX10SYNCHEADER; - output [1:0] PIPETX11CHARISK; - output PIPETX11COMPLIANCE; - output [31:0] PIPETX11DATA; - output PIPETX11DATAVALID; - output PIPETX11ELECIDLE; - output [1:0] PIPETX11EQCONTROL; - output [5:0] PIPETX11EQDEEMPH; - output [1:0] PIPETX11POWERDOWN; - output PIPETX11STARTBLOCK; - output [1:0] PIPETX11SYNCHEADER; - output [1:0] PIPETX12CHARISK; - output PIPETX12COMPLIANCE; - output [31:0] PIPETX12DATA; - output PIPETX12DATAVALID; - output PIPETX12ELECIDLE; - output [1:0] PIPETX12EQCONTROL; - output [5:0] PIPETX12EQDEEMPH; - output [1:0] PIPETX12POWERDOWN; - output PIPETX12STARTBLOCK; - output [1:0] PIPETX12SYNCHEADER; - output [1:0] PIPETX13CHARISK; - output PIPETX13COMPLIANCE; - output [31:0] PIPETX13DATA; - output PIPETX13DATAVALID; - output PIPETX13ELECIDLE; - output [1:0] PIPETX13EQCONTROL; - output [5:0] PIPETX13EQDEEMPH; - output [1:0] PIPETX13POWERDOWN; - output PIPETX13STARTBLOCK; - output [1:0] PIPETX13SYNCHEADER; - output [1:0] PIPETX14CHARISK; - output PIPETX14COMPLIANCE; - output [31:0] PIPETX14DATA; - output PIPETX14DATAVALID; - output PIPETX14ELECIDLE; - output [1:0] PIPETX14EQCONTROL; - output [5:0] PIPETX14EQDEEMPH; - output [1:0] PIPETX14POWERDOWN; - output PIPETX14STARTBLOCK; - output [1:0] PIPETX14SYNCHEADER; - output [1:0] PIPETX15CHARISK; - output PIPETX15COMPLIANCE; - output [31:0] PIPETX15DATA; - output PIPETX15DATAVALID; - output PIPETX15ELECIDLE; - output [1:0] PIPETX15EQCONTROL; - output [5:0] PIPETX15EQDEEMPH; - output [1:0] PIPETX15POWERDOWN; - output PIPETX15STARTBLOCK; - output [1:0] PIPETX15SYNCHEADER; - output PIPETXDEEMPH; - output [2:0] PIPETXMARGIN; - output [1:0] PIPETXRATE; - output PIPETXRCVRDET; - output PIPETXRESET; - output PIPETXSWING; - output PLEQINPROGRESS; - output [1:0] PLEQPHASE; - output PLGEN34EQMISMATCH; - output [3:0] SAXISCCTREADY; - output [3:0] SAXISRQTREADY; - output [31:0] USERSPAREOUT; - input [7:0] AXIUSERIN; - input CFGCONFIGSPACEENABLE; - input [15:0] CFGDEVIDPF0; - input [15:0] CFGDEVIDPF1; - input [15:0] CFGDEVIDPF2; - input [15:0] CFGDEVIDPF3; - input [7:0] CFGDSBUSNUMBER; - input [4:0] CFGDSDEVICENUMBER; - input [2:0] CFGDSFUNCTIONNUMBER; - input [63:0] CFGDSN; - input [7:0] CFGDSPORTNUMBER; - input CFGERRCORIN; - input CFGERRUNCORIN; - input [31:0] CFGEXTREADDATA; - input CFGEXTREADDATAVALID; - input [2:0] CFGFCSEL; - input [3:0] CFGFLRDONE; - input CFGHOTRESETIN; - input [3:0] CFGINTERRUPTINT; - input [2:0] CFGINTERRUPTMSIATTR; - input [7:0] CFGINTERRUPTMSIFUNCTIONNUMBER; - input [31:0] CFGINTERRUPTMSIINT; - input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; - input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; - input [1:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; - input [1:0] CFGINTERRUPTMSISELECT; - input CFGINTERRUPTMSITPHPRESENT; - input [7:0] CFGINTERRUPTMSITPHSTTAG; - input [1:0] CFGINTERRUPTMSITPHTYPE; - input [63:0] CFGINTERRUPTMSIXADDRESS; - input [31:0] CFGINTERRUPTMSIXDATA; - input CFGINTERRUPTMSIXINT; - input [1:0] CFGINTERRUPTMSIXVECPENDING; - input [3:0] CFGINTERRUPTPENDING; - input CFGLINKTRAININGENABLE; - input [9:0] CFGMGMTADDR; - input [3:0] CFGMGMTBYTEENABLE; - input CFGMGMTDEBUGACCESS; - input [7:0] CFGMGMTFUNCTIONNUMBER; - input CFGMGMTREAD; - input CFGMGMTWRITE; - input [31:0] CFGMGMTWRITEDATA; - input CFGMSGTRANSMIT; - input [31:0] CFGMSGTRANSMITDATA; - input [2:0] CFGMSGTRANSMITTYPE; - input [35:0] CFGMSIXRAMREADDATA; - input CFGPMASPML1ENTRYREJECT; - input CFGPMASPMTXL0SENTRYDISABLE; - input CFGPOWERSTATECHANGEACK; - input CFGREQPMTRANSITIONL23READY; - input [7:0] CFGREVIDPF0; - input [7:0] CFGREVIDPF1; - input [7:0] CFGREVIDPF2; - input [7:0] CFGREVIDPF3; - input [15:0] CFGSUBSYSIDPF0; - input [15:0] CFGSUBSYSIDPF1; - input [15:0] CFGSUBSYSIDPF2; - input [15:0] CFGSUBSYSIDPF3; - input [15:0] CFGSUBSYSVENDID; - input [35:0] CFGTPHRAMREADDATA; - input [15:0] CFGVENDID; - input CFGVFFLRDONE; - input [7:0] CFGVFFLRFUNCNUM; - input CONFMCAPREQUESTBYCONF; - input [31:0] CONFREQDATA; - input [3:0] CONFREQREGNUM; - input [1:0] CONFREQTYPE; - input CONFREQVALID; - input CORECLK; - input CORECLKMIREPLAYRAM0; - input CORECLKMIREPLAYRAM1; - input CORECLKMIRXCOMPLETIONRAM0; - input CORECLKMIRXCOMPLETIONRAM1; - input CORECLKMIRXPOSTEDREQUESTRAM0; - input CORECLKMIRXPOSTEDREQUESTRAM1; - input [5:0] DBGSEL0; - input [5:0] DBGSEL1; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input [21:0] MAXISCQTREADY; - input [21:0] MAXISRCTREADY; - input MCAPCLK; - input MCAPPERST0B; - input MCAPPERST1B; - input MGMTRESETN; - input MGMTSTICKYRESETN; - input [5:0] MIREPLAYRAMERRCOR; - input [5:0] MIREPLAYRAMERRUNCOR; - input [127:0] MIREPLAYRAMREADDATA0; - input [127:0] MIREPLAYRAMREADDATA1; - input [11:0] MIRXCOMPLETIONRAMERRCOR; - input [11:0] MIRXCOMPLETIONRAMERRUNCOR; - input [143:0] MIRXCOMPLETIONRAMREADDATA0; - input [143:0] MIRXCOMPLETIONRAMREADDATA1; - input [5:0] MIRXPOSTEDREQUESTRAMERRCOR; - input [5:0] MIRXPOSTEDREQUESTRAMERRUNCOR; - input [143:0] MIRXPOSTEDREQUESTRAMREADDATA0; - input [143:0] MIRXPOSTEDREQUESTRAMREADDATA1; - input [1:0] PCIECOMPLDELIVERED; - input [7:0] PCIECOMPLDELIVEREDTAG0; - input [7:0] PCIECOMPLDELIVEREDTAG1; - input [1:0] PCIECQNPREQ; - input PCIECQNPUSERCREDITRCVD; - input PCIECQPIPELINEEMPTY; - input PCIEPOSTEDREQDELIVERED; - input PIPECLK; - input PIPECLKEN; - input [5:0] PIPEEQFS; - input [5:0] PIPEEQLF; - input PIPERESETN; - input [1:0] PIPERX00CHARISK; - input [31:0] PIPERX00DATA; - input PIPERX00DATAVALID; - input PIPERX00ELECIDLE; - input PIPERX00EQDONE; - input PIPERX00EQLPADAPTDONE; - input PIPERX00EQLPLFFSSEL; - input [17:0] PIPERX00EQLPNEWTXCOEFFORPRESET; - input PIPERX00PHYSTATUS; - input [1:0] PIPERX00STARTBLOCK; - input [2:0] PIPERX00STATUS; - input [1:0] PIPERX00SYNCHEADER; - input PIPERX00VALID; - input [1:0] PIPERX01CHARISK; - input [31:0] PIPERX01DATA; - input PIPERX01DATAVALID; - input PIPERX01ELECIDLE; - input PIPERX01EQDONE; - input PIPERX01EQLPADAPTDONE; - input PIPERX01EQLPLFFSSEL; - input [17:0] PIPERX01EQLPNEWTXCOEFFORPRESET; - input PIPERX01PHYSTATUS; - input [1:0] PIPERX01STARTBLOCK; - input [2:0] PIPERX01STATUS; - input [1:0] PIPERX01SYNCHEADER; - input PIPERX01VALID; - input [1:0] PIPERX02CHARISK; - input [31:0] PIPERX02DATA; - input PIPERX02DATAVALID; - input PIPERX02ELECIDLE; - input PIPERX02EQDONE; - input PIPERX02EQLPADAPTDONE; - input PIPERX02EQLPLFFSSEL; - input [17:0] PIPERX02EQLPNEWTXCOEFFORPRESET; - input PIPERX02PHYSTATUS; - input [1:0] PIPERX02STARTBLOCK; - input [2:0] PIPERX02STATUS; - input [1:0] PIPERX02SYNCHEADER; - input PIPERX02VALID; - input [1:0] PIPERX03CHARISK; - input [31:0] PIPERX03DATA; - input PIPERX03DATAVALID; - input PIPERX03ELECIDLE; - input PIPERX03EQDONE; - input PIPERX03EQLPADAPTDONE; - input PIPERX03EQLPLFFSSEL; - input [17:0] PIPERX03EQLPNEWTXCOEFFORPRESET; - input PIPERX03PHYSTATUS; - input [1:0] PIPERX03STARTBLOCK; - input [2:0] PIPERX03STATUS; - input [1:0] PIPERX03SYNCHEADER; - input PIPERX03VALID; - input [1:0] PIPERX04CHARISK; - input [31:0] PIPERX04DATA; - input PIPERX04DATAVALID; - input PIPERX04ELECIDLE; - input PIPERX04EQDONE; - input PIPERX04EQLPADAPTDONE; - input PIPERX04EQLPLFFSSEL; - input [17:0] PIPERX04EQLPNEWTXCOEFFORPRESET; - input PIPERX04PHYSTATUS; - input [1:0] PIPERX04STARTBLOCK; - input [2:0] PIPERX04STATUS; - input [1:0] PIPERX04SYNCHEADER; - input PIPERX04VALID; - input [1:0] PIPERX05CHARISK; - input [31:0] PIPERX05DATA; - input PIPERX05DATAVALID; - input PIPERX05ELECIDLE; - input PIPERX05EQDONE; - input PIPERX05EQLPADAPTDONE; - input PIPERX05EQLPLFFSSEL; - input [17:0] PIPERX05EQLPNEWTXCOEFFORPRESET; - input PIPERX05PHYSTATUS; - input [1:0] PIPERX05STARTBLOCK; - input [2:0] PIPERX05STATUS; - input [1:0] PIPERX05SYNCHEADER; - input PIPERX05VALID; - input [1:0] PIPERX06CHARISK; - input [31:0] PIPERX06DATA; - input PIPERX06DATAVALID; - input PIPERX06ELECIDLE; - input PIPERX06EQDONE; - input PIPERX06EQLPADAPTDONE; - input PIPERX06EQLPLFFSSEL; - input [17:0] PIPERX06EQLPNEWTXCOEFFORPRESET; - input PIPERX06PHYSTATUS; - input [1:0] PIPERX06STARTBLOCK; - input [2:0] PIPERX06STATUS; - input [1:0] PIPERX06SYNCHEADER; - input PIPERX06VALID; - input [1:0] PIPERX07CHARISK; - input [31:0] PIPERX07DATA; - input PIPERX07DATAVALID; - input PIPERX07ELECIDLE; - input PIPERX07EQDONE; - input PIPERX07EQLPADAPTDONE; - input PIPERX07EQLPLFFSSEL; - input [17:0] PIPERX07EQLPNEWTXCOEFFORPRESET; - input PIPERX07PHYSTATUS; - input [1:0] PIPERX07STARTBLOCK; - input [2:0] PIPERX07STATUS; - input [1:0] PIPERX07SYNCHEADER; - input PIPERX07VALID; - input [1:0] PIPERX08CHARISK; - input [31:0] PIPERX08DATA; - input PIPERX08DATAVALID; - input PIPERX08ELECIDLE; - input PIPERX08EQDONE; - input PIPERX08EQLPADAPTDONE; - input PIPERX08EQLPLFFSSEL; - input [17:0] PIPERX08EQLPNEWTXCOEFFORPRESET; - input PIPERX08PHYSTATUS; - input [1:0] PIPERX08STARTBLOCK; - input [2:0] PIPERX08STATUS; - input [1:0] PIPERX08SYNCHEADER; - input PIPERX08VALID; - input [1:0] PIPERX09CHARISK; - input [31:0] PIPERX09DATA; - input PIPERX09DATAVALID; - input PIPERX09ELECIDLE; - input PIPERX09EQDONE; - input PIPERX09EQLPADAPTDONE; - input PIPERX09EQLPLFFSSEL; - input [17:0] PIPERX09EQLPNEWTXCOEFFORPRESET; - input PIPERX09PHYSTATUS; - input [1:0] PIPERX09STARTBLOCK; - input [2:0] PIPERX09STATUS; - input [1:0] PIPERX09SYNCHEADER; - input PIPERX09VALID; - input [1:0] PIPERX10CHARISK; - input [31:0] PIPERX10DATA; - input PIPERX10DATAVALID; - input PIPERX10ELECIDLE; - input PIPERX10EQDONE; - input PIPERX10EQLPADAPTDONE; - input PIPERX10EQLPLFFSSEL; - input [17:0] PIPERX10EQLPNEWTXCOEFFORPRESET; - input PIPERX10PHYSTATUS; - input [1:0] PIPERX10STARTBLOCK; - input [2:0] PIPERX10STATUS; - input [1:0] PIPERX10SYNCHEADER; - input PIPERX10VALID; - input [1:0] PIPERX11CHARISK; - input [31:0] PIPERX11DATA; - input PIPERX11DATAVALID; - input PIPERX11ELECIDLE; - input PIPERX11EQDONE; - input PIPERX11EQLPADAPTDONE; - input PIPERX11EQLPLFFSSEL; - input [17:0] PIPERX11EQLPNEWTXCOEFFORPRESET; - input PIPERX11PHYSTATUS; - input [1:0] PIPERX11STARTBLOCK; - input [2:0] PIPERX11STATUS; - input [1:0] PIPERX11SYNCHEADER; - input PIPERX11VALID; - input [1:0] PIPERX12CHARISK; - input [31:0] PIPERX12DATA; - input PIPERX12DATAVALID; - input PIPERX12ELECIDLE; - input PIPERX12EQDONE; - input PIPERX12EQLPADAPTDONE; - input PIPERX12EQLPLFFSSEL; - input [17:0] PIPERX12EQLPNEWTXCOEFFORPRESET; - input PIPERX12PHYSTATUS; - input [1:0] PIPERX12STARTBLOCK; - input [2:0] PIPERX12STATUS; - input [1:0] PIPERX12SYNCHEADER; - input PIPERX12VALID; - input [1:0] PIPERX13CHARISK; - input [31:0] PIPERX13DATA; - input PIPERX13DATAVALID; - input PIPERX13ELECIDLE; - input PIPERX13EQDONE; - input PIPERX13EQLPADAPTDONE; - input PIPERX13EQLPLFFSSEL; - input [17:0] PIPERX13EQLPNEWTXCOEFFORPRESET; - input PIPERX13PHYSTATUS; - input [1:0] PIPERX13STARTBLOCK; - input [2:0] PIPERX13STATUS; - input [1:0] PIPERX13SYNCHEADER; - input PIPERX13VALID; - input [1:0] PIPERX14CHARISK; - input [31:0] PIPERX14DATA; - input PIPERX14DATAVALID; - input PIPERX14ELECIDLE; - input PIPERX14EQDONE; - input PIPERX14EQLPADAPTDONE; - input PIPERX14EQLPLFFSSEL; - input [17:0] PIPERX14EQLPNEWTXCOEFFORPRESET; - input PIPERX14PHYSTATUS; - input [1:0] PIPERX14STARTBLOCK; - input [2:0] PIPERX14STATUS; - input [1:0] PIPERX14SYNCHEADER; - input PIPERX14VALID; - input [1:0] PIPERX15CHARISK; - input [31:0] PIPERX15DATA; - input PIPERX15DATAVALID; - input PIPERX15ELECIDLE; - input PIPERX15EQDONE; - input PIPERX15EQLPADAPTDONE; - input PIPERX15EQLPLFFSSEL; - input [17:0] PIPERX15EQLPNEWTXCOEFFORPRESET; - input PIPERX15PHYSTATUS; - input [1:0] PIPERX15STARTBLOCK; - input [2:0] PIPERX15STATUS; - input [1:0] PIPERX15SYNCHEADER; - input PIPERX15VALID; - input [17:0] PIPETX00EQCOEFF; - input PIPETX00EQDONE; - input [17:0] PIPETX01EQCOEFF; - input PIPETX01EQDONE; - input [17:0] PIPETX02EQCOEFF; - input PIPETX02EQDONE; - input [17:0] PIPETX03EQCOEFF; - input PIPETX03EQDONE; - input [17:0] PIPETX04EQCOEFF; - input PIPETX04EQDONE; - input [17:0] PIPETX05EQCOEFF; - input PIPETX05EQDONE; - input [17:0] PIPETX06EQCOEFF; - input PIPETX06EQDONE; - input [17:0] PIPETX07EQCOEFF; - input PIPETX07EQDONE; - input [17:0] PIPETX08EQCOEFF; - input PIPETX08EQDONE; - input [17:0] PIPETX09EQCOEFF; - input PIPETX09EQDONE; - input [17:0] PIPETX10EQCOEFF; - input PIPETX10EQDONE; - input [17:0] PIPETX11EQCOEFF; - input PIPETX11EQDONE; - input [17:0] PIPETX12EQCOEFF; - input PIPETX12EQDONE; - input [17:0] PIPETX13EQCOEFF; - input PIPETX13EQDONE; - input [17:0] PIPETX14EQCOEFF; - input PIPETX14EQDONE; - input [17:0] PIPETX15EQCOEFF; - input PIPETX15EQDONE; - input PLEQRESETEIEOSCOUNT; - input PLGEN2UPSTREAMPREFERDEEMPH; - input PLGEN34REDOEQSPEED; - input PLGEN34REDOEQUALIZATION; - input RESETN; - input [255:0] SAXISCCTDATA; - input [7:0] SAXISCCTKEEP; - input SAXISCCTLAST; - input [32:0] SAXISCCTUSER; - input SAXISCCTVALID; - input [255:0] SAXISRQTDATA; - input [7:0] SAXISRQTKEEP; - input SAXISRQTLAST; - input [61:0] SAXISRQTUSER; - input SAXISRQTVALID; - input USERCLK; - input USERCLK2; - input USERCLKEN; - input [31:0] USERSPAREIN; -endmodule - -module PCIE_3_1 (...); - parameter ARI_CAP_ENABLE = "FALSE"; - parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE"; - parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE"; - parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000; - parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE"; - parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_RC_STRADDLE = "FALSE"; - parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE"; - parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE"; - parameter [1:0] AXISTEN_IF_WIDTH = 2'h2; - parameter CRM_CORE_CLK_FREQ_500 = "TRUE"; - parameter [1:0] CRM_USER_CLK_FREQ = 2'h2; - parameter DEBUG_CFG_LOCAL_MGMT_REG_ACCESS_OVERRIDE = "FALSE"; - parameter DEBUG_PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter DEBUG_TL_DISABLE_RX_TLP_ORDER_CHECKS = "FALSE"; - parameter [7:0] DNSTREAM_LINK_NUM = 8'h00; - parameter [8:0] LL_ACK_TIMEOUT = 9'h000; - parameter LL_ACK_TIMEOUT_EN = "FALSE"; - parameter integer LL_ACK_TIMEOUT_FUNC = 0; - parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000; - parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000; - parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000; - parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000; - parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE"; - parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000; - parameter LL_REPLAY_TIMEOUT_EN = "FALSE"; - parameter integer LL_REPLAY_TIMEOUT_FUNC = 0; - parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA; - parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE"; - parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE"; - parameter [11:0] MCAP_CAP_NEXTPTR = 12'h000; - parameter MCAP_CONFIGURE_OVERRIDE = "FALSE"; - parameter MCAP_ENABLE = "FALSE"; - parameter MCAP_EOS_DESIGN_SWITCH = "FALSE"; - parameter [31:0] MCAP_FPGA_BITSTREAM_VERSION = 32'h00000000; - parameter MCAP_GATE_IO_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_GATE_MEM_ENABLE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INPUT_GATE_DESIGN_SWITCH = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_EOS = "FALSE"; - parameter MCAP_INTERRUPT_ON_MCAP_ERROR = "FALSE"; - parameter [15:0] MCAP_VSEC_ID = 16'h0000; - parameter [11:0] MCAP_VSEC_LEN = 12'h02C; - parameter [3:0] MCAP_VSEC_REV = 4'h0; - parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [3:0] PF0_ARI_CAP_VER = 4'h1; - parameter [5:0] PF0_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF0_BAR0_CONTROL = 3'h4; - parameter [5:0] PF0_BAR1_APERTURE_SIZE = 6'h00; - parameter [2:0] PF0_BAR1_CONTROL = 3'h0; - parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR3_CONTROL = 3'h0; - parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_BAR5_CONTROL = 3'h0; - parameter [7:0] PF0_BIST_REGISTER = 8'h00; - parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF0_CLASS_CODE = 24'h000000; - parameter [15:0] PF0_DEVICE_ID = 16'h0000; - parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE"; - parameter PF0_DEV_CAP2_ARI_FORWARD_ENABLE = "FALSE"; - parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE"; - parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE"; - parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0; - parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE"; - parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0; - parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0; - parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE"; - parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE"; - parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF0_DPA_CAP_VER = 4'h1; - parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF0_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF0_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF0_INTERRUPT_PIN = 3'h1; - parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7; - parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7; - parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE"; - parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000; - parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000; - parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_LTR_CAP_VER = 4'h1; - parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00; - parameter PF0_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [31:0] PF0_PB_CAP_DATA_REG_D0 = 32'h00000000; - parameter [31:0] PF0_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; - parameter [31:0] PF0_PB_CAP_DATA_REG_D1 = 32'h00000000; - parameter [31:0] PF0_PB_CAP_DATA_REG_D3HOT = 32'h00000000; - parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000; - parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF0_PB_CAP_VER = 4'h1; - parameter [7:0] PF0_PM_CAP_ID = 8'h01; - parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00; - parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE"; - parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE"; - parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE"; - parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3; - parameter PF0_PM_CSR_NOSOFTRESET = "TRUE"; - parameter PF0_RBAR_CAP_ENABLE = "FALSE"; - parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF0_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF0_RBAR_CONTROL_INDEX0 = 3'h0; - parameter [2:0] PF0_RBAR_CONTROL_INDEX1 = 3'h0; - parameter [2:0] PF0_RBAR_CONTROL_INDEX2 = 3'h0; - parameter [4:0] PF0_RBAR_CONTROL_SIZE0 = 5'h00; - parameter [4:0] PF0_RBAR_CONTROL_SIZE1 = 5'h00; - parameter [4:0] PF0_RBAR_CONTROL_SIZE2 = 5'h00; - parameter [2:0] PF0_RBAR_NUM = 3'h1; - parameter [7:0] PF0_REVISION_ID = 8'h00; - parameter [11:0] PF0_SECONDARY_PCIE_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000; - parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF0_TPHR_CAP_ENABLE = "FALSE"; - parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF0_TPHR_CAP_VER = 4'h1; - parameter PF0_VC_CAP_ENABLE = "FALSE"; - parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000; - parameter [3:0] PF0_VC_CAP_VER = 4'h1; - parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF1_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF1_BAR0_CONTROL = 3'h4; - parameter [5:0] PF1_BAR1_APERTURE_SIZE = 6'h00; - parameter [2:0] PF1_BAR1_CONTROL = 3'h0; - parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR3_CONTROL = 3'h0; - parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_BAR5_CONTROL = 3'h0; - parameter [7:0] PF1_BIST_REGISTER = 8'h00; - parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF1_CLASS_CODE = 24'h000000; - parameter [15:0] PF1_DEVICE_ID = 16'h0000; - parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF1_DPA_CAP_VER = 4'h1; - parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF1_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF1_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF1_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00; - parameter PF1_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [31:0] PF1_PB_CAP_DATA_REG_D0 = 32'h00000000; - parameter [31:0] PF1_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; - parameter [31:0] PF1_PB_CAP_DATA_REG_D1 = 32'h00000000; - parameter [31:0] PF1_PB_CAP_DATA_REG_D3HOT = 32'h00000000; - parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000; - parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF1_PB_CAP_VER = 4'h1; - parameter [7:0] PF1_PM_CAP_ID = 8'h01; - parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3; - parameter PF1_RBAR_CAP_ENABLE = "FALSE"; - parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF1_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF1_RBAR_CONTROL_INDEX0 = 3'h0; - parameter [2:0] PF1_RBAR_CONTROL_INDEX1 = 3'h0; - parameter [2:0] PF1_RBAR_CONTROL_INDEX2 = 3'h0; - parameter [4:0] PF1_RBAR_CONTROL_SIZE0 = 5'h00; - parameter [4:0] PF1_RBAR_CONTROL_SIZE1 = 5'h00; - parameter [4:0] PF1_RBAR_CONTROL_SIZE2 = 5'h00; - parameter [2:0] PF1_RBAR_NUM = 3'h1; - parameter [7:0] PF1_REVISION_ID = 8'h00; - parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000; - parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF1_TPHR_CAP_ENABLE = "FALSE"; - parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF1_TPHR_CAP_VER = 4'h1; - parameter PF2_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF2_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF2_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF2_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF2_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF2_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF2_BAR0_CONTROL = 3'h4; - parameter [5:0] PF2_BAR1_APERTURE_SIZE = 6'h00; - parameter [2:0] PF2_BAR1_CONTROL = 3'h0; - parameter [4:0] PF2_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR3_CONTROL = 3'h0; - parameter [4:0] PF2_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_BAR5_CONTROL = 3'h0; - parameter [7:0] PF2_BIST_REGISTER = 8'h00; - parameter [7:0] PF2_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF2_CLASS_CODE = 24'h000000; - parameter [15:0] PF2_DEVICE_ID = 16'h0000; - parameter [2:0] PF2_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF2_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF2_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF2_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF2_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF2_DPA_CAP_VER = 4'h1; - parameter [11:0] PF2_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF2_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF2_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF2_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF2_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF2_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF2_MSI_CAP_NEXTPTR = 8'h00; - parameter PF2_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [31:0] PF2_PB_CAP_DATA_REG_D0 = 32'h00000000; - parameter [31:0] PF2_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; - parameter [31:0] PF2_PB_CAP_DATA_REG_D1 = 32'h00000000; - parameter [31:0] PF2_PB_CAP_DATA_REG_D3HOT = 32'h00000000; - parameter [11:0] PF2_PB_CAP_NEXTPTR = 12'h000; - parameter PF2_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF2_PB_CAP_VER = 4'h1; - parameter [7:0] PF2_PM_CAP_ID = 8'h01; - parameter [7:0] PF2_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] PF2_PM_CAP_VER_ID = 3'h3; - parameter PF2_RBAR_CAP_ENABLE = "FALSE"; - parameter [11:0] PF2_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF2_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF2_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF2_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF2_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF2_RBAR_CONTROL_INDEX0 = 3'h0; - parameter [2:0] PF2_RBAR_CONTROL_INDEX1 = 3'h0; - parameter [2:0] PF2_RBAR_CONTROL_INDEX2 = 3'h0; - parameter [4:0] PF2_RBAR_CONTROL_SIZE0 = 5'h00; - parameter [4:0] PF2_RBAR_CONTROL_SIZE1 = 5'h00; - parameter [4:0] PF2_RBAR_CONTROL_SIZE2 = 5'h00; - parameter [2:0] PF2_RBAR_NUM = 3'h1; - parameter [7:0] PF2_REVISION_ID = 8'h00; - parameter [4:0] PF2_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF2_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF2_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF2_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF2_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF2_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF2_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF2_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF2_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF2_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF2_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF2_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF2_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF2_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF2_SUBSYSTEM_ID = 16'h0000; - parameter PF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF2_TPHR_CAP_ENABLE = "FALSE"; - parameter PF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF2_TPHR_CAP_VER = 4'h1; - parameter PF3_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE"; - parameter PF3_AER_CAP_ECRC_GEN_CAPABLE = "FALSE"; - parameter [11:0] PF3_AER_CAP_NEXTPTR = 12'h000; - parameter [11:0] PF3_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] PF3_ARI_CAP_NEXT_FUNC = 8'h00; - parameter [5:0] PF3_BAR0_APERTURE_SIZE = 6'h03; - parameter [2:0] PF3_BAR0_CONTROL = 3'h4; - parameter [5:0] PF3_BAR1_APERTURE_SIZE = 6'h00; - parameter [2:0] PF3_BAR1_CONTROL = 3'h0; - parameter [4:0] PF3_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR3_CONTROL = 3'h0; - parameter [4:0] PF3_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_BAR5_CONTROL = 3'h0; - parameter [7:0] PF3_BIST_REGISTER = 8'h00; - parameter [7:0] PF3_CAPABILITY_POINTER = 8'h50; - parameter [23:0] PF3_CLASS_CODE = 24'h000000; - parameter [15:0] PF3_DEVICE_ID = 16'h0000; - parameter [2:0] PF3_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3; - parameter [11:0] PF3_DPA_CAP_NEXTPTR = 12'h000; - parameter [4:0] PF3_DPA_CAP_SUB_STATE_CONTROL = 5'h00; - parameter PF3_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE"; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00; - parameter [7:0] PF3_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00; - parameter [3:0] PF3_DPA_CAP_VER = 4'h1; - parameter [11:0] PF3_DSN_CAP_NEXTPTR = 12'h10C; - parameter [4:0] PF3_EXPANSION_ROM_APERTURE_SIZE = 5'h03; - parameter PF3_EXPANSION_ROM_ENABLE = "FALSE"; - parameter [7:0] PF3_INTERRUPT_LINE = 8'h00; - parameter [2:0] PF3_INTERRUPT_PIN = 3'h1; - parameter [7:0] PF3_MSIX_CAP_NEXTPTR = 8'h00; - parameter integer PF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer PF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] PF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] PF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer PF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] PF3_MSI_CAP_NEXTPTR = 8'h00; - parameter PF3_MSI_CAP_PERVECMASKCAP = "FALSE"; - parameter [31:0] PF3_PB_CAP_DATA_REG_D0 = 32'h00000000; - parameter [31:0] PF3_PB_CAP_DATA_REG_D0_SUSTAINED = 32'h00000000; - parameter [31:0] PF3_PB_CAP_DATA_REG_D1 = 32'h00000000; - parameter [31:0] PF3_PB_CAP_DATA_REG_D3HOT = 32'h00000000; - parameter [11:0] PF3_PB_CAP_NEXTPTR = 12'h000; - parameter PF3_PB_CAP_SYSTEM_ALLOCATED = "FALSE"; - parameter [3:0] PF3_PB_CAP_VER = 4'h1; - parameter [7:0] PF3_PM_CAP_ID = 8'h01; - parameter [7:0] PF3_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] PF3_PM_CAP_VER_ID = 3'h3; - parameter PF3_RBAR_CAP_ENABLE = "FALSE"; - parameter [11:0] PF3_RBAR_CAP_NEXTPTR = 12'h000; - parameter [19:0] PF3_RBAR_CAP_SIZE0 = 20'h00000; - parameter [19:0] PF3_RBAR_CAP_SIZE1 = 20'h00000; - parameter [19:0] PF3_RBAR_CAP_SIZE2 = 20'h00000; - parameter [3:0] PF3_RBAR_CAP_VER = 4'h1; - parameter [2:0] PF3_RBAR_CONTROL_INDEX0 = 3'h0; - parameter [2:0] PF3_RBAR_CONTROL_INDEX1 = 3'h0; - parameter [2:0] PF3_RBAR_CONTROL_INDEX2 = 3'h0; - parameter [4:0] PF3_RBAR_CONTROL_SIZE0 = 5'h00; - parameter [4:0] PF3_RBAR_CONTROL_SIZE1 = 5'h00; - parameter [4:0] PF3_RBAR_CONTROL_SIZE2 = 5'h00; - parameter [2:0] PF3_RBAR_NUM = 3'h1; - parameter [7:0] PF3_REVISION_ID = 8'h00; - parameter [4:0] PF3_SRIOV_BAR0_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR0_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR1_APERTURE_SIZE = 5'h00; - parameter [2:0] PF3_SRIOV_BAR1_CONTROL = 3'h0; - parameter [4:0] PF3_SRIOV_BAR2_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR2_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR3_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR3_CONTROL = 3'h0; - parameter [4:0] PF3_SRIOV_BAR4_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR4_CONTROL = 3'h4; - parameter [4:0] PF3_SRIOV_BAR5_APERTURE_SIZE = 5'h03; - parameter [2:0] PF3_SRIOV_BAR5_CONTROL = 3'h0; - parameter [15:0] PF3_SRIOV_CAP_INITIAL_VF = 16'h0000; - parameter [11:0] PF3_SRIOV_CAP_NEXTPTR = 12'h000; - parameter [15:0] PF3_SRIOV_CAP_TOTAL_VF = 16'h0000; - parameter [3:0] PF3_SRIOV_CAP_VER = 4'h1; - parameter [15:0] PF3_SRIOV_FIRST_VF_OFFSET = 16'h0000; - parameter [15:0] PF3_SRIOV_FUNC_DEP_LINK = 16'h0000; - parameter [31:0] PF3_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000; - parameter [15:0] PF3_SRIOV_VF_DEVICE_ID = 16'h0000; - parameter [15:0] PF3_SUBSYSTEM_ID = 16'h0000; - parameter PF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter PF3_TPHR_CAP_ENABLE = "FALSE"; - parameter PF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] PF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] PF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] PF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] PF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] PF3_TPHR_CAP_VER = 4'h1; - parameter PL_DISABLE_AUTO_EQ_SPEED_CHANGE_TO_GEN3 = "FALSE"; - parameter PL_DISABLE_AUTO_SPEED_CHANGE_TO_GEN2 = "FALSE"; - parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE"; - parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE"; - parameter PL_DISABLE_GEN3_LFSR_UPDATE_ON_SKP = "TRUE"; - parameter PL_DISABLE_RETRAIN_ON_FRAMING_ERROR = "FALSE"; - parameter PL_DISABLE_SCRAMBLING = "FALSE"; - parameter PL_DISABLE_SYNC_HEADER_FRAMING_ERROR = "FALSE"; - parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE"; - parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE"; - parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE"; - parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02; - parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1; - parameter PL_EQ_BYPASS_PHASE23 = "FALSE"; - parameter [2:0] PL_EQ_DEFAULT_GEN3_RX_PRESET_HINT = 3'h3; - parameter [3:0] PL_EQ_DEFAULT_GEN3_TX_PRESET = 4'h4; - parameter PL_EQ_PHASE01_RX_ADAPT = "FALSE"; - parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE"; - parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00; - parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00; - parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4; - parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8; - parameter integer PL_N_FTS_COMCLK_GEN1 = 255; - parameter integer PL_N_FTS_COMCLK_GEN2 = 255; - parameter integer PL_N_FTS_COMCLK_GEN3 = 255; - parameter integer PL_N_FTS_GEN1 = 255; - parameter integer PL_N_FTS_GEN2 = 255; - parameter integer PL_N_FTS_GEN3 = 255; - parameter PL_REPORT_ALL_PHY_ERRORS = "TRUE"; - parameter PL_SIM_FAST_LINK_TRAINING = "FALSE"; - parameter PL_UPSTREAM_FACING = "TRUE"; - parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC; - parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000; - parameter PM_ENABLE_L23_ENTRY = "FALSE"; - parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE"; - parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000; - parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0; - parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064; - parameter [31:0] SIM_JTAG_IDCODE = 32'h00000000; - parameter SIM_VERSION = "1.0"; - parameter integer SPARE_BIT0 = 0; - parameter integer SPARE_BIT1 = 0; - parameter integer SPARE_BIT2 = 0; - parameter integer SPARE_BIT3 = 0; - parameter integer SPARE_BIT4 = 0; - parameter integer SPARE_BIT5 = 0; - parameter integer SPARE_BIT6 = 0; - parameter integer SPARE_BIT7 = 0; - parameter integer SPARE_BIT8 = 0; - parameter [7:0] SPARE_BYTE0 = 8'h00; - parameter [7:0] SPARE_BYTE1 = 8'h00; - parameter [7:0] SPARE_BYTE2 = 8'h00; - parameter [7:0] SPARE_BYTE3 = 8'h00; - parameter [31:0] SPARE_WORD0 = 32'h00000000; - parameter [31:0] SPARE_WORD1 = 32'h00000000; - parameter [31:0] SPARE_WORD2 = 32'h00000000; - parameter [31:0] SPARE_WORD3 = 32'h00000000; - parameter SRIOV_CAP_ENABLE = "FALSE"; - parameter TL_COMPLETION_RAM_SIZE_16K = "TRUE"; - parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20; - parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h2FAF080; - parameter [11:0] TL_CREDITS_CD = 12'h3E0; - parameter [7:0] TL_CREDITS_CH = 8'h20; - parameter [11:0] TL_CREDITS_NPD = 12'h028; - parameter [7:0] TL_CREDITS_NPH = 8'h20; - parameter [11:0] TL_CREDITS_PD = 12'h198; - parameter [7:0] TL_CREDITS_PH = 8'h20; - parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE"; - parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE"; - parameter TL_LEGACY_MODE_ENABLE = "FALSE"; - parameter [1:0] TL_PF_ENABLE_REG = 2'h0; - parameter TL_TX_MUX_STRICT_PRIORITY = "TRUE"; - parameter TWO_LAYER_MODE_DLCMSM_ENABLE = "TRUE"; - parameter TWO_LAYER_MODE_ENABLE = "FALSE"; - parameter TWO_LAYER_MODE_WIDTH_256 = "TRUE"; - parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000; - parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50; - parameter integer VF0_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF0_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF0_PM_CAP_ID = 8'h01; - parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3; - parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF0_TPHR_CAP_ENABLE = "FALSE"; - parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF0_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF1_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF1_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF1_PM_CAP_ID = 8'h01; - parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3; - parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF1_TPHR_CAP_ENABLE = "FALSE"; - parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF1_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF2_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF2_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF2_PM_CAP_ID = 8'h01; - parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3; - parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF2_TPHR_CAP_ENABLE = "FALSE"; - parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF2_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF3_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF3_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF3_PM_CAP_ID = 8'h01; - parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3; - parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF3_TPHR_CAP_ENABLE = "FALSE"; - parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF3_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF4_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF4_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF4_PM_CAP_ID = 8'h01; - parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3; - parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF4_TPHR_CAP_ENABLE = "FALSE"; - parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF4_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF5_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF5_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF5_PM_CAP_ID = 8'h01; - parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3; - parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF5_TPHR_CAP_ENABLE = "FALSE"; - parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF5_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF6_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF6_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF6_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF6_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF6_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF6_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF6_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF6_PM_CAP_ID = 8'h01; - parameter [7:0] VF6_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF6_PM_CAP_VER_ID = 3'h3; - parameter VF6_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF6_TPHR_CAP_ENABLE = "FALSE"; - parameter VF6_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF6_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF6_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF6_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF6_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF6_TPHR_CAP_VER = 4'h1; - parameter [11:0] VF7_ARI_CAP_NEXTPTR = 12'h000; - parameter integer VF7_MSIX_CAP_PBA_BIR = 0; - parameter [28:0] VF7_MSIX_CAP_PBA_OFFSET = 29'h00000050; - parameter integer VF7_MSIX_CAP_TABLE_BIR = 0; - parameter [28:0] VF7_MSIX_CAP_TABLE_OFFSET = 29'h00000040; - parameter [10:0] VF7_MSIX_CAP_TABLE_SIZE = 11'h000; - parameter integer VF7_MSI_CAP_MULTIMSGCAP = 0; - parameter [7:0] VF7_PM_CAP_ID = 8'h01; - parameter [7:0] VF7_PM_CAP_NEXTPTR = 8'h00; - parameter [2:0] VF7_PM_CAP_VER_ID = 3'h3; - parameter VF7_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE"; - parameter VF7_TPHR_CAP_ENABLE = "FALSE"; - parameter VF7_TPHR_CAP_INT_VEC_MODE = "TRUE"; - parameter [11:0] VF7_TPHR_CAP_NEXTPTR = 12'h000; - parameter [2:0] VF7_TPHR_CAP_ST_MODE_SEL = 3'h0; - parameter [1:0] VF7_TPHR_CAP_ST_TABLE_LOC = 2'h0; - parameter [10:0] VF7_TPHR_CAP_ST_TABLE_SIZE = 11'h000; - parameter [3:0] VF7_TPHR_CAP_VER = 4'h1; - output [2:0] CFGCURRENTSPEED; - output [3:0] CFGDPASUBSTATECHANGE; - output CFGERRCOROUT; - output CFGERRFATALOUT; - output CFGERRNONFATALOUT; - output [7:0] CFGEXTFUNCTIONNUMBER; - output CFGEXTREADRECEIVED; - output [9:0] CFGEXTREGISTERNUMBER; - output [3:0] CFGEXTWRITEBYTEENABLE; - output [31:0] CFGEXTWRITEDATA; - output CFGEXTWRITERECEIVED; - output [11:0] CFGFCCPLD; - output [7:0] CFGFCCPLH; - output [11:0] CFGFCNPD; - output [7:0] CFGFCNPH; - output [11:0] CFGFCPD; - output [7:0] CFGFCPH; - output [3:0] CFGFLRINPROCESS; - output [11:0] CFGFUNCTIONPOWERSTATE; - output [15:0] CFGFUNCTIONSTATUS; - output CFGHOTRESETOUT; - output [31:0] CFGINTERRUPTMSIDATA; - output [3:0] CFGINTERRUPTMSIENABLE; - output CFGINTERRUPTMSIFAIL; - output CFGINTERRUPTMSIMASKUPDATE; - output [11:0] CFGINTERRUPTMSIMMENABLE; - output CFGINTERRUPTMSISENT; - output [7:0] CFGINTERRUPTMSIVFENABLE; - output [3:0] CFGINTERRUPTMSIXENABLE; - output CFGINTERRUPTMSIXFAIL; - output [3:0] CFGINTERRUPTMSIXMASK; - output CFGINTERRUPTMSIXSENT; - output [7:0] CFGINTERRUPTMSIXVFENABLE; - output [7:0] CFGINTERRUPTMSIXVFMASK; - output CFGINTERRUPTSENT; - output [1:0] CFGLINKPOWERSTATE; - output CFGLOCALERROR; - output CFGLTRENABLE; - output [5:0] CFGLTSSMSTATE; - output [2:0] CFGMAXPAYLOAD; - output [2:0] CFGMAXREADREQ; - output [31:0] CFGMGMTREADDATA; - output CFGMGMTREADWRITEDONE; - output CFGMSGRECEIVED; - output [7:0] CFGMSGRECEIVEDDATA; - output [4:0] CFGMSGRECEIVEDTYPE; - output CFGMSGTRANSMITDONE; - output [3:0] CFGNEGOTIATEDWIDTH; - output [1:0] CFGOBFFENABLE; - output [15:0] CFGPERFUNCSTATUSDATA; - output CFGPERFUNCTIONUPDATEDONE; - output CFGPHYLINKDOWN; - output [1:0] CFGPHYLINKSTATUS; - output CFGPLSTATUSCHANGE; - output CFGPOWERSTATECHANGEINTERRUPT; - output [3:0] CFGRCBSTATUS; - output [3:0] CFGTPHFUNCTIONNUM; - output [3:0] CFGTPHREQUESTERENABLE; - output [11:0] CFGTPHSTMODE; - output [4:0] CFGTPHSTTADDRESS; - output CFGTPHSTTREADENABLE; - output [3:0] CFGTPHSTTWRITEBYTEVALID; - output [31:0] CFGTPHSTTWRITEDATA; - output CFGTPHSTTWRITEENABLE; - output [7:0] CFGVFFLRINPROCESS; - output [23:0] CFGVFPOWERSTATE; - output [15:0] CFGVFSTATUS; - output [7:0] CFGVFTPHREQUESTERENABLE; - output [23:0] CFGVFTPHSTMODE; - output CONFMCAPDESIGNSWITCH; - output CONFMCAPEOS; - output CONFMCAPINUSEBYPCIE; - output CONFREQREADY; - output [31:0] CONFRESPRDATA; - output CONFRESPVALID; - output [15:0] DBGDATAOUT; - output DBGMCAPCSB; - output [31:0] DBGMCAPDATA; - output DBGMCAPEOS; - output DBGMCAPERROR; - output DBGMCAPMODE; - output DBGMCAPRDATAVALID; - output DBGMCAPRDWRB; - output DBGMCAPRESET; - output DBGPLDATABLOCKRECEIVEDAFTEREDS; - output DBGPLGEN3FRAMINGERRORDETECTED; - output DBGPLGEN3SYNCHEADERERRORDETECTED; - output [7:0] DBGPLINFERREDRXELECTRICALIDLE; - output [15:0] DRPDO; - output DRPRDY; - output LL2LMMASTERTLPSENT0; - output LL2LMMASTERTLPSENT1; - output [3:0] LL2LMMASTERTLPSENTTLPID0; - output [3:0] LL2LMMASTERTLPSENTTLPID1; - output [255:0] LL2LMMAXISRXTDATA; - output [17:0] LL2LMMAXISRXTUSER; - output [7:0] LL2LMMAXISRXTVALID; - output [7:0] LL2LMSAXISTXTREADY; - output [255:0] MAXISCQTDATA; - output [7:0] MAXISCQTKEEP; - output MAXISCQTLAST; - output [84:0] MAXISCQTUSER; - output MAXISCQTVALID; - output [255:0] MAXISRCTDATA; - output [7:0] MAXISRCTKEEP; - output MAXISRCTLAST; - output [74:0] MAXISRCTUSER; - output MAXISRCTVALID; - output [9:0] MICOMPLETIONRAMREADADDRESSAL; - output [9:0] MICOMPLETIONRAMREADADDRESSAU; - output [9:0] MICOMPLETIONRAMREADADDRESSBL; - output [9:0] MICOMPLETIONRAMREADADDRESSBU; - output [3:0] MICOMPLETIONRAMREADENABLEL; - output [3:0] MICOMPLETIONRAMREADENABLEU; - output [9:0] MICOMPLETIONRAMWRITEADDRESSAL; - output [9:0] MICOMPLETIONRAMWRITEADDRESSAU; - output [9:0] MICOMPLETIONRAMWRITEADDRESSBL; - output [9:0] MICOMPLETIONRAMWRITEADDRESSBU; - output [71:0] MICOMPLETIONRAMWRITEDATAL; - output [71:0] MICOMPLETIONRAMWRITEDATAU; - output [3:0] MICOMPLETIONRAMWRITEENABLEL; - output [3:0] MICOMPLETIONRAMWRITEENABLEU; - output [8:0] MIREPLAYRAMADDRESS; - output [1:0] MIREPLAYRAMREADENABLE; - output [143:0] MIREPLAYRAMWRITEDATA; - output [1:0] MIREPLAYRAMWRITEENABLE; - output [8:0] MIREQUESTRAMREADADDRESSA; - output [8:0] MIREQUESTRAMREADADDRESSB; - output [3:0] MIREQUESTRAMREADENABLE; - output [8:0] MIREQUESTRAMWRITEADDRESSA; - output [8:0] MIREQUESTRAMWRITEADDRESSB; - output [143:0] MIREQUESTRAMWRITEDATA; - output [3:0] MIREQUESTRAMWRITEENABLE; - output [5:0] PCIECQNPREQCOUNT; - output PCIEPERST0B; - output PCIEPERST1B; - output [3:0] PCIERQSEQNUM; - output PCIERQSEQNUMVLD; - output [5:0] PCIERQTAG; - output [1:0] PCIERQTAGAV; - output PCIERQTAGVLD; - output [1:0] PCIETFCNPDAV; - output [1:0] PCIETFCNPHAV; - output [1:0] PIPERX0EQCONTROL; - output [5:0] PIPERX0EQLPLFFS; - output [3:0] PIPERX0EQLPTXPRESET; - output [2:0] PIPERX0EQPRESET; - output PIPERX0POLARITY; - output [1:0] PIPERX1EQCONTROL; - output [5:0] PIPERX1EQLPLFFS; - output [3:0] PIPERX1EQLPTXPRESET; - output [2:0] PIPERX1EQPRESET; - output PIPERX1POLARITY; - output [1:0] PIPERX2EQCONTROL; - output [5:0] PIPERX2EQLPLFFS; - output [3:0] PIPERX2EQLPTXPRESET; - output [2:0] PIPERX2EQPRESET; - output PIPERX2POLARITY; - output [1:0] PIPERX3EQCONTROL; - output [5:0] PIPERX3EQLPLFFS; - output [3:0] PIPERX3EQLPTXPRESET; - output [2:0] PIPERX3EQPRESET; - output PIPERX3POLARITY; - output [1:0] PIPERX4EQCONTROL; - output [5:0] PIPERX4EQLPLFFS; - output [3:0] PIPERX4EQLPTXPRESET; - output [2:0] PIPERX4EQPRESET; - output PIPERX4POLARITY; - output [1:0] PIPERX5EQCONTROL; - output [5:0] PIPERX5EQLPLFFS; - output [3:0] PIPERX5EQLPTXPRESET; - output [2:0] PIPERX5EQPRESET; - output PIPERX5POLARITY; - output [1:0] PIPERX6EQCONTROL; - output [5:0] PIPERX6EQLPLFFS; - output [3:0] PIPERX6EQLPTXPRESET; - output [2:0] PIPERX6EQPRESET; - output PIPERX6POLARITY; - output [1:0] PIPERX7EQCONTROL; - output [5:0] PIPERX7EQLPLFFS; - output [3:0] PIPERX7EQLPTXPRESET; - output [2:0] PIPERX7EQPRESET; - output PIPERX7POLARITY; - output [1:0] PIPETX0CHARISK; - output PIPETX0COMPLIANCE; - output [31:0] PIPETX0DATA; - output PIPETX0DATAVALID; - output PIPETX0DEEMPH; - output PIPETX0ELECIDLE; - output [1:0] PIPETX0EQCONTROL; - output [5:0] PIPETX0EQDEEMPH; - output [3:0] PIPETX0EQPRESET; - output [2:0] PIPETX0MARGIN; - output [1:0] PIPETX0POWERDOWN; - output [1:0] PIPETX0RATE; - output PIPETX0RCVRDET; - output PIPETX0RESET; - output PIPETX0STARTBLOCK; - output PIPETX0SWING; - output [1:0] PIPETX0SYNCHEADER; - output [1:0] PIPETX1CHARISK; - output PIPETX1COMPLIANCE; - output [31:0] PIPETX1DATA; - output PIPETX1DATAVALID; - output PIPETX1DEEMPH; - output PIPETX1ELECIDLE; - output [1:0] PIPETX1EQCONTROL; - output [5:0] PIPETX1EQDEEMPH; - output [3:0] PIPETX1EQPRESET; - output [2:0] PIPETX1MARGIN; - output [1:0] PIPETX1POWERDOWN; - output [1:0] PIPETX1RATE; - output PIPETX1RCVRDET; - output PIPETX1RESET; - output PIPETX1STARTBLOCK; - output PIPETX1SWING; - output [1:0] PIPETX1SYNCHEADER; - output [1:0] PIPETX2CHARISK; - output PIPETX2COMPLIANCE; - output [31:0] PIPETX2DATA; - output PIPETX2DATAVALID; - output PIPETX2DEEMPH; - output PIPETX2ELECIDLE; - output [1:0] PIPETX2EQCONTROL; - output [5:0] PIPETX2EQDEEMPH; - output [3:0] PIPETX2EQPRESET; - output [2:0] PIPETX2MARGIN; - output [1:0] PIPETX2POWERDOWN; - output [1:0] PIPETX2RATE; - output PIPETX2RCVRDET; - output PIPETX2RESET; - output PIPETX2STARTBLOCK; - output PIPETX2SWING; - output [1:0] PIPETX2SYNCHEADER; - output [1:0] PIPETX3CHARISK; - output PIPETX3COMPLIANCE; - output [31:0] PIPETX3DATA; - output PIPETX3DATAVALID; - output PIPETX3DEEMPH; - output PIPETX3ELECIDLE; - output [1:0] PIPETX3EQCONTROL; - output [5:0] PIPETX3EQDEEMPH; - output [3:0] PIPETX3EQPRESET; - output [2:0] PIPETX3MARGIN; - output [1:0] PIPETX3POWERDOWN; - output [1:0] PIPETX3RATE; - output PIPETX3RCVRDET; - output PIPETX3RESET; - output PIPETX3STARTBLOCK; - output PIPETX3SWING; - output [1:0] PIPETX3SYNCHEADER; - output [1:0] PIPETX4CHARISK; - output PIPETX4COMPLIANCE; - output [31:0] PIPETX4DATA; - output PIPETX4DATAVALID; - output PIPETX4DEEMPH; - output PIPETX4ELECIDLE; - output [1:0] PIPETX4EQCONTROL; - output [5:0] PIPETX4EQDEEMPH; - output [3:0] PIPETX4EQPRESET; - output [2:0] PIPETX4MARGIN; - output [1:0] PIPETX4POWERDOWN; - output [1:0] PIPETX4RATE; - output PIPETX4RCVRDET; - output PIPETX4RESET; - output PIPETX4STARTBLOCK; - output PIPETX4SWING; - output [1:0] PIPETX4SYNCHEADER; - output [1:0] PIPETX5CHARISK; - output PIPETX5COMPLIANCE; - output [31:0] PIPETX5DATA; - output PIPETX5DATAVALID; - output PIPETX5DEEMPH; - output PIPETX5ELECIDLE; - output [1:0] PIPETX5EQCONTROL; - output [5:0] PIPETX5EQDEEMPH; - output [3:0] PIPETX5EQPRESET; - output [2:0] PIPETX5MARGIN; - output [1:0] PIPETX5POWERDOWN; - output [1:0] PIPETX5RATE; - output PIPETX5RCVRDET; - output PIPETX5RESET; - output PIPETX5STARTBLOCK; - output PIPETX5SWING; - output [1:0] PIPETX5SYNCHEADER; - output [1:0] PIPETX6CHARISK; - output PIPETX6COMPLIANCE; - output [31:0] PIPETX6DATA; - output PIPETX6DATAVALID; - output PIPETX6DEEMPH; - output PIPETX6ELECIDLE; - output [1:0] PIPETX6EQCONTROL; - output [5:0] PIPETX6EQDEEMPH; - output [3:0] PIPETX6EQPRESET; - output [2:0] PIPETX6MARGIN; - output [1:0] PIPETX6POWERDOWN; - output [1:0] PIPETX6RATE; - output PIPETX6RCVRDET; - output PIPETX6RESET; - output PIPETX6STARTBLOCK; - output PIPETX6SWING; - output [1:0] PIPETX6SYNCHEADER; - output [1:0] PIPETX7CHARISK; - output PIPETX7COMPLIANCE; - output [31:0] PIPETX7DATA; - output PIPETX7DATAVALID; - output PIPETX7DEEMPH; - output PIPETX7ELECIDLE; - output [1:0] PIPETX7EQCONTROL; - output [5:0] PIPETX7EQDEEMPH; - output [3:0] PIPETX7EQPRESET; - output [2:0] PIPETX7MARGIN; - output [1:0] PIPETX7POWERDOWN; - output [1:0] PIPETX7RATE; - output PIPETX7RCVRDET; - output PIPETX7RESET; - output PIPETX7STARTBLOCK; - output PIPETX7SWING; - output [1:0] PIPETX7SYNCHEADER; - output PLEQINPROGRESS; - output [1:0] PLEQPHASE; - output [3:0] SAXISCCTREADY; - output [3:0] SAXISRQTREADY; - output [31:0] SPAREOUT; - input CFGCONFIGSPACEENABLE; - input [15:0] CFGDEVID; - input [7:0] CFGDSBUSNUMBER; - input [4:0] CFGDSDEVICENUMBER; - input [2:0] CFGDSFUNCTIONNUMBER; - input [63:0] CFGDSN; - input [7:0] CFGDSPORTNUMBER; - input CFGERRCORIN; - input CFGERRUNCORIN; - input [31:0] CFGEXTREADDATA; - input CFGEXTREADDATAVALID; - input [2:0] CFGFCSEL; - input [3:0] CFGFLRDONE; - input CFGHOTRESETIN; - input [3:0] CFGINTERRUPTINT; - input [2:0] CFGINTERRUPTMSIATTR; - input [3:0] CFGINTERRUPTMSIFUNCTIONNUMBER; - input [31:0] CFGINTERRUPTMSIINT; - input [31:0] CFGINTERRUPTMSIPENDINGSTATUS; - input CFGINTERRUPTMSIPENDINGSTATUSDATAENABLE; - input [3:0] CFGINTERRUPTMSIPENDINGSTATUSFUNCTIONNUM; - input [3:0] CFGINTERRUPTMSISELECT; - input CFGINTERRUPTMSITPHPRESENT; - input [8:0] CFGINTERRUPTMSITPHSTTAG; - input [1:0] CFGINTERRUPTMSITPHTYPE; - input [63:0] CFGINTERRUPTMSIXADDRESS; - input [31:0] CFGINTERRUPTMSIXDATA; - input CFGINTERRUPTMSIXINT; - input [3:0] CFGINTERRUPTPENDING; - input CFGLINKTRAININGENABLE; - input [18:0] CFGMGMTADDR; - input [3:0] CFGMGMTBYTEENABLE; - input CFGMGMTREAD; - input CFGMGMTTYPE1CFGREGACCESS; - input CFGMGMTWRITE; - input [31:0] CFGMGMTWRITEDATA; - input CFGMSGTRANSMIT; - input [31:0] CFGMSGTRANSMITDATA; - input [2:0] CFGMSGTRANSMITTYPE; - input [2:0] CFGPERFUNCSTATUSCONTROL; - input [3:0] CFGPERFUNCTIONNUMBER; - input CFGPERFUNCTIONOUTPUTREQUEST; - input CFGPOWERSTATECHANGEACK; - input CFGREQPMTRANSITIONL23READY; - input [7:0] CFGREVID; - input [15:0] CFGSUBSYSID; - input [15:0] CFGSUBSYSVENDID; - input [31:0] CFGTPHSTTREADDATA; - input CFGTPHSTTREADDATAVALID; - input [15:0] CFGVENDID; - input [7:0] CFGVFFLRDONE; - input CONFMCAPREQUESTBYCONF; - input [31:0] CONFREQDATA; - input [3:0] CONFREQREGNUM; - input [1:0] CONFREQTYPE; - input CONFREQVALID; - input CORECLK; - input CORECLKMICOMPLETIONRAML; - input CORECLKMICOMPLETIONRAMU; - input CORECLKMIREPLAYRAM; - input CORECLKMIREQUESTRAM; - input DBGCFGLOCALMGMTREGOVERRIDE; - input [3:0] DBGDATASEL; - input [9:0] DRPADDR; - input DRPCLK; - input [15:0] DRPDI; - input DRPEN; - input DRPWE; - input [13:0] LL2LMSAXISTXTUSER; - input LL2LMSAXISTXTVALID; - input [3:0] LL2LMTXTLPID0; - input [3:0] LL2LMTXTLPID1; - input [21:0] MAXISCQTREADY; - input [21:0] MAXISRCTREADY; - input MCAPCLK; - input MCAPPERST0B; - input MCAPPERST1B; - input MGMTRESETN; - input MGMTSTICKYRESETN; - input [143:0] MICOMPLETIONRAMREADDATA; - input [143:0] MIREPLAYRAMREADDATA; - input [143:0] MIREQUESTRAMREADDATA; - input PCIECQNPREQ; - input PIPECLK; - input [5:0] PIPEEQFS; - input [5:0] PIPEEQLF; - input PIPERESETN; - input [1:0] PIPERX0CHARISK; - input [31:0] PIPERX0DATA; - input PIPERX0DATAVALID; - input PIPERX0ELECIDLE; - input PIPERX0EQDONE; - input PIPERX0EQLPADAPTDONE; - input PIPERX0EQLPLFFSSEL; - input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET; - input PIPERX0PHYSTATUS; - input PIPERX0STARTBLOCK; - input [2:0] PIPERX0STATUS; - input [1:0] PIPERX0SYNCHEADER; - input PIPERX0VALID; - input [1:0] PIPERX1CHARISK; - input [31:0] PIPERX1DATA; - input PIPERX1DATAVALID; - input PIPERX1ELECIDLE; - input PIPERX1EQDONE; - input PIPERX1EQLPADAPTDONE; - input PIPERX1EQLPLFFSSEL; - input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET; - input PIPERX1PHYSTATUS; - input PIPERX1STARTBLOCK; - input [2:0] PIPERX1STATUS; - input [1:0] PIPERX1SYNCHEADER; - input PIPERX1VALID; - input [1:0] PIPERX2CHARISK; - input [31:0] PIPERX2DATA; - input PIPERX2DATAVALID; - input PIPERX2ELECIDLE; - input PIPERX2EQDONE; - input PIPERX2EQLPADAPTDONE; - input PIPERX2EQLPLFFSSEL; - input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET; - input PIPERX2PHYSTATUS; - input PIPERX2STARTBLOCK; - input [2:0] PIPERX2STATUS; - input [1:0] PIPERX2SYNCHEADER; - input PIPERX2VALID; - input [1:0] PIPERX3CHARISK; - input [31:0] PIPERX3DATA; - input PIPERX3DATAVALID; - input PIPERX3ELECIDLE; - input PIPERX3EQDONE; - input PIPERX3EQLPADAPTDONE; - input PIPERX3EQLPLFFSSEL; - input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET; - input PIPERX3PHYSTATUS; - input PIPERX3STARTBLOCK; - input [2:0] PIPERX3STATUS; - input [1:0] PIPERX3SYNCHEADER; - input PIPERX3VALID; - input [1:0] PIPERX4CHARISK; - input [31:0] PIPERX4DATA; - input PIPERX4DATAVALID; - input PIPERX4ELECIDLE; - input PIPERX4EQDONE; - input PIPERX4EQLPADAPTDONE; - input PIPERX4EQLPLFFSSEL; - input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET; - input PIPERX4PHYSTATUS; - input PIPERX4STARTBLOCK; - input [2:0] PIPERX4STATUS; - input [1:0] PIPERX4SYNCHEADER; - input PIPERX4VALID; - input [1:0] PIPERX5CHARISK; - input [31:0] PIPERX5DATA; - input PIPERX5DATAVALID; - input PIPERX5ELECIDLE; - input PIPERX5EQDONE; - input PIPERX5EQLPADAPTDONE; - input PIPERX5EQLPLFFSSEL; - input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET; - input PIPERX5PHYSTATUS; - input PIPERX5STARTBLOCK; - input [2:0] PIPERX5STATUS; - input [1:0] PIPERX5SYNCHEADER; - input PIPERX5VALID; - input [1:0] PIPERX6CHARISK; - input [31:0] PIPERX6DATA; - input PIPERX6DATAVALID; - input PIPERX6ELECIDLE; - input PIPERX6EQDONE; - input PIPERX6EQLPADAPTDONE; - input PIPERX6EQLPLFFSSEL; - input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET; - input PIPERX6PHYSTATUS; - input PIPERX6STARTBLOCK; - input [2:0] PIPERX6STATUS; - input [1:0] PIPERX6SYNCHEADER; - input PIPERX6VALID; - input [1:0] PIPERX7CHARISK; - input [31:0] PIPERX7DATA; - input PIPERX7DATAVALID; - input PIPERX7ELECIDLE; - input PIPERX7EQDONE; - input PIPERX7EQLPADAPTDONE; - input PIPERX7EQLPLFFSSEL; - input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET; - input PIPERX7PHYSTATUS; - input PIPERX7STARTBLOCK; - input [2:0] PIPERX7STATUS; - input [1:0] PIPERX7SYNCHEADER; - input PIPERX7VALID; - input [17:0] PIPETX0EQCOEFF; - input PIPETX0EQDONE; - input [17:0] PIPETX1EQCOEFF; - input PIPETX1EQDONE; - input [17:0] PIPETX2EQCOEFF; - input PIPETX2EQDONE; - input [17:0] PIPETX3EQCOEFF; - input PIPETX3EQDONE; - input [17:0] PIPETX4EQCOEFF; - input PIPETX4EQDONE; - input [17:0] PIPETX5EQCOEFF; - input PIPETX5EQDONE; - input [17:0] PIPETX6EQCOEFF; - input PIPETX6EQDONE; - input [17:0] PIPETX7EQCOEFF; - input PIPETX7EQDONE; - input PLEQRESETEIEOSCOUNT; - input PLGEN2UPSTREAMPREFERDEEMPH; - input RESETN; - input [255:0] SAXISCCTDATA; - input [7:0] SAXISCCTKEEP; - input SAXISCCTLAST; - input [32:0] SAXISCCTUSER; - input SAXISCCTVALID; - input [255:0] SAXISRQTDATA; - input [7:0] SAXISRQTKEEP; - input SAXISRQTLAST; - input [59:0] SAXISRQTUSER; - input SAXISRQTVALID; - input [31:0] SPAREIN; - input USERCLK; -endmodule - -module SYSMONE1 (...); - parameter [15:0] INIT_40 = 16'h0; - parameter [15:0] INIT_41 = 16'h0; - parameter [15:0] INIT_42 = 16'h0; - parameter [15:0] INIT_43 = 16'h0; - parameter [15:0] INIT_44 = 16'h0; - parameter [15:0] INIT_45 = 16'h0; - parameter [15:0] INIT_46 = 16'h0; - parameter [15:0] INIT_47 = 16'h0; - parameter [15:0] INIT_48 = 16'h0; - parameter [15:0] INIT_49 = 16'h0; - parameter [15:0] INIT_4A = 16'h0; - parameter [15:0] INIT_4B = 16'h0; - parameter [15:0] INIT_4C = 16'h0; - parameter [15:0] INIT_4D = 16'h0; - parameter [15:0] INIT_4E = 16'h0; - parameter [15:0] INIT_4F = 16'h0; - parameter [15:0] INIT_50 = 16'h0; - parameter [15:0] INIT_51 = 16'h0; - parameter [15:0] INIT_52 = 16'h0; - parameter [15:0] INIT_53 = 16'h0; - parameter [15:0] INIT_54 = 16'h0; - parameter [15:0] INIT_55 = 16'h0; - parameter [15:0] INIT_56 = 16'h0; - parameter [15:0] INIT_57 = 16'h0; - parameter [15:0] INIT_58 = 16'h0; - parameter [15:0] INIT_59 = 16'h0; - parameter [15:0] INIT_5A = 16'h0; - parameter [15:0] INIT_5B = 16'h0; - parameter [15:0] INIT_5C = 16'h0; - parameter [15:0] INIT_5D = 16'h0; - parameter [15:0] INIT_5E = 16'h0; - parameter [15:0] INIT_5F = 16'h0; - parameter [15:0] INIT_60 = 16'h0; - parameter [15:0] INIT_61 = 16'h0; - parameter [15:0] INIT_62 = 16'h0; - parameter [15:0] INIT_63 = 16'h0; - parameter [15:0] INIT_64 = 16'h0; - parameter [15:0] INIT_65 = 16'h0; - parameter [15:0] INIT_66 = 16'h0; - parameter [15:0] INIT_67 = 16'h0; - parameter [15:0] INIT_68 = 16'h0; - parameter [15:0] INIT_69 = 16'h0; - parameter [15:0] INIT_6A = 16'h0; - parameter [15:0] INIT_6B = 16'h0; - parameter [15:0] INIT_6C = 16'h0; - parameter [15:0] INIT_6D = 16'h0; - parameter [15:0] INIT_6E = 16'h0; - parameter [15:0] INIT_6F = 16'h0; - parameter [15:0] INIT_70 = 16'h0; - parameter [15:0] INIT_71 = 16'h0; - parameter [15:0] INIT_72 = 16'h0; - parameter [15:0] INIT_73 = 16'h0; - parameter [15:0] INIT_74 = 16'h0; - parameter [15:0] INIT_75 = 16'h0; - parameter [15:0] INIT_76 = 16'h0; - parameter [15:0] INIT_77 = 16'h0; - parameter [15:0] INIT_78 = 16'h0; - parameter [15:0] INIT_79 = 16'h0; - parameter [15:0] INIT_7A = 16'h0; - parameter [15:0] INIT_7B = 16'h0; - parameter [15:0] INIT_7C = 16'h0; - parameter [15:0] INIT_7D = 16'h0; - parameter [15:0] INIT_7E = 16'h0; - parameter [15:0] INIT_7F = 16'h0; - parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_DCLK_INVERTED = 1'b0; - parameter SIM_MONITOR_FILE = "design.txt"; - parameter integer SYSMON_VUSER0_BANK = 0; - parameter SYSMON_VUSER0_MONITOR = "NONE"; - parameter integer SYSMON_VUSER1_BANK = 0; - parameter SYSMON_VUSER1_MONITOR = "NONE"; - parameter integer SYSMON_VUSER2_BANK = 0; - parameter SYSMON_VUSER2_MONITOR = "NONE"; - parameter integer SYSMON_VUSER3_BANK = 0; - parameter SYSMON_VUSER3_MONITOR = "NONE"; - output [15:0] ALM; - output BUSY; - output [5:0] CHANNEL; - output [15:0] DO; - output DRDY; - output EOC; - output EOS; - output I2C_SCLK_TS; - output I2C_SDA_TS; - output JTAGBUSY; - output JTAGLOCKED; - output JTAGMODIFIED; - output [4:0] MUXADDR; - output OT; - input CONVST; - (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) - input CONVSTCLK; - input [7:0] DADDR; - (* invertible_pin = "IS_DCLK_INVERTED" *) - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input I2C_SCLK; - input I2C_SDA; - input RESET; - input [15:0] VAUXN; - input [15:0] VAUXP; - input VN; - input VP; -endmodule - -module SYSMONE4 (...); - parameter [15:0] COMMON_N_SOURCE = 16'hFFFF; - parameter [15:0] INIT_40 = 16'h0000; - parameter [15:0] INIT_41 = 16'h0000; - parameter [15:0] INIT_42 = 16'h0000; - parameter [15:0] INIT_43 = 16'h0000; - parameter [15:0] INIT_44 = 16'h0000; - parameter [15:0] INIT_45 = 16'h0000; - parameter [15:0] INIT_46 = 16'h0000; - parameter [15:0] INIT_47 = 16'h0000; - parameter [15:0] INIT_48 = 16'h0000; - parameter [15:0] INIT_49 = 16'h0000; - parameter [15:0] INIT_4A = 16'h0000; - parameter [15:0] INIT_4B = 16'h0000; - parameter [15:0] INIT_4C = 16'h0000; - parameter [15:0] INIT_4D = 16'h0000; - parameter [15:0] INIT_4E = 16'h0000; - parameter [15:0] INIT_4F = 16'h0000; - parameter [15:0] INIT_50 = 16'h0000; - parameter [15:0] INIT_51 = 16'h0000; - parameter [15:0] INIT_52 = 16'h0000; - parameter [15:0] INIT_53 = 16'h0000; - parameter [15:0] INIT_54 = 16'h0000; - parameter [15:0] INIT_55 = 16'h0000; - parameter [15:0] INIT_56 = 16'h0000; - parameter [15:0] INIT_57 = 16'h0000; - parameter [15:0] INIT_58 = 16'h0000; - parameter [15:0] INIT_59 = 16'h0000; - parameter [15:0] INIT_5A = 16'h0000; - parameter [15:0] INIT_5B = 16'h0000; - parameter [15:0] INIT_5C = 16'h0000; - parameter [15:0] INIT_5D = 16'h0000; - parameter [15:0] INIT_5E = 16'h0000; - parameter [15:0] INIT_5F = 16'h0000; - parameter [15:0] INIT_60 = 16'h0000; - parameter [15:0] INIT_61 = 16'h0000; - parameter [15:0] INIT_62 = 16'h0000; - parameter [15:0] INIT_63 = 16'h0000; - parameter [15:0] INIT_64 = 16'h0000; - parameter [15:0] INIT_65 = 16'h0000; - parameter [15:0] INIT_66 = 16'h0000; - parameter [15:0] INIT_67 = 16'h0000; - parameter [15:0] INIT_68 = 16'h0000; - parameter [15:0] INIT_69 = 16'h0000; - parameter [15:0] INIT_6A = 16'h0000; - parameter [15:0] INIT_6B = 16'h0000; - parameter [15:0] INIT_6C = 16'h0000; - parameter [15:0] INIT_6D = 16'h0000; - parameter [15:0] INIT_6E = 16'h0000; - parameter [15:0] INIT_6F = 16'h0000; - parameter [15:0] INIT_70 = 16'h0000; - parameter [15:0] INIT_71 = 16'h0000; - parameter [15:0] INIT_72 = 16'h0000; - parameter [15:0] INIT_73 = 16'h0000; - parameter [15:0] INIT_74 = 16'h0000; - parameter [15:0] INIT_75 = 16'h0000; - parameter [15:0] INIT_76 = 16'h0000; - parameter [15:0] INIT_77 = 16'h0000; - parameter [15:0] INIT_78 = 16'h0000; - parameter [15:0] INIT_79 = 16'h0000; - parameter [15:0] INIT_7A = 16'h0000; - parameter [15:0] INIT_7B = 16'h0000; - parameter [15:0] INIT_7C = 16'h0000; - parameter [15:0] INIT_7D = 16'h0000; - parameter [15:0] INIT_7E = 16'h0000; - parameter [15:0] INIT_7F = 16'h0000; - parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0; - parameter [0:0] IS_DCLK_INVERTED = 1'b0; - parameter SIM_DEVICE = "ULTRASCALE_PLUS"; - parameter SIM_MONITOR_FILE = "design.txt"; - parameter integer SYSMON_VUSER0_BANK = 0; - parameter SYSMON_VUSER0_MONITOR = "NONE"; - parameter integer SYSMON_VUSER1_BANK = 0; - parameter SYSMON_VUSER1_MONITOR = "NONE"; - parameter integer SYSMON_VUSER2_BANK = 0; - parameter SYSMON_VUSER2_MONITOR = "NONE"; - parameter integer SYSMON_VUSER3_BANK = 0; - parameter SYSMON_VUSER3_MONITOR = "NONE"; - output [15:0] ADC_DATA; - output [15:0] ALM; - output BUSY; - output [5:0] CHANNEL; - output [15:0] DO; - output DRDY; - output EOC; - output EOS; - output I2C_SCLK_TS; - output I2C_SDA_TS; - output JTAGBUSY; - output JTAGLOCKED; - output JTAGMODIFIED; - output [4:0] MUXADDR; - output OT; - output SMBALERT_TS; - input CONVST; - (* invertible_pin = "IS_CONVSTCLK_INVERTED" *) - input CONVSTCLK; - input [7:0] DADDR; - (* invertible_pin = "IS_DCLK_INVERTED" *) - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input I2C_SCLK; - input I2C_SDA; - input RESET; - input [15:0] VAUXN; - input [15:0] VAUXP; - input VN; - input VP; -endmodule - -module DSP48E2 (...); - parameter integer ACASCREG = 1; - parameter integer ADREG = 1; - parameter integer ALUMODEREG = 1; - parameter AMULTSEL = "A"; - parameter integer AREG = 1; - parameter AUTORESET_PATDET = "NO_RESET"; - parameter AUTORESET_PRIORITY = "RESET"; - parameter A_INPUT = "DIRECT"; - parameter integer BCASCREG = 1; - parameter BMULTSEL = "B"; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer CARRYINREG = 1; - parameter integer CARRYINSELREG = 1; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer INMODEREG = 1; - parameter [3:0] IS_ALUMODE_INVERTED = 4'b0000; - parameter [0:0] IS_CARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [4:0] IS_INMODE_INVERTED = 5'b00000; - parameter [8:0] IS_OPMODE_INVERTED = 9'b000000000; - parameter [0:0] IS_RSTALLCARRYIN_INVERTED = 1'b0; - parameter [0:0] IS_RSTALUMODE_INVERTED = 1'b0; - parameter [0:0] IS_RSTA_INVERTED = 1'b0; - parameter [0:0] IS_RSTB_INVERTED = 1'b0; - parameter [0:0] IS_RSTCTRL_INVERTED = 1'b0; - parameter [0:0] IS_RSTC_INVERTED = 1'b0; - parameter [0:0] IS_RSTD_INVERTED = 1'b0; - parameter [0:0] IS_RSTINMODE_INVERTED = 1'b0; - parameter [0:0] IS_RSTM_INVERTED = 1'b0; - parameter [0:0] IS_RSTP_INVERTED = 1'b0; - parameter [47:0] MASK = 48'h3FFFFFFFFFFF; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter [47:0] PATTERN = 48'h000000000000; - parameter PREADDINSEL = "A"; - parameter integer PREG = 1; - parameter [47:0] RND = 48'h000000000000; - parameter SEL_MASK = "MASK"; - parameter SEL_PATTERN = "PATTERN"; - parameter USE_MULT = "MULTIPLY"; - parameter USE_PATTERN_DETECT = "NO_PATDET"; - parameter USE_SIMD = "ONE48"; - parameter USE_WIDEXOR = "FALSE"; - parameter XORSIMD = "XOR24_48_96"; - output [29:0] ACOUT; - output [17:0] BCOUT; - output CARRYCASCOUT; - output [3:0] CARRYOUT; - output MULTSIGNOUT; - output OVERFLOW; - output [47:0] P; - output PATTERNBDETECT; - output PATTERNDETECT; - output [47:0] PCOUT; - output UNDERFLOW; - output [7:0] XOROUT; - input [29:0] A; - input [29:0] ACIN; - (* invertible_pin = "IS_ALUMODE_INVERTED" *) - input [3:0] ALUMODE; - input [17:0] B; - input [17:0] BCIN; - input [47:0] C; - input CARRYCASCIN; - (* invertible_pin = "IS_CARRYIN_INVERTED" *) - input CARRYIN; - input [2:0] CARRYINSEL; - input CEA1; - input CEA2; - input CEAD; - input CEALUMODE; - input CEB1; - input CEB2; - input CEC; - input CECARRYIN; - input CECTRL; - input CED; - input CEINMODE; - input CEM; - input CEP; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [26:0] D; - (* invertible_pin = "IS_INMODE_INVERTED" *) - input [4:0] INMODE; - input MULTSIGNIN; - (* invertible_pin = "IS_OPMODE_INVERTED" *) - input [8:0] OPMODE; - input [47:0] PCIN; - (* invertible_pin = "IS_RSTA_INVERTED" *) - input RSTA; - (* invertible_pin = "IS_RSTALLCARRYIN_INVERTED" *) - input RSTALLCARRYIN; - (* invertible_pin = "IS_RSTALUMODE_INVERTED" *) - input RSTALUMODE; - (* invertible_pin = "IS_RSTB_INVERTED" *) - input RSTB; - (* invertible_pin = "IS_RSTC_INVERTED" *) - input RSTC; - (* invertible_pin = "IS_RSTCTRL_INVERTED" *) - input RSTCTRL; - (* invertible_pin = "IS_RSTD_INVERTED" *) - input RSTD; - (* invertible_pin = "IS_RSTINMODE_INVERTED" *) - input RSTINMODE; - (* invertible_pin = "IS_RSTM_INVERTED" *) - input RSTM; - (* invertible_pin = "IS_RSTP_INVERTED" *) - input RSTP; -endmodule - -module FIFO18E2 (...); - parameter CASCADE_ORDER = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter [35:0] INIT = 36'h000000000; - parameter [0:0] IS_RDCLK_INVERTED = 1'b0; - parameter [0:0] IS_RDEN_INVERTED = 1'b0; - parameter [0:0] IS_RSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter [0:0] IS_WRCLK_INVERTED = 1'b0; - parameter [0:0] IS_WREN_INVERTED = 1'b0; - parameter integer PROG_EMPTY_THRESH = 256; - parameter integer PROG_FULL_THRESH = 256; - parameter RDCOUNT_TYPE = "RAW_PNTR"; - parameter integer READ_WIDTH = 4; - parameter REGISTER_MODE = "UNREGISTERED"; - parameter RSTREG_PRIORITY = "RSTREG"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [35:0] SRVAL = 36'h000000000; - parameter WRCOUNT_TYPE = "RAW_PNTR"; - parameter integer WRITE_WIDTH = 4; - output [31:0] CASDOUT; - output [3:0] CASDOUTP; - output CASNXTEMPTY; - output CASPRVRDEN; - output [31:0] DOUT; - output [3:0] DOUTP; - output EMPTY; - output FULL; - output PROGEMPTY; - output PROGFULL; - output [12:0] RDCOUNT; - output RDERR; - output RDRSTBUSY; - output [12:0] WRCOUNT; - output WRERR; - output WRRSTBUSY; - input [31:0] CASDIN; - input [3:0] CASDINP; - input CASDOMUX; - input CASDOMUXEN; - input CASNXTRDEN; - input CASOREGIMUX; - input CASOREGIMUXEN; - input CASPRVEMPTY; - input [31:0] DIN; - input [3:0] DINP; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - input SLEEP; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module FIFO36E2 (...); - parameter CASCADE_ORDER = "NONE"; - parameter CLOCK_DOMAINS = "INDEPENDENT"; - parameter EN_ECC_PIPE = "FALSE"; - parameter EN_ECC_READ = "FALSE"; - parameter EN_ECC_WRITE = "FALSE"; - parameter FIRST_WORD_FALL_THROUGH = "FALSE"; - parameter [71:0] INIT = 72'h000000000000000000; - parameter [0:0] IS_RDCLK_INVERTED = 1'b0; - parameter [0:0] IS_RDEN_INVERTED = 1'b0; - parameter [0:0] IS_RSTREG_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter [0:0] IS_WRCLK_INVERTED = 1'b0; - parameter [0:0] IS_WREN_INVERTED = 1'b0; - parameter integer PROG_EMPTY_THRESH = 256; - parameter integer PROG_FULL_THRESH = 256; - parameter RDCOUNT_TYPE = "RAW_PNTR"; - parameter integer READ_WIDTH = 4; - parameter REGISTER_MODE = "UNREGISTERED"; - parameter RSTREG_PRIORITY = "RSTREG"; - parameter SLEEP_ASYNC = "FALSE"; - parameter [71:0] SRVAL = 72'h000000000000000000; - parameter WRCOUNT_TYPE = "RAW_PNTR"; - parameter integer WRITE_WIDTH = 4; - output [63:0] CASDOUT; - output [7:0] CASDOUTP; - output CASNXTEMPTY; - output CASPRVRDEN; - output DBITERR; - output [63:0] DOUT; - output [7:0] DOUTP; - output [7:0] ECCPARITY; - output EMPTY; - output FULL; - output PROGEMPTY; - output PROGFULL; - output [13:0] RDCOUNT; - output RDERR; - output RDRSTBUSY; - output SBITERR; - output [13:0] WRCOUNT; - output WRERR; - output WRRSTBUSY; - input [63:0] CASDIN; - input [7:0] CASDINP; - input CASDOMUX; - input CASDOMUXEN; - input CASNXTRDEN; - input CASOREGIMUX; - input CASOREGIMUXEN; - input CASPRVEMPTY; - input [63:0] DIN; - input [7:0] DINP; - input INJECTDBITERR; - input INJECTSBITERR; - (* clkbuf_sink *) - (* invertible_pin = "IS_RDCLK_INVERTED" *) - input RDCLK; - (* invertible_pin = "IS_RDEN_INVERTED" *) - input RDEN; - input REGCE; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RSTREG_INVERTED" *) - input RSTREG; - input SLEEP; - (* clkbuf_sink *) - (* invertible_pin = "IS_WRCLK_INVERTED" *) - input WRCLK; - (* invertible_pin = "IS_WREN_INVERTED" *) - input WREN; -endmodule - -module URAM288 (...); - parameter integer AUTO_SLEEP_LATENCY = 8; - parameter integer AVG_CONS_INACTIVE_CYCLES = 10; - parameter BWE_MODE_A = "PARITY_INTERLEAVED"; - parameter BWE_MODE_B = "PARITY_INTERLEAVED"; - parameter CASCADE_ORDER_A = "NONE"; - parameter CASCADE_ORDER_B = "NONE"; - parameter EN_AUTO_SLEEP_MODE = "FALSE"; - parameter EN_ECC_RD_A = "FALSE"; - parameter EN_ECC_RD_B = "FALSE"; - parameter EN_ECC_WR_A = "FALSE"; - parameter EN_ECC_WR_B = "FALSE"; - parameter IREG_PRE_A = "FALSE"; - parameter IREG_PRE_B = "FALSE"; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_EN_A_INVERTED = 1'b0; - parameter [0:0] IS_EN_B_INVERTED = 1'b0; - parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0; - parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0; - parameter [0:0] IS_RST_A_INVERTED = 1'b0; - parameter [0:0] IS_RST_B_INVERTED = 1'b0; - parameter MATRIX_ID = "NONE"; - parameter integer NUM_UNIQUE_SELF_ADDR_A = 1; - parameter integer NUM_UNIQUE_SELF_ADDR_B = 1; - parameter integer NUM_URAM_IN_MATRIX = 1; - parameter OREG_A = "FALSE"; - parameter OREG_B = "FALSE"; - parameter OREG_ECC_A = "FALSE"; - parameter OREG_ECC_B = "FALSE"; - parameter REG_CAS_A = "FALSE"; - parameter REG_CAS_B = "FALSE"; - parameter RST_MODE_A = "SYNC"; - parameter RST_MODE_B = "SYNC"; - parameter [10:0] SELF_ADDR_A = 11'h000; - parameter [10:0] SELF_ADDR_B = 11'h000; - parameter [10:0] SELF_MASK_A = 11'h7FF; - parameter [10:0] SELF_MASK_B = 11'h7FF; - parameter USE_EXT_CE_A = "FALSE"; - parameter USE_EXT_CE_B = "FALSE"; - output [22:0] CAS_OUT_ADDR_A; - output [22:0] CAS_OUT_ADDR_B; - output [8:0] CAS_OUT_BWE_A; - output [8:0] CAS_OUT_BWE_B; - output CAS_OUT_DBITERR_A; - output CAS_OUT_DBITERR_B; - output [71:0] CAS_OUT_DIN_A; - output [71:0] CAS_OUT_DIN_B; - output [71:0] CAS_OUT_DOUT_A; - output [71:0] CAS_OUT_DOUT_B; - output CAS_OUT_EN_A; - output CAS_OUT_EN_B; - output CAS_OUT_RDACCESS_A; - output CAS_OUT_RDACCESS_B; - output CAS_OUT_RDB_WR_A; - output CAS_OUT_RDB_WR_B; - output CAS_OUT_SBITERR_A; - output CAS_OUT_SBITERR_B; - output DBITERR_A; - output DBITERR_B; - output [71:0] DOUT_A; - output [71:0] DOUT_B; - output RDACCESS_A; - output RDACCESS_B; - output SBITERR_A; - output SBITERR_B; - input [22:0] ADDR_A; - input [22:0] ADDR_B; - input [8:0] BWE_A; - input [8:0] BWE_B; - input [22:0] CAS_IN_ADDR_A; - input [22:0] CAS_IN_ADDR_B; - input [8:0] CAS_IN_BWE_A; - input [8:0] CAS_IN_BWE_B; - input CAS_IN_DBITERR_A; - input CAS_IN_DBITERR_B; - input [71:0] CAS_IN_DIN_A; - input [71:0] CAS_IN_DIN_B; - input [71:0] CAS_IN_DOUT_A; - input [71:0] CAS_IN_DOUT_B; - input CAS_IN_EN_A; - input CAS_IN_EN_B; - input CAS_IN_RDACCESS_A; - input CAS_IN_RDACCESS_B; - input CAS_IN_RDB_WR_A; - input CAS_IN_RDB_WR_B; - input CAS_IN_SBITERR_A; - input CAS_IN_SBITERR_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [71:0] DIN_A; - input [71:0] DIN_B; - (* invertible_pin = "IS_EN_A_INVERTED" *) - input EN_A; - (* invertible_pin = "IS_EN_B_INVERTED" *) - input EN_B; - input INJECT_DBITERR_A; - input INJECT_DBITERR_B; - input INJECT_SBITERR_A; - input INJECT_SBITERR_B; - input OREG_CE_A; - input OREG_CE_B; - input OREG_ECC_CE_A; - input OREG_ECC_CE_B; - (* invertible_pin = "IS_RDB_WR_A_INVERTED" *) - input RDB_WR_A; - (* invertible_pin = "IS_RDB_WR_B_INVERTED" *) - input RDB_WR_B; - (* invertible_pin = "IS_RST_A_INVERTED" *) - input RST_A; - (* invertible_pin = "IS_RST_B_INVERTED" *) - input RST_B; - input SLEEP; -endmodule - -module URAM288_BASE (...); - parameter integer AUTO_SLEEP_LATENCY = 8; - parameter integer AVG_CONS_INACTIVE_CYCLES = 10; - parameter BWE_MODE_A = "PARITY_INTERLEAVED"; - parameter BWE_MODE_B = "PARITY_INTERLEAVED"; - parameter EN_AUTO_SLEEP_MODE = "FALSE"; - parameter EN_ECC_RD_A = "FALSE"; - parameter EN_ECC_RD_B = "FALSE"; - parameter EN_ECC_WR_A = "FALSE"; - parameter EN_ECC_WR_B = "FALSE"; - parameter IREG_PRE_A = "FALSE"; - parameter IREG_PRE_B = "FALSE"; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_EN_A_INVERTED = 1'b0; - parameter [0:0] IS_EN_B_INVERTED = 1'b0; - parameter [0:0] IS_RDB_WR_A_INVERTED = 1'b0; - parameter [0:0] IS_RDB_WR_B_INVERTED = 1'b0; - parameter [0:0] IS_RST_A_INVERTED = 1'b0; - parameter [0:0] IS_RST_B_INVERTED = 1'b0; - parameter OREG_A = "FALSE"; - parameter OREG_B = "FALSE"; - parameter OREG_ECC_A = "FALSE"; - parameter OREG_ECC_B = "FALSE"; - parameter RST_MODE_A = "SYNC"; - parameter RST_MODE_B = "SYNC"; - parameter USE_EXT_CE_A = "FALSE"; - parameter USE_EXT_CE_B = "FALSE"; - output DBITERR_A; - output DBITERR_B; - output [71:0] DOUT_A; - output [71:0] DOUT_B; - output SBITERR_A; - output SBITERR_B; - input [22:0] ADDR_A; - input [22:0] ADDR_B; - input [8:0] BWE_A; - input [8:0] BWE_B; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [71:0] DIN_A; - input [71:0] DIN_B; - (* invertible_pin = "IS_EN_A_INVERTED" *) - input EN_A; - (* invertible_pin = "IS_EN_B_INVERTED" *) - input EN_B; - input INJECT_DBITERR_A; - input INJECT_DBITERR_B; - input INJECT_SBITERR_A; - input INJECT_SBITERR_B; - input OREG_CE_A; - input OREG_CE_B; - input OREG_ECC_CE_A; - input OREG_ECC_CE_B; - (* invertible_pin = "IS_RDB_WR_A_INVERTED" *) - input RDB_WR_A; - (* invertible_pin = "IS_RDB_WR_B_INVERTED" *) - input RDB_WR_B; - (* invertible_pin = "IS_RST_A_INVERTED" *) - input RST_A; - (* invertible_pin = "IS_RST_B_INVERTED" *) - input RST_B; - input SLEEP; -endmodule - -module RAM128X1S (...); - parameter [127:0] INIT = 128'h00000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input A6; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM256X1D (...); - parameter [255:0] INIT = 256'h0000000000000000000000000000000000000000000000000000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DPO; - output SPO; - input [7:0] A; - input D; - input [7:0] DPRA; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM256X1S (...); - parameter [255:0] INIT = 256'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input [7:0] A; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [1:0] DOA; - output [1:0] DOB; - output [1:0] DOC; - output [1:0] DOD; - input [4:0] ADDRA; - input [4:0] ADDRB; - input [4:0] ADDRC; - input [4:0] ADDRD; - input [1:0] DIA; - input [1:0] DIB; - input [1:0] DIC; - input [1:0] DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32M16 (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [63:0] INIT_E = 64'h0000000000000000; - parameter [63:0] INIT_F = 64'h0000000000000000; - parameter [63:0] INIT_G = 64'h0000000000000000; - parameter [63:0] INIT_H = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output [1:0] DOA; - output [1:0] DOB; - output [1:0] DOC; - output [1:0] DOD; - output [1:0] DOE; - output [1:0] DOF; - output [1:0] DOG; - output [1:0] DOH; - input [4:0] ADDRA; - input [4:0] ADDRB; - input [4:0] ADDRC; - input [4:0] ADDRD; - input [4:0] ADDRE; - input [4:0] ADDRF; - input [4:0] ADDRG; - input [4:0] ADDRH; - input [1:0] DIA; - input [1:0] DIB; - input [1:0] DIC; - input [1:0] DID; - input [1:0] DIE; - input [1:0] DIF; - input [1:0] DIG; - input [1:0] DIH; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM32X1S (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM512X1S (...); - parameter [511:0] INIT = 512'h0; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input [8:0] A; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64M (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DOA; - output DOB; - output DOC; - output DOD; - input [5:0] ADDRA; - input [5:0] ADDRB; - input [5:0] ADDRC; - input [5:0] ADDRD; - input DIA; - input DIB; - input DIC; - input DID; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64M8 (...); - parameter [63:0] INIT_A = 64'h0000000000000000; - parameter [63:0] INIT_B = 64'h0000000000000000; - parameter [63:0] INIT_C = 64'h0000000000000000; - parameter [63:0] INIT_D = 64'h0000000000000000; - parameter [63:0] INIT_E = 64'h0000000000000000; - parameter [63:0] INIT_F = 64'h0000000000000000; - parameter [63:0] INIT_G = 64'h0000000000000000; - parameter [63:0] INIT_H = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output DOA; - output DOB; - output DOC; - output DOD; - output DOE; - output DOF; - output DOG; - output DOH; - input [5:0] ADDRA; - input [5:0] ADDRB; - input [5:0] ADDRC; - input [5:0] ADDRD; - input [5:0] ADDRE; - input [5:0] ADDRF; - input [5:0] ADDRG; - input [5:0] ADDRH; - input DIA; - input DIB; - input DIC; - input DID; - input DIE; - input DIF; - input DIG; - input DIH; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module RAM64X1S (...); - parameter [63:0] INIT = 64'h0000000000000000; - parameter [0:0] IS_WCLK_INVERTED = 1'b0; - output O; - input A0; - input A1; - input A2; - input A3; - input A4; - input A5; - input D; - (* clkbuf_sink *) - (* invertible_pin = "IS_WCLK_INVERTED" *) - input WCLK; - input WE; -endmodule - -module AND2B1L (...); - parameter [0:0] IS_SRI_INVERTED = 1'b0; - output O; - input DI; - (* invertible_pin = "IS_SRI_INVERTED" *) - input SRI; -endmodule - -module CARRY8 (...); - parameter CARRY_TYPE = "SINGLE_CY8"; - output [7:0] CO; - output [7:0] O; - input CI; - input CI_TOP; - input [7:0] DI; - input [7:0] S; -endmodule - -module CFGLUT5 (...); - parameter [31:0] INIT = 32'h00000000; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - output CDO; - output O5; - output O6; - input I4; - input I3; - input I2; - input I1; - input I0; - input CDI; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; -endmodule - -module MUXF9 (...); - output O; - input I0; - input I1; - input S; -endmodule - -module OR2L (...); - parameter [0:0] IS_SRI_INVERTED = 1'b0; - output O; - input DI; - (* invertible_pin = "IS_SRI_INVERTED" *) - input SRI; -endmodule - -module BUFG_GT (...); - (* clkbuf_driver *) - output O; - input CE; - input CEMASK; - input CLR; - input CLRMASK; - input [2:0] DIV; - input I; -endmodule - -module BUFG_GT_SYNC (...); - output CESYNC; - output CLRSYNC; - input CE; - input CLK; - input CLR; -endmodule - -module BUFG_PS (...); - (* clkbuf_driver *) - output O; - input I; -endmodule - -module BUFGCE (...); - parameter CE_TYPE = "SYNC"; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_I_INVERTED = 1'b0; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_I_INVERTED" *) - input I; -endmodule - -module BUFGCE_1 (...); - (* clkbuf_driver *) - output O; - input CE; - input I; -endmodule - -module BUFGCE_DIV (...); - parameter integer BUFGCE_DIVIDE = 1; - parameter [0:0] IS_CE_INVERTED = 1'b0; - parameter [0:0] IS_CLR_INVERTED = 1'b0; - parameter [0:0] IS_I_INVERTED = 1'b0; - (* clkbuf_driver *) - output O; - (* invertible_pin = "IS_CE_INVERTED" *) - input CE; - (* invertible_pin = "IS_CLR_INVERTED" *) - input CLR; - (* invertible_pin = "IS_I_INVERTED" *) - input I; -endmodule - -module BUFGMUX (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_1 (...); - parameter CLK_SEL_TYPE = "SYNC"; - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module BUFGMUX_CTRL (...); - (* clkbuf_driver *) - output O; - input I0; - input I1; - input S; -endmodule - -module MMCME3_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; - parameter COMPENSATION = "AUTO"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN2_INVERTED = 1'b0; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PSEN_INVERTED = 1'b0; - parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter SS_EN = "FALSE"; - parameter SS_MODE = "CENTER_HIGH"; - parameter integer SS_MOD_PERIOD = 10000; - parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter STARTUP_WAIT = "FALSE"; - output CDDCDONE; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output [15:0] DO; - output DRDY; - output LOCKED; - output PSDONE; - input CDDCREQ; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN1_INVERTED" *) - input CLKIN1; - (* invertible_pin = "IS_CLKIN2_INVERTED" *) - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input PSCLK; - (* invertible_pin = "IS_PSEN_INVERTED" *) - input PSEN; - (* invertible_pin = "IS_PSINCDEC_INVERTED" *) - input PSINCDEC; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME3_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN1_INVERTED" *) - input CLKIN1; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME4_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; - parameter COMPENSATION = "AUTO"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN2_INVERTED = 1'b0; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PSEN_INVERTED = 1'b0; - parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter SS_EN = "FALSE"; - parameter SS_MODE = "CENTER_HIGH"; - parameter integer SS_MOD_PERIOD = 10000; - parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 800.000; - parameter STARTUP_WAIT = "FALSE"; - output CDDCDONE; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output [15:0] DO; - output DRDY; - output LOCKED; - output PSDONE; - input CDDCREQ; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN1_INVERTED" *) - input CLKIN1; - (* invertible_pin = "IS_CLKIN2_INVERTED" *) - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input PSCLK; - (* invertible_pin = "IS_PSEN_INVERTED" *) - input PSEN; - (* invertible_pin = "IS_PSINCDEC_INVERTED" *) - input PSINCDEC; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME4_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN1_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN1_INVERTED" *) - input CLKIN1; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PLLE3_ADV (...); - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 70.000; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter real CLKPFD_FREQ_MAX = 667.500; - parameter real CLKPFD_FREQ_MIN = 70.000; - parameter COMPENSATION = "AUTO"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER = 0.010; - parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1335.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUTPHY; - output [15:0] DO; - output DRDY; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN_INVERTED" *) - input CLKIN; - input CLKOUTPHYEN; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PLLE3_BASE (...); - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUTPHY; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN_INVERTED" *) - input CLKIN; - input CLKOUTPHYEN; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PLLE4_ADV (...); - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 70.000; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter real CLKPFD_FREQ_MAX = 667.500; - parameter real CLKPFD_FREQ_MIN = 70.000; - parameter COMPENSATION = "AUTO"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER = 0.010; - parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1500.000; - parameter real VCOCLK_FREQ_MIN = 750.000; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUTPHY; - output [15:0] DO; - output DRDY; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN_INVERTED" *) - input CLKIN; - input CLKOUTPHYEN; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module PLLE4_BASE (...); - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUTPHY_MODE = "VCO_2X"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKFBIN_INVERTED = 1'b0; - parameter [0:0] IS_CLKIN_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUTPHY; - output LOCKED; - (* invertible_pin = "IS_CLKFBIN_INVERTED" *) - input CLKFBIN; - (* invertible_pin = "IS_CLKIN_INVERTED" *) - input CLKIN; - input CLKOUTPHYEN; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME2_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter CLKFBOUT_USE_FINE_PS = "FALSE"; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 10.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter CLKOUT0_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter CLKOUT1_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter CLKOUT2_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT3_USE_FINE_PS = "FALSE"; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter CLKOUT4_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter CLKOUT5_USE_FINE_PS = "FALSE"; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter CLKOUT6_USE_FINE_PS = "FALSE"; - parameter real CLKPFD_FREQ_MAX = 550.000; - parameter real CLKPFD_FREQ_MIN = 10.000; - parameter COMPENSATION = "ZHOLD"; - parameter integer DIVCLK_DIVIDE = 1; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PSEN_INVERTED = 1'b0; - parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter SS_EN = "FALSE"; - parameter SS_MODE = "CENTER_HIGH"; - parameter integer SS_MOD_PERIOD = 10000; - parameter STARTUP_WAIT = "FALSE"; - parameter real VCOCLK_FREQ_MAX = 1600.000; - parameter real VCOCLK_FREQ_MIN = 600.000; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKFBSTOPPED; - output CLKINSTOPPED; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output [15:0] DO; - output DRDY; - output LOCKED; - output PSDONE; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input [6:0] DADDR; - input DCLK; - input DEN; - input [15:0] DI; - input DWE; - input PSCLK; - (* invertible_pin = "IS_PSEN_INVERTED" *) - input PSEN; - (* invertible_pin = "IS_PSINCDEC_INVERTED" *) - input PSINCDEC; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module MMCME2_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter real CLKFBOUT_MULT_F = 5.000; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKOUT0_DIVIDE_F = 1.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter CLKOUT4_CASCADE = "FALSE"; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer CLKOUT6_DIVIDE = 1; - parameter real CLKOUT6_DUTY_CYCLE = 0.500; - parameter real CLKOUT6_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKFBOUTB; - output CLKOUT0; - output CLKOUT0B; - output CLKOUT1; - output CLKOUT1B; - output CLKOUT2; - output CLKOUT2B; - output CLKOUT3; - output CLKOUT3B; - output CLKOUT4; - output CLKOUT5; - output CLKOUT6; - output LOCKED; - input CLKFBIN; - input CLKIN1; - input PWRDWN; - input RST; -endmodule - -module PLLE2_ADV (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter COMPENSATION = "ZHOLD"; - parameter STARTUP_WAIT = "FALSE"; - parameter integer CLKOUT0_DIVIDE = 1; - parameter integer CLKOUT1_DIVIDE = 1; - parameter integer CLKOUT2_DIVIDE = 1; - parameter integer CLKOUT3_DIVIDE = 1; - parameter integer CLKOUT4_DIVIDE = 1; - parameter integer CLKOUT5_DIVIDE = 1; - parameter integer DIVCLK_DIVIDE = 1; - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter real CLKIN2_PERIOD = 0.000; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0; - parameter [0:0] IS_PWRDWN_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REF_JITTER1 = 0.010; - parameter real REF_JITTER2 = 0.010; - parameter real VCOCLK_FREQ_MAX = 2133.000; - parameter real VCOCLK_FREQ_MIN = 800.000; - parameter real CLKIN_FREQ_MAX = 1066.000; - parameter real CLKIN_FREQ_MIN = 19.000; - parameter real CLKPFD_FREQ_MAX = 550.0; - parameter real CLKPFD_FREQ_MIN = 19.0; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output DRDY; - output LOCKED; - output [15:0] DO; - input CLKFBIN; - input CLKIN1; - input CLKIN2; - (* invertible_pin = "IS_CLKINSEL_INVERTED" *) - input CLKINSEL; - input DCLK; - input DEN; - input DWE; - (* invertible_pin = "IS_PWRDWN_INVERTED" *) - input PWRDWN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input [15:0] DI; - input [6:0] DADDR; -endmodule - -module PLLE2_BASE (...); - parameter BANDWIDTH = "OPTIMIZED"; - parameter integer CLKFBOUT_MULT = 5; - parameter real CLKFBOUT_PHASE = 0.000; - parameter real CLKIN1_PERIOD = 0.000; - parameter integer CLKOUT0_DIVIDE = 1; - parameter real CLKOUT0_DUTY_CYCLE = 0.500; - parameter real CLKOUT0_PHASE = 0.000; - parameter integer CLKOUT1_DIVIDE = 1; - parameter real CLKOUT1_DUTY_CYCLE = 0.500; - parameter real CLKOUT1_PHASE = 0.000; - parameter integer CLKOUT2_DIVIDE = 1; - parameter real CLKOUT2_DUTY_CYCLE = 0.500; - parameter real CLKOUT2_PHASE = 0.000; - parameter integer CLKOUT3_DIVIDE = 1; - parameter real CLKOUT3_DUTY_CYCLE = 0.500; - parameter real CLKOUT3_PHASE = 0.000; - parameter integer CLKOUT4_DIVIDE = 1; - parameter real CLKOUT4_DUTY_CYCLE = 0.500; - parameter real CLKOUT4_PHASE = 0.000; - parameter integer CLKOUT5_DIVIDE = 1; - parameter real CLKOUT5_DUTY_CYCLE = 0.500; - parameter real CLKOUT5_PHASE = 0.000; - parameter integer DIVCLK_DIVIDE = 1; - parameter real REF_JITTER1 = 0.010; - parameter STARTUP_WAIT = "FALSE"; - output CLKFBOUT; - output CLKOUT0; - output CLKOUT1; - output CLKOUT2; - output CLKOUT3; - output CLKOUT4; - output CLKOUT5; - output LOCKED; - input CLKFBIN; - input CLKIN1; - input PWRDWN; - input RST; -endmodule - -(* keep *) -module BSCANE2 (...); - parameter DISABLE_JTAG = "FALSE"; - parameter integer JTAG_CHAIN = 1; - output CAPTURE; - output DRCK; - output RESET; - output RUNTEST; - output SEL; - output SHIFT; - output TCK; - output TDI; - output TMS; - output UPDATE; - input TDO; -endmodule - -module DNA_PORTE2 (...); - parameter [95:0] SIM_DNA_VALUE = 96'h000000000000000000000000; - output DOUT; - input CLK; - input DIN; - input READ; - input SHIFT; -endmodule - -module EFUSE_USR (...); - parameter [31:0] SIM_EFUSE_VALUE = 32'h00000000; - output [31:0] EFUSEUSR; -endmodule - -module FRAME_ECCE3 (...); - output CRCERROR; - output ECCERRORNOTSINGLE; - output ECCERRORSINGLE; - output ENDOFFRAME; - output ENDOFSCAN; - output [25:0] FAR; - input [1:0] FARSEL; - input ICAPBOTCLK; - input ICAPTOPCLK; -endmodule - -(* keep *) -module ICAPE3 (...); - parameter [31:0] DEVICE_ID = 32'h03628093; - parameter ICAP_AUTO_SWITCH = "DISABLE"; - parameter SIM_CFG_FILE_NAME = "NONE"; - output AVAIL; - output [31:0] O; - output PRDONE; - output PRERROR; - input CLK; - input CSIB; - input RDWRB; - input [31:0] I; -endmodule - -(* keep *) -module MASTER_JTAG (...); - output TDO; - input TCK; - input TDI; - input TMS; -endmodule - -(* keep *) -module STARTUPE3 (...); - parameter PROG_USR = "FALSE"; - parameter real SIM_CCLK_FREQ = 0.0; - output CFGCLK; - output CFGMCLK; - output [3:0] DI; - output EOS; - output PREQ; - input [3:0] DO; - input [3:0] DTS; - input FCSBO; - input FCSBTS; - input GSR; - input GTS; - input KEYCLEARB; - input PACK; - input USRCCLKO; - input USRCCLKTS; - input USRDONEO; - input USRDONETS; -endmodule - -module USR_ACCESSE2 (...); - output CFGCLK; - output DATAVALID; - output [31:0] DATA; -endmodule - -(* keep *) -module BITSLICE_CONTROL (...); - parameter CTRL_CLK = "EXTERNAL"; - parameter DIV_MODE = "DIV2"; - parameter EN_CLK_TO_EXT_NORTH = "DISABLE"; - parameter EN_CLK_TO_EXT_SOUTH = "DISABLE"; - parameter EN_DYN_ODLY_MODE = "FALSE"; - parameter EN_OTHER_NCLK = "FALSE"; - parameter EN_OTHER_PCLK = "FALSE"; - parameter IDLY_VT_TRACK = "TRUE"; - parameter INV_RXCLK = "FALSE"; - parameter ODLY_VT_TRACK = "TRUE"; - parameter QDLY_VT_TRACK = "TRUE"; - parameter [5:0] READ_IDLE_COUNT = 6'h00; - parameter REFCLK_SRC = "PLLCLK"; - parameter integer ROUNDING_FACTOR = 16; - parameter RXGATE_EXTEND = "FALSE"; - parameter RX_CLK_PHASE_N = "SHIFT_0"; - parameter RX_CLK_PHASE_P = "SHIFT_0"; - parameter RX_GATING = "DISABLE"; - parameter SELF_CALIBRATE = "ENABLE"; - parameter SERIAL_MODE = "FALSE"; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter SIM_SPEEDUP = "FAST"; - parameter real SIM_VERSION = 2.0; - parameter TX_GATING = "DISABLE"; - output CLK_TO_EXT_NORTH; - output CLK_TO_EXT_SOUTH; - output DLY_RDY; - output [6:0] DYN_DCI; - output NCLK_NIBBLE_OUT; - output PCLK_NIBBLE_OUT; - output [15:0] RIU_RD_DATA; - output RIU_VALID; - output [39:0] RX_BIT_CTRL_OUT0; - output [39:0] RX_BIT_CTRL_OUT1; - output [39:0] RX_BIT_CTRL_OUT2; - output [39:0] RX_BIT_CTRL_OUT3; - output [39:0] RX_BIT_CTRL_OUT4; - output [39:0] RX_BIT_CTRL_OUT5; - output [39:0] RX_BIT_CTRL_OUT6; - output [39:0] TX_BIT_CTRL_OUT0; - output [39:0] TX_BIT_CTRL_OUT1; - output [39:0] TX_BIT_CTRL_OUT2; - output [39:0] TX_BIT_CTRL_OUT3; - output [39:0] TX_BIT_CTRL_OUT4; - output [39:0] TX_BIT_CTRL_OUT5; - output [39:0] TX_BIT_CTRL_OUT6; - output [39:0] TX_BIT_CTRL_OUT_TRI; - output VTC_RDY; - input CLK_FROM_EXT; - input EN_VTC; - input NCLK_NIBBLE_IN; - input PCLK_NIBBLE_IN; - input [3:0] PHY_RDCS0; - input [3:0] PHY_RDCS1; - input [3:0] PHY_RDEN; - input [3:0] PHY_WRCS0; - input [3:0] PHY_WRCS1; - input PLL_CLK; - input REFCLK; - input [5:0] RIU_ADDR; - input RIU_CLK; - input RIU_NIBBLE_SEL; - input [15:0] RIU_WR_DATA; - input RIU_WR_EN; - input RST; - input [39:0] RX_BIT_CTRL_IN0; - input [39:0] RX_BIT_CTRL_IN1; - input [39:0] RX_BIT_CTRL_IN2; - input [39:0] RX_BIT_CTRL_IN3; - input [39:0] RX_BIT_CTRL_IN4; - input [39:0] RX_BIT_CTRL_IN5; - input [39:0] RX_BIT_CTRL_IN6; - input [3:0] TBYTE_IN; - input [39:0] TX_BIT_CTRL_IN0; - input [39:0] TX_BIT_CTRL_IN1; - input [39:0] TX_BIT_CTRL_IN2; - input [39:0] TX_BIT_CTRL_IN3; - input [39:0] TX_BIT_CTRL_IN4; - input [39:0] TX_BIT_CTRL_IN5; - input [39:0] TX_BIT_CTRL_IN6; - input [39:0] TX_BIT_CTRL_IN_TRI; -endmodule - -(* keep *) -module DCIRESET (...); - output LOCKED; - input RST; -endmodule - -module HPIO_VREF (...); - parameter VREF_CNTR = "OFF"; - output VREF; - input [6:0] FABRIC_VREF_TUNE; -endmodule - -module IBUF_ANALOG (...); - output O; - (* iopad_external_pin *) - input I; -endmodule - -module IBUF_IBUFDISABLE (...); - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - input IBUFDISABLE; -endmodule - -module IBUF_INTERMDISABLE (...); - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_DELAY_VALUE = "0"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IFD_DELAY_VALUE = "AUTO"; - parameter IOSTANDARD = "DEFAULT"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; -endmodule - -module IBUFDS_DIFF_OUT_IBUFDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; -endmodule - -module IBUFDS_DIFF_OUT_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUFDS_DPHY (...); - parameter DIFF_TERM = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output HSRX_O; - output LPRX_O_N; - output LPRX_O_P; - input HSRX_DISABLE; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input LPRX_DISABLE; -endmodule - -module IBUFDS_IBUFDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; -endmodule - -module IBUFDS_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; - input INTERMDISABLE; -endmodule - -module IBUFDSE3 (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter USE_IBUFDISABLE = "FALSE"; - parameter integer SIM_INPUT_BUFFER_OFFSET = 0; - output O; - (* iopad_external_pin *) - input I; - (* iopad_external_pin *) - input IB; - input IBUFDISABLE; - input [3:0] OSC; - input [1:0] OSC_EN; -endmodule - -module IBUFE3 (...); - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter USE_IBUFDISABLE = "FALSE"; - parameter integer SIM_INPUT_BUFFER_OFFSET = 0; - output O; - (* iopad_external_pin *) - input I; - input IBUFDISABLE; - input [3:0] OSC; - input OSC_EN; - input VREF; -endmodule - -(* keep *) -module IDELAYCTRL (...); - parameter SIM_DEVICE = "7SERIES"; - output RDY; - (* clkbuf_sink *) - input REFCLK; - input RST; -endmodule - -module IDELAYE3 (...); - parameter CASCADE = "NONE"; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_SRC = "IDATAIN"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter LOOPBACK = "FALSE"; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter UPDATE_MODE = "ASYNC"; - output CASC_OUT; - output [8:0] CNTVALUEOUT; - output DATAOUT; - input CASC_IN; - input CASC_RETURN; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [8:0] CNTVALUEIN; - input DATAIN; - input EN_VTC; - input IDATAIN; - input INC; - input LOAD; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module IOBUF (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input T; -endmodule - -module IOBUF_DCIEN (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input T; -endmodule - -module IOBUF_INTERMDISABLE (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input T; -endmodule - -module IOBUFDS (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - output O; - (* iopad_external_pin *) - inout IO; - inout IOB; - input I; - input T; -endmodule - -module IOBUFDS_DCIEN (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input T; -endmodule - -module IOBUFDS_DIFF_OUT (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input TM; - input TS; -endmodule - -module IOBUFDS_DIFF_OUT_DCIEN (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input TM; - input TS; -endmodule - -module IOBUFDS_DIFF_OUT_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - output OB; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input TM; - input TS; -endmodule - -module IOBUFDS_INTERMDISABLE (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SIM_DEVICE = "7SERIES"; - parameter SLEW = "SLOW"; - parameter USE_IBUFDISABLE = "TRUE"; - output O; - (* iopad_external_pin *) - inout IO; - (* iopad_external_pin *) - inout IOB; - input I; - input IBUFDISABLE; - input INTERMDISABLE; - input T; -endmodule - -module IOBUFDSE3 (...); - parameter DIFF_TERM = "FALSE"; - parameter DQS_BIAS = "FALSE"; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter integer SIM_INPUT_BUFFER_OFFSET = 0; - parameter USE_IBUFDISABLE = "FALSE"; - output O; - (* iopad_external_pin *) - inout IO; - inout IOB; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input [3:0] OSC; - input [1:0] OSC_EN; - input T; -endmodule - -module IOBUFE3 (...); - parameter integer DRIVE = 12; - parameter IBUF_LOW_PWR = "TRUE"; - parameter IOSTANDARD = "DEFAULT"; - parameter USE_IBUFDISABLE = "FALSE"; - parameter integer SIM_INPUT_BUFFER_OFFSET = 0; - output O; - (* iopad_external_pin *) - inout IO; - input DCITERMDISABLE; - input I; - input IBUFDISABLE; - input [3:0] OSC; - input OSC_EN; - input T; - input VREF; -endmodule - -module ISERDESE3 (...); - parameter integer DATA_WIDTH = 8; - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter FIFO_ENABLE = "FALSE"; - parameter FIFO_SYNC_MODE = "FALSE"; - parameter IDDR_MODE = "FALSE"; - parameter [0:0] IS_CLK_B_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - output FIFO_EMPTY; - output INTERNAL_DIVCLK; - output [7:0] Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* clkbuf_sink *) - input CLKDIV; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_B_INVERTED" *) - input CLK_B; - input D; - (* clkbuf_sink *) - input FIFO_RD_CLK; - input FIFO_RD_EN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module KEEPER (...); - inout O; -endmodule - -module OBUFDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; -endmodule - -module OBUFDS_DPHY (...); - parameter IOSTANDARD = "DEFAULT"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input HSTX_I; - input HSTX_T; - input LPTX_I_N; - input LPTX_I_P; - input LPTX_T; -endmodule - -module OBUFT (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter integer DRIVE = 12; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - input I; - input T; -endmodule - -module OBUFTDS (...); - parameter CAPACITANCE = "DONT_CARE"; - parameter IOSTANDARD = "DEFAULT"; - parameter SLEW = "SLOW"; - (* iopad_external_pin *) - output O; - (* iopad_external_pin *) - output OB; - input I; - input T; -endmodule - -module ODELAYE3 (...); - parameter CASCADE = "NONE"; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter UPDATE_MODE = "ASYNC"; - output CASC_OUT; - output [8:0] CNTVALUEOUT; - output DATAOUT; - input CASC_IN; - input CASC_RETURN; - input CE; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [8:0] CNTVALUEIN; - input EN_VTC; - input INC; - input LOAD; - input ODATAIN; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; -endmodule - -module OSERDESE3 (...); - parameter integer DATA_WIDTH = 8; - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLKDIV_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter ODDR_MODE = "FALSE"; - parameter OSERDES_D_BYPASS = "FALSE"; - parameter OSERDES_T_BYPASS = "FALSE"; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - output OQ; - output T_OUT; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLKDIV_INVERTED" *) - input CLKDIV; - input [7:0] D; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - input T; -endmodule - -module PULLDOWN (...); - output O; -endmodule - -module PULLUP (...); - output O; -endmodule - -module RIU_OR (...); - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - output [15:0] RIU_RD_DATA; - output RIU_RD_VALID; - input [15:0] RIU_RD_DATA_LOW; - input [15:0] RIU_RD_DATA_UPP; - input RIU_RD_VALID_LOW; - input RIU_RD_VALID_UPP; -endmodule - -module RX_BITSLICE (...); - parameter CASCADE = "TRUE"; - parameter DATA_TYPE = "NONE"; - parameter integer DATA_WIDTH = 8; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter integer DELAY_VALUE_EXT = 0; - parameter FIFO_SYNC_MODE = "FALSE"; - parameter [0:0] IS_CLK_EXT_INVERTED = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_DLY_EXT_INVERTED = 1'b0; - parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter UPDATE_MODE = "ASYNC"; - parameter UPDATE_MODE_EXT = "ASYNC"; - output [8:0] CNTVALUEOUT; - output [8:0] CNTVALUEOUT_EXT; - output FIFO_EMPTY; - output FIFO_WRCLK_OUT; - output [7:0] Q; - output [39:0] RX_BIT_CTRL_OUT; - output [39:0] TX_BIT_CTRL_OUT; - input CE; - input CE_EXT; - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - (* invertible_pin = "IS_CLK_EXT_INVERTED" *) - input CLK_EXT; - input [8:0] CNTVALUEIN; - input [8:0] CNTVALUEIN_EXT; - input DATAIN; - input EN_VTC; - input EN_VTC_EXT; - input FIFO_RD_CLK; - input FIFO_RD_EN; - input INC; - input INC_EXT; - input LOAD; - input LOAD_EXT; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RST_DLY_INVERTED" *) - input RST_DLY; - (* invertible_pin = "IS_RST_DLY_EXT_INVERTED" *) - input RST_DLY_EXT; - input [39:0] RX_BIT_CTRL_IN; - input [39:0] TX_BIT_CTRL_IN; -endmodule - -module RXTX_BITSLICE (...); - parameter FIFO_SYNC_MODE = "FALSE"; - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_RX_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RX_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_RX_RST_INVERTED = 1'b0; - parameter [0:0] IS_TX_CLK_INVERTED = 1'b0; - parameter [0:0] IS_TX_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_TX_RST_INVERTED = 1'b0; - parameter LOOPBACK = "FALSE"; - parameter NATIVE_ODELAY_BYPASS = "FALSE"; - parameter ENABLE_PRE_EMPHASIS = "FALSE"; - parameter RX_DATA_TYPE = "NONE"; - parameter integer RX_DATA_WIDTH = 8; - parameter RX_DELAY_FORMAT = "TIME"; - parameter RX_DELAY_TYPE = "FIXED"; - parameter integer RX_DELAY_VALUE = 0; - parameter real RX_REFCLK_FREQUENCY = 300.0; - parameter RX_UPDATE_MODE = "ASYNC"; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter TBYTE_CTL = "TBYTE_IN"; - parameter integer TX_DATA_WIDTH = 8; - parameter TX_DELAY_FORMAT = "TIME"; - parameter TX_DELAY_TYPE = "FIXED"; - parameter integer TX_DELAY_VALUE = 0; - parameter TX_OUTPUT_PHASE_90 = "FALSE"; - parameter real TX_REFCLK_FREQUENCY = 300.0; - parameter TX_UPDATE_MODE = "ASYNC"; - output FIFO_EMPTY; - output FIFO_WRCLK_OUT; - output O; - output [7:0] Q; - output [39:0] RX_BIT_CTRL_OUT; - output [8:0] RX_CNTVALUEOUT; - output [39:0] TX_BIT_CTRL_OUT; - output [8:0] TX_CNTVALUEOUT; - output T_OUT; - input [7:0] D; - input DATAIN; - input FIFO_RD_CLK; - input FIFO_RD_EN; - input [39:0] RX_BIT_CTRL_IN; - input RX_CE; - (* invertible_pin = "IS_RX_CLK_INVERTED" *) - input RX_CLK; - input [8:0] RX_CNTVALUEIN; - input RX_EN_VTC; - input RX_INC; - input RX_LOAD; - (* invertible_pin = "IS_RX_RST_INVERTED" *) - input RX_RST; - (* invertible_pin = "IS_RX_RST_DLY_INVERTED" *) - input RX_RST_DLY; - input T; - input TBYTE_IN; - input [39:0] TX_BIT_CTRL_IN; - input TX_CE; - (* invertible_pin = "IS_TX_CLK_INVERTED" *) - input TX_CLK; - input [8:0] TX_CNTVALUEIN; - input TX_EN_VTC; - input TX_INC; - input TX_LOAD; - (* invertible_pin = "IS_TX_RST_INVERTED" *) - input TX_RST; - (* invertible_pin = "IS_TX_RST_DLY_INVERTED" *) - input TX_RST_DLY; -endmodule - -module TX_BITSLICE (...); - parameter integer DATA_WIDTH = 8; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter ENABLE_PRE_EMPHASIS = "FALSE"; - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter NATIVE_ODELAY_BYPASS = "FALSE"; - parameter OUTPUT_PHASE_90 = "FALSE"; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter TBYTE_CTL = "TBYTE_IN"; - parameter UPDATE_MODE = "ASYNC"; - output [8:0] CNTVALUEOUT; - output O; - output [39:0] RX_BIT_CTRL_OUT; - output [39:0] TX_BIT_CTRL_OUT; - output T_OUT; - input CE; - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [8:0] CNTVALUEIN; - input [7:0] D; - input EN_VTC; - input INC; - input LOAD; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RST_DLY_INVERTED" *) - input RST_DLY; - input [39:0] RX_BIT_CTRL_IN; - input T; - input TBYTE_IN; - input [39:0] TX_BIT_CTRL_IN; -endmodule - -module TX_BITSLICE_TRI (...); - parameter integer DATA_WIDTH = 8; - parameter DELAY_FORMAT = "TIME"; - parameter DELAY_TYPE = "FIXED"; - parameter integer DELAY_VALUE = 0; - parameter [0:0] INIT = 1'b1; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter [0:0] IS_RST_DLY_INVERTED = 1'b0; - parameter [0:0] IS_RST_INVERTED = 1'b0; - parameter NATIVE_ODELAY_BYPASS = "FALSE"; - parameter OUTPUT_PHASE_90 = "FALSE"; - parameter real REFCLK_FREQUENCY = 300.0; - parameter SIM_DEVICE = "ULTRASCALE"; - parameter real SIM_VERSION = 2.0; - parameter UPDATE_MODE = "ASYNC"; - output [39:0] BIT_CTRL_OUT; - output [8:0] CNTVALUEOUT; - output TRI_OUT; - input [39:0] BIT_CTRL_IN; - input CE; - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input [8:0] CNTVALUEIN; - input EN_VTC; - input INC; - input LOAD; - (* invertible_pin = "IS_RST_INVERTED" *) - input RST; - (* invertible_pin = "IS_RST_DLY_INVERTED" *) - input RST_DLY; -endmodule - -module HARD_SYNC (...); - parameter [0:0] INIT = 1'b0; - parameter [0:0] IS_CLK_INVERTED = 1'b0; - parameter integer LATENCY = 2; - output DOUT; - (* clkbuf_sink *) - (* invertible_pin = "IS_CLK_INVERTED" *) - input CLK; - input DIN; -endmodule - -module IDDRE1 (...); - parameter DDR_CLK_EDGE = "OPPOSITE_EDGE"; - parameter [0:0] IS_CB_INVERTED = 1'b0; - parameter [0:0] IS_C_INVERTED = 1'b0; - output Q1; - output Q2; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* clkbuf_sink *) - (* invertible_pin = "IS_CB_INVERTED" *) - input CB; - input D; - input R; -endmodule - -module ODDRE1 (...); - parameter [0:0] IS_C_INVERTED = 1'b0; - parameter [0:0] IS_D1_INVERTED = 1'b0; - parameter [0:0] IS_D2_INVERTED = 1'b0; - parameter [0:0] SRVAL = 1'b0; - output Q; - (* clkbuf_sink *) - (* invertible_pin = "IS_C_INVERTED" *) - input C; - (* invertible_pin = "IS_D1_INVERTED" *) - input D1; - (* invertible_pin = "IS_D2_INVERTED" *) - input D2; - input SR; -endmodule - -(* keep *) -module PS8 (...); - output [7:0] ADMA2PLCACK; - output [7:0] ADMA2PLTVLD; - output DPAUDIOREFCLK; - output DPAUXDATAOEN; - output DPAUXDATAOUT; - output DPLIVEVIDEODEOUT; - output [31:0] DPMAXISMIXEDAUDIOTDATA; - output DPMAXISMIXEDAUDIOTID; - output DPMAXISMIXEDAUDIOTVALID; - output DPSAXISAUDIOTREADY; - output DPVIDEOOUTHSYNC; - output [35:0] DPVIDEOOUTPIXEL1; - output DPVIDEOOUTVSYNC; - output DPVIDEOREFCLK; - output EMIOCAN0PHYTX; - output EMIOCAN1PHYTX; - output [1:0] EMIOENET0DMABUSWIDTH; - output EMIOENET0DMATXENDTOG; - output [93:0] EMIOENET0GEMTSUTIMERCNT; - output [7:0] EMIOENET0GMIITXD; - output EMIOENET0GMIITXEN; - output EMIOENET0GMIITXER; - output EMIOENET0MDIOMDC; - output EMIOENET0MDIOO; - output EMIOENET0MDIOTN; - output [7:0] EMIOENET0RXWDATA; - output EMIOENET0RXWEOP; - output EMIOENET0RXWERR; - output EMIOENET0RXWFLUSH; - output EMIOENET0RXWSOP; - output [44:0] EMIOENET0RXWSTATUS; - output EMIOENET0RXWWR; - output [2:0] EMIOENET0SPEEDMODE; - output EMIOENET0TXRRD; - output [3:0] EMIOENET0TXRSTATUS; - output [1:0] EMIOENET1DMABUSWIDTH; - output EMIOENET1DMATXENDTOG; - output [7:0] EMIOENET1GMIITXD; - output EMIOENET1GMIITXEN; - output EMIOENET1GMIITXER; - output EMIOENET1MDIOMDC; - output EMIOENET1MDIOO; - output EMIOENET1MDIOTN; - output [7:0] EMIOENET1RXWDATA; - output EMIOENET1RXWEOP; - output EMIOENET1RXWERR; - output EMIOENET1RXWFLUSH; - output EMIOENET1RXWSOP; - output [44:0] EMIOENET1RXWSTATUS; - output EMIOENET1RXWWR; - output [2:0] EMIOENET1SPEEDMODE; - output EMIOENET1TXRRD; - output [3:0] EMIOENET1TXRSTATUS; - output [1:0] EMIOENET2DMABUSWIDTH; - output EMIOENET2DMATXENDTOG; - output [7:0] EMIOENET2GMIITXD; - output EMIOENET2GMIITXEN; - output EMIOENET2GMIITXER; - output EMIOENET2MDIOMDC; - output EMIOENET2MDIOO; - output EMIOENET2MDIOTN; - output [7:0] EMIOENET2RXWDATA; - output EMIOENET2RXWEOP; - output EMIOENET2RXWERR; - output EMIOENET2RXWFLUSH; - output EMIOENET2RXWSOP; - output [44:0] EMIOENET2RXWSTATUS; - output EMIOENET2RXWWR; - output [2:0] EMIOENET2SPEEDMODE; - output EMIOENET2TXRRD; - output [3:0] EMIOENET2TXRSTATUS; - output [1:0] EMIOENET3DMABUSWIDTH; - output EMIOENET3DMATXENDTOG; - output [7:0] EMIOENET3GMIITXD; - output EMIOENET3GMIITXEN; - output EMIOENET3GMIITXER; - output EMIOENET3MDIOMDC; - output EMIOENET3MDIOO; - output EMIOENET3MDIOTN; - output [7:0] EMIOENET3RXWDATA; - output EMIOENET3RXWEOP; - output EMIOENET3RXWERR; - output EMIOENET3RXWFLUSH; - output EMIOENET3RXWSOP; - output [44:0] EMIOENET3RXWSTATUS; - output EMIOENET3RXWWR; - output [2:0] EMIOENET3SPEEDMODE; - output EMIOENET3TXRRD; - output [3:0] EMIOENET3TXRSTATUS; - output EMIOGEM0DELAYREQRX; - output EMIOGEM0DELAYREQTX; - output EMIOGEM0PDELAYREQRX; - output EMIOGEM0PDELAYREQTX; - output EMIOGEM0PDELAYRESPRX; - output EMIOGEM0PDELAYRESPTX; - output EMIOGEM0RXSOF; - output EMIOGEM0SYNCFRAMERX; - output EMIOGEM0SYNCFRAMETX; - output EMIOGEM0TSUTIMERCMPVAL; - output EMIOGEM0TXRFIXEDLAT; - output EMIOGEM0TXSOF; - output EMIOGEM1DELAYREQRX; - output EMIOGEM1DELAYREQTX; - output EMIOGEM1PDELAYREQRX; - output EMIOGEM1PDELAYREQTX; - output EMIOGEM1PDELAYRESPRX; - output EMIOGEM1PDELAYRESPTX; - output EMIOGEM1RXSOF; - output EMIOGEM1SYNCFRAMERX; - output EMIOGEM1SYNCFRAMETX; - output EMIOGEM1TSUTIMERCMPVAL; - output EMIOGEM1TXRFIXEDLAT; - output EMIOGEM1TXSOF; - output EMIOGEM2DELAYREQRX; - output EMIOGEM2DELAYREQTX; - output EMIOGEM2PDELAYREQRX; - output EMIOGEM2PDELAYREQTX; - output EMIOGEM2PDELAYRESPRX; - output EMIOGEM2PDELAYRESPTX; - output EMIOGEM2RXSOF; - output EMIOGEM2SYNCFRAMERX; - output EMIOGEM2SYNCFRAMETX; - output EMIOGEM2TSUTIMERCMPVAL; - output EMIOGEM2TXRFIXEDLAT; - output EMIOGEM2TXSOF; - output EMIOGEM3DELAYREQRX; - output EMIOGEM3DELAYREQTX; - output EMIOGEM3PDELAYREQRX; - output EMIOGEM3PDELAYREQTX; - output EMIOGEM3PDELAYRESPRX; - output EMIOGEM3PDELAYRESPTX; - output EMIOGEM3RXSOF; - output EMIOGEM3SYNCFRAMERX; - output EMIOGEM3SYNCFRAMETX; - output EMIOGEM3TSUTIMERCMPVAL; - output EMIOGEM3TXRFIXEDLAT; - output EMIOGEM3TXSOF; - output [95:0] EMIOGPIOO; - output [95:0] EMIOGPIOTN; - output EMIOI2C0SCLO; - output EMIOI2C0SCLTN; - output EMIOI2C0SDAO; - output EMIOI2C0SDATN; - output EMIOI2C1SCLO; - output EMIOI2C1SCLTN; - output EMIOI2C1SDAO; - output EMIOI2C1SDATN; - output EMIOSDIO0BUSPOWER; - output [2:0] EMIOSDIO0BUSVOLT; - output EMIOSDIO0CLKOUT; - output EMIOSDIO0CMDENA; - output EMIOSDIO0CMDOUT; - output [7:0] EMIOSDIO0DATAENA; - output [7:0] EMIOSDIO0DATAOUT; - output EMIOSDIO0LEDCONTROL; - output EMIOSDIO1BUSPOWER; - output [2:0] EMIOSDIO1BUSVOLT; - output EMIOSDIO1CLKOUT; - output EMIOSDIO1CMDENA; - output EMIOSDIO1CMDOUT; - output [7:0] EMIOSDIO1DATAENA; - output [7:0] EMIOSDIO1DATAOUT; - output EMIOSDIO1LEDCONTROL; - output EMIOSPI0MO; - output EMIOSPI0MOTN; - output EMIOSPI0SCLKO; - output EMIOSPI0SCLKTN; - output EMIOSPI0SO; - output EMIOSPI0SSNTN; - output [2:0] EMIOSPI0SSON; - output EMIOSPI0STN; - output EMIOSPI1MO; - output EMIOSPI1MOTN; - output EMIOSPI1SCLKO; - output EMIOSPI1SCLKTN; - output EMIOSPI1SO; - output EMIOSPI1SSNTN; - output [2:0] EMIOSPI1SSON; - output EMIOSPI1STN; - output [2:0] EMIOTTC0WAVEO; - output [2:0] EMIOTTC1WAVEO; - output [2:0] EMIOTTC2WAVEO; - output [2:0] EMIOTTC3WAVEO; - output EMIOU2DSPORTVBUSCTRLUSB30; - output EMIOU2DSPORTVBUSCTRLUSB31; - output EMIOU3DSPORTVBUSCTRLUSB30; - output EMIOU3DSPORTVBUSCTRLUSB31; - output EMIOUART0DTRN; - output EMIOUART0RTSN; - output EMIOUART0TX; - output EMIOUART1DTRN; - output EMIOUART1RTSN; - output EMIOUART1TX; - output EMIOWDT0RSTO; - output EMIOWDT1RSTO; - output FMIOGEM0FIFORXCLKTOPLBUFG; - output FMIOGEM0FIFOTXCLKTOPLBUFG; - output FMIOGEM1FIFORXCLKTOPLBUFG; - output FMIOGEM1FIFOTXCLKTOPLBUFG; - output FMIOGEM2FIFORXCLKTOPLBUFG; - output FMIOGEM2FIFOTXCLKTOPLBUFG; - output FMIOGEM3FIFORXCLKTOPLBUFG; - output FMIOGEM3FIFOTXCLKTOPLBUFG; - output FMIOGEMTSUCLKTOPLBUFG; - output [31:0] FTMGPO; - output [7:0] GDMA2PLCACK; - output [7:0] GDMA2PLTVLD; - output [39:0] MAXIGP0ARADDR; - output [1:0] MAXIGP0ARBURST; - output [3:0] MAXIGP0ARCACHE; - output [15:0] MAXIGP0ARID; - output [7:0] MAXIGP0ARLEN; - output MAXIGP0ARLOCK; - output [2:0] MAXIGP0ARPROT; - output [3:0] MAXIGP0ARQOS; - output [2:0] MAXIGP0ARSIZE; - output [15:0] MAXIGP0ARUSER; - output MAXIGP0ARVALID; - output [39:0] MAXIGP0AWADDR; - output [1:0] MAXIGP0AWBURST; - output [3:0] MAXIGP0AWCACHE; - output [15:0] MAXIGP0AWID; - output [7:0] MAXIGP0AWLEN; - output MAXIGP0AWLOCK; - output [2:0] MAXIGP0AWPROT; - output [3:0] MAXIGP0AWQOS; - output [2:0] MAXIGP0AWSIZE; - output [15:0] MAXIGP0AWUSER; - output MAXIGP0AWVALID; - output MAXIGP0BREADY; - output MAXIGP0RREADY; - output [127:0] MAXIGP0WDATA; - output MAXIGP0WLAST; - output [15:0] MAXIGP0WSTRB; - output MAXIGP0WVALID; - output [39:0] MAXIGP1ARADDR; - output [1:0] MAXIGP1ARBURST; - output [3:0] MAXIGP1ARCACHE; - output [15:0] MAXIGP1ARID; - output [7:0] MAXIGP1ARLEN; - output MAXIGP1ARLOCK; - output [2:0] MAXIGP1ARPROT; - output [3:0] MAXIGP1ARQOS; - output [2:0] MAXIGP1ARSIZE; - output [15:0] MAXIGP1ARUSER; - output MAXIGP1ARVALID; - output [39:0] MAXIGP1AWADDR; - output [1:0] MAXIGP1AWBURST; - output [3:0] MAXIGP1AWCACHE; - output [15:0] MAXIGP1AWID; - output [7:0] MAXIGP1AWLEN; - output MAXIGP1AWLOCK; - output [2:0] MAXIGP1AWPROT; - output [3:0] MAXIGP1AWQOS; - output [2:0] MAXIGP1AWSIZE; - output [15:0] MAXIGP1AWUSER; - output MAXIGP1AWVALID; - output MAXIGP1BREADY; - output MAXIGP1RREADY; - output [127:0] MAXIGP1WDATA; - output MAXIGP1WLAST; - output [15:0] MAXIGP1WSTRB; - output MAXIGP1WVALID; - output [39:0] MAXIGP2ARADDR; - output [1:0] MAXIGP2ARBURST; - output [3:0] MAXIGP2ARCACHE; - output [15:0] MAXIGP2ARID; - output [7:0] MAXIGP2ARLEN; - output MAXIGP2ARLOCK; - output [2:0] MAXIGP2ARPROT; - output [3:0] MAXIGP2ARQOS; - output [2:0] MAXIGP2ARSIZE; - output [15:0] MAXIGP2ARUSER; - output MAXIGP2ARVALID; - output [39:0] MAXIGP2AWADDR; - output [1:0] MAXIGP2AWBURST; - output [3:0] MAXIGP2AWCACHE; - output [15:0] MAXIGP2AWID; - output [7:0] MAXIGP2AWLEN; - output MAXIGP2AWLOCK; - output [2:0] MAXIGP2AWPROT; - output [3:0] MAXIGP2AWQOS; - output [2:0] MAXIGP2AWSIZE; - output [15:0] MAXIGP2AWUSER; - output MAXIGP2AWVALID; - output MAXIGP2BREADY; - output MAXIGP2RREADY; - output [127:0] MAXIGP2WDATA; - output MAXIGP2WLAST; - output [15:0] MAXIGP2WSTRB; - output MAXIGP2WVALID; - output OSCRTCCLK; - output [3:0] PLCLK; - output PMUAIBAFIFMFPDREQ; - output PMUAIBAFIFMLPDREQ; - output [46:0] PMUERRORTOPL; - output [31:0] PMUPLGPO; - output PSPLEVENTO; - output [63:0] PSPLIRQFPD; - output [99:0] PSPLIRQLPD; - output [3:0] PSPLSTANDBYWFE; - output [3:0] PSPLSTANDBYWFI; - output PSPLTRACECTL; - output [31:0] PSPLTRACEDATA; - output [3:0] PSPLTRIGACK; - output [3:0] PSPLTRIGGER; - output PSS_ALTO_CORE_PAD_MGTTXN0OUT; - output PSS_ALTO_CORE_PAD_MGTTXN1OUT; - output PSS_ALTO_CORE_PAD_MGTTXN2OUT; - output PSS_ALTO_CORE_PAD_MGTTXN3OUT; - output PSS_ALTO_CORE_PAD_MGTTXP0OUT; - output PSS_ALTO_CORE_PAD_MGTTXP1OUT; - output PSS_ALTO_CORE_PAD_MGTTXP2OUT; - output PSS_ALTO_CORE_PAD_MGTTXP3OUT; - output PSS_ALTO_CORE_PAD_PADO; - output RPUEVENTO0; - output RPUEVENTO1; - output [43:0] SACEFPDACADDR; - output [2:0] SACEFPDACPROT; - output [3:0] SACEFPDACSNOOP; - output SACEFPDACVALID; - output SACEFPDARREADY; - output SACEFPDAWREADY; - output [5:0] SACEFPDBID; - output [1:0] SACEFPDBRESP; - output SACEFPDBUSER; - output SACEFPDBVALID; - output SACEFPDCDREADY; - output SACEFPDCRREADY; - output [127:0] SACEFPDRDATA; - output [5:0] SACEFPDRID; - output SACEFPDRLAST; - output [3:0] SACEFPDRRESP; - output SACEFPDRUSER; - output SACEFPDRVALID; - output SACEFPDWREADY; - output SAXIACPARREADY; - output SAXIACPAWREADY; - output [4:0] SAXIACPBID; - output [1:0] SAXIACPBRESP; - output SAXIACPBVALID; - output [127:0] SAXIACPRDATA; - output [4:0] SAXIACPRID; - output SAXIACPRLAST; - output [1:0] SAXIACPRRESP; - output SAXIACPRVALID; - output SAXIACPWREADY; - output SAXIGP0ARREADY; - output SAXIGP0AWREADY; - output [5:0] SAXIGP0BID; - output [1:0] SAXIGP0BRESP; - output SAXIGP0BVALID; - output [3:0] SAXIGP0RACOUNT; - output [7:0] SAXIGP0RCOUNT; - output [127:0] SAXIGP0RDATA; - output [5:0] SAXIGP0RID; - output SAXIGP0RLAST; - output [1:0] SAXIGP0RRESP; - output SAXIGP0RVALID; - output [3:0] SAXIGP0WACOUNT; - output [7:0] SAXIGP0WCOUNT; - output SAXIGP0WREADY; - output SAXIGP1ARREADY; - output SAXIGP1AWREADY; - output [5:0] SAXIGP1BID; - output [1:0] SAXIGP1BRESP; - output SAXIGP1BVALID; - output [3:0] SAXIGP1RACOUNT; - output [7:0] SAXIGP1RCOUNT; - output [127:0] SAXIGP1RDATA; - output [5:0] SAXIGP1RID; - output SAXIGP1RLAST; - output [1:0] SAXIGP1RRESP; - output SAXIGP1RVALID; - output [3:0] SAXIGP1WACOUNT; - output [7:0] SAXIGP1WCOUNT; - output SAXIGP1WREADY; - output SAXIGP2ARREADY; - output SAXIGP2AWREADY; - output [5:0] SAXIGP2BID; - output [1:0] SAXIGP2BRESP; - output SAXIGP2BVALID; - output [3:0] SAXIGP2RACOUNT; - output [7:0] SAXIGP2RCOUNT; - output [127:0] SAXIGP2RDATA; - output [5:0] SAXIGP2RID; - output SAXIGP2RLAST; - output [1:0] SAXIGP2RRESP; - output SAXIGP2RVALID; - output [3:0] SAXIGP2WACOUNT; - output [7:0] SAXIGP2WCOUNT; - output SAXIGP2WREADY; - output SAXIGP3ARREADY; - output SAXIGP3AWREADY; - output [5:0] SAXIGP3BID; - output [1:0] SAXIGP3BRESP; - output SAXIGP3BVALID; - output [3:0] SAXIGP3RACOUNT; - output [7:0] SAXIGP3RCOUNT; - output [127:0] SAXIGP3RDATA; - output [5:0] SAXIGP3RID; - output SAXIGP3RLAST; - output [1:0] SAXIGP3RRESP; - output SAXIGP3RVALID; - output [3:0] SAXIGP3WACOUNT; - output [7:0] SAXIGP3WCOUNT; - output SAXIGP3WREADY; - output SAXIGP4ARREADY; - output SAXIGP4AWREADY; - output [5:0] SAXIGP4BID; - output [1:0] SAXIGP4BRESP; - output SAXIGP4BVALID; - output [3:0] SAXIGP4RACOUNT; - output [7:0] SAXIGP4RCOUNT; - output [127:0] SAXIGP4RDATA; - output [5:0] SAXIGP4RID; - output SAXIGP4RLAST; - output [1:0] SAXIGP4RRESP; - output SAXIGP4RVALID; - output [3:0] SAXIGP4WACOUNT; - output [7:0] SAXIGP4WCOUNT; - output SAXIGP4WREADY; - output SAXIGP5ARREADY; - output SAXIGP5AWREADY; - output [5:0] SAXIGP5BID; - output [1:0] SAXIGP5BRESP; - output SAXIGP5BVALID; - output [3:0] SAXIGP5RACOUNT; - output [7:0] SAXIGP5RCOUNT; - output [127:0] SAXIGP5RDATA; - output [5:0] SAXIGP5RID; - output SAXIGP5RLAST; - output [1:0] SAXIGP5RRESP; - output SAXIGP5RVALID; - output [3:0] SAXIGP5WACOUNT; - output [7:0] SAXIGP5WCOUNT; - output SAXIGP5WREADY; - output SAXIGP6ARREADY; - output SAXIGP6AWREADY; - output [5:0] SAXIGP6BID; - output [1:0] SAXIGP6BRESP; - output SAXIGP6BVALID; - output [3:0] SAXIGP6RACOUNT; - output [7:0] SAXIGP6RCOUNT; - output [127:0] SAXIGP6RDATA; - output [5:0] SAXIGP6RID; - output SAXIGP6RLAST; - output [1:0] SAXIGP6RRESP; - output SAXIGP6RVALID; - output [3:0] SAXIGP6WACOUNT; - output [7:0] SAXIGP6WCOUNT; - output SAXIGP6WREADY; - inout [3:0] PSS_ALTO_CORE_PAD_BOOTMODE; - inout PSS_ALTO_CORE_PAD_CLK; - inout PSS_ALTO_CORE_PAD_DONEB; - inout [17:0] PSS_ALTO_CORE_PAD_DRAMA; - inout PSS_ALTO_CORE_PAD_DRAMACTN; - inout PSS_ALTO_CORE_PAD_DRAMALERTN; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMBA; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMBG; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMCK; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKE; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMCKN; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMCSN; - inout [8:0] PSS_ALTO_CORE_PAD_DRAMDM; - inout [71:0] PSS_ALTO_CORE_PAD_DRAMDQ; - inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQS; - inout [8:0] PSS_ALTO_CORE_PAD_DRAMDQSN; - inout [1:0] PSS_ALTO_CORE_PAD_DRAMODT; - inout PSS_ALTO_CORE_PAD_DRAMPARITY; - inout PSS_ALTO_CORE_PAD_DRAMRAMRSTN; - inout PSS_ALTO_CORE_PAD_ERROROUT; - inout PSS_ALTO_CORE_PAD_ERRORSTATUS; - inout PSS_ALTO_CORE_PAD_INITB; - inout PSS_ALTO_CORE_PAD_JTAGTCK; - inout PSS_ALTO_CORE_PAD_JTAGTDI; - inout PSS_ALTO_CORE_PAD_JTAGTDO; - inout PSS_ALTO_CORE_PAD_JTAGTMS; - inout [77:0] PSS_ALTO_CORE_PAD_MIO; - inout PSS_ALTO_CORE_PAD_PORB; - inout PSS_ALTO_CORE_PAD_PROGB; - inout PSS_ALTO_CORE_PAD_RCALIBINOUT; - inout PSS_ALTO_CORE_PAD_SRSTB; - inout PSS_ALTO_CORE_PAD_ZQ; - input [7:0] ADMAFCICLK; - input AIBPMUAFIFMFPDACK; - input AIBPMUAFIFMLPDACK; - input DDRCEXTREFRESHRANK0REQ; - input DDRCEXTREFRESHRANK1REQ; - input DDRCREFRESHPLCLK; - input DPAUXDATAIN; - input DPEXTERNALCUSTOMEVENT1; - input DPEXTERNALCUSTOMEVENT2; - input DPEXTERNALVSYNCEVENT; - input DPHOTPLUGDETECT; - input [7:0] DPLIVEGFXALPHAIN; - input [35:0] DPLIVEGFXPIXEL1IN; - input DPLIVEVIDEOINDE; - input DPLIVEVIDEOINHSYNC; - input [35:0] DPLIVEVIDEOINPIXEL1; - input DPLIVEVIDEOINVSYNC; - input DPMAXISMIXEDAUDIOTREADY; - input DPSAXISAUDIOCLK; - input [31:0] DPSAXISAUDIOTDATA; - input DPSAXISAUDIOTID; - input DPSAXISAUDIOTVALID; - input DPVIDEOINCLK; - input EMIOCAN0PHYRX; - input EMIOCAN1PHYRX; - input EMIOENET0DMATXSTATUSTOG; - input EMIOENET0EXTINTIN; - input EMIOENET0GMIICOL; - input EMIOENET0GMIICRS; - input EMIOENET0GMIIRXCLK; - input [7:0] EMIOENET0GMIIRXD; - input EMIOENET0GMIIRXDV; - input EMIOENET0GMIIRXER; - input EMIOENET0GMIITXCLK; - input EMIOENET0MDIOI; - input EMIOENET0RXWOVERFLOW; - input EMIOENET0TXRCONTROL; - input [7:0] EMIOENET0TXRDATA; - input EMIOENET0TXRDATARDY; - input EMIOENET0TXREOP; - input EMIOENET0TXRERR; - input EMIOENET0TXRFLUSHED; - input EMIOENET0TXRSOP; - input EMIOENET0TXRUNDERFLOW; - input EMIOENET0TXRVALID; - input EMIOENET1DMATXSTATUSTOG; - input EMIOENET1EXTINTIN; - input EMIOENET1GMIICOL; - input EMIOENET1GMIICRS; - input EMIOENET1GMIIRXCLK; - input [7:0] EMIOENET1GMIIRXD; - input EMIOENET1GMIIRXDV; - input EMIOENET1GMIIRXER; - input EMIOENET1GMIITXCLK; - input EMIOENET1MDIOI; - input EMIOENET1RXWOVERFLOW; - input EMIOENET1TXRCONTROL; - input [7:0] EMIOENET1TXRDATA; - input EMIOENET1TXRDATARDY; - input EMIOENET1TXREOP; - input EMIOENET1TXRERR; - input EMIOENET1TXRFLUSHED; - input EMIOENET1TXRSOP; - input EMIOENET1TXRUNDERFLOW; - input EMIOENET1TXRVALID; - input EMIOENET2DMATXSTATUSTOG; - input EMIOENET2EXTINTIN; - input EMIOENET2GMIICOL; - input EMIOENET2GMIICRS; - input EMIOENET2GMIIRXCLK; - input [7:0] EMIOENET2GMIIRXD; - input EMIOENET2GMIIRXDV; - input EMIOENET2GMIIRXER; - input EMIOENET2GMIITXCLK; - input EMIOENET2MDIOI; - input EMIOENET2RXWOVERFLOW; - input EMIOENET2TXRCONTROL; - input [7:0] EMIOENET2TXRDATA; - input EMIOENET2TXRDATARDY; - input EMIOENET2TXREOP; - input EMIOENET2TXRERR; - input EMIOENET2TXRFLUSHED; - input EMIOENET2TXRSOP; - input EMIOENET2TXRUNDERFLOW; - input EMIOENET2TXRVALID; - input EMIOENET3DMATXSTATUSTOG; - input EMIOENET3EXTINTIN; - input EMIOENET3GMIICOL; - input EMIOENET3GMIICRS; - input EMIOENET3GMIIRXCLK; - input [7:0] EMIOENET3GMIIRXD; - input EMIOENET3GMIIRXDV; - input EMIOENET3GMIIRXER; - input EMIOENET3GMIITXCLK; - input EMIOENET3MDIOI; - input EMIOENET3RXWOVERFLOW; - input EMIOENET3TXRCONTROL; - input [7:0] EMIOENET3TXRDATA; - input EMIOENET3TXRDATARDY; - input EMIOENET3TXREOP; - input EMIOENET3TXRERR; - input EMIOENET3TXRFLUSHED; - input EMIOENET3TXRSOP; - input EMIOENET3TXRUNDERFLOW; - input EMIOENET3TXRVALID; - input EMIOENETTSUCLK; - input [1:0] EMIOGEM0TSUINCCTRL; - input [1:0] EMIOGEM1TSUINCCTRL; - input [1:0] EMIOGEM2TSUINCCTRL; - input [1:0] EMIOGEM3TSUINCCTRL; - input [95:0] EMIOGPIOI; - input EMIOHUBPORTOVERCRNTUSB20; - input EMIOHUBPORTOVERCRNTUSB21; - input EMIOHUBPORTOVERCRNTUSB30; - input EMIOHUBPORTOVERCRNTUSB31; - input EMIOI2C0SCLI; - input EMIOI2C0SDAI; - input EMIOI2C1SCLI; - input EMIOI2C1SDAI; - input EMIOSDIO0CDN; - input EMIOSDIO0CMDIN; - input [7:0] EMIOSDIO0DATAIN; - input EMIOSDIO0FBCLKIN; - input EMIOSDIO0WP; - input EMIOSDIO1CDN; - input EMIOSDIO1CMDIN; - input [7:0] EMIOSDIO1DATAIN; - input EMIOSDIO1FBCLKIN; - input EMIOSDIO1WP; - input EMIOSPI0MI; - input EMIOSPI0SCLKI; - input EMIOSPI0SI; - input EMIOSPI0SSIN; - input EMIOSPI1MI; - input EMIOSPI1SCLKI; - input EMIOSPI1SI; - input EMIOSPI1SSIN; - input [2:0] EMIOTTC0CLKI; - input [2:0] EMIOTTC1CLKI; - input [2:0] EMIOTTC2CLKI; - input [2:0] EMIOTTC3CLKI; - input EMIOUART0CTSN; - input EMIOUART0DCDN; - input EMIOUART0DSRN; - input EMIOUART0RIN; - input EMIOUART0RX; - input EMIOUART1CTSN; - input EMIOUART1DCDN; - input EMIOUART1DSRN; - input EMIOUART1RIN; - input EMIOUART1RX; - input EMIOWDT0CLKI; - input EMIOWDT1CLKI; - input FMIOGEM0FIFORXCLKFROMPL; - input FMIOGEM0FIFOTXCLKFROMPL; - input FMIOGEM0SIGNALDETECT; - input FMIOGEM1FIFORXCLKFROMPL; - input FMIOGEM1FIFOTXCLKFROMPL; - input FMIOGEM1SIGNALDETECT; - input FMIOGEM2FIFORXCLKFROMPL; - input FMIOGEM2FIFOTXCLKFROMPL; - input FMIOGEM2SIGNALDETECT; - input FMIOGEM3FIFORXCLKFROMPL; - input FMIOGEM3FIFOTXCLKFROMPL; - input FMIOGEM3SIGNALDETECT; - input FMIOGEMTSUCLKFROMPL; - input [31:0] FTMGPI; - input [7:0] GDMAFCICLK; - input MAXIGP0ACLK; - input MAXIGP0ARREADY; - input MAXIGP0AWREADY; - input [15:0] MAXIGP0BID; - input [1:0] MAXIGP0BRESP; - input MAXIGP0BVALID; - input [127:0] MAXIGP0RDATA; - input [15:0] MAXIGP0RID; - input MAXIGP0RLAST; - input [1:0] MAXIGP0RRESP; - input MAXIGP0RVALID; - input MAXIGP0WREADY; - input MAXIGP1ACLK; - input MAXIGP1ARREADY; - input MAXIGP1AWREADY; - input [15:0] MAXIGP1BID; - input [1:0] MAXIGP1BRESP; - input MAXIGP1BVALID; - input [127:0] MAXIGP1RDATA; - input [15:0] MAXIGP1RID; - input MAXIGP1RLAST; - input [1:0] MAXIGP1RRESP; - input MAXIGP1RVALID; - input MAXIGP1WREADY; - input MAXIGP2ACLK; - input MAXIGP2ARREADY; - input MAXIGP2AWREADY; - input [15:0] MAXIGP2BID; - input [1:0] MAXIGP2BRESP; - input MAXIGP2BVALID; - input [127:0] MAXIGP2RDATA; - input [15:0] MAXIGP2RID; - input MAXIGP2RLAST; - input [1:0] MAXIGP2RRESP; - input MAXIGP2RVALID; - input MAXIGP2WREADY; - input NFIQ0LPDRPU; - input NFIQ1LPDRPU; - input NIRQ0LPDRPU; - input NIRQ1LPDRPU; - input [7:0] PL2ADMACVLD; - input [7:0] PL2ADMATACK; - input [7:0] PL2GDMACVLD; - input [7:0] PL2GDMATACK; - input PLACECLK; - input PLACPINACT; - input [3:0] PLFPGASTOP; - input [2:0] PLLAUXREFCLKFPD; - input [1:0] PLLAUXREFCLKLPD; - input [31:0] PLPMUGPI; - input [3:0] PLPSAPUGICFIQ; - input [3:0] PLPSAPUGICIRQ; - input PLPSEVENTI; - input [7:0] PLPSIRQ0; - input [7:0] PLPSIRQ1; - input PLPSTRACECLK; - input [3:0] PLPSTRIGACK; - input [3:0] PLPSTRIGGER; - input [3:0] PMUERRORFROMPL; - input PSS_ALTO_CORE_PAD_MGTRXN0IN; - input PSS_ALTO_CORE_PAD_MGTRXN1IN; - input PSS_ALTO_CORE_PAD_MGTRXN2IN; - input PSS_ALTO_CORE_PAD_MGTRXN3IN; - input PSS_ALTO_CORE_PAD_MGTRXP0IN; - input PSS_ALTO_CORE_PAD_MGTRXP1IN; - input PSS_ALTO_CORE_PAD_MGTRXP2IN; - input PSS_ALTO_CORE_PAD_MGTRXP3IN; - input PSS_ALTO_CORE_PAD_PADI; - input PSS_ALTO_CORE_PAD_REFN0IN; - input PSS_ALTO_CORE_PAD_REFN1IN; - input PSS_ALTO_CORE_PAD_REFN2IN; - input PSS_ALTO_CORE_PAD_REFN3IN; - input PSS_ALTO_CORE_PAD_REFP0IN; - input PSS_ALTO_CORE_PAD_REFP1IN; - input PSS_ALTO_CORE_PAD_REFP2IN; - input PSS_ALTO_CORE_PAD_REFP3IN; - input RPUEVENTI0; - input RPUEVENTI1; - input SACEFPDACREADY; - input [43:0] SACEFPDARADDR; - input [1:0] SACEFPDARBAR; - input [1:0] SACEFPDARBURST; - input [3:0] SACEFPDARCACHE; - input [1:0] SACEFPDARDOMAIN; - input [5:0] SACEFPDARID; - input [7:0] SACEFPDARLEN; - input SACEFPDARLOCK; - input [2:0] SACEFPDARPROT; - input [3:0] SACEFPDARQOS; - input [3:0] SACEFPDARREGION; - input [2:0] SACEFPDARSIZE; - input [3:0] SACEFPDARSNOOP; - input [15:0] SACEFPDARUSER; - input SACEFPDARVALID; - input [43:0] SACEFPDAWADDR; - input [1:0] SACEFPDAWBAR; - input [1:0] SACEFPDAWBURST; - input [3:0] SACEFPDAWCACHE; - input [1:0] SACEFPDAWDOMAIN; - input [5:0] SACEFPDAWID; - input [7:0] SACEFPDAWLEN; - input SACEFPDAWLOCK; - input [2:0] SACEFPDAWPROT; - input [3:0] SACEFPDAWQOS; - input [3:0] SACEFPDAWREGION; - input [2:0] SACEFPDAWSIZE; - input [2:0] SACEFPDAWSNOOP; - input [15:0] SACEFPDAWUSER; - input SACEFPDAWVALID; - input SACEFPDBREADY; - input [127:0] SACEFPDCDDATA; - input SACEFPDCDLAST; - input SACEFPDCDVALID; - input [4:0] SACEFPDCRRESP; - input SACEFPDCRVALID; - input SACEFPDRACK; - input SACEFPDRREADY; - input SACEFPDWACK; - input [127:0] SACEFPDWDATA; - input SACEFPDWLAST; - input [15:0] SACEFPDWSTRB; - input SACEFPDWUSER; - input SACEFPDWVALID; - input SAXIACPACLK; - input [39:0] SAXIACPARADDR; - input [1:0] SAXIACPARBURST; - input [3:0] SAXIACPARCACHE; - input [4:0] SAXIACPARID; - input [7:0] SAXIACPARLEN; - input SAXIACPARLOCK; - input [2:0] SAXIACPARPROT; - input [3:0] SAXIACPARQOS; - input [2:0] SAXIACPARSIZE; - input [1:0] SAXIACPARUSER; - input SAXIACPARVALID; - input [39:0] SAXIACPAWADDR; - input [1:0] SAXIACPAWBURST; - input [3:0] SAXIACPAWCACHE; - input [4:0] SAXIACPAWID; - input [7:0] SAXIACPAWLEN; - input SAXIACPAWLOCK; - input [2:0] SAXIACPAWPROT; - input [3:0] SAXIACPAWQOS; - input [2:0] SAXIACPAWSIZE; - input [1:0] SAXIACPAWUSER; - input SAXIACPAWVALID; - input SAXIACPBREADY; - input SAXIACPRREADY; - input [127:0] SAXIACPWDATA; - input SAXIACPWLAST; - input [15:0] SAXIACPWSTRB; - input SAXIACPWVALID; - input [48:0] SAXIGP0ARADDR; - input [1:0] SAXIGP0ARBURST; - input [3:0] SAXIGP0ARCACHE; - input [5:0] SAXIGP0ARID; - input [7:0] SAXIGP0ARLEN; - input SAXIGP0ARLOCK; - input [2:0] SAXIGP0ARPROT; - input [3:0] SAXIGP0ARQOS; - input [2:0] SAXIGP0ARSIZE; - input SAXIGP0ARUSER; - input SAXIGP0ARVALID; - input [48:0] SAXIGP0AWADDR; - input [1:0] SAXIGP0AWBURST; - input [3:0] SAXIGP0AWCACHE; - input [5:0] SAXIGP0AWID; - input [7:0] SAXIGP0AWLEN; - input SAXIGP0AWLOCK; - input [2:0] SAXIGP0AWPROT; - input [3:0] SAXIGP0AWQOS; - input [2:0] SAXIGP0AWSIZE; - input SAXIGP0AWUSER; - input SAXIGP0AWVALID; - input SAXIGP0BREADY; - input SAXIGP0RCLK; - input SAXIGP0RREADY; - input SAXIGP0WCLK; - input [127:0] SAXIGP0WDATA; - input SAXIGP0WLAST; - input [15:0] SAXIGP0WSTRB; - input SAXIGP0WVALID; - input [48:0] SAXIGP1ARADDR; - input [1:0] SAXIGP1ARBURST; - input [3:0] SAXIGP1ARCACHE; - input [5:0] SAXIGP1ARID; - input [7:0] SAXIGP1ARLEN; - input SAXIGP1ARLOCK; - input [2:0] SAXIGP1ARPROT; - input [3:0] SAXIGP1ARQOS; - input [2:0] SAXIGP1ARSIZE; - input SAXIGP1ARUSER; - input SAXIGP1ARVALID; - input [48:0] SAXIGP1AWADDR; - input [1:0] SAXIGP1AWBURST; - input [3:0] SAXIGP1AWCACHE; - input [5:0] SAXIGP1AWID; - input [7:0] SAXIGP1AWLEN; - input SAXIGP1AWLOCK; - input [2:0] SAXIGP1AWPROT; - input [3:0] SAXIGP1AWQOS; - input [2:0] SAXIGP1AWSIZE; - input SAXIGP1AWUSER; - input SAXIGP1AWVALID; - input SAXIGP1BREADY; - input SAXIGP1RCLK; - input SAXIGP1RREADY; - input SAXIGP1WCLK; - input [127:0] SAXIGP1WDATA; - input SAXIGP1WLAST; - input [15:0] SAXIGP1WSTRB; - input SAXIGP1WVALID; - input [48:0] SAXIGP2ARADDR; - input [1:0] SAXIGP2ARBURST; - input [3:0] SAXIGP2ARCACHE; - input [5:0] SAXIGP2ARID; - input [7:0] SAXIGP2ARLEN; - input SAXIGP2ARLOCK; - input [2:0] SAXIGP2ARPROT; - input [3:0] SAXIGP2ARQOS; - input [2:0] SAXIGP2ARSIZE; - input SAXIGP2ARUSER; - input SAXIGP2ARVALID; - input [48:0] SAXIGP2AWADDR; - input [1:0] SAXIGP2AWBURST; - input [3:0] SAXIGP2AWCACHE; - input [5:0] SAXIGP2AWID; - input [7:0] SAXIGP2AWLEN; - input SAXIGP2AWLOCK; - input [2:0] SAXIGP2AWPROT; - input [3:0] SAXIGP2AWQOS; - input [2:0] SAXIGP2AWSIZE; - input SAXIGP2AWUSER; - input SAXIGP2AWVALID; - input SAXIGP2BREADY; - input SAXIGP2RCLK; - input SAXIGP2RREADY; - input SAXIGP2WCLK; - input [127:0] SAXIGP2WDATA; - input SAXIGP2WLAST; - input [15:0] SAXIGP2WSTRB; - input SAXIGP2WVALID; - input [48:0] SAXIGP3ARADDR; - input [1:0] SAXIGP3ARBURST; - input [3:0] SAXIGP3ARCACHE; - input [5:0] SAXIGP3ARID; - input [7:0] SAXIGP3ARLEN; - input SAXIGP3ARLOCK; - input [2:0] SAXIGP3ARPROT; - input [3:0] SAXIGP3ARQOS; - input [2:0] SAXIGP3ARSIZE; - input SAXIGP3ARUSER; - input SAXIGP3ARVALID; - input [48:0] SAXIGP3AWADDR; - input [1:0] SAXIGP3AWBURST; - input [3:0] SAXIGP3AWCACHE; - input [5:0] SAXIGP3AWID; - input [7:0] SAXIGP3AWLEN; - input SAXIGP3AWLOCK; - input [2:0] SAXIGP3AWPROT; - input [3:0] SAXIGP3AWQOS; - input [2:0] SAXIGP3AWSIZE; - input SAXIGP3AWUSER; - input SAXIGP3AWVALID; - input SAXIGP3BREADY; - input SAXIGP3RCLK; - input SAXIGP3RREADY; - input SAXIGP3WCLK; - input [127:0] SAXIGP3WDATA; - input SAXIGP3WLAST; - input [15:0] SAXIGP3WSTRB; - input SAXIGP3WVALID; - input [48:0] SAXIGP4ARADDR; - input [1:0] SAXIGP4ARBURST; - input [3:0] SAXIGP4ARCACHE; - input [5:0] SAXIGP4ARID; - input [7:0] SAXIGP4ARLEN; - input SAXIGP4ARLOCK; - input [2:0] SAXIGP4ARPROT; - input [3:0] SAXIGP4ARQOS; - input [2:0] SAXIGP4ARSIZE; - input SAXIGP4ARUSER; - input SAXIGP4ARVALID; - input [48:0] SAXIGP4AWADDR; - input [1:0] SAXIGP4AWBURST; - input [3:0] SAXIGP4AWCACHE; - input [5:0] SAXIGP4AWID; - input [7:0] SAXIGP4AWLEN; - input SAXIGP4AWLOCK; - input [2:0] SAXIGP4AWPROT; - input [3:0] SAXIGP4AWQOS; - input [2:0] SAXIGP4AWSIZE; - input SAXIGP4AWUSER; - input SAXIGP4AWVALID; - input SAXIGP4BREADY; - input SAXIGP4RCLK; - input SAXIGP4RREADY; - input SAXIGP4WCLK; - input [127:0] SAXIGP4WDATA; - input SAXIGP4WLAST; - input [15:0] SAXIGP4WSTRB; - input SAXIGP4WVALID; - input [48:0] SAXIGP5ARADDR; - input [1:0] SAXIGP5ARBURST; - input [3:0] SAXIGP5ARCACHE; - input [5:0] SAXIGP5ARID; - input [7:0] SAXIGP5ARLEN; - input SAXIGP5ARLOCK; - input [2:0] SAXIGP5ARPROT; - input [3:0] SAXIGP5ARQOS; - input [2:0] SAXIGP5ARSIZE; - input SAXIGP5ARUSER; - input SAXIGP5ARVALID; - input [48:0] SAXIGP5AWADDR; - input [1:0] SAXIGP5AWBURST; - input [3:0] SAXIGP5AWCACHE; - input [5:0] SAXIGP5AWID; - input [7:0] SAXIGP5AWLEN; - input SAXIGP5AWLOCK; - input [2:0] SAXIGP5AWPROT; - input [3:0] SAXIGP5AWQOS; - input [2:0] SAXIGP5AWSIZE; - input SAXIGP5AWUSER; - input SAXIGP5AWVALID; - input SAXIGP5BREADY; - input SAXIGP5RCLK; - input SAXIGP5RREADY; - input SAXIGP5WCLK; - input [127:0] SAXIGP5WDATA; - input SAXIGP5WLAST; - input [15:0] SAXIGP5WSTRB; - input SAXIGP5WVALID; - input [48:0] SAXIGP6ARADDR; - input [1:0] SAXIGP6ARBURST; - input [3:0] SAXIGP6ARCACHE; - input [5:0] SAXIGP6ARID; - input [7:0] SAXIGP6ARLEN; - input SAXIGP6ARLOCK; - input [2:0] SAXIGP6ARPROT; - input [3:0] SAXIGP6ARQOS; - input [2:0] SAXIGP6ARSIZE; - input SAXIGP6ARUSER; - input SAXIGP6ARVALID; - input [48:0] SAXIGP6AWADDR; - input [1:0] SAXIGP6AWBURST; - input [3:0] SAXIGP6AWCACHE; - input [5:0] SAXIGP6AWID; - input [7:0] SAXIGP6AWLEN; - input SAXIGP6AWLOCK; - input [2:0] SAXIGP6AWPROT; - input [3:0] SAXIGP6AWQOS; - input [2:0] SAXIGP6AWSIZE; - input SAXIGP6AWUSER; - input SAXIGP6AWVALID; - input SAXIGP6BREADY; - input SAXIGP6RCLK; - input SAXIGP6RREADY; - input SAXIGP6WCLK; - input [127:0] SAXIGP6WDATA; - input SAXIGP6WLAST; - input [15:0] SAXIGP6WSTRB; - input SAXIGP6WVALID; - input [59:0] STMEVENT; -endmodule - -- cgit v1.2.3 From 0e5dbc4abc2fb3a0d98d2dfb07e8642058d69bb1 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Wed, 6 Nov 2019 19:48:18 +0100 Subject: fix wide luts --- techlibs/gowin/cells_map.v | 24 ++++++++++++------------ tests/arch/gowin/mux.ys | 17 ++++++++++------- 2 files changed, 22 insertions(+), 19 deletions(-) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index 62cb080d9..93a49679c 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -104,27 +104,27 @@ module \$lut (A, Y); end else if (WIDTH == 5) begin wire f0, f1; - \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0)); - \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1)); - MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y)); + \$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[3:0]), .Y(f0)); + \$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[3:0]), .Y(f1)); + MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[4]), .O(Y)); end else if (WIDTH == 6) begin wire f0, f1; - \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0)); - \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1)); - MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y)); + \$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[4:0]), .Y(f0)); + \$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[4:0]), .Y(f1)); + MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[5]), .O(Y)); end else if (WIDTH == 7) begin wire f0, f1; - \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0)); - \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1)); - MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y)); + \$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[5:0]), .Y(f0)); + \$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[5:0]), .Y(f1)); + MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[6]), .O(Y)); end else if (WIDTH == 8) begin wire f0, f1; - \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0)); - \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1)); - MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y)); + \$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[6:0]), .Y(f0)); + \$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[6:0]), .Y(f1)); + MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[7]), .O(Y)); end else begin wire _TECHMAP_FAIL_ = 1; end diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index f7e478c87..4990be421 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -15,33 +15,36 @@ select -assert-none t:LUT3 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux4 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 2 t:LUT4 +select -assert-count 4 t:LUT4 +select -assert-count 2 t:MUX2_LUT5 +select -assert-count 1 t:MUX2_LUT6 select -assert-count 6 t:IBUF select -assert-count 1 t:OBUF -select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux8 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module select -assert-count 11 t:IBUF select -assert-count 1 t:OBUF -select -assert-none t:LUT4 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux16 proc -equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin -nowidelut # equivalency check +equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-count 20 t:IBUF select -assert-count 1 t:OBUF +show -select -assert-none t:LUT4 t:LUT3 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT4 t:MUX2_LUT6 t:MUX2_LUT5 t:MUX2_LUT6 t:MUX2_LUT7 t:MUX2_LUT8 t:IBUF t:OBUF %% t:* %D -- cgit v1.2.3 From 65f197e28f789aa6bcfd8f4841c0e1ebb91b99a8 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 7 Nov 2019 13:30:03 +0100 Subject: Add check for valid macro names in macro definitions Signed-off-by: Clifford Wolf --- frontends/verilog/preproc.cc | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index dea22ee8a..7e107dc26 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -490,13 +490,17 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons } while (newline_count-- > 0) return_char('\n'); - // printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str()); - defines_map[name] = value; - if (state == 2) - defines_with_args.insert(name); - else - defines_with_args.erase(name); - global_defines_cache[name] = std::pair(value, state == 2); + if (strchr("abcdefghijklmnopqrstuvwxyz_ABCDEFGHIJKLMNOPQRSTUVWXYZ$0123456789", name[0])) { + // printf("define: >>%s<< -> >>%s<<\n", name.c_str(), value.c_str()); + defines_map[name] = value; + if (state == 2) + defines_with_args.insert(name); + else + defines_with_args.erase(name); + global_defines_cache[name] = std::pair(value, state == 2); + } else { + log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str()); + } continue; } -- cgit v1.2.3 From 362f4f996d49cca4be240d5c96fba013dd56a8cb Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Mon, 11 Nov 2019 15:07:29 +0100 Subject: Do not map $eq and $ne in cmp2lut, only proper arithmetic cmp Signed-off-by: Clifford Wolf --- techlibs/common/cmp2lut.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/common/cmp2lut.v b/techlibs/common/cmp2lut.v index 0d0757767..1c8192b85 100644 --- a/techlibs/common/cmp2lut.v +++ b/techlibs/common/cmp2lut.v @@ -7,7 +7,7 @@ // with n <= k inputs should be techmapped in this way, because this shortens the critical path // from n to 1 by avoiding carry chains. -(* techmap_celltype = "$eq $ne $lt $le $gt $ge" *) +(* techmap_celltype = "$lt $le $gt $ge" *) module _90_lut_cmp_ (A, B, Y); parameter A_SIGNED = 0; -- cgit v1.2.3 From 3e0ffe05a79d3196b3644cddf422edb927673b04 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Mon, 11 Nov 2019 15:41:33 +0100 Subject: Fixed tests --- tests/arch/anlogic/fsm.ys | 11 +++++++---- tests/arch/ecp5/fsm.ys | 13 +++++++++---- tests/arch/efinix/fsm.ys | 8 +++++--- tests/arch/ice40/fsm.ys | 13 ++++++++----- tests/arch/xilinx/fsm.ys | 6 +++++- 5 files changed, 34 insertions(+), 17 deletions(-) diff --git a/tests/arch/anlogic/fsm.ys b/tests/arch/anlogic/fsm.ys index f45951b13..0bcc4e011 100644 --- a/tests/arch/anlogic/fsm.ys +++ b/tests/arch/anlogic/fsm.ys @@ -1,12 +1,15 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc -#flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check -equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check +flatten + +equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module + select -assert-count 1 t:AL_MAP_LUT2 select -assert-count 5 t:AL_MAP_LUT5 select -assert-count 1 t:AL_MAP_LUT6 diff --git a/tests/arch/ecp5/fsm.ys b/tests/arch/ecp5/fsm.ys index f834a4c6b..ba91e5fc0 100644 --- a/tests/arch/ecp5/fsm.ys +++ b/tests/arch/ecp5/fsm.ys @@ -2,11 +2,16 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc flatten -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check + +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module + select -assert-count 1 t:L6MUX21 -select -assert-count 13 t:LUT4 -select -assert-count 5 t:PFUMX -select -assert-count 5 t:TRELLIS_FF +select -assert-count 15 t:LUT4 +select -assert-count 6 t:PFUMX +select -assert-count 6 t:TRELLIS_FF select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/efinix/fsm.ys b/tests/arch/efinix/fsm.ys index a8ba70fdb..a2db2ad98 100644 --- a/tests/arch/efinix/fsm.ys +++ b/tests/arch/efinix/fsm.ys @@ -2,9 +2,11 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc flatten -#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'. -#equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -equiv_opt -map +/efinix/cells_sim.v synth_efinix # equivalency check + +equiv_opt -run :prove -map +/efinix/cells_sim.v synth_efinix +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module diff --git a/tests/arch/ice40/fsm.ys b/tests/arch/ice40/fsm.ys index 5aacc6c73..223ba070e 100644 --- a/tests/arch/ice40/fsm.ys +++ b/tests/arch/ice40/fsm.ys @@ -2,12 +2,15 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc flatten -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check + +equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module +select -assert-count 4 t:SB_DFF select -assert-count 2 t:SB_DFFESR -select -assert-count 2 t:SB_DFFSR -select -assert-count 1 t:SB_DFFSS -select -assert-count 13 t:SB_LUT4 -select -assert-none t:SB_DFFESR t:SB_DFFSR t:SB_DFFSS t:SB_LUT4 %% t:* %D +select -assert-count 15 t:SB_LUT4 +select -assert-none t:SB_DFFESR t:SB_DFF t:SB_LUT4 %% t:* %D diff --git a/tests/arch/xilinx/fsm.ys b/tests/arch/xilinx/fsm.ys index d2b481421..2a72c34e8 100644 --- a/tests/arch/xilinx/fsm.ys +++ b/tests/arch/xilinx/fsm.ys @@ -2,7 +2,11 @@ read_verilog ../common/fsm.v hierarchy -top fsm proc flatten -equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx # equivalency check + +equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx +miter -equiv -make_assert -flatten gold gate miter +sat -verify -prove-asserts -show-public -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd fsm # Constrain all select calls below inside the top module -- cgit v1.2.3 From ab8c521030a2c91a1e388d6f3c627a7f7dd525b2 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 11 Nov 2019 17:51:26 +0100 Subject: fix fsm test with proper clock enable polarity --- techlibs/gowin/cells_map.v | 8 ++++---- tests/arch/gowin/fsm.ys | 11 +++++++++++ 2 files changed, 15 insertions(+), 4 deletions(-) create mode 100644 tests/arch/gowin/fsm.ys diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index 93a49679c..881c2e9bb 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -23,11 +23,11 @@ module \$__DFFS_NP0_ (input D, C, R, output Q); DFFNR _TECHMAP_REPLACE_ (.D(D), // DFFRE D Flip-Flop with Clock Enable and Synchronous Reset module \$__DFFSE_PN0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule -module \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule +module \$__DFFSE_PP0 (input D, C, R, E, output Q); DFFRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule // DFFNRE D Flip-Flop with Negative-Edge Clock,Clock Enable, and Synchronous Reset module \$__DFFNSE_PN0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(!R), .CE(E)); endmodule -module \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(!E)); endmodule +module \$__DFFNSE_PP0 (input D, C, R, E, output Q); DFFNRE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .RESET(R), .CE(E)); endmodule // DFFS D Flip-Flop with Synchronous Set module \$__DFFS_PN1_ (input D, C, R, output Q); DFFS _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R)); endmodule @@ -39,11 +39,11 @@ module \$__DFFS_NP1_ (input D, C, R, output Q); DFFNS _TECHMAP_REPLACE_ (.D(D), // DFFSE D Flip-Flop with Clock Enable and Synchronous Set module \$__DFFSE_PN1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule -module \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule +module \$__DFFSE_PP1 (input D, C, R, E, output Q); DFFSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule // DFFNSE D Flip-Flop with Negative-Edge Clock,Clock Enable,and Synchronous Set module \$__DFFSE_NN1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(!R), .CE(E)); endmodule -module \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(!E)); endmodule +module \$__DFFSE_NP1 (input D, C, R, E, output Q); DFFNSE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .SET(R), .CE(E)); endmodule // DFFP D Flip-Flop with Asynchronous Preset module \$_DFF_PP1_ (input D, C, R, output Q); DFFP _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .PRESET(R)); endmodule diff --git a/tests/arch/gowin/fsm.ys b/tests/arch/gowin/fsm.ys new file mode 100644 index 000000000..ce4504522 --- /dev/null +++ b/tests/arch/gowin/fsm.ys @@ -0,0 +1,11 @@ +read_verilog ../common/fsm.v +hierarchy -top fsm +proc +flatten + +equiv_opt -run :prove -map +/gowin/cells_sim.v synth_gowin # equivalency check +miter -equiv -make_assert -flatten gold gate miter +sat -verify -show-all -dump_vcd x.vcd -prove-asserts -set-at 1 in_reset 1 -seq 20 -prove-skip 1 miter + +#design -load postopt +#shell -- cgit v1.2.3 From eef32195bd1afb4f029bf3039377e65f0beabac2 Mon Sep 17 00:00:00 2001 From: whitequark Date: Mon, 11 Nov 2019 23:13:00 +0000 Subject: flowmap: don't break if that creates a k+2 (and larger) LUT either. Fixes #1405. --- passes/techmap/flowmap.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 5807178dd..96eee45db 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -1050,7 +1050,7 @@ struct FlowmapWorker auto cut_inputs = cut_lut_at_gate(lut, lut_gate); pool gate_inputs = cut_inputs.first, other_inputs = cut_inputs.second; - if (gate_inputs.empty() && (int)other_inputs.size() == order) + if (gate_inputs.empty() && (int)other_inputs.size() >= order) { if (debug_relax) log(" Breaking would result in a (k+1)-LUT.\n"); -- cgit v1.2.3 From c68722818a09ce541c380178ff17e548db9c897d Mon Sep 17 00:00:00 2001 From: whitequark Date: Tue, 12 Nov 2019 00:15:43 +0000 Subject: =?UTF-8?q?flowmap:=20when=20doing=20mincut,=20ensure=20source=20i?= =?UTF-8?q?s=20always=20in=20X,=20not=20X=CC=85.?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixes #1475. --- passes/techmap/flowmap.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/techmap/flowmap.cc b/passes/techmap/flowmap.cc index 96eee45db..a2ad87f7d 100644 --- a/passes/techmap/flowmap.cc +++ b/passes/techmap/flowmap.cc @@ -394,7 +394,7 @@ struct FlowGraph pair, pool> edge_cut() { - pool x, xi; + pool x = {source}, xi; // X and X̅ in the paper NodePrime source_prime = {source, true}; pool visited; @@ -437,6 +437,7 @@ struct FlowGraph for (auto collapsed_node : collapsed[sink]) xi.insert(collapsed_node); + log_assert(x[source] && !xi[source]); log_assert(!x[sink] && xi[sink]); return {x, xi}; } -- cgit v1.2.3 From d88cc139a029764cf62d95b2eaaff99e270a134a Mon Sep 17 00:00:00 2001 From: Makai Mann Date: Mon, 11 Nov 2019 16:40:51 -0800 Subject: Add an info string symbol for bad states in btor backend --- backends/btor/btor.cc | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 9e316a055..2babd454c 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1070,7 +1070,16 @@ struct BtorWorker bad_properties.push_back(nid_en_and_not_a); } else { int nid = next_nid++; - btorf("%d bad %d\n", nid, nid_en_and_not_a); + + string infostr = + cell->attributes.count("\\src") + ? cell->attributes.at("\\src") + .decode_string() + .c_str() + : log_id(cell); + + std::replace(infostr.begin(), infostr.end(), ' ', '_'); + btorf("%d bad %d %s\n", nid, nid_en_and_not_a, infostr.c_str()); } btorf_pop(log_id(cell)); -- cgit v1.2.3 From 16df8f5a323e6ac2ccdb33fa115c59c9c7c3d856 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Nov 2019 14:26:02 +0100 Subject: Bugfix in fsm_detect Signed-off-by: Clifford Wolf --- passes/fsm/fsm_detect.cc | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 5ae991b28..61e6f8011 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -158,22 +158,24 @@ static void detect_fsm(RTLIL::Wire *wire) std::set cellport_list; sig2user.find(sig_q, cellport_list); + auto sig_q_bits = sig_q.to_sigbit_pool(); + for (auto &cellport : cellport_list) { RTLIL::Cell *cell = cellport.first; bool set_output = false, clr_output = false; - if (cell->type == "$ne") + if (cell->type.in("$ne", "$reduce_or", "$reduce_bool")) set_output = true; - if (cell->type == "$eq") + if (cell->type.in("$eq", "$logic_not", "$reduce_and")) clr_output = true; - if (!set_output && !clr_output) { - clr_output = true; + if (set_output || clr_output) { for (auto &port_it : cell->connections()) - if (port_it.first != "\\A" || port_it.first != "\\Y") - clr_output = false; + for (auto bit : assign_map(port_it.second)) + if (bit.wire != nullptr && !sig_q_bits.count(bit)) + goto next_cellport; } if (set_output || clr_output) { @@ -184,6 +186,7 @@ static void detect_fsm(RTLIL::Wire *wire) ce.set(sig, val); } } + next_cellport:; } SigSpec sig_y = sig_d, sig_undef; -- cgit v1.2.3 From 4be5a0fd7c1573f81c6c70a16601f7ce5ab87210 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Tue, 12 Nov 2019 17:31:30 +0100 Subject: Update fsm_detect bugfix Signed-off-by: Clifford Wolf --- passes/fsm/fsm_detect.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index 61e6f8011..fb3896669 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -173,9 +173,10 @@ static void detect_fsm(RTLIL::Wire *wire) if (set_output || clr_output) { for (auto &port_it : cell->connections()) - for (auto bit : assign_map(port_it.second)) - if (bit.wire != nullptr && !sig_q_bits.count(bit)) - goto next_cellport; + if (cell->input(port_it.first)) + for (auto bit : assign_map(port_it.second)) + if (bit.wire != nullptr && !sig_q_bits.count(bit)) + goto next_cellport; } if (set_output || clr_output) { -- cgit v1.2.3 From 07c854b7afc793a589df06c7fce200260378b379 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Wed, 13 Nov 2019 13:41:16 +0100 Subject: Add "autoname" pass and use it in "synth_ice40" Signed-off-by: Clifford Wolf --- passes/cmds/Makefile.inc | 1 + passes/cmds/autoname.cc | 134 ++++++++++++++++++++++++++++++++++++++++++ techlibs/ice40/synth_ice40.cc | 1 + 3 files changed, 136 insertions(+) create mode 100644 passes/cmds/autoname.cc diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index cf9663d1d..c7edc30fb 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -5,6 +5,7 @@ OBJS += passes/cmds/design.o OBJS += passes/cmds/select.o OBJS += passes/cmds/show.o OBJS += passes/cmds/rename.o +OBJS += passes/cmds/autoname.o OBJS += passes/cmds/connect.o OBJS += passes/cmds/scatter.o OBJS += passes/cmds/setundef.o diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc new file mode 100644 index 000000000..4614a8153 --- /dev/null +++ b/passes/cmds/autoname.cc @@ -0,0 +1,134 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +int autoname_worker(Module *module) +{ + dict> proposed_cell_names; + dict> proposed_wire_names; + dict wire_score; + int best_score = -1; + + for (auto cell : module->selected_cells()) + for (auto &conn : cell->connections()) + for (auto bit : conn.second) + if (bit.wire != nullptr) + wire_score[bit.wire]++; + + for (auto cell : module->selected_cells()) { + if (cell->name[0] == '$') { + for (auto &conn : cell->connections()) { + string suffix = stringf("_%s_%s", log_id(cell->type), log_id(conn.first)); + for (auto bit : conn.second) + if (bit.wire != nullptr && bit.wire->name[0] != '$') { + IdString new_name(bit.wire->name.str() + suffix); + int score = wire_score.at(bit.wire); + if (cell->output(conn.first)) score = 0; + score = 10000*score + new_name.size(); + if (!proposed_cell_names.count(cell) || score < proposed_cell_names.at(cell).first) { + if (best_score < 0 || score < best_score) + best_score = score; + proposed_cell_names[cell] = make_pair(score, new_name); + } + } + } + } else { + for (auto &conn : cell->connections()) { + string suffix = stringf("_%s", log_id(conn.first)); + for (auto bit : conn.second) + if (bit.wire != nullptr && bit.wire->name[0] == '$') { + IdString new_name(cell->name.str() + suffix); + int score = wire_score.at(bit.wire); + if (cell->output(conn.first)) score = 0; + score = 10000*score + new_name.size(); + if (!proposed_wire_names.count(bit.wire) || score < proposed_wire_names.at(bit.wire).first) { + if (best_score < 0 || score < best_score) + best_score = score; + proposed_wire_names[bit.wire] = make_pair(score, new_name); + } + } + } + } + } + + for (auto &it : proposed_cell_names) { + if (best_score*2 < it.second.first) + continue; + IdString n = module->uniquify(it.second.second); + log_debug("Rename cell %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); + module->rename(it.first, n); + } + + for (auto &it : proposed_wire_names) { + if (best_score*2 < it.second.first) + continue; + IdString n = module->uniquify(it.second.second); + log_debug("Rename wire %s in %s to %s.\n", log_id(it.first), log_id(module), log_id(n)); + module->rename(it.first, n); + } + + return proposed_cell_names.size() + proposed_wire_names.size(); +} + +struct AutonamePass : public Pass { + AutonamePass() : Pass("autoname", "automatically assign names to objects") { } + void help() YS_OVERRIDE + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" autoname [selection]\n"); + log("\n"); + log("Assign auto-generated public names to objects with private names (the ones\n"); + log("with $-prefix).\n"); + log("\n"); + } + void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE + { + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + // if (args[argidx] == "-foo") { + // foo = true; + // continue; + // } + break; + } + + log_header(design, "Executing AUTONAME pass.\n"); + + for (auto module : design->selected_modules()) + { + int count = 0, iter = 0; + while (1) { + iter++; + int n = autoname_worker(module); + if (!n) break; + count += n; + } + if (count > 0) + log("Renamed %d objects in module %s (%d iterations).\n", count, log_id(module), iter); + } + } +} AutonamePass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index c942126e1..901194b06 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -380,6 +380,7 @@ struct SynthIce40Pass : public ScriptPass if (check_label("check")) { + run("autoname"); run("hierarchy -check"); run("stat"); run("check -noinit"); -- cgit v1.2.3 From cd44826d5026316d9b44ae33c1fcf0d8faf550c4 Mon Sep 17 00:00:00 2001 From: Clifford Wolf Date: Thu, 14 Nov 2019 11:57:38 +0100 Subject: Use cell name for btor bad state props when it is a public name Signed-off-by: Clifford Wolf --- backends/btor/btor.cc | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index 2babd454c..c1da4b127 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -1070,15 +1070,11 @@ struct BtorWorker bad_properties.push_back(nid_en_and_not_a); } else { int nid = next_nid++; - - string infostr = - cell->attributes.count("\\src") - ? cell->attributes.at("\\src") - .decode_string() - .c_str() - : log_id(cell); - - std::replace(infostr.begin(), infostr.end(), ' ', '_'); + string infostr = log_id(cell); + if (infostr[0] == '$' && cell->attributes.count("\\src")) { + infostr = cell->attributes.at("\\src").decode_string().c_str(); + std::replace(infostr.begin(), infostr.end(), ' ', '_'); + } btorf("%d bad %d %s\n", nid, nid_en_and_not_a, infostr.c_str()); } -- cgit v1.2.3 From f5804a84fd6d9b7d4d50529fcb5c46e3dde89086 Mon Sep 17 00:00:00 2001 From: David Shah Date: Thu, 14 Nov 2019 18:43:15 +0000 Subject: wreduce: Don't trim zeros or sext when not matching ARST_VALUE Signed-off-by: David Shah --- passes/opt/wreduce.cc | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc index c02c355cb..04b882db9 100644 --- a/passes/opt/wreduce.cc +++ b/passes/opt/wreduce.cc @@ -143,13 +143,18 @@ struct WreduceWorker SigSpec sig_d = mi.sigmap(cell->getPort(ID(D))); SigSpec sig_q = mi.sigmap(cell->getPort(ID(Q))); - Const initval; + bool is_adff = (cell->type == ID($adff)); + Const initval, arst_value; int width_before = GetSize(sig_q); if (width_before == 0) return; + if (cell->parameters.count(ID(ARST_VALUE))) { + arst_value = cell->parameters[ID(ARST_VALUE)]; + } + bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0; bool sign_ext = !zero_ext; @@ -163,7 +168,8 @@ struct WreduceWorker for (int i = GetSize(sig_q)-1; i >= 0; i--) { - if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx)) { + if (zero_ext && sig_d[i] == State::S0 && (initval[i] == State::S0 || initval[i] == State::Sx) && + (!is_adff || i >= GetSize(arst_value) || arst_value[i] == State::S0 || arst_value[i] == State::Sx)) { module->connect(sig_q[i], State::S0); remove_init_bits.insert(sig_q[i]); sig_d.remove(i); @@ -171,7 +177,8 @@ struct WreduceWorker continue; } - if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1]) { + if (sign_ext && i > 0 && sig_d[i] == sig_d[i-1] && initval[i] == initval[i-1] && + (!is_adff || i >= GetSize(arst_value) || arst_value[i] == arst_value[i-1])) { module->connect(sig_q[i], sig_q[i-1]); remove_init_bits.insert(sig_q[i]); sig_d.remove(i); @@ -214,7 +221,6 @@ struct WreduceWorker // Narrow ARST_VALUE parameter to new size. if (cell->parameters.count(ID(ARST_VALUE))) { - Const arst_value = cell->getParam(ID(ARST_VALUE)); arst_value.bits.resize(GetSize(sig_q)); cell->setParam(ID(ARST_VALUE), arst_value); } -- cgit v1.2.3 From 51e4e29bb1f7c030b0cac351c522dc41f7587be2 Mon Sep 17 00:00:00 2001 From: David Shah Date: Fri, 15 Nov 2019 21:03:11 +0000 Subject: ecp5: Use new autoname pass for better cell/net names Signed-off-by: David Shah --- techlibs/ecp5/synth_ecp5.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/techlibs/ecp5/synth_ecp5.cc b/techlibs/ecp5/synth_ecp5.cc index 800a8ce22..4cbb56ea1 100644 --- a/techlibs/ecp5/synth_ecp5.cc +++ b/techlibs/ecp5/synth_ecp5.cc @@ -339,6 +339,7 @@ struct SynthEcp5Pass : public ScriptPass if (check_label("check")) { + run("autoname"); run("hierarchy -check"); run("stat"); run("check -noinit"); -- cgit v1.2.3 From 3c643c57dfee9956697e8629a746bc04439be5a2 Mon Sep 17 00:00:00 2001 From: whitequark Date: Fri, 15 Nov 2019 03:11:46 +0000 Subject: write_verilog: add -extmem option, to write split memory init files. Some toolchains (in particular Quartus) are pathologically slow if a large amount of assignments in `initial` blocks are used. --- backends/verilog/verilog_backend.cc | 90 ++++++++++++++++++++++++++++++++----- 1 file changed, 80 insertions(+), 10 deletions(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 24e397bda..54d0f6148 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -33,11 +33,11 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, defparam, decimal, siminit; -int auto_name_counter, auto_name_offset, auto_name_digits; +bool verbose, norename, noattr, attr2comment, noexpr, nodec, nohex, nostr, extmem, defparam, decimal, siminit; +int auto_name_counter, auto_name_offset, auto_name_digits, extmem_counter; std::map auto_name_map; std::set reg_wires, reg_ct; -std::string auto_prefix; +std::string auto_prefix, extmem_prefix; RTLIL::Module *active_module; dict active_initdata; @@ -1069,14 +1069,64 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "reg [%d:%d] %s [%d:%d];\n", indent.c_str(), width-1, 0, mem_id.c_str(), size+offset-1, offset); if (use_init) { - f << stringf("%s" "initial begin\n", indent.c_str()); - for (int i=0; iparameters["\\INIT"].extract(i*width, width); + for (int j=0; j expressions within that clock domain @@ -1777,8 +1827,16 @@ struct VerilogBackend : public Backend { log(" deactivates this feature and instead will write string constants\n"); log(" as binary numbers.\n"); log("\n"); + log(" -extmem\n"); + log(" instead of initializing memories using assignments to individual\n"); + log(" elements, use the '$readmemh' function to read initialization data\n"); + log(" from a file. This data is written to a file named by appending\n"); + log(" a sequential index to the Verilog filename and replacing the extension\n"); + log(" with '.mem', e.g. 'write_verilog -extmem foo.v' writes 'foo-1.mem',\n"); + log(" 'foo-2.mem' and so on.\n"); + log("\n"); log(" -defparam\n"); - log(" Use 'defparam' statements instead of the Verilog-2001 syntax for\n"); + log(" use 'defparam' statements instead of the Verilog-2001 syntax for\n"); log(" cell parameters.\n"); log("\n"); log(" -blackboxes\n"); @@ -1812,6 +1870,7 @@ struct VerilogBackend : public Backend { nodec = false; nohex = false; nostr = false; + extmem = false; defparam = false; decimal = false; siminit = false; @@ -1885,6 +1944,11 @@ struct VerilogBackend : public Backend { nostr = true; continue; } + if (arg == "-extmem") { + extmem = true; + extmem_counter = 1; + continue; + } if (arg == "-defparam") { defparam = true; continue; @@ -1912,6 +1976,12 @@ struct VerilogBackend : public Backend { break; } extra_args(f, filename, args, argidx); + if (extmem) + { + if (filename.empty()) + log_cmd_error("Option -extmem must be used with a filename.\n"); + extmem_prefix = filename.substr(0, filename.rfind('.')); + } design->sort(); -- cgit v1.2.3 From 38e72d6e13b908007577b7782078ac8b968496f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Mon, 18 Nov 2019 04:16:48 +0100 Subject: Fix #1496. --- passes/techmap/extract_fa.cc | 12 ++++++++---- tests/various/bug1496.ys | 13 +++++++++++++ 2 files changed, 21 insertions(+), 4 deletions(-) create mode 100644 tests/various/bug1496.ys diff --git a/passes/techmap/extract_fa.cc b/passes/techmap/extract_fa.cc index 29700c37b..9f3bb525b 100644 --- a/passes/techmap/extract_fa.cc +++ b/passes/techmap/extract_fa.cc @@ -262,10 +262,14 @@ struct ExtractFaWorker pool new_leaves = leaves; new_leaves.erase(bit); - if (cell->hasPort(ID::A)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::A)))); - if (cell->hasPort(ID::B)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::B)))); - if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C))))); - if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D))))); + for (auto port : {ID::A, ID::B, ID(C), ID(D)}) { + if (!cell->hasPort(port)) + continue; + auto bit = sigmap(SigBit(cell->getPort(port))); + if (!bit.wire) + continue; + new_leaves.insert(bit); + } if (GetSize(new_leaves) > maxbreadth) continue; diff --git a/tests/various/bug1496.ys b/tests/various/bug1496.ys new file mode 100644 index 000000000..d050161dc --- /dev/null +++ b/tests/various/bug1496.ys @@ -0,0 +1,13 @@ +read_ilang << EOF +module \top + wire input 1 \A + wire output 2 \Y + cell $_AND_ \sub + connect \A \A + connect \B 1'0 + connect \Y \Y + end +end +EOF + +extract_fa -- cgit v1.2.3 From dd8c7e1ddda152e9c06d4b950564eb4aa1051c98 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Mon, 18 Nov 2019 14:25:46 +0100 Subject: add help for nowidelut and abc9 options --- techlibs/gowin/synth_gowin.cc | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index a70ff93bb..bb6d44e00 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -64,6 +64,12 @@ struct SynthGowinPass : public ScriptPass log(" -retime\n"); log(" run 'abc' with -dff option\n"); log("\n"); + log(" -nowidelut\n"); + log(" do not use muxes to implement LUTs larger than LUT4s\n"); + log("\n"); + log(" -abc9\n"); + log(" use new ABC9 flow (EXPERIMENTAL)\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -173,7 +179,7 @@ struct SynthGowinPass : public ScriptPass { run("synth -run coarse"); } - + if (!nobram && check_label("bram", "(skip if -nobram)")) { run("memory_bram -rules +/gowin/bram.txt"); -- cgit v1.2.3 From 7a9081440c33af05cd5b24b4eb8907ac2ba4876a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Mon, 18 Nov 2019 03:47:56 +0100 Subject: xilinx: Add simulation models for MULT18X18* and DSP48A*. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This adds simulation models for the following primitives: - MULT18X18 and MULT18X18S (Virtex 2*, Spartan 3) - MULT18X18SIO (Spartan 3E, Spartan 3A) - DSP48A (Spartan 3A DSP) — implemented in terms of DSP48A1 - DSP48A1 (Spartan 6) --- techlibs/xilinx/cells_sim.v | 511 ++++++++++++++++++++++++++++++++++++++++++ techlibs/xilinx/cells_xtra.py | 10 +- techlibs/xilinx/cells_xtra.v | 127 ----------- 3 files changed, 516 insertions(+), 132 deletions(-) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 03985b1be..5faddcd52 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -581,6 +581,515 @@ module SRLC32E ( endgenerate endmodule +// DSP + +// Virtex 2, Virtex 2 Pro, Spartan 3. + +// Asynchronous mode. + +module MULT18X18 ( + input signed [17:0] A, + input signed [17:0] B, + output signed [35:0] P +); + +assign P = A * B; + +endmodule + +// Synchronous mode. + +module MULT18X18S ( + input signed [17:0] A, + input signed [17:0] B, + output reg signed [35:0] P, + (* clkbuf_sink *) + input C, + input CE, + input R +); + +always @(posedge C) + if (R) + P <= 0; + else if (CE) + P <= A * B; + +endmodule + +// Spartan 3E, Spartan 3A. + +module MULT18X18SIO ( + input signed [17:0] A, + input signed [17:0] B, + output signed [35:0] P, + (* clkbuf_sink *) + input CLK, + input CEA, + input CEB, + input CEP, + input RSTA, + input RSTB, + input RSTP, + input signed [17:0] BCIN, + output signed [17:0] BCOUT +); + +parameter integer AREG = 1; +parameter integer BREG = 1; +parameter B_INPUT = "DIRECT"; +parameter integer PREG = 1; + +// The multiplier. +wire signed [35:0] P_MULT; +assign P_MULT = A_MULT * B_MULT; + +// The cascade output. +assign BCOUT = B_MULT; + +// The B input multiplexer. +wire signed [17:0] B_MUX; +assign B_MUX = (B_INPUT == "DIRECT") ? B : BCIN; + +// The registers. +reg signed [17:0] A_REG; +reg signed [17:0] B_REG; +reg signed [35:0] P_REG; + +initial begin + A_REG = 0; + B_REG = 0; + P_REG = 0; +end + +always @(posedge CLK) begin + if (RSTA) + A_REG <= 0; + else if (CEA) + A_REG <= A; + + if (RSTB) + B_REG <= 0; + else if (CEB) + B_REG <= B_MUX; + + if (RSTP) + P_REG <= 0; + else if (CEP) + P_REG <= P_MULT; +end + +// The register enables. +wire signed [17:0] A_MULT; +wire signed [17:0] B_MULT; +assign A_MULT = (AREG == 1) ? A_REG : A; +assign B_MULT = (BREG == 1) ? B_REG : B_MUX; +assign P = (PREG == 1) ? P_REG : P_MULT; + +endmodule + +// Spartan 3A DSP. + +module DSP48A ( + input signed [17:0] A, + input signed [17:0] B, + input signed [47:0] C, + input signed [17:0] D, + input signed [47:0] PCIN, + input CARRYIN, + input [7:0] OPMODE, + output signed [47:0] P, + output signed [17:0] BCOUT, + output signed [47:0] PCOUT, + output CARRYOUT, + (* clkbuf_sink *) + input CLK, + input CEA, + input CEB, + input CEC, + input CED, + input CEM, + input CECARRYIN, + input CEOPMODE, + input CEP, + input RSTA, + input RSTB, + input RSTC, + input RSTD, + input RSTM, + input RSTCARRYIN, + input RSTOPMODE, + input RSTP +); + +parameter integer A0REG = 0; +parameter integer A1REG = 1; +parameter integer B0REG = 0; +parameter integer B1REG = 1; +parameter integer CREG = 1; +parameter integer DREG = 1; +parameter integer MREG = 1; +parameter integer CARRYINREG = 1; +parameter integer OPMODEREG = 1; +parameter integer PREG = 1; +parameter CARRYINSEL = "CARRYIN"; +parameter RSTTYPE = "SYNC"; + +// This is a strict subset of Spartan 6 -- reuse its model. + +DSP48A1 #( + .A0REG(A0REG), + .A1REG(A1REG), + .B0REG(B0REG), + .B1REG(B1REG), + .CREG(CREG), + .DREG(DREG), + .MREG(MREG), + .CARRYINREG(CARRYINREG), + .CARRYOUTREG(0), + .OPMODEREG(OPMODEREG), + .PREG(PREG), + .CARRYINSEL(CARRYINSEL), + .RSTTYPE(RSTTYPE) +) upgrade ( + .A(A), + .B(B), + .C(C), + .D(D), + .PCIN(PCIN), + .CARRYIN(CARRYIN), + .OPMODE(OPMODE), + // M unconnected + .P(P), + .BCOUT(BCOUT), + .PCOUT(PCOUT), + .CARRYOUT(CARRYOUT), + // CARRYOUTF unconnected + .CLK(CLK), + .CEA(CEA), + .CEB(CEB), + .CEC(CEC), + .CED(CED), + .CEM(CEM), + .CECARRYIN(CECARRYIN), + .CEOPMODE(CEOPMODE), + .CEP(CEP), + .RSTA(RSTA), + .RSTB(RSTB), + .RSTC(RSTC), + .RSTD(RSTD), + .RSTM(RSTM), + .RSTCARRYIN(RSTCARRYIN), + .RSTOPMODE(RSTOPMODE), + .RSTP(RSTP) +); + +endmodule + +// Spartan 6. + +module DSP48A1 ( + input signed [17:0] A, + input signed [17:0] B, + input signed [47:0] C, + input signed [17:0] D, + input signed [47:0] PCIN, + input CARRYIN, + input [7:0] OPMODE, + output signed [35:0] M, + output signed [47:0] P, + output signed [17:0] BCOUT, + output signed [47:0] PCOUT, + output CARRYOUT, + output CARRYOUTF, + (* clkbuf_sink *) + input CLK, + input CEA, + input CEB, + input CEC, + input CED, + input CEM, + input CECARRYIN, + input CEOPMODE, + input CEP, + input RSTA, + input RSTB, + input RSTC, + input RSTD, + input RSTM, + input RSTCARRYIN, + input RSTOPMODE, + input RSTP +); + +parameter integer A0REG = 0; +parameter integer A1REG = 1; +parameter integer B0REG = 0; +parameter integer B1REG = 1; +parameter integer CREG = 1; +parameter integer DREG = 1; +parameter integer MREG = 1; +parameter integer CARRYINREG = 1; +parameter integer CARRYOUTREG = 1; +parameter integer OPMODEREG = 1; +parameter integer PREG = 1; +parameter CARRYINSEL = "OPMODE5"; +parameter RSTTYPE = "SYNC"; + +wire signed [35:0] M_MULT; +wire signed [47:0] P_IN; +wire signed [17:0] A0_OUT; +wire signed [17:0] B0_OUT; +wire signed [17:0] A1_OUT; +wire signed [17:0] B1_OUT; +wire signed [17:0] B1_IN; +wire signed [47:0] C_OUT; +wire signed [17:0] D_OUT; +wire signed [7:0] OPMODE_OUT; +wire CARRYIN_OUT; +wire CARRYOUT_IN; +wire CARRYIN_IN; +reg signed [47:0] XMUX; +reg signed [47:0] ZMUX; + +// The registers. +reg signed [17:0] A0_REG; +reg signed [17:0] A1_REG; +reg signed [17:0] B0_REG; +reg signed [17:0] B1_REG; +reg signed [47:0] C_REG; +reg signed [17:0] D_REG; +reg signed [35:0] M_REG; +reg signed [47:0] P_REG; +reg [7:0] OPMODE_REG; +reg CARRYIN_REG; +reg CARRYOUT_REG; + +initial begin + A0_REG = 0; + A1_REG = 0; + B0_REG = 0; + B1_REG = 0; + C_REG = 0; + D_REG = 0; + M_REG = 0; + P_REG = 0; + OPMODE_REG = 0; + CARRYIN_REG = 0; + CARRYOUT_REG = 0; +end + +generate + +if (RSTTYPE == "SYNC") begin + always @(posedge CLK) begin + if (RSTA) begin + A0_REG <= 0; + A1_REG <= 0; + end else if (CEA) begin + A0_REG <= A; + A1_REG <= A0_OUT; + end + end + + always @(posedge CLK) begin + if (RSTB) begin + B0_REG <= 0; + B1_REG <= 0; + end else if (CEB) begin + B0_REG <= B; + B1_REG <= B1_IN; + end + end + + always @(posedge CLK) begin + if (RSTC) begin + C_REG <= 0; + end else if (CEC) begin + C_REG <= C; + end + end + + always @(posedge CLK) begin + if (RSTD) begin + D_REG <= 0; + end else if (CED) begin + D_REG <= D; + end + end + + always @(posedge CLK) begin + if (RSTM) begin + M_REG <= 0; + end else if (CEM) begin + M_REG <= M_MULT; + end + end + + always @(posedge CLK) begin + if (RSTP) begin + P_REG <= 0; + end else if (CEP) begin + P_REG <= P_IN; + end + end + + always @(posedge CLK) begin + if (RSTOPMODE) begin + OPMODE_REG <= 0; + end else if (CEOPMODE) begin + OPMODE_REG <= OPMODE; + end + end + + always @(posedge CLK) begin + if (RSTCARRYIN) begin + CARRYIN_REG <= 0; + CARRYOUT_REG <= 0; + end else if (CECARRYIN) begin + CARRYIN_REG <= CARRYIN_IN; + CARRYOUT_REG <= CARRYOUT_IN; + end + end +end else begin + always @(posedge CLK, posedge RSTA) begin + if (RSTA) begin + A0_REG <= 0; + A1_REG <= 0; + end else if (CEA) begin + A0_REG <= A; + A1_REG <= A0_OUT; + end + end + + always @(posedge CLK, posedge RSTB) begin + if (RSTB) begin + B0_REG <= 0; + B1_REG <= 0; + end else if (CEB) begin + B0_REG <= B; + B1_REG <= B1_IN; + end + end + + always @(posedge CLK, posedge RSTC) begin + if (RSTC) begin + C_REG <= 0; + end else if (CEC) begin + C_REG <= C; + end + end + + always @(posedge CLK, posedge RSTD) begin + if (RSTD) begin + D_REG <= 0; + end else if (CED) begin + D_REG <= D; + end + end + + always @(posedge CLK, posedge RSTM) begin + if (RSTM) begin + M_REG <= 0; + end else if (CEM) begin + M_REG <= M_MULT; + end + end + + always @(posedge CLK, posedge RSTP) begin + if (RSTP) begin + P_REG <= 0; + end else if (CEP) begin + P_REG <= P_IN; + end + end + + always @(posedge CLK, posedge RSTOPMODE) begin + if (RSTOPMODE) begin + OPMODE_REG <= 0; + end else if (CEOPMODE) begin + OPMODE_REG <= OPMODE; + end + end + + always @(posedge CLK, posedge RSTCARRYIN) begin + if (RSTCARRYIN) begin + CARRYIN_REG <= 0; + CARRYOUT_REG <= 0; + end else if (CECARRYIN) begin + CARRYIN_REG <= CARRYIN_IN; + CARRYOUT_REG <= CARRYOUT_IN; + end + end +end + +endgenerate + +// The register enables. +assign A0_OUT = (A0REG == 1) ? A0_REG : A; +assign A1_OUT = (A1REG == 1) ? A1_REG : A0_OUT; +assign B0_OUT = (B0REG == 1) ? B0_REG : B; +assign B1_OUT = (B1REG == 1) ? B1_REG : B1_IN; +assign C_OUT = (CREG == 1) ? C_REG : C; +assign D_OUT = (DREG == 1) ? D_REG : D; +assign M = (MREG == 1) ? M_REG : M_MULT; +assign P = (PREG == 1) ? P_REG : P_IN; +assign OPMODE_OUT = (OPMODEREG == 1) ? OPMODE_REG : OPMODE; +assign CARRYIN_OUT = (CARRYINREG == 1) ? CARRYIN_REG : CARRYIN_IN; +assign CARRYOUT = (CARRYOUTREG == 1) ? CARRYOUT_REG : CARRYOUT_IN; +assign CARRYOUTF = CARRYOUT; + +// The pre-adder. +wire signed [17:0] PREADDER; +assign B1_IN = OPMODE_OUT[4] ? PREADDER : B0_OUT; +assign PREADDER = OPMODE_OUT[6] ? D_OUT - B0_OUT : D_OUT + B0_OUT; + +// The multiplier. +assign M_MULT = A1_OUT * B1_OUT; + +// The carry in selection. +assign CARRYIN_IN = (CARRYINSEL == "OPMODE5") ? OPMODE_OUT[5] : CARRYIN; + +// The post-adder inputs. +always @* begin + case (OPMODE_OUT[1:0]) + 2'b00: XMUX <= 0; + 2'b01: XMUX <= M; + 2'b10: XMUX <= P; + 2'b11: XMUX <= {D_OUT[11:0], B1_OUT, A1_OUT}; + default: XMUX <= 48'hxxxxxxxxxxxx; + endcase +end + +always @* begin + case (OPMODE_OUT[3:2]) + 2'b00: ZMUX <= 0; + 2'b01: ZMUX <= PCIN; + 2'b10: ZMUX <= P; + 2'b11: ZMUX <= C_OUT; + default: ZMUX <= 48'hxxxxxxxxxxxx; + endcase +end + +// The post-adder. +wire signed [48:0] X_EXT; +wire signed [48:0] Z_EXT; +assign X_EXT = XMUX; +assign Z_EXT = ZMUX; +assign {CARRYOUT_IN, P_IN} = OPMODE_OUT[7] ? (Z_EXT - (X_EXT + CARRYIN_OUT)) : (Z_EXT + X_EXT + CARRYIN_OUT); + +// Cascade outputs. +assign BCOUT = B1_OUT; +assign PCOUT = P; + +endmodule + +// TODO: DSP48 (Virtex 4). + +// TODO: DSP48E (Virtex 5). + +// Virtex 6, Series 7. + module DSP48E1 ( output [29:0] ACOUT, output [17:0] BCOUT, @@ -1043,3 +1552,5 @@ module DSP48E1 ( endgenerate endmodule + +// TODO: DSP48E2 (Ultrascale). diff --git a/techlibs/xilinx/cells_xtra.py b/techlibs/xilinx/cells_xtra.py index ef7ce856a..f401ebe78 100644 --- a/techlibs/xilinx/cells_xtra.py +++ b/techlibs/xilinx/cells_xtra.py @@ -204,11 +204,11 @@ CELLS = [ Cell('URAM288_BASE', port_attrs={'CLK': ['clkbuf_sink']}), # Multipliers and DSP. - Cell('MULT18X18'), # Spartan 3 - Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 - Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E - Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP - Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 + # Cell('MULT18X18'), # Virtex 2, Spartan 3 + # Cell('MULT18X18S', port_attrs={'C': ['clkbuf_sink']}), # Spartan 3 + # Cell('MULT18X18SIO', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3E + # Cell('DSP48A', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 3A DSP + # Cell('DSP48A1', port_attrs={'CLK': ['clkbuf_sink']}), # Spartan 6 Cell('DSP48', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 4 Cell('DSP48E', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 5 #Cell('DSP48E1', port_attrs={'CLK': ['clkbuf_sink']}), # Virtex 6 / Series 7 diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v index 72a3b6cbb..ce0949f2c 100644 --- a/techlibs/xilinx/cells_xtra.v +++ b/techlibs/xilinx/cells_xtra.v @@ -6218,133 +6218,6 @@ module URAM288_BASE (...); input SLEEP; endmodule -module MULT18X18 (...); - output [35:0] P; - input [17:0] A; - input [17:0] B; -endmodule - -module MULT18X18S (...); - output [35:0] P; - input [17:0] A; - input [17:0] B; - (* clkbuf_sink *) - input C; - input CE; - input R; -endmodule - -module MULT18X18SIO (...); - parameter integer AREG = 1; - parameter integer BREG = 1; - parameter B_INPUT = "DIRECT"; - parameter integer PREG = 1; - output [17:0] BCOUT; - output [35:0] P; - input [17:0] A; - input [17:0] B; - input [17:0] BCIN; - input CEA; - input CEB; - input CEP; - (* clkbuf_sink *) - input CLK; - input RSTA; - input RSTB; - input RSTP; -endmodule - -module DSP48A (...); - parameter integer A0REG = 0; - parameter integer A1REG = 1; - parameter integer B0REG = 0; - parameter integer B1REG = 1; - parameter integer CARRYINREG = 1; - parameter CARRYINSEL = "CARRYIN"; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter RSTTYPE = "SYNC"; - output [17:0] BCOUT; - output CARRYOUT; - output [47:0] P; - output [47:0] PCOUT; - input [17:0] A; - input [17:0] B; - input [47:0] C; - input CARRYIN; - input CEA; - input CEB; - input CEC; - input CECARRYIN; - input CED; - input CEM; - input CEOPMODE; - input CEP; - (* clkbuf_sink *) - input CLK; - input [17:0] D; - input [7:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTB; - input RSTC; - input RSTCARRYIN; - input RSTD; - input RSTM; - input RSTOPMODE; - input RSTP; -endmodule - -module DSP48A1 (...); - parameter integer A0REG = 0; - parameter integer A1REG = 1; - parameter integer B0REG = 0; - parameter integer B1REG = 1; - parameter integer CARRYINREG = 1; - parameter integer CARRYOUTREG = 1; - parameter CARRYINSEL = "OPMODE5"; - parameter integer CREG = 1; - parameter integer DREG = 1; - parameter integer MREG = 1; - parameter integer OPMODEREG = 1; - parameter integer PREG = 1; - parameter RSTTYPE = "SYNC"; - output [17:0] BCOUT; - output CARRYOUT; - output CARRYOUTF; - output [35:0] M; - output [47:0] P; - output [47:0] PCOUT; - input [17:0] A; - input [17:0] B; - input [47:0] C; - input CARRYIN; - input CEA; - input CEB; - input CEC; - input CECARRYIN; - input CED; - input CEM; - input CEOPMODE; - input CEP; - (* clkbuf_sink *) - input CLK; - input [17:0] D; - input [7:0] OPMODE; - input [47:0] PCIN; - input RSTA; - input RSTB; - input RSTC; - input RSTCARRYIN; - input RSTD; - input RSTM; - input RSTOPMODE; - input RSTP; -endmodule - module DSP48 (...); parameter integer AREG = 1; parameter integer BREG = 1; -- cgit v1.2.3 From 15232a48af60fb7da3c3afdd144882ace2194197 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marcin=20Ko=C5=9Bcielnicki?= Date: Mon, 18 Nov 2019 08:19:53 +0100 Subject: Fix #1462, #1480. --- passes/pmgen/xilinx_dsp.pmg | 12 +++++++----- passes/pmgen/xilinx_dsp_CREG.pmg | 8 ++++---- tests/various/bug1462.ys | 11 +++++++++++ tests/various/bug1480.ys | 18 ++++++++++++++++++ 4 files changed, 40 insertions(+), 9 deletions(-) create mode 100644 tests/various/bug1462.ys create mode 100644 tests/various/bug1480.ys diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index 604aa222b..0ba529011 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -98,16 +98,16 @@ code sigA sigB sigC sigD sigM clock if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { // Only care about those bits that are used int i; - for (i = 0; i < GetSize(P); i++) { - if (nusers(P[i]) <= 1) + for (i = GetSize(P)-1; i >= 0; i--) + if (nusers(P[i]) > 1) break; - sigM.append(P[i]); - } + i++; log_assert(nusers(P.extract_end(i)) <= 1); // This sigM could have no users if downstream sinks (e.g. $add) is // narrower than $mul result, for example - if (sigM.empty()) + if (i == 0) reject; + sigM = P.extract(0, i); } else sigM = P; @@ -460,6 +460,8 @@ arg argD argQ clock code dff = nullptr; + if (GetSize(argQ) == 0) + reject; for (const auto &c : argQ.chunks()) { // Abandon matches when 'Q' is a constant if (!c.wire) diff --git a/passes/pmgen/xilinx_dsp_CREG.pmg b/passes/pmgen/xilinx_dsp_CREG.pmg index a57043009..5cd34162e 100644 --- a/passes/pmgen/xilinx_dsp_CREG.pmg +++ b/passes/pmgen/xilinx_dsp_CREG.pmg @@ -63,12 +63,12 @@ code sigC sigP clock if (param(dsp, \USE_MULT, Const("MULTIPLY")).decode_string() == "MULTIPLY") { // Only care about those bits that are used int i; - for (i = 0; i < GetSize(P); i++) { - if (nusers(P[i]) <= 1) + for (i = GetSize(P)-1; i >= 0; i--) + if (nusers(P[i]) > 1) break; - sigP.append(P[i]); - } + i++; log_assert(nusers(P.extract_end(i)) <= 1); + sigP = P.extract(0, i); } else sigP = P; diff --git a/tests/various/bug1462.ys b/tests/various/bug1462.ys new file mode 100644 index 000000000..15cab5121 --- /dev/null +++ b/tests/various/bug1462.ys @@ -0,0 +1,11 @@ +read_verilog << EOF +module top(...); +input wire [31:0] A; +output wire [31:0] P; + +assign P = A * 32'h12300000; + +endmodule +EOF + +synth_xilinx diff --git a/tests/various/bug1480.ys b/tests/various/bug1480.ys new file mode 100644 index 000000000..84faea08a --- /dev/null +++ b/tests/various/bug1480.ys @@ -0,0 +1,18 @@ +read_verilog << EOF +module top(...); + +input signed [17:0] A; +input signed [17:0] B; +output X; +output Y; + +wire [35:0] P; +assign P = A * B; + +assign X = P[0]; +assign Y = P[35]; + +endmodule +EOF + +synth_xilinx -- cgit v1.2.3 From 8ab412eb16b1d4f98117247bf85e0c37627ee459 Mon Sep 17 00:00:00 2001 From: Pepijn de Vos Date: Tue, 19 Nov 2019 15:53:44 +0100 Subject: Remove dff init altogether The hardware does not actually support it. In reality it is always initialised to its reset value. --- techlibs/gowin/cells_map.v | 5 +++-- techlibs/gowin/synth_gowin.cc | 1 - 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/techlibs/gowin/cells_map.v b/techlibs/gowin/cells_map.v index 881c2e9bb..9845e56a7 100644 --- a/techlibs/gowin/cells_map.v +++ b/techlibs/gowin/cells_map.v @@ -1,9 +1,10 @@ -//TODO all DFF* have INIT +//All DFF* have INIT, but the hardware is always initialised to the reset +//value regardless. The parameter is ignored. // DFFN D Flip-Flop with Negative-Edge Clock module \$_DFF_N_ (input D, C, output Q); DFFN _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule // DFF D Flip-Flop -module \$_DFF_P_ #(parameter INIT = 1'b0) (input D, C, output Q); DFF #(.INIT(INIT)) _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule +module \$_DFF_P_ (input D, C, output Q); DFF _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C)); endmodule // DFFE D Flip-Flop with Clock Enable module \$_DFFE_PP_ (input D, C, E, output Q); DFFE _TECHMAP_REPLACE_ (.D(D), .Q(Q), .CLK(C), .CE(E)); endmodule diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc index bb6d44e00..3c1426414 100644 --- a/techlibs/gowin/synth_gowin.cc +++ b/techlibs/gowin/synth_gowin.cc @@ -238,7 +238,6 @@ struct SynthGowinPass : public ScriptPass run("hilomap -singleton -hicell VCC V -locell GND G"); run("iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O " "-toutpad TBUF OEN:I:O -tinoutpad IOBUF OEN:O:I:IO", "(unless -noiopads)"); - run("dffinit -ff DFF Q INIT"); run("clean"); } -- cgit v1.2.3