| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 1 | -1/+1 | |
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| | * | Liberty file parser now accepts superfluous ; | Niels Moseley | 2019-03-27 | 3 | -2/+97 | |
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| | * | Fix "verific -extnets" for more complex situations | Clifford Wolf | 2019-03-26 | 1 | -0/+22 | |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | Updated the liberty parser to accept [A:B] ranges (AST has not been ↵ | Niels Moseley | 2019-03-24 | 6 | -0/+541 | |
| | | | | | | | | | updated). Liberty parser now also accepts key : value pair lines that do not end in ';'. | |||||
| | * | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-03-19 | 11 | -31/+175 | |
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| | | * | fix local name resolution in prefix constructs | Zachary Snow | 2019-03-18 | 1 | -0/+56 | |
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| | | * | Fix handling of task output ports in clocked always blocks, fixes #857 | Clifford Wolf | 2019-03-07 | 1 | -0/+19 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails | Jim Lawson | 2019-03-04 | 1 | -0/+1 | |
| | | | | | | | | | | | | | Mark dff_init.v as expected to fail since it uses "initial value". | |||||
| | | * | Hotfix for "make test" | Clifford Wolf | 2019-02-28 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 1 | -1/+1 | |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 3 | -3/+1 | |
| | | | | | | | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) | |||||
| | * | | One more merge conflict | Eddie Hung | 2019-02-17 | 1 | -6/+1 | |
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| | * | | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-02-17 | 5 | -8/+97 | |
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| * | \ \ | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-26 | 5 | -1/+94 | |
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| | * | | | Merge pull request #812 from ucb-bar/arrayhierarchyfixes | Clifford Wolf | 2019-02-24 | 2 | -1/+68 | |
| | |\ \ \ | | | | | | | | | | | Define basic_cell_type() function and use it to derive the cell type … | |||||
| | | * | | | Address requested changes - don't require non-$ name. | Jim Lawson | 2019-02-22 | 2 | -4/+7 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Suppress warning if name does begin with a `$`. Fix hierachy tests so they have something to grep. Announce hierarchy test types. | |||||
| | | * | | | Fix normal (non-array) hierarchy -auto-top. | Jim Lawson | 2019-02-19 | 2 | -1/+65 | |
| | | | | | | | | | | | | | | | | | | | | | Add simple test. | |||||
| | * | | | | Merge pull request #824 from litghost/fix_reduce_on_ff | Clifford Wolf | 2019-02-24 | 2 | -0/+24 | |
| | |\ \ \ \ | | | | | | | | | | | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | |||||
| | | * | | | | Fix WREDUCE on FF not fixing ARST_VALUE parameter. | Keith Rothman | 2019-02-22 | 2 | -0/+24 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adds test case that fails without code change. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| | * | | | | | Fix handling of defparam for when default_nettype is none | Clifford Wolf | 2019-02-24 | 1 | -0/+2 | |
| | |/ / / / | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| * | | | | | Uncomment out more tests | Eddie Hung | 2019-02-26 | 1 | -25/+39 | |
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| * | | | | | Enable two inout tests | Eddie Hung | 2019-02-26 | 1 | -16/+14 | |
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| * | | | | | Add broken testcases | Eddie Hung | 2019-02-25 | 1 | -0/+46 | |
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| * | | | | | Revert "tests/simple to also do LUT synth" | Eddie Hung | 2019-02-21 | 1 | -1/+0 | |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 5994382a20a0b7e890d22d032eecb39b61e0b3ce. | |||||
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-02-21 | 1 | -4/+2 | |
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| | * | | | | Revert "Add -B option to autotest.sh to append to backend_opts" | Eddie Hung | 2019-02-21 | 1 | -4/+2 | |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b. | |||||
| * | | | | | tests/simple to also do LUT synth | Eddie Hung | 2019-02-21 | 1 | -0/+1 | |
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| * | | | | | Working simple_abc9 tests | Eddie Hung | 2019-02-21 | 1 | -2/+2 | |
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| * | | | | | Add abc9.v testcase to simple_abc9 | Eddie Hung | 2019-02-21 | 1 | -4/+46 | |
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| * | | | | | Merge branch 'clifford/dffsrfix' of https://github.com/YosysHQ/yosys into xaig | Eddie Hung | 2019-02-21 | 1 | -21/+0 | |
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| | * | | | | Remove simple_defparam tests | Eddie Hung | 2019-02-20 | 1 | -21/+0 | |
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| * | | | | | simple_abc9 tests to now preserve memories | Eddie Hung | 2019-02-20 | 1 | -1/+1 | |
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| * | | | | | Move tests/techmap/abc9 to simple_abc9 | Eddie Hung | 2019-02-20 | 4 | -23/+0 | |
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| * | | | | | Add tests/simple_abc9 | Eddie Hung | 2019-02-20 | 1 | -0/+23 | |
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| * | | | | | Add a quick abc9 test | Eddie Hung | 2019-02-19 | 4 | -0/+29 | |
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| * | | | | | Merge branch 'master' into xaig | Eddie Hung | 2019-02-19 | 5 | -8/+92 | |
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| | * | | | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 5 | -8/+93 | |
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| | | * | | Append (instead of over-writing) EXTRA_FLAGS | Jim Lawson | 2019-02-15 | 1 | -1/+1 | |
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| | | * | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 4 | -7/+92 | |
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | |||||
| * | | | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 2 | -2/+6 | |
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| * | | | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 | |
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| * | | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig | Eddie Hung | 2019-02-06 | 3 | -2/+67 | |
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| | * | | Add tests for simple cases using defparam | Eddie Hung | 2019-02-06 | 1 | -0/+21 | |
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| | * | | Add -B option to autotest.sh to append to backend_opts | Eddie Hung | 2019-02-06 | 1 | -2/+4 | |
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| | * | | Extend testcase | Eddie Hung | 2019-02-06 | 1 | -2/+34 | |
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| | * | | Add testcase | Eddie Hung | 2019-02-06 | 1 | -0/+10 | |
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| * | | Revert most of autotest.sh; for non *.v use Yosys to translate | Eddie Hung | 2019-02-06 | 1 | -7/+9 | |
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| * | | Rename ASCII tests | Eddie Hung | 2019-02-06 | 15 | -0/+0 | |
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| * | | Add tests | Eddie Hung | 2019-02-04 | 16 | -8/+109 | |
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| * | Remove asicworld tests for (unsupported) switch-level modelling | Clifford Wolf | 2019-01-27 | 4 | -69/+0 | |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
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index : iCE40/yosys | |
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