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* Extend sign extension testsEddie Hung2019-06-201-4/+16
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* Remove leftover commentEddie Hung2019-06-201-3/+0
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* Add testEddie Hung2019-06-201-0/+24
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* Update some .gitignore filesClifford Wolf2019-06-202-3/+3
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add proper test for SV-style arraysClifford Wolf2019-06-203-6/+16
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-202-0/+6
|\ | | | | | | towoe-unpacked_arrays
| * Unpacked array declaration using sizeTobias Wölfel2019-06-192-0/+6
| | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
* | Merge pull request #1105 from YosysHQ/clifford/fixlogicinitClifford Wolf2019-06-192-14/+37
|\ \ | | | | | | Improve handling of initial/default values
| * | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* / Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add some more commentsEddie Hung2019-06-101-1/+6
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* Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
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* Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
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* Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
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* Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
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* Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-072-0/+31
|\ | | | | elaboration system tasks
| * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-0/+31
| |\ | | | | | | | | | clifford/pr983
| | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
| | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
* | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
|/ / | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-072-12/+1
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-074-3/+42
|\ \ | | | | | | | | | into tux3-implicit_named_connection
| * | SystemVerilog support for implicit named port connectionstux32019-06-064-3/+42
| | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
* | | Moved tests that fail with Icarus Verilog to /tests/various. Those tests are ↵Maciej Kurc2019-06-044-0/+46
| | | | | | | | | | | | | | | | | | just for parsing Verilog. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | | Added tests for attributesMaciej Kurc2019-06-039-0/+219
|/ / | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Merge pull request #1049 from YosysHQ/clifford/fix1047Clifford Wolf2019-05-281-0/+4
|\ \ | | | | | | Do not use shiftmul peepopt pattern when mul result is truncated
| * | Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047Clifford Wolf2019-05-281-0/+4
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Add actual wandwor test that is part of "make test"Clifford Wolf2019-05-282-33/+36
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | Merge branch 'master' into wandworStefan Biereigel2019-05-272-0/+76
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| * | Fix initEddie Hung2019-05-241-27/+27
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| * | Fix typosEddie Hung2019-05-241-6/+6
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| * | Add more testsEddie Hung2019-05-242-20/+41
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| * | Call procEddie Hung2019-05-241-1/+1
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| * | Fix duplicate driverEddie Hung2019-05-241-15/+15
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| * | Add opt_rmdff testsEddie Hung2019-05-232-0/+55
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* | | reformat wand/wor testStefan Biereigel2019-05-271-22/+21
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* | | remove port direction workaround from test caseStefan Biereigel2019-05-271-2/+1
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* | | add simple test case for wand/worStefan Biereigel2019-05-231-0/+35
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* | Added tests for Verilog frontent for attributes on parameters and localparamsMaciej Kurc2019-05-162-0/+22
| | | | | | | | Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
* | Add test case from #997Clifford Wolf2019-05-071-0/+12
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #946 from YosysHQ/clifford/specifyClifford Wolf2019-05-062-0/+86
|\ \ | | | | | | Add specify parser
| * | Improve tests/various/specify.ysClifford Wolf2019-05-061-2/+32
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | More testingEddie Hung2019-05-032-2/+5
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| * | Fix spacingEddie Hung2019-05-031-6/+6
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| * | Add quick-and-dirty specify testsEddie Hung2019-05-032-0/+53
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* | | Merge pull request #975 from YosysHQ/clifford/fix968Clifford Wolf2019-05-061-0/+25
|\ \ \ | | | | | | | | Re-enable "final loop assignment" feature and fix opt_clean warnings
| * | | Merge branch 'master' of github.com:YosysHQ/yosys into clifford/fix968Clifford Wolf2019-05-066-5/+60
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| * | | Add additional test cases for for-loopsClifford Wolf2019-05-011-0/+25
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | Merge pull request #871 from YosysHQ/verific_importClifford Wolf2019-05-061-0/+52
|\ \ \ \ | |_|/ / |/| | | Improve verific -chparam and add hierarchy -chparam
| * | | Add tests/various/chparam.shClifford Wolf2019-05-061-0/+52
| | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | | | iverilog with simcells.v as wellEddie Hung2019-05-031-1/+2
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