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* xilinx: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-183-46/+15
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* nexus: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-2/+2
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* ecp5: Use `memory_libmap` pass.Marcelina Kościelnicka2022-05-181-135/+18
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* proc_rom: Add special handling of const-0 address bits.Marcelina Kościelnicka2022-05-181-0/+146
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* Merge pull request #3314 from jix/sva_value_change_logic_wideJannis Harder2022-05-162-2/+43
|\ | | | | verific: Use new value change logic also for $stable of wide signals.
| * verific: Use new value change logic also for $stable of wide signals.Jannis Harder2022-05-112-2/+43
| | | | | | | | I missed this in the previous PR.
* | Add proc_rom pass.Marcelina Kościelnicka2022-05-131-0/+43
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* Merge pull request #3305 from jix/sva_value_change_logicJannis Harder2022-05-097-1/+96
|\ | | | | verific: Improve logic generated for SVA value change expressions
| * verific: Improve logic generated for SVA value change expressionsJannis Harder2022-05-097-1/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previously generated logic assumed an unconstrained past value in the initial state and did not handle 'x values. While the current formal verification flow uses 2-valued logic, SVA value change expressions require a past value of 'x during the initial state to behave in the expected way (i.e. to consider both an initial 0 and an initial 1 as $changed and an initial 1 as $rose and an initial 0 as $fell). This patch now generates logic that at the same time a) provides the expected behavior in a 2-valued logic setting, not depending on any dont-care optimizations, and b) properly handles 'x values in yosys simulation
* | Merge pull request #3297 from jix/sva_nested_clk_elseJannis Harder2022-05-091-0/+11
|\ \ | |/ |/| verific: Fix conditions of SVAs with explicit clocks within procedures
| * verific: Fix conditions of SVAs with explicit clocks within proceduresJannis Harder2022-05-031-0/+11
| | | | | | | | | | | | | | | | | | For SVAs that have an explicit clock and are contained in a procedure which conditionally executes the assertion, verific expresses this using a mux with one input connected to constant 1 and the other output connected to an SVA_AT. The existing code only handled the case where the first input is connected to 1. This patch also handles the other case.
* | Fix running sva testsMiodrag Milanovic2022-05-091-4/+3
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* | opt_mem: Remove constant-value bit lanes.Marcelina Kościelnicka2022-05-072-15/+2
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* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-052-0/+30
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* opt_merge: Add `-keepdc` option required for formal verificationJannis Harder2022-04-011-0/+50
| | | | | | | | The `-keepdc` option prevents merging flipflops with dont-care bits in their initial value, as, in general, this is not a valid transform for formal verification. The keepdc option of `opt` is passed along to `opt_merge` now.
* Fix valgrind tests when using verificMiodrag Milanovic2022-03-304-8/+8
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* Proper example codeMiodrag Milanovic2022-03-142-1/+3
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* intel_alm: M10K write-enable is negative-trueLofty2022-03-091-1/+2
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* Merge pull request #3207 from nakengelhardt/json_escape_quotesMiodrag Milanović2022-03-042-0/+15
|\ | | | | fix handling of escaped chars in json backend and frontend (mostly)
| * fix handling of escaped chars in json backend and frontendN. Engelhardt2022-02-182-0/+15
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* | test dlatchsr and adlatchMiodrag Milanovic2022-02-164-4/+94
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* | Added test casesMiodrag Milanovic2022-02-1638-0/+896
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* verilog: support for time scale delay valuesZachary Snow2022-02-141-0/+25
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* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-144-5/+51
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-112-0/+108
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* verilog: fix const func eval with upto variablesZachary Snow2022-02-112-0/+84
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* gowin: Fix LUT RAM inference, add more models.Marcelina Kościelnicka2022-02-091-3/+2
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* Merge pull request #3185 from YosysHQ/micko/co_simMiodrag Milanović2022-02-077-0/+953
|\ | | | | Add co-simulation in sim pass
| * bug fix and cleanupsMiodrag Milanovic2022-02-041-2/+2
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| * Add test cases for co-simulationMiodrag Milanovic2022-02-027-0/+953
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* | opt_reduce: Add $bmux and $demux optimization patterns.Marcelina Kościelnicka2022-01-302-0/+208
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* Merge pull request #3120 from Icenowy/anlogic-bramMiodrag Milanović2022-01-192-1/+14
|\ | | | | anlogic: support BRAM mapping
| * anlogic: support BRAM mappingIcenowy Zheng2021-12-172-1/+14
| | | | | | | | | | | | | | | | | | | | | | Anlogic FPGAs all have two kinds of BRAMs, one is 9bit*1K when being true dual port (or 18bit*512 when simple dual port), the other is 16bit*2K. Supports mapping of these two kinds of BRAMs. 9Kbit BRAM in SDP mode and 32Kbit BRAM with 8bit width are not support yet. Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
* | sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-078-0/+135
| | | | | | | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* | sv: fix size cast internal expression extensionZachary Snow2022-01-072-0/+145
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* | logger: fix unmatched expected warnings and errorsZachary Snow2022-01-041-0/+42
| | | | | | | | | | | | | | | | - Prevent unmatched expected error patterns from self-matching - Prevent infinite recursion on unmatched expected warnings - Always print the error message for unmatched error patterns - Add test coverage for all unmatched message types - Add test coverage for excess matched logs and warnings
* | fix iverilog compatibility for new case expr testsZachary Snow2022-01-032-2/+2
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* | fixup verilog doubleslash testZachary Snow2022-01-032-0/+3
| | | | | | | | | | - add generated doubleslash.v to .gitignore - ensure backend verilog can be read again
* | sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+7
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* | memory_share: Fix SAT-based sharing for wide ports.Marcelina Kościelnicka2021-12-201-0/+34
| | | | | | | | Fixes #3117.
* | fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-172-0/+43
|/ | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* preprocessor: do not destroy double slash escaped identifiersThomas Sailer2021-12-151-0/+19
| | | | | | | | | | | The preprocessor currently destroys double slash containing escaped identifiers (for example \a//b ). This is due to next_token trying to convert single line comments (//) into /* */ comments. This then leads to an unintuitive error message like this: ERROR: syntax error, unexpected '*' This patch fixes the error by recognizing escaped identifiers and returning them as single token. It also adds a testcase.
* Fix the tests we just brokeClaire Xenia Wolf2021-12-106-10/+10
| | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
* Add gitignore for gatemateMiodrag Milanovic2021-12-031-0/+4
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* sta: very crude static timing analysis passLofty2021-11-251-0/+81
| | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* Support parameters using struct as a wiretype (#3050)Kamil Rakoczy2021-11-161-0/+51
| | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* synth_gatemate: Update passPatrick Urban2021-11-131-4/+8
| | | | | | * remove `write_edif` and `write_blif` options * remove redundant `abc` call before muxcover * update style
* synth_gatemate: Apply new test practice with assert-maxPatrick Urban2021-11-137-12/+12
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* synth_gatemate: Fix fsm testPatrick Urban2021-11-131-2/+2
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* Allow initial blocks to be disabled during testsPatrick Urban2021-11-136-4/+20
| | | | Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
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