aboutsummaryrefslogtreecommitdiffstats
path: root/tests
Commit message (Collapse)AuthorAgeFilesLines
* Merge pull request #1147 from YosysHQ/clifford/fix1144Clifford Wolf2019-07-092-1/+12
| | | Improve specify dummy parser
* Merge pull request #1153 from YosysHQ/dave/fix_multi_muxDavid Shah2019-07-092-0/+20
| | | memory_dff: Fix checking of feedback mux input when more than one mux
* autotest.sh to define _AUTOTB when test_autotbEddie Hung2019-07-091-1/+1
|
* Merge pull request #1146 from gsomlo/gls-test-abc-extClifford Wolf2019-07-093-6/+21
| | | tests: use optional ABCEXTERNAL when specified
* Merge pull request #1139 from YosysHQ/dave/check-sim-iverilogEddie Hung2019-06-271-0/+18
|\ | | | | tests: Check that Icarus can parse arch sim models
| * Add simcells.v, simlib.v, and some outputEddie Hung2019-06-271-1/+11
| |
| * tests: Check that Icarus can parse arch sim modelsDavid Shah2019-06-261-0/+8
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1143 from YosysHQ/clifford/fix1135Eddie Hung2019-06-272-5/+26
|\ \ | | | | | | Add "pmux2shiftx -norange"
| * | Add #1135 testcaseEddie Hung2019-06-272-5/+26
| |/
* / Copy tests from eddie/fix1132Eddie Hung2019-06-271-0/+320
|/
* Add testcase from #335, fixed by #1130Eddie Hung2019-06-251-0/+28
|
* Merge pull request #1130 from YosysHQ/eddie/fix710Clifford Wolf2019-06-252-1/+22
|\ | | | | memory_dff: walk through more than one mux for computing read enable
| * Add testEddie Hung2019-06-242-1/+22
| |
* | Merge remote-tracking branch 'origin/master' into eddie/muxpackEddie Hung2019-06-225-1/+298
|\|
| * Merge pull request #1108 from YosysHQ/clifford/fix1091Eddie Hung2019-06-211-1/+140
| |\ | | | | | | Add support for partial matches to muxcover
| | * Missing a `clean` and `opt_expr -mux_bool` in testEddie Hung2019-06-201-0/+4
| | |
| | * Add testEddie Hung2019-06-201-1/+136
| | |
| * | Merge pull request #1085 from YosysHQ/eddie/shregmap_improveEddie Hung2019-06-212-0/+114
| |\ \ | | | | | | | | Improve shregmap to handle case where first flop is common to two chains
| | * | Add shregmap -tech xilinx testEddie Hung2019-06-122-2/+63
| | | |
| | * | Add testEddie Hung2019-06-102-0/+53
| | | |
| * | | Merge pull request #1119 from YosysHQ/eddie/fix1118Clifford Wolf2019-06-211-0/+11
| |\ \ \ | | | | | | | | | | Make genvar a signed type
| | * | | Add testEddie Hung2019-06-201-0/+11
| | | |/ | | |/|
| * | | Extend sign extension testsEddie Hung2019-06-201-4/+16
| | | |
| * | | Remove leftover commentEddie Hung2019-06-201-3/+0
| | | |
| * | | Add testEddie Hung2019-06-201-0/+24
| |/ /
* | | Add more testsEddie Hung2019-06-212-21/+51
| | |
* | | Fix testcaseEddie Hung2019-06-211-3/+4
| | |
* | | Add more muxpack tests, with overlapping entriesEddie Hung2019-06-212-1/+84
| | |
* | | Merge branch 'master' into eddie/muxpackEddie Hung2019-06-216-21/+62
|\| |
| * | Update some .gitignore filesClifford Wolf2019-06-202-3/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add proper test for SV-style arraysClifford Wolf2019-06-203-6/+16
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'unpacked_arrays' of https://github.com/towoe/yosys-sv into ↵Clifford Wolf2019-06-202-0/+6
| |\ \ | | | | | | | | | | | | towoe-unpacked_arrays
| | * | Unpacked array declaration using sizeTobias Wölfel2019-06-192-0/+6
| | |/ | | | | | | | | | | | | | | | | | | | | | Allows fixed-sized array dimension specified by a single number. This commit is based on the work from PeterCrozier https://github.com/YosysHQ/yosys/pull/560. But is split out of the original work.
| * | Merge pull request #1105 from YosysHQ/clifford/fixlogicinitClifford Wolf2019-06-192-14/+37
| |\ \ | | | | | | | | Improve handling of initial/default values
| | * | Add defvalue test, minor autotest fixes for .sv filesClifford Wolf2019-06-192-14/+37
| | |/ | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * / Make tests/aiger less chattyClifford Wolf2019-06-191-4/+6
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge remote-tracking branch 'origin/master' into eddie/muxpackEddie Hung2019-06-101-1/+6
|\|
| * Add some more commentsEddie Hung2019-06-101-1/+6
| |
* | Merge branch 'master' into eddie/muxpackEddie Hung2019-06-0728-33/+138
|\|
| * Test *.aag too, by using *.aig as referenceEddie Hung2019-06-071-0/+19
| |
| * Use ABC to convert from AIGER to VerilogEddie Hung2019-06-071-2/+3
| |
| * Use ABC to convert AIGER to Verilog, then sat against YosysEddie Hung2019-06-071-21/+15
| |
| * Add symbols to AIGER test inputs for ABCEddie Hung2019-06-0722-8/+40
| |
| * Merge pull request #1077 from YosysHQ/clifford/pr983Clifford Wolf2019-06-072-0/+31
| |\ | | | | | | elaboration system tasks
| | * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-0/+31
| | |\ | | | | | | | | | | | | clifford/pr983
| | | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | | Rename implicit_ports.sv test to implicit_ports.vClifford Wolf2019-06-071-0/+0
| |/ / | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Cleanup tux3-implicit_named_connectionClifford Wolf2019-06-072-12/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge branch 'implicit_named_connection' of https://github.com/tux3/yosys ↵Clifford Wolf2019-06-074-3/+42
| |\ \ | | | | | | | | | | | | into tux3-implicit_named_connection
| | * | SystemVerilog support for implicit named port connectionstux32019-06-064-3/+42
| | | | | | | | | | | | | | | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-13 21:37:40 +0000