| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Modified errors into warnings | Udi Finkelstein | 2018-06-05 | 1 | -4/+38 |
| | | | | | No longer false warnings for memories and assertions | ||||
| * | reg_wire_error test needs the -sv flag so it is run via a script so it had ↵ | Udi Finkelstein | 2018-06-05 | 2 | -0/+41 |
| | | | | | to be moved out of the tests/simple dir that only runs Verilog files | ||||
| * | Added "pmuxtree" command | Clifford Wolf | 2015-04-07 | 1 | -0/+51 |
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| * | Added tests/various/constmsk_test.ys | Clifford Wolf | 2014-09-04 | 3 | -0/+68 |
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| * | Added tests/various/.gitignore | Clifford Wolf | 2014-07-26 | 1 | -0/+1 |
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| * | Added tests/various/submod_extract.ys | Clifford Wolf | 2014-07-26 | 2 | -0/+27 |
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index : iCE40/yosys | |
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