| Commit message (Collapse) | Author | Age | Files | Lines | |
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| * | support file locations containing spaces | Miodrag Milanovic | 2022-08-08 | 1 | -8/+8 |
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| * | Fixes in vcdcd.pl for newer Perl versions | Claire Xenia Wolf | 2021-10-19 | 1 | -3/+3 |
| | | | | | Signed-off-by: Claire Xenia Wolf <claire@clairexen.net> | ||||
| * | memory_dff: Remove now-useless write port handling. | Marcelina Kościelnicka | 2021-03-08 | 1 | -1/+1 |
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| * | Replace opt_rmdff with opt_dff. | Marcelina Kościelnicka | 2020-08-07 | 1 | -3/+3 |
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| * | autotest.sh to define _AUTOTB when test_autotb | Eddie Hung | 2019-06-28 | 1 | -1/+1 |
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| * | tests: use optional ABCEXTERNAL when specified | Gabriel L. Somlo | 2019-06-27 | 1 | -2/+5 |
| | | | | | | | | | | Commits 65924fd1, abc40924, and ebe29b66 hard-code the invocation of yosys-abc, which fails if ABCEXTERNAL was specified during the build. Allow tests to utilize an optional, externally specified abc binary. Signed-off-by: Gabriel Somlo <gsomlo@gmail.com> | ||||
| * | Add defvalue test, minor autotest fixes for .sv files | Clifford Wolf | 2019-06-19 | 1 | -14/+15 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Use ABC to convert from AIGER to Verilog | Eddie Hung | 2019-06-07 | 1 | -2/+3 |
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| * | SystemVerilog support for implicit named port connections | tux3 | 2019-06-06 | 1 | -2/+13 |
| | | | | | | This is the `foo foo(.port1, .port2);` SystemVerilog syntax introduced in IEEE1800-2005. | ||||
| * | iverilog with simcells.v as well | Eddie Hung | 2019-05-03 | 1 | -1/+2 |
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| * | Fix tests | Clifford Wolf | 2019-04-21 | 1 | -2/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-03-19 | 1 | -7/+5 |
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| | * | Hotfix for "make test" | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add "write_verilog -siminit" | Clifford Wolf | 2019-02-28 | 1 | -1/+1 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Fix FIRRTL to Verilog process instance subfield assignment. | Jim Lawson | 2019-02-25 | 1 | -1/+1 |
| | | | | | | | | | | | | | Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module. Enable tests which were disabled due to incorrect treatment of subfields. Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`) | ||||
| | * | Revert "Add -B option to autotest.sh to append to backend_opts" | Eddie Hung | 2019-02-21 | 1 | -4/+2 |
| | | | | | | | | | This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b. | ||||
| | * | Merge https://github.com/YosysHQ/yosys into dff_init | Eddie Hung | 2019-02-17 | 2 | -7/+42 |
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| * | | | One more merge conflict | Eddie Hung | 2019-02-17 | 1 | -6/+1 |
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| * | | | Merge https://github.com/YosysHQ/yosys into read_aiger | Eddie Hung | 2019-02-17 | 2 | -7/+46 |
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| | * | | Update cells supported for verilog to FIRRTL conversion. | Jim Lawson | 2019-02-15 | 2 | -7/+42 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issue warning messages for missing parameterized modules and attempts to set initial values. Replace simple "if (cell-type)" with "else if" chain. Fix FIRRTL shift handling. Add support for parameterized modules, $shift, $shiftx. Handle default output file. Deal with no top module. Automatically run pmuxtree pass. Allow EXTRA_FLAGS and SEED parameters to be set in the environment for tests/tools/autotest.mk. Support FIRRTL regression testing in tests/tools/autotest.sh Add xfirrtl files to test directories to exclude files from FIRRTL regression tests that are known to fail. | ||||
| * | | | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 1 | -1/+1 |
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| * | | | Merge branch 'dff_init' of https://github.com/eddiehung/yosys into xaig | Eddie Hung | 2019-02-06 | 1 | -2/+4 |
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| | * | | Add -B option to autotest.sh to append to backend_opts | Eddie Hung | 2019-02-06 | 1 | -2/+4 |
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| * | | Revert most of autotest.sh; for non *.v use Yosys to translate | Eddie Hung | 2019-02-06 | 1 | -7/+9 |
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| * | | Add tests | Eddie Hung | 2019-02-04 | 1 | -8/+13 |
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| * | Fixed typo (sikp -> skip) | Udi Finkelstein | 2018-06-05 | 1 | -1/+1 |
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| * | autotest.sh: Change from /bin/bash to /usr/bin/env bash | Johnny Sorocil | 2018-05-06 | 1 | -1/+1 |
| | | | | | | This enables running tests on Unix systems which are not shipped with bash installed in /bin/bash (eg *BSDs and Solaris). | ||||
| * | Merge branch 'master' of https://github.com/brouhaha/yosys | Clifford Wolf | 2016-09-23 | 1 | -1/+6 |
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| | * | Add optional SEED=n command line option to Makefile, and -S n command line ↵ | Eric Smith | 2016-09-22 | 1 | -1/+6 |
| | | | | | | | | | option to test scripts, for deterministic regression tests. | ||||
| * | | Added autotest.sh -I | Clifford Wolf | 2016-09-20 | 1 | -16/+19 |
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| * | Fix for modules with big interfaces. | Kaj Tuomi | 2016-09-13 | 1 | -2/+2 |
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| * | Added "test_autotb -seed" (and "autotest.sh -S") | Clifford Wolf | 2016-08-06 | 1 | -2/+4 |
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| * | Fixed autotest.sh handling of `timescale | Clifford Wolf | 2016-07-02 | 1 | -14/+10 |
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| * | Improvements and fixes in autotest.sh script and test_autotb | Clifford Wolf | 2016-05-20 | 1 | -6/+6 |
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| * | Fix for Modelsim transcript line warp issue #164 | Kaj Tuomi | 2016-05-19 | 1 | -4/+4 |
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| * | Optionally use ${CC} when compiling test utils. | Sergey Kvachonok | 2016-03-25 | 1 | -1/+1 |
| | | | | | Default to gcc when not set. | ||||
| * | Switched to Python 3 | Clifford Wolf | 2015-08-22 | 1 | -4/+1 |
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| * | Another block of spelling fixes | Larry Doolittle | 2015-08-14 | 1 | -1/+1 |
| | | | | | Smaller this time | ||||
| * | Spell check (by Larry Doolittle) | Clifford Wolf | 2015-08-14 | 1 | -1/+1 |
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| * | Some test related fixes | Clifford Wolf | 2015-02-12 | 1 | -1/+1 |
| | | | | | (incl. removal of three bad test cases) | ||||
| * | Refactoring of memory_bram and xilinx brams | Clifford Wolf | 2015-01-18 | 1 | -0/+2 |
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| * | Tiny fix in vcdcd.pl | Clifford Wolf | 2015-01-13 | 1 | -2/+2 |
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| * | Added "synth" command | Clifford Wolf | 2014-09-14 | 1 | -2/+2 |
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| * | Fixed autotest for non-basename arguments | Clifford Wolf | 2014-09-06 | 1 | -0/+3 |
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| * | Added autotest -e (do not use -noexpr on write_verilog) | Clifford Wolf | 2014-08-30 | 1 | -2/+4 |
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| * | Added "wreduce" to some of the standard test benches | Clifford Wolf | 2014-08-03 | 1 | -1/+1 |
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| * | Added "test_autotb -n <num_iter>" option | Clifford Wolf | 2014-08-01 | 1 | -2/+5 |
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| * | Added "make -j{N}" support to "make test" | Clifford Wolf | 2014-07-30 | 2 | -6/+23 |
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| * | Renamed "write_autotest" to "test_autotb" and moved to passes/tests/ | Clifford Wolf | 2014-07-29 | 1 | -1/+1 |
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| * | Added "opt_const -fine" and "opt_reduce -fine" | Clifford Wolf | 2014-07-21 | 1 | -1/+1 |
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