iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Hell let's add the original #1381 testcase too	Eddie Hung	2019-09-20	1	-3/+22
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*	Add testcase	Eddie Hung	2019-09-20	1	-0/+43
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*	Added extractinv pass	Marcin Kościelnicki	2019-09-19	1	-0/+41
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*	Add -match-init option to dff2dffs.	Marcin Kościelnicki	2019-09-11	1	-0/+50
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*	techmap: Add support for extracting init values of ports	Marcin Kościelnicki	2019-09-07	1	-0/+98
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*	improve clkbuf_inhibit propagation upwards through hierarchy	Marcin Kościelnicki	2019-08-27	1	-5/+33
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*	Improve tests to check that clkbuf is connected to expected	Eddie Hung	2019-08-26	1	-6/+21
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*	Check clkbuf_inhibit=1 is ignored for custom selection	Eddie Hung	2019-08-23	1	-0/+1
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*	Add simple clkbufmap tests	Eddie Hung	2019-08-23	1	-0/+52
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*	tests/techmap/run-test.sh to cope with *.ys	Eddie Hung	2019-08-23	2	-7/+18
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*	Add test	Eddie Hung	2019-08-20	3	-0/+15
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*	Added read-enable to memory model	Clifford Wolf	2015-09-25	1	-1/+8
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*	Added $meminit support to "memory" command	Clifford Wolf	2015-02-14	1	-0/+5
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*	Changed tests/techmap/mem_simple_4x1_map for new $mem/$memwr WR_EN interface	Clifford Wolf	2014-07-16	1	-2/+13
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*	Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh	Clifford Wolf	2014-03-11	1	-1/+1
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*	Use "verilog -noattr" in tests/techmap/mem_simple_4x1 test (for old iverilog)	Clifford Wolf	2014-03-11	1	-1/+1
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*	Use private namespace in mem_simple_4x1_map	Clifford Wolf	2014-02-21	1	-4/+4
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*	Added tests/techmap/mem_simple_4x1	Clifford Wolf	2014-02-21	7	-0/+214