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* | | | Merge blockram testsEddie Hung2019-12-163-47/+81
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* | | | Fixing compiler warning/issues. Moving test script to the correct placeDiego H2019-12-161-6/+6
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* | | | Removing fixed attribute value to !ramstyle rulesDiego H2019-12-151-3238/+0
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* | | | Merging attribute rules into a single match block; Adding testsDiego H2019-12-153-0/+3373
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* | | | Renaming BRAM memory tests for the sake of uniformityDiego H2019-12-132-6/+6
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* | | | Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.Diego H2019-12-121-2/+2
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* | | | Adding a note (TODO) in the memory_params.ys check fileDiego H2019-12-121-0/+2
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* | | | Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1Diego H2019-12-122-0/+90
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* | | Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-093-23/+136
|\ \ \ | |_|/ |/| | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
| * | unmap $__ICE40_CARRY_WRAPPER in testEddie Hung2019-12-091-1/+21
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| * | ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-3/+5
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| * | Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-2/+2
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| * | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+30
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| * | Check SB_CARRY name also preservedEddie Hung2019-12-031-0/+1
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| * | Add testcaseEddie Hung2019-12-031-0/+60
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* | | tests: arch: xilinx: Change order of arguments in macc.shJan Kowalewski2019-12-061-1/+1
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* | Merge pull request #1524 from pepijndevos/gowindffinitClifford Wolf2019-12-033-2/+301
|\ \ | |/ |/| Gowin: add and test DFF init values
| * update testPepijn de Vos2019-12-031-2/+3
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| * Use -match-init to not synth contradicting init valuesPepijn de Vos2019-12-031-10/+12
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| * attempt to fix formattingPepijn de Vos2019-11-251-138/+138
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| * gowin: add and test dff init valuesPepijn de Vos2019-11-252-0/+296
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* | No need for -abc9Eddie Hung2019-11-261-1/+1
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* | Add citationEddie Hung2019-11-261-0/+1
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* | Add testcase derived from fastfir_dynamictaps benchmarkEddie Hung2019-11-261-0/+68
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* | xilinx: Use INV instead of LUT1 when applicableMarcin Koƛcielnicki2019-11-254-8/+8
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* gowin: Remove show command from tests.Marcin Koƛcielnicki2019-11-221-1/+0
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* Merge branch 'master' of https://github.com/YosysHQ/yosys into gowinPepijn de Vos2019-11-165-17/+34
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| * Fixed testsMiodrag Milanovic2019-11-115-17/+34
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* | fix fsm test with proper clock enable polarityPepijn de Vos2019-11-111-0/+11
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* | fix wide lutsPepijn de Vos2019-11-061-7/+10
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* | don't cound exact luts in big muxes; futile and fragilePepijn de Vos2019-10-301-3/+0
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* | add tristate buffer and testPepijn de Vos2019-10-281-0/+13
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* | do not use wide luts in testcasePepijn de Vos2019-10-281-3/+3
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* | ALU sim tweaksPepijn de Vos2019-10-241-2/+2
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* | Add some testsPepijn de Vos2019-10-2110-0/+224
|/ | | | | | | | Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram
* fixed errorMiodrag Milanovic2019-10-181-1/+1
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* Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
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* Common memory test now sharedMiodrag Milanovic2019-10-1810-89/+5
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* Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
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* Share common testsMiodrag Milanovic2019-10-18103-1316/+178
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* fix yosys pathMiodrag Milanovic2019-10-181-2/+2
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* Fix path to yosysMiodrag Milanovic2019-10-185-5/+5
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* Moved all tests in arch sub directoryMiodrag Milanovic2019-10-18150-0/+3548
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* Add simcells.v, simlib.v, and some outputEddie Hung2019-06-271-1/+11
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* tests: Check that Icarus can parse arch sim modelsDavid Shah2019-06-261-0/+8
Signed-off-by: David Shah <dave@ds0.me>