| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | ice40_wrapcarry to really preserve attributes via -unwrap option | Eddie Hung | 2019-12-09 | 1 | -3/+5 |
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| * | Drop keep=0 attributes on SB_CARRY | Eddie Hung | 2019-12-06 | 1 | -2/+2 |
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| * | Add WIP test for unwrapping $__ICE40_CARRY_WRAPPER | Eddie Hung | 2019-12-05 | 1 | -0/+30 |
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| * | Check SB_CARRY name also preserved | Eddie Hung | 2019-12-03 | 1 | -0/+1 |
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| * | Add testcase | Eddie Hung | 2019-12-03 | 1 | -0/+60 |
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| * | Merge pull request #1524 from pepijndevos/gowindffinit | Clifford Wolf | 2019-12-03 | 3 | -2/+301 |
| |\ | | | | | Gowin: add and test DFF init values | ||||
| | * | update test | Pepijn de Vos | 2019-12-03 | 1 | -2/+3 |
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| | * | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 1 | -10/+12 |
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| | * | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 1 | -138/+138 |
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| | * | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 2 | -0/+296 |
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| * | | No need for -abc9 | Eddie Hung | 2019-11-26 | 1 | -1/+1 |
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| * | | Add citation | Eddie Hung | 2019-11-26 | 1 | -0/+1 |
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| * | | Add testcase derived from fastfir_dynamictaps benchmark | Eddie Hung | 2019-11-26 | 1 | -0/+68 |
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| * | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 4 | -8/+8 |
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| * | gowin: Remove show command from tests. | Marcin Kościelnicki | 2019-11-22 | 1 | -1/+0 |
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| * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-16 | 5 | -17/+34 |
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| | * | Fixed tests | Miodrag Milanovic | 2019-11-11 | 5 | -17/+34 |
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| * | | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 1 | -0/+11 |
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| * | | fix wide luts | Pepijn de Vos | 2019-11-06 | 1 | -7/+10 |
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| * | | don't cound exact luts in big muxes; futile and fragile | Pepijn de Vos | 2019-10-30 | 1 | -3/+0 |
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| * | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 1 | -0/+13 |
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| * | | do not use wide luts in testcase | Pepijn de Vos | 2019-10-28 | 1 | -3/+3 |
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| * | | ALU sim tweaks | Pepijn de Vos | 2019-10-24 | 1 | -2/+2 |
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| * | | Add some tests | Pepijn de Vos | 2019-10-21 | 10 | -0/+224 |
| |/ | | | | | | | | Copied from Efinix. * fsm is broken * latch and tribuf are not implemented yet * memory maps to dram | ||||
| * | fixed error | Miodrag Milanovic | 2019-10-18 | 1 | -1/+1 |
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| * | Unify verilog style | Miodrag Milanovic | 2019-10-18 | 11 | -191/+157 |
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| * | Common memory test now shared | Miodrag Milanovic | 2019-10-18 | 10 | -89/+5 |
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| * | Remove not needed tests | Miodrag Milanovic | 2019-10-18 | 4 | -52/+0 |
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| * | Share common tests | Miodrag Milanovic | 2019-10-18 | 103 | -1316/+178 |
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| * | fix yosys path | Miodrag Milanovic | 2019-10-18 | 1 | -2/+2 |
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| * | Fix path to yosys | Miodrag Milanovic | 2019-10-18 | 5 | -5/+5 |
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| * | Moved all tests in arch sub directory | Miodrag Milanovic | 2019-10-18 | 150 | -0/+3548 |
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| * | Add simcells.v, simlib.v, and some output | Eddie Hung | 2019-06-27 | 1 | -1/+11 |
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| * | tests: Check that Icarus can parse arch sim models | David Shah | 2019-06-26 | 1 | -0/+8 |
| Signed-off-by: David Shah <dave@ds0.me> | |||||
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index : iCE40/yosys | |
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