| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Do not do call equiv_opt when no sim model exists | Eddie Hung | 2019-12-31 | 2 | -4/+4 |
| | | |||||
| * | Call equiv_opt with -multiclock and -assert | Eddie Hung | 2019-12-31 | 1 | -1/+1 |
| | | |||||
| * | Merge pull request #1599 from YosysHQ/eddie/retry_1588 | Eddie Hung | 2019-12-30 | 1 | -0/+16 |
| |\ | | | | | Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once" | ||||
| | * | Add #1598 testcase | Eddie Hung | 2019-12-27 | 1 | -0/+16 |
| | | | |||||
| * | | Update resource count | Eddie Hung | 2019-12-28 | 1 | -3/+3 |
| |/ | |||||
| * | Rename memory tests to lutram, add more xilinx tests | Eddie Hung | 2019-12-12 | 1 | -3/+3 |
| | | |||||
| * | Fixed tests | Miodrag Milanovic | 2019-11-11 | 1 | -4/+9 |
| | | |||||
| * | Common memory test now shared | Miodrag Milanovic | 2019-10-18 | 2 | -22/+1 |
| | | |||||
| * | Share common tests | Miodrag Milanovic | 2019-10-18 | 22 | -302/+11 |
| | | |||||
| * | Fix path to yosys | Miodrag Milanovic | 2019-10-18 | 1 | -1/+1 |
| | | |||||
| * | Moved all tests in arch sub directory | Miodrag Milanovic | 2019-10-18 | 32 | -0/+668 |
 |
index : iCE40/yosys | |
| [no description] |
| aboutsummaryrefslogtreecommitdiffstats |