| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add some more comments | Eddie Hung | 2019-06-10 | 1 | -1/+6 |
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| * | Test *.aag too, by using *.aig as reference | Eddie Hung | 2019-06-07 | 1 | -0/+19 |
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| * | Use ABC to convert AIGER to Verilog, then sat against Yosys | Eddie Hung | 2019-06-07 | 1 | -21/+15 |
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| * | Add symbols to AIGER test inputs for ABC | Eddie Hung | 2019-06-07 | 22 | -8/+40 |
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| * | Add tests/aiger/.gitignore | Clifford Wolf | 2019-04-19 | 1 | -0/+2 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Support and differentiate between ASCII and binary AIG testing | Eddie Hung | 2019-02-08 | 1 | -1/+5 |
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| * | Add binary AIGs converted from AAG | Eddie Hung | 2019-02-08 | 14 | -0/+51 |
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| * | Rename ASCII tests | Eddie Hung | 2019-02-06 | 15 | -0/+96 |
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index : iCE40/yosys | |
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