| Commit message (Expand) | Author | Age | Files | Lines | ||
|---|---|---|---|---|---|---|
| ... | ||||||
| | * | | | | | xilinx: Support multiplier mapping for all families. | Marcin Kościelnicki | 2019-10-22 | 9 | -9/+269 | |
| | * | | | | | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_reg | Clifford Wolf | 2019-10-22 | 2 | -0/+2 | |
| | |\ \ \ \ \ | | |_|_|_|/ | |/| | | | | ||||||
| | | * | | | | Call memory_dff before DSP mapping to reserve registers (fixes #1447) | N. Engelhardt | 2019-10-17 | 2 | -0/+2 | |
| | * | | | | | ecp5: Pass -nomfs to abc9 | David Shah | 2019-10-20 | 1 | -2/+2 | |
| | | |/ / / | |/| | | | ||||||
| | * | | | | Makefile: don't assume python is called `python3` | Sean Cross | 2019-10-19 | 4 | -6/+6 | |
| | * | | | | Merge branch 'master' into mmicko/efinix | Miodrag Milanović | 2019-10-18 | 37 | -474/+305 | |
| | |\| | | | ||||||
| | | * | | | ecp5: Add ECLKBRIDGECS blackbox | David Shah | 2019-10-11 | 1 | -0/+7 | |
| | | * | | | ecp5: Add attrmvcp to copy syn_useioff to driving FF | David Shah | 2019-10-10 | 1 | -0/+1 | |
| | | * | | | ecp5: Set syn_useioff on IO FFs to enable packing | David Shah | 2019-10-10 | 1 | -8/+8 | |
| | | * | | | xilinx: Add simulation model for IBUFG. | Marcin Kościelnicki | 2019-10-10 | 5 | -33/+14 | |
| | * | | | | FF should be initialized to 0 | Miodrag Milanovic | 2019-10-04 | 1 | -1/+3 | |
| | * | | | | Add missing latch mapping | Miodrag Milanovic | 2019-10-04 | 1 | -0/+12 | |
| * | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-08 | 1 | -5/+9 | |
| |\ \ \ \ \ | | |/ / / | |/| | | | ||||||
| | * | | | | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9 | Eddie Hung | 2019-10-08 | 31 | -228/+236 | |
| | |\ \ \ \ | ||||||
| | | * \ \ \ | Merge branch 'master' into eddie/abc_to_abc9 | Eddie Hung | 2019-10-04 | 4 | -181/+9 | |
| | | |\ \ \ \ | ||||||
| | * | | | | | | Add comment on why partial multipliers are 18x18 | Eddie Hung | 2019-10-04 | 1 | -4/+8 | |
| | * | | | | | | Fix typo in check_label() | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| | | |/ / / / | |/| | | | | ||||||
| * | | | | | | Cleanup | Eddie Hung | 2019-10-07 | 1 | -7/+2 | |
| * | | | | | | Rename $currQ to $abc9_currQ | Eddie Hung | 2019-10-07 | 1 | -46/+46 | |
| * | | | | | | Update comments in abc9_map.v | Eddie Hung | 2019-10-07 | 1 | -131/+57 | |
| * | | | | | | Remove -D_ABC9 | Eddie Hung | 2019-10-07 | 1 | -2/+0 | |
| * | | | | | | Do not require changes to cells_sim.v; try and work out comb model | Eddie Hung | 2019-10-05 | 4 | -230/+200 | |
| * | | | | | | abc -> abc9 | Eddie Hung | 2019-10-04 | 1 | -3/+3 | |
| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-04 | 4 | -181/+9 | |
| |\| | | | | | ||||||
| | * | | | | | Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9` | Eddie Hung | 2019-10-04 | 1 | -2/+6 | |
| | * | | | | | Remove DSP48E1 from *_cells_xtra.v | Eddie Hung | 2019-10-04 | 3 | -178/+2 | |
| * | | | | | | Use read_args for read_verilog | Eddie Hung | 2019-10-04 | 1 | -3/+6 | |
| * | | | | | | Fix merge issues | Eddie Hung | 2019-10-04 | 2 | -9/+10 | |
| * | | | | | | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dff | Eddie Hung | 2019-10-04 | 31 | -278/+294 | |
| |\ \ \ \ \ \ | | |/ / / / | |/| | | | | ||||||
| | * | | | | | Rename abc_* names/attributes to more precisely be abc9_* | Eddie Hung | 2019-10-04 | 31 | -227/+235 | |
| | |/ / / / | ||||||
| | * | | | | Panic over. Model was elsewhere. Re-arrange for consistency | Eddie Hung | 2019-10-04 | 5 | -31/+4 | |
| | * | | | | Oops | Eddie Hung | 2019-10-04 | 1 | -1/+1 | |
| | * | | | | Ohmilord this wasn't added all this time!?! | Eddie Hung | 2019-10-04 | 1 | -0/+29 | |
| | |/ / / | ||||||
| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-10-03 | 6 | -2/+184 | |
| |\| | | | ||||||
| | * | | | ecp5: Fix shuffle_enable port | David Shah | 2019-10-01 | 1 | -2/+2 | |
| | * | | | ecp5: Add support for mapping 36-bit wide PDP BRAMs | David Shah | 2019-10-01 | 6 | -1/+183 | |
| * | | | | English | Eddie Hung | 2019-10-03 | 1 | -3/+3 | |
| * | | | | More fixes | Eddie Hung | 2019-10-01 | 1 | -16/+16 | |
| * | | | | Escape Verilog identifiers for legality outside of Yosys | Eddie Hung | 2019-10-01 | 1 | -48/+48 | |
| * | | | | Remove need for $currQ port connection | Eddie Hung | 2019-09-30 | 2 | -111/+118 | |
| * | | | | Add explanation to abc_map.v | Eddie Hung | 2019-09-30 | 1 | -0/+16 | |
| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-30 | 8 | -124/+122 | |
| |\| | | | ||||||
| | * | | | Add LDCE/LDPE sim library, remove from *cells_xtra.{v,py} | Eddie Hung | 2019-09-30 | 6 | -122/+46 | |
| | * | | | synth_xilinx: Support latches, remove used-up FF init values. | Marcin Kościelnicki | 2019-09-30 | 2 | -2/+76 | |
| * | | | | Missing endmodule | Eddie Hung | 2019-09-29 | 1 | -0/+1 | |
| * | | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-09-29 | 19 | -31/+3401 | |
| |\| | | | ||||||
| | * | | | Merge pull request #1359 from YosysHQ/xc7dsp | Eddie Hung | 2019-09-29 | 19 | -31/+3395 | |
| | |\ \ \ | ||||||
| | | * | | | Re-order | Eddie Hung | 2019-09-27 | 2 | -2/+2 | |
| | | * | | | Missing (* mul2dsp *) for sliceB | Eddie Hung | 2019-09-27 | 1 | -2/+2 | |
| | | * | | | Combine 'flatten' & 'coarse' labels in synth_ecp5 so proc run once | Eddie Hung | 2019-09-26 | 1 | -9/+4 | |
 |
index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
| aboutsummaryrefslogtreecommitdiffstats |