| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | More fixes for bugs found using xsthammer | Clifford Wolf | 2013-06-13 | 1 | -8/+7 | |
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| * | More sign-extension related fixes | Clifford Wolf | 2013-06-10 | 1 | -12/+13 | |
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| * | Implemented technology mapping for multipliers (using array multiplier) | Clifford Wolf | 2013-06-03 | 1 | -4/+30 | |
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| * | Fixed clock related parameter names for $memrd and $memwr in techlibs/simlib.v | Clifford Wolf | 2013-04-07 | 1 | -4/+4 | |
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| * | Added EXTRA_TARGETS Makefile variable | Clifford Wolf | 2013-03-28 | 1 | -1/+1 | |
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| * | Tiny bugfix in simlib.v | Clifford Wolf | 2013-03-26 | 1 | -1/+0 | |
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| * | Fixed stdcells.v for $adff with undef reset value | Clifford Wolf | 2013-03-24 | 1 | -63/+68 | |
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| * | More support code for $sr cells | Clifford Wolf | 2013-03-14 | 1 | -0/+21 | |
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| * | added .gitignore files | Clifford Wolf | 2013-01-05 | 1 | -0/+1 | |
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| * | initial import | Clifford Wolf | 2013-01-05 | 5 | -0/+2447 | |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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