aboutsummaryrefslogtreecommitdiffstats
path: root/techlibs
Commit message (Expand)AuthorAgeFilesLines
...
| * | Fix ECP5 cells_sim for iverilogMiodrag Milanovic2019-03-011-2/+3
| * | Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_modeClifford Wolf2019-02-281-2/+2
| |\ \
| | * | ice40: use 2 bits for READ/WRITE MODE for SB_RAM mapElms2019-02-281-2/+2
| | |/
| * | Reduce amount of trailing whitespace in code baseLarry Doolittle2019-02-286-19/+19
| * | Merge pull request #794 from daveshah1/ecp5improveClifford Wolf2019-02-287-12/+388
| |\ \ | | |/ | |/|
| | * ecp5: Compatibility with Migen AsyncResetSynchronizerDavid Shah2019-02-252-0/+20
| | * ecp5: Add DDRDLLADavid Shah2019-02-191-0/+9
| | * ecp5: Add DELAYF/DELAYG blackboxesDavid Shah2019-02-191-0/+18
| | * ecp5: Add ECLKSYNCB blackboxDavid Shah2019-02-131-1/+7
| | * ecp5: Full set of IO-related blackboxesDavid Shah2019-02-121-0/+102
| | * ecp5: Support for flipflop initialisationDavid Shah2019-01-223-4/+199
| | * ecp5: Add LSRMODE to flipflops for PRLD supportDavid Shah2019-01-211-7/+16
| | * ecp5: More blackboxesDavid Shah2019-01-211-0/+17
| | * ecp5: Increase threshold for ALU mappingDavid Shah2019-01-211-1/+1
| * | techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut moduleLarry Doolittle2019-02-261-22/+22
| * | Clean up some whitepsace outliersLarry Doolittle2019-02-261-2/+2
* | | Add shregmap -init_msb_first and use in synth_xilinxEddie Hung2019-03-141-2/+2
* | | Fix cells_map for SRLEddie Hung2019-03-141-19/+17
* | | Move shregmap until after first techmapEddie Hung2019-03-131-2/+2
* | | Refactor $__SHREG__ in cells_map.vEddie Hung2019-03-131-32/+24
* | | Remove SRL16/32 from cells_xtraEddie Hung2019-02-282-18/+2
* | | Add SRL16 and SRL32 sim modelsEddie Hung2019-02-281-0/+39
* | | Fix SRL16/32 techmap off-by-oneEddie Hung2019-02-281-18/+24
* | | synth_xilinx to call shregmap with enable supportEddie Hung2019-02-282-24/+29
* | | synth_xilinx to use shregmap with -params tooEddie Hung2019-02-282-22/+19
* | | synth_xilinx to now have shregmap call after dff2dffeEddie Hung2019-02-281-0/+2
* | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32Eddie Hung2019-02-281-0/+71
|/ /
* | Merge pull request #740 from daveshah1/improve_dressClifford Wolf2019-02-222-3/+3
|\ \
| * | ecp5: Use abc -dressDavid Shah2019-02-061-2/+2
| * | ice40: Use abc -dress in synth_ice40David Shah2019-02-061-1/+1
* | | Bugfix in ice40_dspClifford Wolf2019-02-212-20/+33
* | | Add ice40 test_dsp_map test case generatorClifford Wolf2019-02-202-0/+99
* | | Add "synth_ice40 -dsp"Clifford Wolf2019-02-201-3/+27
* | | Improve iCE40 SB_MAC16 modelClifford Wolf2019-02-205-121/+179
* | | Add first draft of functional SB_MAC16 modelClifford Wolf2019-02-194-53/+467
|/ /
* / Fixed Anlogic simulation modelMiodrag Milanovic2019-01-251-1/+1
|/
* Add SF2 IO buffer insertionClifford Wolf2019-01-174-1/+168
* Add "synth_sf2 -vlog", fix "synth_sf2 -edif"Clifford Wolf2019-01-171-2/+17
* Merge pull request #777 from mmicko/achronix_cell_sim_fixClifford Wolf2019-01-041-1/+1
|\
| * Fix cells_sim.v for Achronix FPGAMiodrag Milanovic2019-01-041-1/+1
* | Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-044-8/+16
|/
* Merge pull request #755 from Icenowy/anlogic-dram-initClifford Wolf2019-01-026-2/+96
|\
| * anlogic: implement DRAM initializationIcenowy Zheng2018-12-206-2/+96
* | Merge pull request #750 from Icenowy/anlogic-ff-initClifford Wolf2019-01-022-14/+15
|\ \
| * | anlogic: set the init value of DFFsIcenowy Zheng2018-12-182-14/+15
* | | Merge pull request #772 from whitequark/synth_lutClifford Wolf2019-01-022-7/+41
|\ \ \
| * | | synth_ice40: use 4-LUT coarse synthesis mode.whitequark2019-01-021-1/+1
| * | | synth: add k-LUT mode.whitequark2019-01-021-2/+36
| * | | synth: improve script documentation. NFC.whitequark2019-01-021-6/+6
* | | | Merge pull request #771 from whitequark/techmap_cmp2lutClifford Wolf2019-01-022-1/+106
|\| | |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 22:02:53 +0000