| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-04-22 | 12 | -21/+480 |
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| | | * | | | Merge pull request #941 from Wren6991/sim_lib_io_clke | Clifford Wolf | 2019-04-22 | 1 | -10/+19 |
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| | | | * | | | ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp... | Luke Wren | 2019-04-21 | 1 | -10/+19 |
| | | * | | | | Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master | Clifford Wolf | 2019-04-22 | 10 | -10/+458 |
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| | | | * | | | | GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow | Diego | 2019-04-12 | 10 | -11/+459 |
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| | | * | | | | Re-added clean after techmap in synth_xilinx | Clifford Wolf | 2019-04-22 | 1 | -0/+2 |
| | | * | | | | Merge pull request #916 from YosysHQ/map_cells_before_map_luts | Clifford Wolf | 2019-04-22 | 1 | -10/+10 |
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| | | * \ \ \ \ | Merge pull request #911 from mmicko/gowin-nobram | Clifford Wolf | 2019-04-22 | 1 | -1/+1 |
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| | | | * | | | | Make nobram false by default for gowin | Miodrag Milanovic | 2019-04-02 | 1 | -1/+1 |
| | * | | | | | | Tidy up, fix for -nosrl | Eddie Hung | 2019-04-21 | 2 | -12/+16 |
| | * | | | | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-21 | 1 | -2/+2 |
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| | | * | | | | | Merge branch 'master' into map_cells_before_map_luts | Eddie Hung | 2019-04-21 | 6 | -59/+85 |
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| | * | | | | | | Add comments | Eddie Hung | 2019-04-21 | 1 | -0/+7 |
| | * | | | | | | Use new pmux2shiftx from #944, remove my old attempt | Eddie Hung | 2019-04-21 | 1 | -3/+8 |
| | * | | | | | | Merge remote-tracking branch 'origin' into xc7srl | Eddie Hung | 2019-04-20 | 4 | -44/+69 |
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| | | * | | | | | Revert "synth_* with -retime option now calls abc with -D 1 as well" | Eddie Hung | 2019-04-18 | 11 | -15/+15 |
| | | * | | | | | Merge branch 'master' into eddie/fix_retime | Eddie Hung | 2019-04-18 | 4 | -44/+69 |
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| | | * | | | | | synth_* with -retime option now calls abc with -D 1 as well | Eddie Hung | 2019-04-10 | 11 | -15/+15 |
| | * | | | | | | Call shregmap twice -- once for variable, another for fixed | Eddie Hung | 2019-04-05 | 2 | -8/+14 |
| | * | | | | | | Move dffinit til after abc | Eddie Hung | 2019-04-05 | 3 | -2/+2 |
| | * | | | | | | Merge branch 'eddie/fix_retime' into xc7srl | Eddie Hung | 2019-04-05 | 4 | -11/+12 |
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| | | * | | | | | Move techamp t:$_DFF_?N? to before abc call | Eddie Hung | 2019-04-05 | 1 | -2/+2 |
| | | * | | | | | Retry | Eddie Hung | 2019-04-05 | 1 | -1/+1 |
| | | * | | | | | Resolve @daveshah1 comment, update synth_xilinx help | Eddie Hung | 2019-04-05 | 2 | -7/+9 |
| | | * | | | | | synth_xilinx to techmap FFs after abc call, otherwise -retime fails | Eddie Hung | 2019-04-05 | 1 | -3/+3 |
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| | * | | | | | techmap inside map_cells stage | Eddie Hung | 2019-04-05 | 2 | -2/+1 |
| | * | | | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -0/+1 |
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| | | * | | | | Missing techmap entry in help | Eddie Hung | 2019-04-04 | 1 | -0/+1 |
| | * | | | | | Use soft-logic, not LUT3 instantiation | Eddie Hung | 2019-04-04 | 1 | -4/+2 |
| | * | | | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -12/+12 |
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| | | * | | | | synth_xilinx to map_cells before map_luts | Eddie Hung | 2019-04-04 | 1 | -12/+12 |
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| | * | | | | Cleanup comments | Eddie Hung | 2019-04-04 | 1 | -5/+4 |
| | * | | | | t:$dff* -> t:$dff t:$dffe | Eddie Hung | 2019-04-04 | 1 | -2/+2 |
| | * | | | | -nosrl meant when -nobram | Eddie Hung | 2019-04-03 | 1 | -1/+1 |
| | * | | | | Remove duplicate STARTUPE2 | Eddie Hung | 2019-04-03 | 1 | -1/+0 |
| | * | | | | Disable shregmap in synth_xilinx if -retime | Eddie Hung | 2019-04-03 | 1 | -3/+3 |
| | * | | | | synth_xilinx to use shregmap with -minlen 3 | Eddie Hung | 2019-03-25 | 1 | -2/+2 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-22 | 2 | -24/+31 |
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| | * | | | | Add '-nosrl' option to synth_xilinx | Eddie Hung | 2019-03-21 | 1 | -6/+16 |
| | * | | | | Fine tune cells_map.v | Eddie Hung | 2019-03-20 | 1 | -19/+15 |
| | * | | | | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length | Eddie Hung | 2019-03-19 | 1 | -53/+20 |
| | * | | | | Add support for variable length Xilinx SRL > 128 | Eddie Hung | 2019-03-19 | 1 | -11/+67 |
| | * | | | | Restore original synth_xilinx commands | Eddie Hung | 2019-03-19 | 1 | -1/+2 |
| | * | | | | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 |
| | * | | | | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-19 | 1 | -2/+4 |
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| | * | | | | | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 1 | -5/+1 |
| | * | | | | | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 2 | -3/+2 |
| | * | | | | | Working | Eddie Hung | 2019-03-15 | 2 | -47/+78 |
| | * | | | | | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 |
