| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | | Merge pull request #1524 from pepijndevos/gowindffinit | Clifford Wolf | 2019-12-03 | 2 | -112/+270 | |
| | |\ \ | | | | | | | | | Gowin: add and test DFF init values | |||||
| | | * | | Use -match-init to not synth contradicting init values | Pepijn de Vos | 2019-12-03 | 1 | -1/+1 | |
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| | | * | | attempt to fix formatting | Pepijn de Vos | 2019-11-25 | 1 | -154/+154 | |
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| | | * | | gowin: add and test dff init values | Pepijn de Vos | 2019-11-25 | 2 | -41/+199 | |
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| | * | | | xilinx: Add missing blackbox cell for BUFPLL. | Marcin Kościelnicki | 2019-11-29 | 2 | -0/+21 | |
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| * | | | Remove creation of $abc9_control_wire | Eddie Hung | 2019-12-06 | 1 | -16/+6 | |
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| * | | | abc9 to use mergeability class to differentiate sync/async | Eddie Hung | 2019-12-06 | 1 | -12/+15 | |
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| * | | | Remove clkpart | Eddie Hung | 2019-12-05 | 1 | -4/+0 | |
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| * | | | Revert "Special abc9_clock wire to contain only clock signal" | Eddie Hung | 2019-12-05 | 1 | -10/+12 | |
| | | | | | | | | | | | | | This reverts commit 6a2eb5d8f9286b9574647c03e2bdc8b63fccbe4d. | |||||
| * | | | Missing wire declaration | Eddie Hung | 2019-12-04 | 1 | -0/+1 | |
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| * | | | abc9_map.v to transform INIT=1 to INIT=0 | Eddie Hung | 2019-12-04 | 1 | -118/+201 | |
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| * | | | Oh deary me | Eddie Hung | 2019-12-04 | 1 | -4/+4 | |
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| * | | | output reg Q -> output Q to suppress warning | Eddie Hung | 2019-12-04 | 1 | -8/+8 | |
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| * | | | abc9_map.v to do `zinit' and make INIT = 1'b0 | Eddie Hung | 2019-12-04 | 1 | -70/+112 | |
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| * | | | Add abc9_init wire, attach to abc9_flop cell | Eddie Hung | 2019-12-03 | 1 | -2/+12 | |
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| * | | | Revert "Add INIT value to abc9_control" | Eddie Hung | 2019-12-03 | 1 | -8/+8 | |
| | | | | | | | | | | | | | This reverts commit 19bfb4195818be12e6fb962de29ca32444498c22. | |||||
| * | | | techmap abc_unmap.v before xilinx_srl -fixed | Eddie Hung | 2019-12-03 | 1 | -6/+5 | |
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| * | | | Add INIT value to abc9_control | Eddie Hung | 2019-12-02 | 1 | -8/+8 | |
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| * | | | clkpart -unpart into 'finalize' | Eddie Hung | 2019-11-28 | 1 | -3/+4 | |
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| * | | | ean call after abc{,9} | Eddie Hung | 2019-11-27 | 1 | -1/+2 | |
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| * | | | Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff | Eddie Hung | 2019-11-27 | 3 | -25/+30 | |
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| | * | | xilinx: Add simulation models for IOBUF and OBUFT. | Marcin Kościelnicki | 2019-11-26 | 3 | -25/+30 | |
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| * | | | Move 'clean' from map_luts to finalize | Eddie Hung | 2019-11-26 | 1 | -1/+1 | |
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| * | | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-25 | 3 | -5/+11 | |
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| | * | | clkbufmap: Add support for inverters in clock path. | Marcin Kościelnicki | 2019-11-25 | 1 | -1/+5 | |
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| | * | | xilinx: Use INV instead of LUT1 when applicable | Marcin Kościelnicki | 2019-11-25 | 1 | -2/+6 | |
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| | * | coolrunner2: remove spurious log_pop() call, fixes #1463 | Martin Pietryka | 2019-11-23 | 1 | -2/+0 | |
| | | | | | | | | | | | | | | | This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka <martin@pietryka.at> | |||||
| * | | Special abc9_clock wire to contain only clock signal | Eddie Hung | 2019-11-25 | 1 | -12/+10 | |
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| * | | For abc9, run clkpart before ff_map and after abc9 | Eddie Hung | 2019-11-23 | 1 | -0/+2 | |
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| * | | Merge branch 'eddie/clkpart' into xaig_dff | Eddie Hung | 2019-11-22 | 1 | -0/+2 | |
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| | * | gowin: Add missing .gitignore entries | Marcin Kościelnicki | 2019-11-22 | 1 | -0/+2 | |
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| * | | Merge branch 'eddie/xaig_dff_adff' into xaig_dff | Eddie Hung | 2019-11-21 | 1 | -12/+16 | |
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| | * | | Do not drop async control signals in abc_map.v | Eddie Hung | 2019-11-19 | 1 | -12/+16 | |
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| * | | | Add blackbox model for $__ABC9_FF_ so that clock partitioning works | Eddie Hung | 2019-11-20 | 1 | -0/+3 | |
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| * | | | Fix INIT values | Eddie Hung | 2019-11-20 | 1 | -4/+4 | |
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| * | | Merge remote-tracking branch 'origin/master' into xaig_dff | Eddie Hung | 2019-11-19 | 41 | -23094/+31993 | |
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| | * | Merge pull request #1449 from pepijndevos/gowin | Clifford Wolf | 2019-11-19 | 8 | -43/+547 | |
| | |\ | | | | | | | Improvements for gowin support | |||||
| | | * | Remove dff init altogether | Pepijn de Vos | 2019-11-19 | 2 | -3/+3 | |
| | | | | | | | | | | | | | | | | The hardware does not actually support it. In reality it is always initialised to its reset value. | |||||
| | | * | add help for nowidelut and abc9 options | Pepijn de Vos | 2019-11-18 | 1 | -1/+7 | |
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| | | * | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-16 | 4 | -15/+439 | |
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| | | * | | fix fsm test with proper clock enable polarity | Pepijn de Vos | 2019-11-11 | 1 | -4/+4 | |
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| | | * | | Merge branch 'master' of https://github.com/YosysHQ/yosys into gowin | Pepijn de Vos | 2019-11-11 | 22 | -22988/+30572 | |
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| | | * | | | fix wide luts | Pepijn de Vos | 2019-11-06 | 1 | -12/+12 | |
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| | | * | | | add IOBUF | Pepijn de Vos | 2019-10-28 | 2 | -1/+10 | |
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| | | * | | | add tristate buffer and test | Pepijn de Vos | 2019-10-28 | 2 | -2/+8 | |
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| | | * | | | More formatting | Pepijn de Vos | 2019-10-28 | 1 | -55/+49 | |
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| | | * | | | really really fix formatting maybe | Pepijn de Vos | 2019-10-28 | 1 | -41/+41 | |
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| | | * | | | undo formatting fuckup | Pepijn de Vos | 2019-10-28 | 1 | -25/+25 | |
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| | | * | | | add wide luts | Pepijn de Vos | 2019-10-28 | 3 | -36/+119 | |
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| | | * | | | add 32-bit BRAM and byte-enables | Pepijn de Vos | 2019-10-28 | 2 | -4/+25 | |
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index : iCE40/yosys | |
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