| Commit message (Expand) | Author | Age | Files | Lines |
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| | * | | | | Rename to abc_*.{box,lut} | Eddie Hung | 2019-04-18 | 6 | -0/+0 |
| | * | | | | Update Makefile.inc too | Eddie Hung | 2019-04-17 | 1 | -4/+6 |
| | * | | | | Reduce to three devices: hx, lp, u | Eddie Hung | 2019-04-17 | 7 | -4/+23 |
| | * | | | | Add up5k timings | Eddie Hung | 2019-04-17 | 2 | -0/+19 |
| | * | | | | Fix grammar | Eddie Hung | 2019-04-17 | 1 | -2/+2 |
| | * | | | | Update error message | Eddie Hung | 2019-04-17 | 1 | -1/+1 |
| | * | | | | Add "-device" argument to synth_ice40 | Eddie Hung | 2019-04-17 | 4 | -7/+20 |
| | * | | | | Missing abc_flop_q attribute on SPRAM | Eddie Hung | 2019-04-17 | 1 | -1/+1 |
| | * | | | | Map to SB_LUT4 from fastest input first | Eddie Hung | 2019-04-17 | 1 | -7/+11 |
| | * | | | | Mark seq output ports with "abc_flop_q" attr | Eddie Hung | 2019-04-17 | 1 | -24/+24 |
| | * | | | | Also update Makefile.inc | Eddie Hung | 2019-04-17 | 1 | -3/+3 |
| | * | | | | synth_ice40 to use renamed files | Eddie Hung | 2019-04-17 | 1 | -2/+2 |
| | * | | | | Rename to abc.* | Eddie Hung | 2019-04-17 | 3 | -0/+0 |
| | * | | | | Revert "Try using an ICE40_CARRY_LUT primitive to avoid ABC issues" | Eddie Hung | 2019-04-17 | 7 | -102/+35 |
| | * | | | | Try using an ICE40_CARRY_LUT primitive to avoid ABC issues | Eddie Hung | 2019-04-17 | 7 | -35/+102 |
| | * | | | | Fix spacing | Eddie Hung | 2019-04-17 | 1 | -5/+5 |
| | * | | | | Add SB_LUT4 to box library | Eddie Hung | 2019-04-16 | 3 | -0/+16 |
| | * | | | | Add ice40 box files | Eddie Hung | 2019-04-16 | 6 | -1/+27 |
| * | | | | | Merge remote-tracking branch 'origin/xc7srl' into xc7mux | Eddie Hung | 2019-04-22 | 17 | -52/+694 |
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| | * | | | | Update help message | Eddie Hung | 2019-04-22 | 1 | -1/+1 |
| | * | | | | Move 'shregmap -tech xilinx' into map_cells | Eddie Hung | 2019-04-22 | 1 | -17/+20 |
| | * | | | | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-04-22 | 12 | -21/+480 |
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| | | * | | | Merge pull request #941 from Wren6991/sim_lib_io_clke | Clifford Wolf | 2019-04-22 | 1 | -10/+19 |
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| | | | * | | | ice40 cells_sim.v: SB_IO: update clock enable behaviour based on hardware exp... | Luke Wren | 2019-04-21 | 1 | -10/+19 |
| | | * | | | | Merge branch 'master' of https://github.com/dh73/yosys_gowin into dh73-master | Clifford Wolf | 2019-04-22 | 10 | -10/+458 |
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| | | | * | | | | GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow | Diego | 2019-04-12 | 10 | -11/+459 |
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| | | * | | | | Re-added clean after techmap in synth_xilinx | Clifford Wolf | 2019-04-22 | 1 | -0/+2 |
| | | * | | | | Merge pull request #916 from YosysHQ/map_cells_before_map_luts | Clifford Wolf | 2019-04-22 | 1 | -10/+10 |
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| | | * \ \ \ \ | Merge pull request #911 from mmicko/gowin-nobram | Clifford Wolf | 2019-04-22 | 1 | -1/+1 |
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| | | | * | | | | Make nobram false by default for gowin | Miodrag Milanovic | 2019-04-02 | 1 | -1/+1 |
| | * | | | | | | Tidy up, fix for -nosrl | Eddie Hung | 2019-04-21 | 2 | -12/+16 |
| | * | | | | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-21 | 1 | -2/+2 |
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| | | * | | | | | Merge branch 'master' into map_cells_before_map_luts | Eddie Hung | 2019-04-21 | 6 | -59/+85 |
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| | * | | | | | | Add comments | Eddie Hung | 2019-04-21 | 1 | -0/+7 |
| | * | | | | | | Use new pmux2shiftx from #944, remove my old attempt | Eddie Hung | 2019-04-21 | 1 | -3/+8 |
| | * | | | | | | Merge remote-tracking branch 'origin' into xc7srl | Eddie Hung | 2019-04-20 | 4 | -44/+69 |
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| | | * | | | | | Revert "synth_* with -retime option now calls abc with -D 1 as well" | Eddie Hung | 2019-04-18 | 11 | -15/+15 |
| | | * | | | | | Merge branch 'master' into eddie/fix_retime | Eddie Hung | 2019-04-18 | 4 | -44/+69 |
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| | | * | | | | | synth_* with -retime option now calls abc with -D 1 as well | Eddie Hung | 2019-04-10 | 11 | -15/+15 |
| | * | | | | | | Call shregmap twice -- once for variable, another for fixed | Eddie Hung | 2019-04-05 | 2 | -8/+14 |
| | * | | | | | | Move dffinit til after abc | Eddie Hung | 2019-04-05 | 3 | -2/+2 |
| | * | | | | | | Merge branch 'eddie/fix_retime' into xc7srl | Eddie Hung | 2019-04-05 | 4 | -11/+12 |
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| | | * | | | | | Move techamp t:$_DFF_?N? to before abc call | Eddie Hung | 2019-04-05 | 1 | -2/+2 |
| | | * | | | | | Retry | Eddie Hung | 2019-04-05 | 1 | -1/+1 |
| | | * | | | | | Resolve @daveshah1 comment, update synth_xilinx help | Eddie Hung | 2019-04-05 | 2 | -7/+9 |
| | | * | | | | | synth_xilinx to techmap FFs after abc call, otherwise -retime fails | Eddie Hung | 2019-04-05 | 1 | -3/+3 |
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| | * | | | | | techmap inside map_cells stage | Eddie Hung | 2019-04-05 | 2 | -2/+1 |
| | * | | | | | Merge branch 'map_cells_before_map_luts' into xc7srl | Eddie Hung | 2019-04-04 | 1 | -0/+1 |
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| | | * | | | | Missing techmap entry in help | Eddie Hung | 2019-04-04 | 1 | -0/+1 |
| | * | | | | | Use soft-logic, not LUT3 instantiation | Eddie Hung | 2019-04-04 | 1 | -4/+2 |
