| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| | * | Move neg-pol to pos-pol mapping from ff_map to cells_map.v | Eddie Hung | 2019-04-28 | 1 | -0/+8 | |
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| * | | Fix spacing | Eddie Hung | 2019-04-26 | 1 | -4/+4 | |
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| * | | Try a different approach with 'muxcover' | Eddie Hung | 2019-04-26 | 1 | -67/+15 | |
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| * | | Cleanup superseded | Eddie Hung | 2019-04-25 | 1 | -11/+1 | |
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| * | | Tweak | Eddie Hung | 2019-04-22 | 1 | -1/+1 | |
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| * | | Fix for A_WIDTH == 2 but B_WIDTH==3 | Eddie Hung | 2019-04-22 | 1 | -1/+1 | |
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| * | | Trim A_WIDTH by Y_WIDTH-1 | Eddie Hung | 2019-04-22 | 1 | -1/+1 | |
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| * | | Add comment | Eddie Hung | 2019-04-22 | 1 | -0/+3 | |
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| * | | Fix for mux_case_* mappings | Eddie Hung | 2019-04-22 | 1 | -17/+9 | |
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| * | | Fix for non-pow2 width muxes | Eddie Hung | 2019-04-22 | 1 | -9/+18 | |
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| * | | Add synth_xilinx -nomux option | Eddie Hung | 2019-04-22 | 1 | -0/+2 | |
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| * | | Merge remote-tracking branch 'origin/xc7srl' into xc7mux | Eddie Hung | 2019-04-22 | 1 | -0/+125 | |
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| | * | Call shregmap twice -- once for variable, another for fixed | Eddie Hung | 2019-04-05 | 1 | -0/+3 | |
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| | * | techmap inside map_cells stage | Eddie Hung | 2019-04-05 | 1 | -1/+0 | |
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| | * | Use soft-logic, not LUT3 instantiation | Eddie Hung | 2019-04-04 | 1 | -4/+2 | |
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| | * | Cleanup comments | Eddie Hung | 2019-04-04 | 1 | -5/+4 | |
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| | * | Fine tune cells_map.v | Eddie Hung | 2019-03-20 | 1 | -19/+15 | |
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| | * | Revert $__SHREG_ to orig; use $__XILINX_SHREG for variable length | Eddie Hung | 2019-03-19 | 1 | -53/+20 | |
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| | * | Add support for variable length Xilinx SRL > 128 | Eddie Hung | 2019-03-19 | 1 | -11/+67 | |
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| | * | Fix spacing | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
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| | * | Fix INIT for variable length SRs that have been bumped up one | Eddie Hung | 2019-03-19 | 1 | -1/+1 | |
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| | * | Only accept <128 for variable length, only if $shiftx exclusive | Eddie Hung | 2019-03-16 | 1 | -5/+1 | |
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| | * | Cleanup synth_xilinx | Eddie Hung | 2019-03-15 | 1 | -1/+1 | |
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| | * | Working | Eddie Hung | 2019-03-15 | 1 | -40/+69 | |
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| | * | Reverse bits in INIT parameter for Xilinx, since MSB is shifted first | Eddie Hung | 2019-03-14 | 1 | -16/+32 | |
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| | * | Merge remote-tracking branch 'origin/master' into xc7srl | Eddie Hung | 2019-03-14 | 1 | -86/+18 | |
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| | * | | Fix cells_map for SRL | Eddie Hung | 2019-03-14 | 1 | -19/+17 | |
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| | * | | Refactor $__SHREG__ in cells_map.v | Eddie Hung | 2019-03-13 | 1 | -32/+24 | |
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| | * | | Fix SRL16/32 techmap off-by-one | Eddie Hung | 2019-02-28 | 1 | -18/+24 | |
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| | * | | synth_xilinx to call shregmap with enable support | Eddie Hung | 2019-02-28 | 1 | -23/+28 | |
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| | * | | synth_xilinx to use shregmap with -params too | Eddie Hung | 2019-02-28 | 1 | -21/+18 | |
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| | * | | Add techmap rule for $__SHREG_DFF_P_ to SRL16/32 | Eddie Hung | 2019-02-28 | 1 | -0/+71 | |
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| * | | | Fix cells_map.v some more | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
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| * | | | More fine tuning | Eddie Hung | 2019-04-11 | 1 | -2/+2 | |
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| * | | | Fix cells_map.v | Eddie Hung | 2019-04-11 | 1 | -7/+7 | |
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| * | | | Fix typo | Eddie Hung | 2019-04-11 | 1 | -1/+1 | |
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| * | | | Juggle opt calls in synth_xilinx | Eddie Hung | 2019-04-11 | 1 | -27/+32 | |
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| * | | | WIP for cells_map.v -- maybe working? | Eddie Hung | 2019-04-10 | 1 | -32/+27 | |
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| * | | | Try splitting $shiftx with Y_WIDTH > 1 into Y_WIDTH = 1 | Eddie Hung | 2019-04-10 | 1 | -31/+38 | |
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| * | | | Fix for when B_SIGNED = 1 | Eddie Hung | 2019-04-10 | 1 | -1/+8 | |
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| * | | | Tidy up | Eddie Hung | 2019-04-10 | 1 | -1/+1 | |
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| * | | | WIP for $shiftx to wide mux | Eddie Hung | 2019-04-10 | 1 | -1/+63 | |
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| * | | Changes required for VPR place and route synth_xilinx. | Keith Rothman | 2019-03-01 | 1 | -85/+19 | |
| |/ | | | | Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com> | |||||
| * | Improving vpr output support. | Tim 'mithro' Ansell | 2018-04-18 | 1 | -0/+2 | |
| | | | | | | | | * Support output BLIF for Xilinx architectures. * Support using .names in BLIF for Xilinx architectures. * Use the same `NO_LUT` define in both `synth_ice40` and `synth_xilinx`. | |||||
| * | Various cleanups in xilinx techlib | Clifford Wolf | 2015-01-18 | 1 | -0/+84 | |
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index : iCE40/yosys | |
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