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path: root/techlibs/intel/synth_intel.cc

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fix formatting for synth_intel.cc	Ben Widawsky	2019-05-09	1	-222/+211
\| \| \| \| \| \|	This is realized through the recently added .clang-format file. Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
*	Unify usage of noflatten among architectures	Miodrag Milanovic	2019-01-04	1	-2/+2
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*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-6/+6
\| \| \| \| \| \| \| \| \|	o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -- c++ -- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
*	Add "synth_intel --noiopads"	Clifford Wolf	2018-04-30	1	-2/+11
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Fixed broken Quartus backend on dffeas init value (Error (12170): Illegal ↵	c60k28	2018-03-31	1	-4/+23
\| \| \| \|	value for the POWER_UP parameter. Fixed and tested Cyclone V device
*	Add "dffinit -highlow" and fix synth_intel	Clifford Wolf	2018-01-09	1	-1/+1
\| \| \| \|	Signed-off-by: Clifford Wolf <clifford@clifford.at>
*	Initial Cyclone 10 support	dh73	2017-11-08	1	-1/+5
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*	Clean whitespace and permissions in techlibs/intel	Larry Doolittle	2017-10-05	1	-3/+3
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*	Rename "write_verilog -nobasenradix" to "write_verilog -decimal"	Clifford Wolf	2017-10-03	1	-4/+1
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*	Adding Cyclone IV (E, GX), Arria 10, Cyclone V and LPM functions (ALTPLL and ↵	dh73	2017-10-01	1	-0/+241
	M9K); M9K is not finished yet. Achronix Speedster also in this commit. Both Arria10 and Speedster-i are still experimental due complexity, but you can experiment around those devices right now

re for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * --- * * The Verilog frontend. * * This frontend is using the AST frontend library (see frontends/ast/). * Thus this frontend does not generate RTLIL code directly but creates an * AST directly from the Verilog parse tree and then passes this AST to * the AST frontend library. * */ #ifndef VERILOG_FRONTEND_H #define VERILOG_FRONTEND_H #include "kernel/rtlil.h" #include "frontends/ast/ast.h" #include <stdio.h> #include <stdint.h> #include <list> namespace VERILOG_FRONTEND { // this variable is set to a new AST_DESIGN node and then filled with the AST by the bison parser extern struct AST::AstNode *current_ast; // this function converts a Verilog constant to an AST_CONSTANT node AST::AstNode *const2ast(std::string code, char case_type = 0); // state of `default_nettype extern bool default_nettype_wire; } // the pre-processor std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs); // the usual bison/flex stuff extern int frontend_verilog_yydebug; int frontend_verilog_yylex(void); void frontend_verilog_yyerror(char const *fmt, ...); void frontend_verilog_yyrestart(FILE *f); int frontend_verilog_yyparse(void); int frontend_verilog_yylex_destroy(void); int frontend_verilog_yyget_lineno(void); void frontend_verilog_yyset_lineno (int); #endif