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path: root/techlibs/greenpak4/cells_sim.v
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* Refactoring: moved modules still in cells_sim to cells_sim_wipAndrew Zonenberg2017-09-011-136/+1
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* Fixed bug causing GP_SPI model to not synthesizeAndrew Zonenberg2017-08-271-2/+2
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* Finished initial GP_COUNT8/14/8_ADV/14_ADV sim models. Don't support clock ↵Andrew Zonenberg2017-08-141-37/+0
| | | | divide, but do everything else.
* Improved cells_sim_digital model for GP_COUNT8Andrew Zonenberg2017-08-141-39/+0
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* Refactored GreenPAK4 cells_sim into cells_sim_ams and cells_sim_digitalAndrew Zonenberg2017-08-141-428/+3
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* greenpak4: Added POUT to GP_COUNTx cellsAndrew Zonenberg2017-01-011-3/+4
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* greenpak4: Added INT pin to GP_SPIAndrew Zonenberg2016-12-211-1/+3
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* greenpak4: removed unused MISO pin from GP_SPIAndrew Zonenberg2016-12-211-1/+0
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* greenpak4: Removed SPI_BUFFER parameterAndrew Zonenberg2016-12-201-1/+0
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* greenpak4: replaced MOSI/MISO with single one-way SDAT pinAndrew Zonenberg2016-12-201-2/+1
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* greenpak4: Changed port names on GP_SPI for clarityAndrew Zonenberg2016-12-201-4/+4
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* greenpak4: Initial implementation of GP_SPI cellAndrew Zonenberg2016-12-201-0/+27
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* greenpak4: Updated GP_DCMP cell modelAndrew Zonenberg2016-12-171-2/+20
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* greenpak: Fixes to GP_DCMP* blocks. Added GP_CLKBUF.Andrew Zonenberg2016-12-161-5/+10
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* greenpak4: Initial version of GP_DCMP skeleton (not yet usable). Changed ↵Andrew Zonenberg2016-12-151-5/+24
| | | | interface to GP_DCMPMUX
* greenpak4: More fixups of GP_DCMPx cellsAndrew Zonenberg2016-12-151-9/+3
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* greenpak4: And another typo :(Andrew Zonenberg2016-12-151-1/+1
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* greenpak4: Fixed another typoAndrew Zonenberg2016-12-151-1/+1
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* greenpak4: Fixed typoAndrew Zonenberg2016-12-151-1/+1
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* greenpak4: Cleaned up trailing spaces in cells_simAndrew Zonenberg2016-12-141-60/+60
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* greenpak4: Added GP_DCMPREF / GP_DCMPMUXAndrew Zonenberg2016-12-141-0/+23
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* Added GP_PWRDET block, BANDWIDTH_KHZ parameter to GP_ABUFAndrew Zonenberg2016-12-111-1/+9
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* greenpak4: Inverted D latch cells now have nQ instead of Q as output port ↵Andrew Zonenberg2016-12-101-15/+15
| | | | name for consistency
* Added GP_DLATCH and GP_DLATCHIAndrew Zonenberg2016-12-051-0/+18
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* Initial implementation of techlib support for GreenPAK latches. ↵Andrew Zonenberg2016-12-051-0/+68
| | | | Instantiation only, no behavioral inference yet.
* Fixed typo in last commitAndrew Zonenberg2016-10-181-1/+1
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* greenpak4: Added GP_PGEN cell definitionAndrew Zonenberg2016-10-181-0/+21
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* Added GLITCH_FILTER parameter to GP_DELAYAndrew Zonenberg2016-10-181-3/+2
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* greenpak4: added model for GP_EDGEDET blockAndrew Zonenberg2016-10-181-0/+10
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* greenpak4: Changed parameters for GP_SYSRESETAndrew Zonenberg2016-10-161-1/+2
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* greenpak4: Changed name of inverted output ports for consistencyAndrew Zonenberg2016-08-141-15/+15
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* greenpak4: Added GP_DFFxI cellsAndrew Zonenberg2016-08-141-0/+42
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* greenpak4: Renamed ports for better consistency (see azonenberg/openfpga:#6)Andrew Zonenberg2016-08-131-10/+10
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* Added GP_DAC cellAndrew Zonenberg2016-07-111-0/+8
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* Removed VOUT port of GP_BANDGAPAndrew Zonenberg2016-07-111-1/+1
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* greenpak4: add GP_COUNT{8,14}_ADV cells.whitequark2016-07-101-0/+26
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* Added GP_DELAY cellAndrew Zonenberg2016-05-071-0/+29
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* Fixed typo in port nameAndrew Zonenberg2016-05-071-1/+1
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* Fixed extra semicolonAndrew Zonenberg2016-05-071-1/+1
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* Fixed typo in parameter nameAndrew Zonenberg2016-05-071-1/+1
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* Added simulation timescale declarationAndrew Zonenberg2016-05-071-0/+2
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* Renamed module parameterAndrew Zonenberg2016-05-041-4/+4
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* Fixed incorrect signal naming in GP_IOBUFAndrew Zonenberg2016-05-041-2/+2
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* Added tri-state I/O extraction for GreenPakAndrew Zonenberg2016-05-031-2/+2
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* Added GreenPak I/O buffer cellsAndrew Zonenberg2016-05-031-0/+17
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* Added comment to clarify GP_ABUF cellAndrew Zonenberg2016-05-021-0/+2
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* Added GP_ABUF cellAndrew Zonenberg2016-05-021-0/+6
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* Added GP_PGA cellAndrew Zonenberg2016-04-271-0/+11
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* Removed VIN_BUF_ENAndrew Zonenberg2016-04-241-1/+0
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* Renamed VOUT to OUT on GP_ACMP cellAndrew Zonenberg2016-04-231-1/+3
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