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* coolrunner2: Attempt to give wires/cells more meaningful namesR. Ou2020-03-022-23/+66
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* coolrunner2: Fix invalid multiple fanouts of XOR/OR gatesR. Ou2020-03-021-0/+96
| | | | | | | | | | | | | | | | | | | | | | | In some cases where multiple output pins share identical combinatorial logic, yosys would only generate one $sop cell and therefore one MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid, so make the fixup pass duplicate cells when necessary. For example, fixes the following code: module top(input a, input b, input clk_, output reg o, output o2); wire clk; BUFG bufg0 ( .I(clk_), .O(clk), ); always @(posedge clk) o = a ^ b; assign o2 = a ^ b; endmodule
* coolrunner2: Fix packed register+input buffer insertionR. Ou2020-03-021-2/+84
| | | | | The register will be packed with the input buffer if and only if the input buffer doesn't have any other loads.
* coolrunner2: Insert many more required feedthrough cellsR. Ou2020-03-013-102/+215
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* Merge pull request #1709 from rqou/coolrunner2_counterClaire Wolf2020-02-273-0/+165
|\ | | | | Improve CoolRunner-II optimization by using extract_counter pass
| * coolrunner2: Use extract_counter to optimize countersR. Ou2020-02-173-0/+165
| | | | | | | | | | This tends to make much more efficient pterm usage compared to just throwing the problem at ABC
* | coolrunner2: Separate and improve buffer cell insertion passR. Ou2020-02-164-54/+163
|/ | | | | | | The new pass will contain all of the logic for inserting "passthrough" product term and XOR cells as appropriate for the architecture. For example, this commit fixes connecting an input pin directly to another output pin with no logic in between.
* synth_*: call 'opt -fast' after 'techmap'Eddie Hung2020-02-051-2/+2
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* Update doc that "-retime" calls abc with "-dff -D 1"Eddie Hung2019-12-301-1/+1
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* Revert "Revert "synth_* with -retime option now calls abc with -D 1 as well""Eddie Hung2019-12-301-1/+1
| | | | This reverts commit 6008bb7002f874e5c748eaa2050e7b6c17b32745.
* coolrunner2: remove spurious log_pop() call, fixes #1463Martin Pietryka2019-11-231-2/+0
| | | | | | | This was causing a segmentation fault because there is no accompanying log_push() call so header_count.size() became -1. Signed-off-by: Martin Pietryka <martin@pietryka.at>
* Fix spacingEddie Hung2019-08-061-3/+3
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* Make liberal use of IdString.in()Eddie Hung2019-08-061-14/+8
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* Unify usage of noflatten among architecturesMiodrag Milanovic2019-01-041-1/+1
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* Fix typographical and grammatical errors and inconsistencies.whitequark2019-01-021-1/+1
| | | | | | | | | | | | The initial list of hits was generated with the codespell command below, and each hit was evaluated and fixed manually while taking context into consideration. DIRS="kernel/ frontends/ backends/ passes/ techlibs/" DIRS="${DIRS} libs/ezsat/ libs/subcircuit" codespell $DIRS -S *.o -L upto,iff,thru,synopsys,uint More hits were found by looking through comments and strings manually.
* Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-202-6/+6
| | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established)
* coolrunner2: Add an ANDTERM/XOR between chained FFsRobert Ou2018-03-311-0/+58
| | | | | | | In some cases (e.g. the low bits of counters) the design might end up with a flip-flop whose input is directly driven by another flip-flop. This isn't possible in the Coolrunner-II architecture, so add a single AND term and XOR in this case.
* coolrunner2: Split multi-bit netsRobert Ou2018-03-311-0/+1
| | | | | The PAR tool doesn't expect any "dangling" nets with no drivers nor sinks. By splitting the nets, clean removes them.
* coolrunner2: Add extraction for TFFsRobert Ou2018-03-313-0/+54
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* coolrunner2: Move LOC attributes onto the IO cellsRobert Ou2018-01-171-0/+2
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* coolrunner2: Finish fixing special-use p-termsRobert Ou2017-09-011-8/+20
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* coolrunner2: Generate a feed-through AND term when necessaryRobert Ou2017-09-011-13/+31
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* coolrunner2: Initial fixes for special p-termsRobert Ou2017-09-012-1/+81
| | | | | Certain signals can only be controlled by a product term and not a sum-of-products. Do the initial work for fixing this.
* coolrunner2: Fix mapping of flip-flopsRobert Ou2017-09-011-1/+0
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* coolrunner2: Combine some for loops togetherRobert Ou2017-09-011-16/+14
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* coolrunner2: Add INVERT parameter to some BUFGsRobert Ou2017-08-141-2/+6
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* coolrunner2: Add FFs with clock enable to cells_sim.vRobert Ou2017-08-141-0/+60
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* Fix some c++ clang compiler errorsClifford Wolf2017-07-031-3/+3
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* Apply minor coding style changes to coolrunner2 targetClifford Wolf2017-07-032-1/+1
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* coolrunner2: Add a few more primitivesRobert Ou2017-06-251-0/+110
| | | | These cannot be inferred yet, but add them to cells_sim.v for now
* coolrunner2: Initial mapping of latchesRobert Ou2017-06-254-0/+63
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* coolrunner2: Initial mapping of DFFsRobert Ou2017-06-254-0/+76
| | | | | All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)
* coolrunner2: Remove redundant INVERT_PTCRobert Ou2017-06-252-4/+1
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* coolrunner2: Remove debug printsRobert Ou2017-06-251-2/+0
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* coolrunner2: Correctly handle $_NOT_ after $sopRobert Ou2017-06-251-5/+41
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* coolrunner2: Also construct the XOR cell in the macrocellRobert Ou2017-06-252-7/+34
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* coolrunner2: Initial techmapping for $sopRobert Ou2017-06-254-153/+268
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* coolrunner2: Initial commitRobert Ou2017-06-243-0/+223
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