iCE40/yosys - clone of https://github.com/YosysHQ/yosys

	Commit message (Collapse)	Author	Age	Files	Lines
*	coolrunner2: Initial mapping of latches	Robert Ou	2017-06-25	4	-0/+63
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*	coolrunner2: Initial mapping of DFFs	Robert Ou	2017-06-25	4	-0/+76
\| \| \| \| \|	All DFFs map to either FDCP (matches Xilinx) or a custom FDCP_N (negative-edge triggered)
*	coolrunner2: Remove redundant INVERT_PTC	Robert Ou	2017-06-25	2	-4/+1
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*	coolrunner2: Remove debug prints	Robert Ou	2017-06-25	1	-2/+0
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*	coolrunner2: Correctly handle $_NOT_ after $sop	Robert Ou	2017-06-25	1	-5/+41
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*	coolrunner2: Also construct the XOR cell in the macrocell	Robert Ou	2017-06-25	2	-7/+34
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*	coolrunner2: Initial techmapping for $sop	Robert Ou	2017-06-25	4	-153/+268
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*	coolrunner2: Initial commit	Robert Ou	2017-06-24	3	-0/+223