| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | gate2lut: new techlib, for converting Yosys gates to FPGA LUTs. | whitequark | 2018-12-05 | 1 | -0/+1 |
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| * | Add dff2ff.v techmap file | Clifford Wolf | 2017-05-31 | 1 | -0/+1 |
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| * | Added "prep" command | Clifford Wolf | 2015-10-14 | 1 | -0/+1 |
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| * | Added first help messages for cell types | Clifford Wolf | 2015-10-14 | 1 | -0/+15 |
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| * | Adjust makefiles to work with out-of-tree builds | Clifford Wolf | 2015-08-12 | 1 | -7/+0 |
| | | | | | This is based on work done by Larry Doolittle | ||||
| * | Added cells.lib | Clifford Wolf | 2015-01-16 | 1 | -0/+1 |
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| * | Added add_share_file Makefile macro | Clifford Wolf | 2015-01-08 | 1 | -25/+6 |
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| * | Fixed build with SMALL=1 | Clifford Wolf | 2014-12-30 | 1 | -0/+2 |
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| * | Added "synth" command | Clifford Wolf | 2014-09-14 | 1 | -0/+2 |
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| * | Added adff2dff.v (for techmap -share_map) | Clifford Wolf | 2014-08-07 | 1 | -1/+5 |
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| * | Renamed "stdcells.v" to "techmap.v" | Clifford Wolf | 2014-07-31 | 1 | -1/+5 |
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| * | Added "make PRETTY=1" | Clifford Wolf | 2014-07-24 | 1 | -10/+10 |
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| * | Merged addition of SED makefile variable from github.com/Siesh1oo/yosys | Clifford Wolf | 2014-03-11 | 1 | -1/+1 |
| | | | | | (see https://github.com/cliffordwolf/yosys/pull/28) | ||||
| * | Added techlibs/common/pmux2mux.v | Clifford Wolf | 2014-01-17 | 1 | -1/+5 |
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| * | Renamed stdcells_sim.v to simcells.v and fixed blackbox.v | Clifford Wolf | 2013-11-24 | 1 | -3/+11 |
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| * | Install simlib in datdir | Clifford Wolf | 2013-11-19 | 1 | -0/+6 |
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| * | Moved common techlib files to techlibs/common | Clifford Wolf | 2013-09-15 | 1 | -0/+7 |
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index : iCE40/yosys | |
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