| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Leave only real black box cells | Miodrag Milanovic | 2018-12-02 | 1 | -312/+0 |
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| * | Initial support for Anlogic FPGA | Miodrag Milanovic | 2018-12-01 | 7 | -0/+1590 |
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index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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