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As the TD tool doesn't accept the DRAM cell to contain unknown values in
the initial value, the initialzation support of DRAM is previously
skipped.
Now add the support by add a new pass to determine unknown values in the
initial value.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.
Fix the dbits number in the RAM configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.
Enable to synthesis to DRAM.
As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
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