| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Merge pull request #1344 from YosysHQ/eddie/ice40_signed_macc | Eddie Hung | 2019-09-01 | 1 | -5/+0 |
| |\ | | | | | ice40_dsp to allow signed multipliers | ||||
| | * | Do not restrict multiplier to unsigned | Eddie Hung | 2019-08-30 | 1 | -5/+0 |
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| * | | Fix select command error msg, fixes issue #1081 | Miodrag Milanovic | 2019-09-01 | 1 | -2/+2 |
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| * | | Missing dep for test_pmgen | Eddie Hung | 2019-08-30 | 1 | -1/+1 |
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| * | | Merge pull request #1340 from YosysHQ/eddie/abc_no_clean | Eddie Hung | 2019-08-30 | 1 | -16/+10 |
| |\ \ | |/ |/| | abc9 to not call "clean" at end of run (often called outside) | ||||
| | * | Output has priority over input when stitching in abc9 | Eddie Hung | 2019-08-29 | 1 | -13/+10 |
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| | * | abc9 to not call "clean" at end of run (often called outside) | Eddie Hung | 2019-08-29 | 1 | -3/+0 |
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| * | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-30 | 2 | -2/+37 |
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| | * | Fix typo that's gone unnoticed for 5 months!?! | Eddie Hung | 2019-08-29 | 1 | -1/+1 |
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| | * | Merge pull request #1334 from YosysHQ/clifford/async2synclatch | Eddie Hung | 2019-08-28 | 1 | -1/+36 |
| | |\ | | | | | | | Add $dlatch support to async2sync | ||||
| | | * | Add $dlatch support to async2sync | Clifford Wolf | 2019-08-28 | 1 | -1/+36 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | | Cleanup | Eddie Hung | 2019-08-28 | 1 | -4/+0 |
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| * | | | Account for D port being a constant | Eddie Hung | 2019-08-28 | 1 | -4/+4 |
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| * | | | No need to replace Q of slice since $shiftx is autoremove-d | Eddie Hung | 2019-08-28 | 1 | -1/+0 |
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| * | | | More cleanup | Eddie Hung | 2019-08-28 | 1 | -12/+14 |
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| * | | | More cleanup | Eddie Hung | 2019-08-28 | 1 | -9/+6 |
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| * | | | Do not use default_params dict, hardcode default values, cleanup | Eddie Hung | 2019-08-28 | 2 | -25/+21 |
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| * | | | Always generate if no match | Eddie Hung | 2019-08-28 | 1 | -1/+1 |
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| * | | | Rename test_pmgen arg xilinx_srl.{fixed,variable} | Eddie Hung | 2019-08-28 | 1 | -2/+2 |
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| * | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-28 | 5 | -89/+457 |
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| | * | | Fix typo | Clifford Wolf | 2019-08-28 | 1 | -2/+2 |
| | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | | Add "paramap" pass | Clifford Wolf | 2019-08-28 | 1 | -67/+118 |
| | |/ | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Merge pull request #1325 from YosysHQ/eddie/sat_init | Clifford Wolf | 2019-08-28 | 1 | -1/+1 |
| | |\ | | | | | | | In sat: 'x' in init attr should be ignored | ||||
| | | * | Ignore all 1'bx in (* init *) | Eddie Hung | 2019-08-27 | 1 | -3/+1 |
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| | | * | In sat: 'x' in init attr should not override constant | Eddie Hung | 2019-08-22 | 1 | -0/+2 |
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| | * | | improve clkbuf_inhibit propagation upwards through hierarchy | Marcin Kościelnicki | 2019-08-27 | 1 | -1/+12 |
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| | * | | Merge branch 'master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-26 | 4 | -32/+279 |
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| | | * | | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| | * | | | clkbufmap to only check clkbuf_inhibit if no selection given | Eddie Hung | 2019-08-23 | 1 | -5/+18 |
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| | * | | | Review comment from @cliffordwolf | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
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| | * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-23 | 48 | -768/+2262 |
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| | * | | | Merge remote-tracking branch 'origin/master' into mwk/xilinx_bufgmap | Eddie Hung | 2019-08-16 | 41 | -2157/+2152 |
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| | * | | | | move attributes to wires | Marcin Kościelnicki | 2019-08-13 | 2 | -28/+9 |
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| | * | | | | review fixes | Marcin Kościelnicki | 2019-08-13 | 2 | -29/+4 |
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| | * | | | | Add clock buffer insertion pass, improve iopadmap. | Marcin Kościelnicki | 2019-08-13 | 3 | -20/+356 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A few new attributes are defined for use in cell libraries: - iopad_external_pin: marks PAD cell's external-facing pin. Pad insertion will be skipped for ports that are already connected to such a pin. - clkbuf_sink: marks an input pin as a clock pin, requesting clock buffer insertion. - clkbuf_driver: marks an output pin as a clock buffer output pin. Clock buffer insertion will be skipped for nets that are already driven by such a pin. All three are module attributes that should be set to a comma-separeted list of pin names. Clock buffer insertion itself works as follows: 1. All cell ports, starting from bottom up, can be marked as clock sinks (requesting clock buffer insertion) or as clock buffer outputs. 2. If a wire in a given module is driven by a cell port that is a clock buffer output, it is in turn also considered a clock buffer output. 3. If an input port in a non-top module is connected to a clock sink in a contained cell, it is also in turn considered a clock sink. 4. If a wire in a module is driven by a non-clock-buffer cell, and is also connected to a clock sink port in a contained cell, a clock buffer is inserted in this module. 5. For the top module, a clock buffer is also inserted on input ports connected to clock sinks, optionally with a special kind of input PAD (such as IBUFG for Xilinx). 6. Clock buffer insertion on a given wire is skipped if the clkbuf_inhibit attribute is set on it. | ||||
| * | | | | | Missing close bracket | Eddie Hung | 2019-08-26 | 1 | -1/+1 |
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| * | | | | | Revert "In sat: 'x' in init attr should not override constant" | Eddie Hung | 2019-08-26 | 1 | -2/+0 |
| | | | | | | | | | | | | | | | | | | | | | This reverts commit 2b37a093e95036b267481b2dae2046278eef4040. | ||||
| * | | | | | Remove leftover header | Eddie Hung | 2019-08-26 | 1 | -1/+0 |
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| * | | | | | Improve xilinx_srl.fixed generate, add .variable generate | Eddie Hung | 2019-08-26 | 1 | -26/+75 |
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| * | | | | | Account for maxsubcnt overflowing | Eddie Hung | 2019-08-26 | 1 | -1/+1 |
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| * | | | | | Add xilinx_srl_pm.variable to test_pmgen | Eddie Hung | 2019-08-26 | 1 | -0/+2 |
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| * | | | | | Populate generate for xilinx_srl.fixed pattern | Eddie Hung | 2019-08-26 | 1 | -22/+54 |
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| * | | | | | Add xilinx_srl_fixed, fix typos | Eddie Hung | 2019-08-26 | 1 | -2/+6 |
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| * | | | | | Create new $__XILINX_SHREG_ cell for variable length too | Eddie Hung | 2019-08-23 | 1 | -31/+30 |
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| * | | | | | Do not allow Q of last cell of variable length SRL to be (* keep *) | Eddie Hung | 2019-08-23 | 1 | -0/+1 |
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| * | | | | | Also add first.Q to chain_bits since variable length | Eddie Hung | 2019-08-23 | 1 | -0/+1 |
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| * | | | | | Do not enforce !EN_POLARITY on $dffe | Eddie Hung | 2019-08-23 | 1 | -2/+0 |
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| * | | | | | Create new cell for fixed length SRL | Eddie Hung | 2019-08-23 | 1 | -14/+22 |
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| * | | | | | Cleanup FDRE matching | Eddie Hung | 2019-08-23 | 1 | -45/+19 |
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| * | | | | | Oops don't need a finally block | Eddie Hung | 2019-08-23 | 1 | -5/+0 |
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