aboutsummaryrefslogtreecommitdiffstats
path: root/passes
Commit message (Collapse)AuthorAgeFilesLines
* Merge pull request #2450 from nitz/sim-vcd-filenamewhitequark2020-11-251-1/+3
|\ | | | | Add rewrite_filename for sim -vcd argument.
| * Add rewrite_filename for sim -vcd argument.Chris Dailey2020-11-241-1/+3
| |
* | Merge pull request #2428 from whitequark/check-processeswhitequark2020-11-241-22/+55
|\ \ | |/ |/| check: add support for processes
| * check: add support for processes.whitequark2020-11-031-3/+38
| |
| * check: reformat log/help text to match most other passeswhitequark2020-11-031-19/+17
| |
* | Expose abc and data paths as globalsMiodrag Milanovic2020-11-062-29/+2
|/
* This patch adds support for defining the ABC location at runtime instead of ↵Ethan Mahintorabi2020-10-281-1/+6
| | | | | | at compile time. This is helpful in build systems like bazel which do not have stable locations for binaries or directories during the compilation phase. This change should be backwards compatible with the existing behavior.
* Merge pull request #2403 from nakengelhardt/sim_timescaleN. Engelhardt2020-10-221-0/+21
|\ | | | | sim -vcd: add date, version, and option for timescale
| * use strftime instead of put_time for gcc 4.8 compatibilityN. Engelhardt2020-10-211-4/+5
| |
| * wild guessing at the problem because it builds fine on my machinesN. Engelhardt2020-10-161-0/+3
| |
| * sim -vcd: add date, version, and option for timescaleN. Engelhardt2020-10-161-0/+17
| |
* | memory_dff: Fix needlessly duplicating enable bits.Marcelina Kościelnicka2020-10-221-0/+8
| | | | | | | | | | | | | | | | | | When the register being merged into the EN signal happens to be a $sdff, the current code creates a new $mux for every bit, even if they happen to be identical (as is usually the case), preventing proper grouping further down the flow. Fix this by adding a simple cache. Fixes #2409.
* | sim: Use Mem helper.Marcelina Kościelnicka2020-10-211-103/+90
| |
* | clk2fflogic: Use Mem helper.Marcelina Kościelnicka2020-10-211-68/+45
| |
* | opt_mem: Use Mem helpers.Marcelina Kościelnicka2020-10-211-81/+6
| |
* | memory_bram: Use Mem helpers.Marcelina Kościelnicka2020-10-211-121/+90
| |
* | memory_map: Use Mem helpers.Marcelina Kościelnicka2020-10-211-138/+81
| |
* | memory_unpack: Use Mem helpers.Marcelina Kościelnicka2020-10-211-106/+10
| |
* | memory_collect: Use Mem helpers.Marcelina Kościelnicka2020-10-211-223/+9
| |
* | memory_nordff: Use Mem helpers.Marcelina Kościelnicka2020-10-211-63/+9
|/
* opt_clean: Better memory handling.Marcelina Kościelnicka2020-10-081-8/+45
| | | | | | | | Previously, `$memwr` and `$meminit` cells were always preserved (along with the memory itself). With this change, they are instead part of the main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr` cells) is only preserved iff any associated `$memrd` cell needs to be preserved.
* Validate parameters only when they are usedMiodrag Milanovic2020-09-251-5/+7
|
* use the new isPublic() in a few placesN. Engelhardt2020-09-149-17/+17
|
* Merge pull request #2356 from whitequark/flatten-techmap-no-tpl_driven-sigmapwhitequark2020-08-272-9/+6
|\ | | | | flatten, techmap: don't canonicalize tpl driven bits via sigmap
| * flatten, techmap: don't canonicalize tpl driven bits via sigmap.whitequark2020-08-262-9/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For connection `assign a = b;`, `sigmap(a)` returns `b`. This is exactly the opposite of the desired canonicalization for driven bits. Consider the following code: module foo(inout a, b); assign a = b; endmodule module bar(output c); foo f(c, 1'b0); endmodule Before this commit, the inout ports would be swapped after flattening (and cause a crash while attempting to drive a constant value). This issue was introduced in 9f772eb9. Fixes #2183.
* | Merge pull request #2358 from whitequark/rename-ilang-to-rtlilwhitequark2020-08-277-24/+24
|\ \ | | | | | | Replace "ILANG" with "RTLIL" everywhere
| * | Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-267-24/+24
| |/ | | | | | | | | | | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* / dfflegalize: Fix decision tree for adffe.Marcelina Kościelnicka2020-08-271-1/+5
|/ | | | | | | | When an adffe is being legalized, and is not natively supported, prioritize unmapping to adff over converting to dffsre if dffsre is not natively supported itself. Fixes #2361.
* proc: Add -nomux switchPeder Bergebakken Sundt2020-08-201-1/+10
| | | | running proc -nomux will ommit the proc_mux pass
* Merge pull request #2344 from YosysHQ/mwk/opt_share-fixesclairexen2020-08-201-223/+138
|\ | | | | opt_share: Refactor, fix some bugs.
| * opt_share: Refactor, fix some bugs.Marcelina Kościelnicka2020-08-171-223/+138
| | | | | | | | | | | | Fixes #2334. Fixes #2335. Fixes #2336.
* | Merge pull request #2337 from YosysHQ/mwk/clean-keep-wireclairexen2020-08-201-4/+9
|\ \ | | | | | | opt_clean: Fix module keep rules.
| * | opt_clean: Fix module keep rules.Marcelina Kościelnicka2020-08-091-4/+9
| |/ | | | | | | | | | | - wires with keep attribute now force a module to be kept - presence of $memwr and $meminit cells no longer forces a module to be kept
* | Merge pull request #2333 from YosysHQ/mwk/peepopt-shiftmul-signedclairexen2020-08-201-5/+1
|\ \ | | | | | | peeopt.shiftmul: Add a signedness check.
| * | peeopt.shiftmul: Add a signedness check.Marcelina Kościelnicka2020-08-051-5/+1
| | | | | | | | | | | | Fixes #2332.
* | | Merge pull request #2328 from YosysHQ/mwk/opt_dff-cleanupclairexen2020-08-208-1468/+0
|\ \ \ | | | | | | | | Remove passes redundant with opt_dff
| * | | Remove now-redundant dff2dffe pass.Marcelina Kościelnicka2020-08-072-415/+0
| | | |
| * | | Remove now-redundant dff2dffs pass.Marcelina Kościelnicka2020-08-072-166/+0
| | | |
| * | | peepopt: Remove now-redundant dffmux pattern.Marcelina Kościelnicka2020-08-073-175/+0
| | | |
| * | | Remove now-redundant opt_rmdff pass.Marcelina Kościelnicka2020-08-072-712/+0
| | |/ | |/|
* | | Merge pull request #2327 from YosysHQ/mwk/techmap-constmap-fixclairexen2020-08-201-1/+22
|\ \ \ | | | | | | | | techmap.CONSTMAP: Handle outputs before inputs.
| * | | techmap.CONSTMAP: Handle outputs before inputs.Marcelina Kościelnicka2020-08-051-1/+22
| | |/ | |/| | | | | | | Fixes #2321.
* | | Merge pull request #2326 from YosysHQ/mwk/peeopt-muldiv-signclairexen2020-08-201-1/+4
|\ \ \ | | | | | | | | peepopt.muldiv: Add a signedness check.
| * | | peepopt.muldiv: Add a signedness check.Marcelina Kościelnicka2020-08-041-1/+4
| |/ / | | | | | | | | | Fixes #2318.
* | | Merge pull request #2319 from YosysHQ/mwk/techmap-celltype-patternclairexen2020-08-201-4/+32
|\ \ \ | | | | | | | | techmap: Add support for [] wildcards in techmap_celltype.
| * | | techmap: Add support for [] wildcards in techmap_celltype.Marcelina Kościelnicka2020-08-021-4/+32
| |/ / | | | | | | | | | Fixes #1826.
* | / Ensure \A_SIGNED is never used with $shiftxXiretza2020-08-181-0/+4
| |/ |/| | | | | | | It has no effect on the output ($shiftx doesn't perform any sign extension whatsoever), so an attempt to use it should be caught early.
* | Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-072-9/+17
|/
* Add dffunmap pass.Marcelina Kościelnicka2020-07-312-0/+108
| | | | | To be used with backends that cannot deal with fancy FF types (like blif or smt).
* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-312-14/+14
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-09 08:31:30 +0000