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* Merging attribute rules into a single match block; Adding testsDiego H2019-12-151-68/+80
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* Refactoring memory attribute matching based on IEEE 1364.1 and Tool specificDiego H2019-12-131-0/+77
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* Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attrEddie Hung2019-12-091-8/+67
|\ | | | | Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER
| * ice40_wrapcarry -unwrap to preserve 'src' attributeEddie Hung2019-12-091-1/+9
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| * -unwrap to create $lut not SB_LUT4 for opt_lutEddie Hung2019-12-091-7/+5
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| * Sensitive to direct inst of $__ICE40_CARRY_WRAPPER; recreate SB_LUT4Eddie Hung2019-12-091-7/+11
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| * ice40_wrapcarry to really preserve attributes via -unwrap optionEddie Hung2019-12-091-17/+55
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| * Drop keep=0 attributes on SB_CARRYEddie Hung2019-12-061-0/+8
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| * Merge SB_CARRY+SB_LUT4's attributes when creating $__ICE40_CARRY_WRAPPEREddie Hung2019-12-051-0/+1
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| * ice40_wrapcarry to preserve SB_CARRY's attributesEddie Hung2019-12-031-0/+2
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* | iopadmap: Refactor and fix tristate buffer mapping. (#1527)Marcin Kościelnicki2019-12-041-146/+97
|/ | | | | | | The previous code for rerouting wires when inserting tristate buffers was overcomplicated and didn't handle all cases correctly (in particular, only cell connections were rewired — internal connections were not).
* abc9: Fix breaking of SCCsDavid Shah2019-12-011-29/+40
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1536 from YosysHQ/eddie/xilinx_dsp_muladdEddie Hung2019-11-271-3/+3
|\ | | | | xilinx_dsp: consider sign and zero-extension when packing post-multiplier adder
| * Check for either sign or zero extension for postAdd packingEddie Hung2019-11-261-3/+3
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* | Merge pull request #1501 from YosysHQ/dave/mem_copy_attrClifford Wolf2019-11-271-0/+4
|\ \ | | | | | | memory_collect: Copy attr from RTLIL::Memory to cell
| * | memory_collect: Copy attr from RTLIL::Memory to cellDavid Shah2019-11-181-0/+4
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | opt_share: Fix handling of fine cells.Marcin Kościelnicki2019-11-271-4/+11
| |/ |/| | | | | Fixes #1525.
* | clkbufmap: Add support for inverters in clock path.Marcin Kościelnicki2019-11-251-0/+41
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* | Add "opt_mem" passClifford Wolf2019-11-223-0/+146
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | proc_dlatch: Add error handling for incorrect always_(ff|latch|comb) usageDavid Shah2019-11-211-4/+16
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix #1462, #1480.Marcin Kościelnicki2019-11-192-9/+11
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* Fix #1496.Marcin Kościelnicki2019-11-181-4/+8
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* Merge pull request #1492 from YosysHQ/dave/wreduce-fix-arstClifford Wolf2019-11-171-4/+10
|\ | | | | wreduce: Don't trim zeros or sext when not matching ARST_VALUE
| * wreduce: Don't trim zeros or sext when not matching ARST_VALUEDavid Shah2019-11-141-4/+10
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #1490 from YosysHQ/clifford/autonameClifford Wolf2019-11-142-0/+135
|\ \ | |/ |/| Add "autoname" pass and use it in "synth_ice40"
| * Add "autoname" pass and use it in "synth_ice40"Clifford Wolf2019-11-132-0/+135
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #1488 from whitequark/flowmap-fixeswhitequark2019-11-131-2/+3
|\ \ | |/ |/| flowmap: fix a few crashes
| * flowmap: when doing mincut, ensure source is always in X, not X̅.whitequark2019-11-121-1/+2
| | | | | | | | Fixes #1475.
| * flowmap: don't break if that creates a k+2 (and larger) LUT either.whitequark2019-11-111-1/+1
| | | | | | | | Fixes #1405.
* | Update fsm_detect bugfixClifford Wolf2019-11-121-3/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Bugfix in fsm_detectClifford Wolf2019-11-121-6/+9
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Makefile: don't assume python is called `python3`Sean Cross2019-10-191-2/+2
| | | | | | | | | | | | | | | | On some architectures, notably on Windows, the official name for the Python binary from python.org is `python`. The build system assumes that python is called `python3`, which breaks under this architecture. There is already infrastructure in place to determine the name of the Python binary when building PYOSYS. Since Python is now always required to build Yosys, enable this check universally which sets the `PYTHON_EXECUTABLE` variable. Then, reuse this variable in other Makefiles as necessary, rather than hardcoding `python3` everywhere. Signed-off-by: Sean Cross <sean@xobs.io>
* Fix dffmux peepopt init handlingClifford Wolf2019-10-162-27/+113
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Move GENERATE_PATTERN macro to separate utility headerClifford Wolf2019-10-163-128/+157
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Disable left-over log_debug in peepopt_dffmux.pmgClifford Wolf2019-10-161-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Revert "Be mindful that sigmap(wire) could have dupes when checking \init"Eddie Hung2019-10-081-4/+1
| | | | This reverts commit f46ac1df9f8847dac9d9851f2f948d93a1064ff1.
* Merge pull request #1432 from YosysHQ/eddie/fix1427Eddie Hung2019-10-082-48/+85
|\ | | | | Refactor peepopt_dffmux and be sensitive to \init when trimming
| * Fix broken CI, check reset even for constants, trim rstmuxEddie Hung2019-10-021-23/+26
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| * Merge branch 'eddie/fix_sat_init' into eddie/fix1427Eddie Hung2019-10-021-1/+4
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| | * Be mindful that sigmap(wire) could have dupes when checking \initEddie Hung2019-10-021-1/+4
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| * | Refactor peepopt_dffmux and be sensitive to \init when trimmingEddie Hung2019-10-021-32/+63
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* | Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2syncEddie Hung2019-10-081-4/+15
|\ \ | | | | | | async2sync to be called by equiv_opt only when -async2sync given
| * | Add -async2sync to help text as per @daveshah1Eddie Hung2019-10-041-1/+4
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| * | Restore part of docEddie Hung2019-10-031-1/+2
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| * | Add new -async2sync optionEddie Hung2019-10-031-1/+11
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| * | Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"Eddie Hung2019-10-031-2/+0
| | | | | | | | | | | | This reverts commit a39505e329cc05dbd4ad624a1cf0f6caf664fd9a.
| * | Revert "Update doc for equiv_opt"Eddie Hung2019-10-031-3/+2
| |/ | | | | | | This reverts commit a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.
* | Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9Eddie Hung2019-10-081-68/+67
|\ \ | | | | | | Rename abc_* names/attributes to more precisely be abc9_*
| * \ Merge branch 'master' into eddie/abc_to_abc9Eddie Hung2019-10-042-4/+15
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| * | | Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-65/+65
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