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* Merge pull request #736 from whitequark/select_assert_listClifford Wolf2018-12-161-8/+50
|\ | | | | select: print selection if a -assert-* flag causes an error
| * select: print selection if a -assert-* flag causes an error.whitequark2018-12-161-8/+50
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* | Merge pull request #735 from daveshah1/trifixesClifford Wolf2018-12-161-3/+4
|\ \ | | | | | | deminout fixes
| * | deminout: Consider $tribuf cellsDavid Shah2018-12-121-2/+2
| | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
| * | deminout: Don't demote constant-driven inouts to inputsDavid Shah2018-12-121-1/+2
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix equiv_opt indentingClifford Wolf2018-12-161-139/+129
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Merge pull request #724 from whitequark/equiv_optClifford Wolf2018-12-162-1/+168
|\ \ | | | | | | equiv_opt: new command, for verifying optimization passes
| * | equiv_opt: pass -D EQUIV when techmapping.whitequark2018-12-071-2/+4
| | | | | | | | | | | | | | | This allows avoiding techmap crashes e.g. because of large memories in white-box cell models.
| * | equiv_opt: new command, for verifying optimization passes.whitequark2018-12-072-1/+166
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* | | Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdataClifford Wolf2018-12-161-0/+17
|\ \ \ | | | | | | | | memory_bram: Fix initdata bit order after shuffling
| * | | memory_bram: Fix initdata bit order after shufflingGraham Edgecombe2018-12-111-0/+17
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some cases the memory_bram pass shuffles the order of the bits in a memory's RD_DATA port. Although the order of the bits in the WR_DATA and WR_EN ports is changed to match the RD_DATA port, the order of the bits in the initialization data is not. This causes reads of initialized memories to return invalid data (until the initialization data is overwritten). This commit fixes the bug by shuffling the initdata bits in exactly the same order as the RD_DATA/WR_DATA/WR_EN bits.
* | | Merge pull request #714 from daveshah1/abc_preserve_namingClifford Wolf2018-12-161-29/+51
|\ \ \ | | | | | | | | Proof-of-concept: preserve naming through ABC using dress
| * | | abc: Preserve naming through ABC using 'dress' commandDavid Shah2018-12-061-29/+51
| | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | | Merge pull request #722 from whitequark/rename_srcClifford Wolf2018-12-161-0/+50
|\ \ \ \ | | | | | | | | | | rename: add -src, for inferring names from source locations
| * | | | rename: add -src, for inferring names from source locations.whitequark2018-12-051-0/+50
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* | | | Merge pull request #720 from whitequark/masterClifford Wolf2018-12-162-2/+2
|\ \ \ \ | |_|_|/ |/| | | lut2mux: handle 1-bit INIT constant in $lut cells
| * | | lut2mux: handle 1-bit INIT constant in $lut cells.whitequark2018-12-051-1/+1
| | | | | | | | | | | | | | | | | | | | This pass already handles INIT constants shorter than 2^width, but that was not done for the recursion base case.
| * | | opt_lut: simplify type conversion. NFC.whitequark2018-12-051-1/+1
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* | | opt_lut: leave intact LUTs with cascade feeding module outputs.whitequark2018-12-071-0/+6
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* | | opt_lut: show original truth table for both cells.whitequark2018-12-071-2/+3
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* | | opt_lut: add -limit option, for debugging misoptimizations.whitequark2018-12-071-3/+21
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* | Bugfix in opt_expr handling of a<0 and a>=0Clifford Wolf2018-12-061-1/+1
|/ | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Rename opt_lut.cpp to opt_lut.ccClifford Wolf2018-12-051-0/+0
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.whitequark2018-12-051-17/+163
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* opt_lut: always prefer to eliminate 1-LUTs.whitequark2018-12-051-19/+41
| | | | | These are always either buffers or inverters, and keeping the larger LUT preserves more source-level information about the design.
* opt_lut: collect and display statistics.whitequark2018-12-051-4/+33
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* opt_lut: refactor to use a worker. NFC.whitequark2018-12-051-170/+177
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* opt_lut: new pass, to combine LUTs for tighter packing.whitequark2018-12-052-0/+275
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* Fix typoClifford Wolf2018-12-041-1/+1
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Merge pull request #702 from smunaut/min_ce_useClifford Wolf2018-12-041-1/+36
|\ | | | | Add option to only use DFFE is the resulting E signal would be use > N times
| * dff2dffe: Add option for unmap to only remove DFFE with low CE signal useSylvain Munaut2018-11-271-1/+36
| | | | | | | | Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
* | Merge pull request #676 from rafaeltp/masterClifford Wolf2018-12-011-10/+17
|\ \ | |/ |/| Splits SigSpec into bits before calling check_signal_in_fanout (solves #675)
| * using [i] to access individual bits of SigSpec and merging bits into a tmp ↵rafaeltp2018-10-211-11/+12
| | | | | | | | Sig before setting the port to new signal
| * cleaning up for PRrafaeltp2018-10-201-2/+2
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| * fixing code stylerafaeltp2018-10-201-1/+1
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| * solves #675rafaeltp2018-10-201-11/+17
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* | Add iteration limit to "opt_muxtree"Clifford Wolf2018-11-201-1/+17
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | DFFLIBMAP: changed 'missing pin' error into a warning with additional ↵Niels Moseley2018-11-061-1/+10
| | | | | | | | reason/info.
* | Allow square brackets in liberty identifiersClifford Wolf2018-11-051-2/+2
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* | Liberty file newline handling is more relaxed. More descriptive error messageNiels Moseley2018-11-031-4/+7
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* | Report an error when a liberty file contains pin references that reference ↵Niels Moseley2018-11-031-0/+3
|/ | | | non-existing pins
* Refactor code to avoid code duplication + added commentsRuben Undheim2018-10-201-2/+5
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* Support for SystemVerilog interfaces as a port in the top level module + ↵Ruben Undheim2018-10-201-5/+36
| | | | test case
* Merge pull request #672 from daveshah1/fix_bramClifford Wolf2018-10-191-0/+1
|\ | | | | memory_bram: Reset make_outreg when growing read ports
| * memory_bram: Reset make_outreg when growing read portsDavid Shah2018-10-191-0/+1
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Merge pull request #659 from rubund/sv_interfacesClifford Wolf2018-10-181-7/+188
|\ \ | | | | | | Support for SystemVerilog interfaces and modports
| * | Documentation improvements etc.Ruben Undheim2018-10-131-27/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Mention new feature in the SystemVerilog section in the README file - Commented changes much better - Rename a few signals to make it clearer - Prevent warning for unused signals in an easier way - Add myself as copyright holder to 2 files - Fix one potential memory leak (delete 'wire' if not in modport)
| * | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+13
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| * | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-7/+165
| |/ | | | | | | This time doing the changes mostly in AST before RTLIL generation
* | stop check_signal_in_fanout from traversing FFstklam2018-10-131-2/+2
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