| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Cope with possibility that D could connect to Q on same cell | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| * | xilinx_srl to use 'slice' features of pmgen for word level | Eddie Hung | 2019-08-23 | 2 | -32/+49 |
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| * | Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 4 | -34/+279 |
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| | * | Fix port hanlding in pmgen | Clifford Wolf | 2019-08-23 | 1 | -4/+3 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add pmgen slices and choices | Clifford Wolf | 2019-08-23 | 4 | -28/+276 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 1 | -2/+2 |
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| | * | Spelling | Eddie Hung | 2019-08-22 | 1 | -2/+2 |
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| * | | In sat: 'x' in init attr should not override constant | Eddie Hung | 2019-08-22 | 1 | -0/+2 |
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| * | | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-08-22 | 1 | -3/+1 |
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| * | | Add comment as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -0/+11 |
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| * | | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-08-22 | 1 | -15/+10 |
| | | | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. | ||||
| * | | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-08-22 | 1 | -10/+15 |
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| * | | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-08-22 | 1 | -3/+6 |
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| * | | Add doc | Eddie Hung | 2019-08-22 | 1 | -1/+14 |
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| * | | Add copyright | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
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| * | | Remove `shregmap -tech xilinx` additions | Eddie Hung | 2019-08-22 | 1 | -189/+8 |
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| * | | pmgen to also iterate over all module ports | Eddie Hung | 2019-08-22 | 1 | -2/+4 |
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| * | | Remove output_bits | Eddie Hung | 2019-08-22 | 2 | -16/+7 |
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| * | | Forgot to set ud_variable.minlen | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
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| * | | Do not run xilinx_srl_pm in fixed loop | Eddie Hung | 2019-08-22 | 1 | -28/+24 |
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| * | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -7/+12 |
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| | * | Merge pull request #1317 from YosysHQ/eddie/opt_expr_shiftx | Eddie Hung | 2019-08-22 | 1 | -4/+26 |
| | |\ | | | | | | | opt_expr to trim A port of $shiftx/$shift | ||||
| | | * | Copy-paste typo | Eddie Hung | 2019-08-22 | 1 | -1/+1 |
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| | | * | Respect opt_expr -keepdc as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -1/+1 |
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| | | * | Handle $shift and Y_WIDTH > 1 as per @cliffordwolf | Eddie Hung | 2019-08-22 | 1 | -4/+8 |
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| | | * | Add cover() | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
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| | | * | Canonical form | Eddie Hung | 2019-08-22 | 1 | -5/+5 |
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| | | * | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 |
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| * | | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -1/+1 |
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| | * | | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 |
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| * | | Reuse var | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| * | | Revert "Trim shiftx_width when upper bits are 1'bx" | Eddie Hung | 2019-08-21 | 1 | -6/+1 |
| | | | | | | | | | This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb. | ||||
| * | | opt_expr to trim A port of $shiftx if Y_WIDTH == 1 | Eddie Hung | 2019-08-21 | 1 | -0/+17 |
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| * | | Trim shiftx_width when upper bits are 1'bx | Eddie Hung | 2019-08-21 | 1 | -1/+6 |
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| * | | Add comment | Eddie Hung | 2019-08-21 | 1 | -0/+4 |
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| * | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 2 | -14/+164 |
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| * | | Rename pattern to fixed | Eddie Hung | 2019-08-21 | 2 | -10/+10 |
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| * | | attribute -> attr | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | | Use Cell::has_keep_attribute() | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | | xilinx_srl to support FDRE and FDRE_1 | Eddie Hung | 2019-08-21 | 2 | -10/+73 |
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| * | | Fix polarity of EN_POL | Eddie Hung | 2019-08-21 | 1 | -2/+2 |
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| * | | Add CLKPOL == 0 | Eddie Hung | 2019-08-21 | 1 | -0/+2 |
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| * | | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 2 | -8/+11 |
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| * | | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 |
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| * | | Add init support | Eddie Hung | 2019-08-21 | 1 | -2/+11 |
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| * | | Fix spacing | Eddie Hung | 2019-08-21 | 1 | -2/+2 |
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| * | | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -0/+213 |
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| * | Merge pull request #1314 from YosysHQ/eddie/fix_techmap | Clifford Wolf | 2019-08-21 | 1 | -4/+6 |
| |\ | | | | | techmap -max_iter to apply to each module individually | ||||
| | * | Grammar | Eddie Hung | 2019-08-20 | 1 | -1/+1 |
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index : iCE40/yosys | |
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