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If d_bit already in sigbit_chain_next, create extra wire
Eddie Hung
2019-06-10
1
-3
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+6
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Allow muxcover costs to be changed
Eddie Hung
2019-06-07
1
-12
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+42
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Revert "Rename shregmap -tech xilinx -> xilinx_dynamic"
Eddie Hung
2019-06-10
1
-4
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+4
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Revert "shregmap -tech xilinx_dynamic to work -params and -enpol"
Eddie Hung
2019-06-10
1
-26
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+6
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Revert "Refactor to ShregmapTechXilinx7Static"
Eddie Hung
2019-06-10
1
-86
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+46
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Revert "Add -tech xilinx_static"
Eddie Hung
2019-06-10
1
-13
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+2
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Revert "Continue support for ShregmapTechXilinx7Static"
Eddie Hung
2019-06-10
1
-81
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+30
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Revert "shregmap -tech xilinx_static to handle INIT"
Eddie Hung
2019-06-10
1
-32
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+22
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Fine tune aigerparse
Eddie Hung
2019-06-07
1
-1
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+5
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Allow muxcover costs to be changed
Eddie Hung
2019-06-07
1
-12
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+42
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Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
Eddie Hung
2019-06-06
1
-10
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+14
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Fix and test for balanced case
Eddie Hung
2019-06-06
1
-10
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+14
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Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux
Eddie Hung
2019-06-06
5
-2
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+277
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Support cascading $pmux.A with $mux.A and $mux.B
Eddie Hung
2019-06-06
1
-17
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+25
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More cleanup
Eddie Hung
2019-06-06
1
-15
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+20
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Fix spacing
Eddie Hung
2019-06-06
1
-6
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+5
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Non chain user check using next_sig
Eddie Hung
2019-06-06
1
-7
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+5
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Move muxpack from passes/techmap to passes/opt
Eddie Hung
2019-06-06
3
-1
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+1
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Update doc
Eddie Hung
2019-06-06
1
-4
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+5
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Add tests, fix for !=
Eddie Hung
2019-06-06
1
-9
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+32
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Missing file
Eddie Hung
2019-06-06
1
-0
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+232
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Initial adaptation of muxpack from shregmap
Eddie Hung
2019-06-06
1
-0
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+1
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Merge pull request #1071 from YosysHQ/eddie/fix_1070
Clifford Wolf
2019-06-06
1
-2
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+2
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Fix typo in opt_rmdff
Eddie Hung
2019-06-05
1
-2
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+2
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Merge pull request #1072 from YosysHQ/eddie/fix_1069
Clifford Wolf
2019-06-06
1
-0
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+5
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Error out if no top module given before 'sim'
Eddie Hung
2019-06-05
1
-0
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+5
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Missing doc for -tech xilinx in shregmap
Eddie Hung
2019-06-05
1
-0
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+3
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Merge pull request #1067 from YosysHQ/clifford/fix1065
Eddie Hung
2019-06-05
1
-1
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+1
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shregmap -tech xilinx_static to handle INIT
Eddie Hung
2019-06-05
1
-22
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+32
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Continue support for ShregmapTechXilinx7Static
Eddie Hung
2019-06-05
1
-30
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+81
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Add -tech xilinx_static
Eddie Hung
2019-06-05
1
-2
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+13
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Refactor to ShregmapTechXilinx7Static
Eddie Hung
2019-06-05
1
-46
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+86
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shregmap -tech xilinx_dynamic to work -params and -enpol
Eddie Hung
2019-06-05
1
-6
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+26
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-05
2
-27
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+95
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Major rewrite of wire selection in setundef -init
Clifford Wolf
2019-06-05
1
-30
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+89
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Indent fix
Clifford Wolf
2019-06-05
1
-23
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+25
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Merge pull request #999 from jakobwenzel/setundefInitFix
Clifford Wolf
2019-06-05
1
-16
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+23
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initialize more registers in setundef -init
Jakob Wenzel
2019-05-09
1
-16
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+23
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Fix typo in fmcombine log message, fixes #1063
Clifford Wolf
2019-06-05
1
-2
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+2
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Merge remote-tracking branch 'origin/clifford/fix1065' into xc7mux
Eddie Hung
2019-06-05
1
-1
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+1
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Suppress driver-driver conflict warning for unknown cell types, fixes #1065
Clifford Wolf
2019-06-05
1
-1
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+1
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Rename shregmap -tech xilinx -> xilinx_dynamic
Eddie Hung
2019-06-04
1
-4
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+4
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Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-03
2
-4
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+16
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Fix "tee" handling of log_streams
Clifford Wolf
2019-05-31
1
-0
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+5
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Merge pull request #1049 from YosysHQ/clifford/fix1047
Clifford Wolf
2019-05-28
1
-4
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+11
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Do not use shiftmul peepopt pattern when mul result is truncated, fixes #1047
Clifford Wolf
2019-05-28
1
-4
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+11
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Remove dupe
Eddie Hung
2019-06-03
1
-7
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+7
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Merge branch 'xaig' into xc7mux
Eddie Hung
2019-05-31
1
-6
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+0
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Move clean from aigerparse to abc9
Eddie Hung
2019-04-23
1
-0
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+1
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Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig
Eddie Hung
2019-04-22
1
-5
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+159
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