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| * | | | | Extend ExclusiveDatabase to query SigSpec-s (for $pmux)Eddie Hung2019-06-071-19/+27
| * | | | | Add ExclusiveDatabase to check exclusive $eq/$logic_not cell resultsEddie Hung2019-06-071-1/+64
| * | | | | Resolve @cliffordwolf comment on redundant checkEddie Hung2019-06-071-10/+2
| * | | | | Resolve @cliffordwolf comment on sigmapEddie Hung2019-06-071-2/+2
* | | | | | CleanupEddie Hung2019-06-171-3/+3
* | | | | | Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-1/+1
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| * | | | | &scorr before &sweep, remove &retime as recommendedEddie Hung2019-06-171-1/+1
* | | | | | Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-3/+4
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| * | | | | Copy not move parameters/attributesEddie Hung2019-06-171-3/+4
* | | | | | Merge branch 'xaig' into xaig_dffEddie Hung2019-06-171-23/+26
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| * | | | | Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-171-25/+26
* | | | | | Merge remote-tracking branch 'origin/xaig' into xaig_dffEddie Hung2019-06-171-1/+1
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| * | | | | Re-enable &dc2Eddie Hung2019-06-171-1/+1
| * | | | | CleanupEddie Hung2019-06-161-51/+7
* | | | | | CleanupEddie Hung2019-06-151-40/+7
* | | | | | abc9 to recover_init by defaultEddie Hung2019-06-151-11/+6
* | | | | | Do not treat $__ABC_FF_ as a user cellEddie Hung2019-06-151-21/+6
* | | | | | CleanupEddie Hung2019-06-151-10/+7
* | | | | | Use $__ABC_FF_ instead of $_FF_Eddie Hung2019-06-151-13/+21
* | | | | | Fix initialisation of flopsEddie Hung2019-06-151-2/+3
* | | | | | Map to $_FF_ instead of $_DFF_P_ to prevent recursion issuesEddie Hung2019-06-151-13/+13
* | | | | | For now, short $_DFF_[NP]_ from ff_map.v at re-integrationEddie Hung2019-06-151-0/+8
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* | | | | Get rid of compiler warningsEddie Hung2019-06-141-5/+5
* | | | | Update abc9 -D docEddie Hung2019-06-141-1/+2
* | | | | Enable "abc9 -D <num>" for timing-driven synthesisEddie Hung2019-06-141-9/+9
* | | | | Further cleanup based on @daveshah1Eddie Hung2019-06-141-10/+0
* | | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaigEddie Hung2019-06-141-0/+9
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| * | | | | ecp5: Add abc9 optionDavid Shah2019-06-141-0/+9
* | | | | | Remove extra semicolonEddie Hung2019-06-141-1/+1
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* | | | | Rip out all non FPGA stuff from abc9Eddie Hung2019-06-121-343/+111
* | | | | Fix spellingEddie Hung2019-06-121-1/+1
* | | | | Revert "For 'stat' do not count modules with abc_box_id"Eddie Hung2019-06-121-3/+0
* | | | | Be more precise when connecting during ABC9 re-integrationEddie Hung2019-06-121-1/+3
* | | | | Remove hacky wideports_split from abc9Eddie Hung2019-06-121-52/+4
* | | | | Fix compile errors when #if 1 for debugEddie Hung2019-06-121-7/+8
* | | | | Do not call abc9 if no outputsEddie Hung2019-06-121-54/+65
* | | | | More write_xaiger cleanupEddie Hung2019-06-121-1/+1
* | | | | ConsistencyEddie Hung2019-06-121-1/+1
* | | | | Merge branch 'xc7mux' into xaigEddie Hung2019-06-121-1/+1
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| * | | | | Typo: wire delay is -W argumentEddie Hung2019-06-121-1/+1
* | | | | | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...Eddie Hung2019-06-121-6/+3
* | | | | | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"Eddie Hung2019-06-122-267/+0
* | | | | | Revert "Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux"Eddie Hung2019-06-121-14/+10
* | | | | | Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-5/+13
* | | | | | Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx"Eddie Hung2019-06-121-13/+5
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* | | | | Add "-W' wire delay arg to abc9, use from synth_xilinxEddie Hung2019-06-111-5/+13
* | | | | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7...Eddie Hung2019-06-111-15/+10
* | | | | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-111-10/+15
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| * | | | Try way that doesn't involve creating a new wireEddie Hung2019-06-111-10/+15
* | | | | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7muxEddie Hung2019-06-101-3/+6
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