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* Add memory_libmap pass.Marcelina Kościelnicka2022-05-185-0/+3872
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* proc_rom: Add special handling of const-0 address bits.Marcelina Kościelnicka2022-05-181-15/+40
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* opt_ffinv: Use ModIndex instead of ModWalker.Marcelina Kościelnicka2022-05-171-50/+53
| | | | This avoids using out-of-data index information.
* Add opt_ffinv pass.Marcelina Kościelnicka2022-05-132-0/+256
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* Add proc_rom pass.Marcelina Kościelnicka2022-05-133-0/+239
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* Merge pull request #3299 from YosysHQ/mmicko/sim_memoryMiodrag Milanović2022-05-091-2/+18
|\ | | | | sim pass: support for memories
| * fix crash when no fst inputMiodrag Milanovic2022-05-041-1/+2
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| * Start restoring memory state from VCD/FSTMiodrag Milanovic2022-05-041-2/+17
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* | opt_mem: Remove constant-value bit lanes.Marcelina Kościelnicka2022-05-071-13/+143
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* | memory_share: fix wrong argidx in extra_argsimhcyx2022-05-051-1/+1
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* | abc: Use dict/pool instead of std::map/std::setMarcelina Kościelnicka2022-05-041-14/+14
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* AIM file could have gaps in or between inputs and initsMiodrag Milanovic2022-05-021-3/+6
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* Merge pull request #3257 from jix/tribuf-formalJannis Harder2022-04-251-3/+46
|\ | | | | tribuf: `-formal` option: convert all to logic and detect conflicts
| * tribuf: `-formal` option: convert all to logic and detect conflictsJannis Harder2022-04-121-3/+46
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* | Match $anyseq input if connected to public wireMiodrag Milanovic2022-04-221-6/+12
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* | Treat $anyseq as input from FSTMiodrag Milanovic2022-04-221-0/+21
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* | Last sample from input does not represent changeMiodrag Milanovic2022-04-221-1/+2
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* | latches are always set to zeroMiodrag Milanovic2022-04-221-6/+1
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* | If not multiclock, output only on clock edgesMiodrag Milanovic2022-04-221-0/+18
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* | Set init state for all wires from FST and set pastMiodrag Milanovic2022-04-221-13/+12
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* | Fix multiclock for btor2 witnessMiodrag Milanovic2022-04-221-5/+9
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* | Merge pull request #3280 from YosysHQ/micko/fix_readaiwMiodrag Milanović2022-04-181-2/+2
|\ \ | | | | | | Fix reading aiw from other solvers
| * | Fix reading aiw from other solversMiodrag Milanovic2022-04-151-2/+2
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* | memory_share: Fix up mismatched address widths.Marcelina Kościelnicka2022-04-151-0/+14
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* | opt_dff: Fix behavior on $ff with D == Q.Marcelina Kościelnicka2022-04-151-1/+1
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* Use wrap_async_control_gate if ff is fineMiodrag Milanovic2022-04-081-9/+11
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* Makefile: properly conditionalize features requiring compression.Iris Johnson2022-04-071-0/+2
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* Merge pull request #3269 from YosysHQ/micko/fix_autotopCatherine2022-04-071-13/+13
|\ | | | | Reorder steps in -auto-top to fix synth command, fixes #3261
| * Reorder steps in -auto-top to fix synth command, fixes #3261Miodrag Milanovic2022-04-051-13/+13
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* | abc: Add support for FFs with reset in -dffMarcelina Kościelnicka2022-04-071-90/+229
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* show: Fix width labels.Marcelina Kościelnicka2022-04-041-23/+18
| | | | See #3266.
* past_ad initial value settingMiodrag Milanovic2022-04-021-0/+3
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* setInitState can be only one altering valuesMiodrag Milanovic2022-04-021-4/+6
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* Set past_d value for init stateMiodrag Milanovic2022-04-021-0/+2
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* Merge pull request #3264 from jix/invalid_ff_dcinit_mergeJannis Harder2022-04-022-2/+21
|\ | | | | opt_merge: Add `-keepdc` option required for formal verification
| * opt_merge: Add `-keepdc` option required for formal verificationJannis Harder2022-04-012-2/+21
| | | | | | | | | | | | | | | | The `-keepdc` option prevents merging flipflops with dont-care bits in their initial value, as, in general, this is not a valid transform for formal verification. The keepdc option of `opt` is passed along to `opt_merge` now.
* | Set init values for wrapped async control signalsMiodrag Milanovic2022-04-011-0/+2
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* Support memories in aiw and multiclockMiodrag Milanovic2022-03-311-16/+86
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* Merge pull request #3194 from Ravenslofty/abc9-flow3mfsLofty2022-03-281-1/+7
|\ | | | | abc9: add flow3mfs script
| * abc9: add flow3mfs scriptLofty2022-02-101-1/+7
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* | abc9_ops: Also derive blackboxes with timing infogatecat2022-03-241-5/+10
| | | | | | | | Signed-off-by: gatecat <gatecat@ds0.me>
* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
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* | Proper SigBit forming in simMiodrag Milanovic2022-03-221-4/+4
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* | More verbose warningsMiodrag Milanovic2022-03-181-5/+7
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* | Recognize registers and set initial state for them in tbMiodrag Milanovic2022-03-161-6/+32
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* | Update sim help message.Miodrag Milanovic2022-03-161-1/+2
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* | Merge pull request #3232 from YosysHQ/micko/fst2tbMiodrag Milanović2022-03-141-0/+319
|\ \ | | | | | | Added fst2tb pass for generating testbench
| * | Added fst2tb pass for generating testbenchMiodrag Milanovic2022-03-141-0/+319
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* | | Merge pull request #3213 from antonblanchard/abc-typoClaire Xen2022-03-141-2/+2
|\ \ \ | |/ / |/| | abc: Fix {I} and {P} substitution
| * | abc: Fix {I} and {P} substitutionAnton Blanchard2022-02-231-2/+2
| | | | | | | | | | | | We were searching for {D} after the first match of {I} or {P}.
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