| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | | | | | | Do not use log_id as it strips \\, also fix scc for |wire| > 1 | Eddie Hung | 2019-06-24 | 1 | -13/+30 | |
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| * | | | | | | Fix abc9's scc breaker, also break on abc_scc_break attr | Eddie Hung | 2019-06-24 | 1 | -9/+31 | |
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| * | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-21 | 2 | -48/+114 | |
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| | * \ \ \ \ \ | Merge pull request #1108 from YosysHQ/clifford/fix1091 | Eddie Hung | 2019-06-21 | 1 | -45/+99 | |
| | |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | Add support for partial matches to muxcover | |||||
| | | * | | | | | | Replace "muxcover -freedecode" with "muxcover -dmux=cost" | Clifford Wolf | 2019-06-21 | 1 | -15/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | Add "muxcover -freedecode" | Clifford Wolf | 2019-06-21 | 1 | -0/+14 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | | * | | | | | | Improvements in muxcover | Clifford Wolf | 2019-06-20 | 1 | -38/+55 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Slightly under-estimate cost of decoder muxes - Prefer larger muxes at tree root at same cost - Don't double-count input cost for partial muxes - Add debug log output | |||||
| | | * | | | | | | Add support for partial matches to muxcover, fixes #1091 | Clifford Wolf | 2019-06-20 | 1 | -7/+31 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | Merge pull request #1085 from YosysHQ/eddie/shregmap_improve | Eddie Hung | 2019-06-21 | 1 | -3/+15 | |
| | |\ \ \ \ \ \ \ | | |/ / / / / / | |/| | | | | | | Improve shregmap to handle case where first flop is common to two chains | |||||
| | | * | | | | | | Actually, there might not be any harm in updating sigmap... | Eddie Hung | 2019-06-20 | 1 | -3/+1 | |
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| | | * | | | | | | Add comment as per @cliffordwolf | Eddie Hung | 2019-06-20 | 1 | -0/+11 | |
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| | | * | | | | | | Revert "Try way that doesn't involve creating a new wire" | Eddie Hung | 2019-06-11 | 1 | -15/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 2f427acc9ed23c77e89386f4fbf53ac580bf0f0b. | |||||
| * | | | | | | | | Do not rename non LUT cells in abc9 | Eddie Hung | 2019-06-21 | 1 | -11/+16 | |
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| * | | | | | | | | Fix gcc warning of potentially uninitialised | Eddie Hung | 2019-06-20 | 1 | -2/+2 | |
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| * | | | | | | | | Fix simple_abc9/generate test with 1'bx at MSB | Eddie Hung | 2019-06-20 | 1 | -1/+1 | |
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| * | | | | | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-20 | 2 | -3/+5 | |
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| | * | | | | | | | Improve shregmap help message, fixes #1113 | Clifford Wolf | 2019-06-20 | 1 | -0/+2 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | |||||
| | * | | | | | | | Fix bug in #1078, add entry to CHANGELOG | Eddie Hung | 2019-06-19 | 1 | -3/+3 | |
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| * | | | | | | | | Do not call "setundef -zero" in abc9 | Eddie Hung | 2019-06-20 | 1 | -5/+2 | |
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| * | | | | | | | &scorr before &sweep, remove &retime as recommended | Eddie Hung | 2019-06-17 | 1 | -1/+1 | |
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| * | | | | | | Copy not move parameters/attributes | Eddie Hung | 2019-06-17 | 1 | -3/+4 | |
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| * | | | | | Fix leak removing cells during ABC integration; also preserve attr | Eddie Hung | 2019-06-17 | 1 | -25/+26 | |
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| * | | | | Re-enable &dc2 | Eddie Hung | 2019-06-17 | 1 | -1/+1 | |
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| * | | | | Cleanup | Eddie Hung | 2019-06-16 | 1 | -51/+7 | |
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| * | | | Get rid of compiler warnings | Eddie Hung | 2019-06-14 | 1 | -5/+5 | |
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| * | | | Update abc9 -D doc | Eddie Hung | 2019-06-14 | 1 | -1/+2 | |
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| * | | | Enable "abc9 -D <num>" for timing-driven synthesis | Eddie Hung | 2019-06-14 | 1 | -9/+9 | |
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| * | | | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -10/+0 | |
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| * | | | Merge branch 'xaig' of github.com:YosysHQ/yosys into xaig | Eddie Hung | 2019-06-14 | 1 | -0/+9 | |
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| | * | | | ecp5: Add abc9 option | David Shah | 2019-06-14 | 1 | -0/+9 | |
| | | | | | | | | | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me> | |||||
| * | | | | Remove extra semicolon | Eddie Hung | 2019-06-14 | 1 | -1/+1 | |
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| * | | | Rip out all non FPGA stuff from abc9 | Eddie Hung | 2019-06-12 | 1 | -343/+111 | |
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| * | | | Fix spelling | Eddie Hung | 2019-06-12 | 1 | -1/+1 | |
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| * | | | Be more precise when connecting during ABC9 re-integration | Eddie Hung | 2019-06-12 | 1 | -1/+3 | |
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| * | | | Remove hacky wideports_split from abc9 | Eddie Hung | 2019-06-12 | 1 | -52/+4 | |
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| * | | | Fix compile errors when #if 1 for debug | Eddie Hung | 2019-06-12 | 1 | -7/+8 | |
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| * | | | Do not call abc9 if no outputs | Eddie Hung | 2019-06-12 | 1 | -54/+65 | |
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| * | | | More write_xaiger cleanup | Eddie Hung | 2019-06-12 | 1 | -1/+1 | |
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| * | | | Consistency | Eddie Hung | 2019-06-12 | 1 | -1/+1 | |
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| * | | | Merge branch 'xc7mux' into xaig | Eddie Hung | 2019-06-12 | 1 | -1/+1 | |
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| | * | | | Typo: wire delay is -W argument | Eddie Hung | 2019-06-12 | 1 | -1/+1 | |
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| * | | | | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into ↵ | Eddie Hung | 2019-06-12 | 1 | -6/+3 | |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xc7mux" This reverts commit a138381ac3f2c820d187f08531ffd823d6cbcfd5, reversing changes made to b77c5da76919f7f99f171a0a2775896fbc8debc2. | |||||
| * | | | | Retry "Add "-W' wire delay arg to abc9, use from synth_xilinx" | Eddie Hung | 2019-06-12 | 1 | -5/+13 | |
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| * | | | | Revert "Add "-W' wire delay arg to abc9, use from synth_xilinx" | Eddie Hung | 2019-06-12 | 1 | -13/+5 | |
| |/ / / | | | | | | | | | | This reverts commit 2dffa4685b830313204f5d04314a14ed6ecac8ec. | |||||
| * | | | Add "-W' wire delay arg to abc9, use from synth_xilinx | Eddie Hung | 2019-06-11 | 1 | -5/+13 | |
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| * | | | Revert "Merge remote-tracking branch 'origin/eddie/shregmap_improve' into ↵ | Eddie Hung | 2019-06-11 | 1 | -15/+10 | |
| | | | | | | | | | | | | | | | | | | | | | | xc7mux" This reverts commit 5174082208ef9bea22ad1ba62622947375b3e83b, reversing changes made to 54379f9872ba3abdf5328994abcf5abfc7288c6b. | |||||
| * | | | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux | Eddie Hung | 2019-06-11 | 1 | -10/+15 | |
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| | * | | Try way that doesn't involve creating a new wire | Eddie Hung | 2019-06-11 | 1 | -10/+15 | |
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| * | | | Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux | Eddie Hung | 2019-06-10 | 1 | -3/+6 | |
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| | * | | If d_bit already in sigbit_chain_next, create extra wire | Eddie Hung | 2019-06-10 | 1 | -3/+6 | |
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index : iCE40/yosys | |
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