iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	3	-7/+4
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*	Added techmap -extern	Clifford Wolf	2014-07-27	1	-16/+64
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*	Added topological sorting to techmap	Clifford Wolf	2014-07-27	1	-20/+52
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	2	-21/+19
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	6	-21/+21
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	4	-10/+10
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	3	-12/+12
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*	Changed more code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	3	-17/+7
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*	More RTLIL::Cell API usage cleanups	Clifford Wolf	2014-07-26	1	-2/+2
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	6	-16/+18
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	6	-128/+128
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	6	-128/+128
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*	Added copy-constructor-like module->addCell(name, other) method	Clifford Wolf	2014-07-26	1	-8/+4
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	6	-122/+59
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*	Added "make SMALL=1"	Clifford Wolf	2014-07-24	1	-1/+4
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*	Added "make PRETTY=1"	Clifford Wolf	2014-07-24	1	-6/+6
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*	Removed RTLIL::SigSpec::expand() method	Clifford Wolf	2014-07-23	2	-131/+69
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*	Fixed all users of SigSpec::chunks_rw() and removed it	Clifford Wolf	2014-07-23	3	-25/+24
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 3/3	Clifford Wolf	2014-07-23	2	-3/+3
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*	Refactoring {SigSpec\|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3	Clifford Wolf	2014-07-23	2	-3/+3
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*	SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, ↵	Clifford Wolf	2014-07-22	3	-3/+3
\| \| \| \|	created interim RTLIL::SigSpec::chunks_rw()
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	4	-78/+78
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	4	-78/+78
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*	Replaced depricated NEW_WIRE macro with module->addWire() calls	Clifford Wolf	2014-07-21	1	-2/+2
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*	Removed deprecated module->new_wire()	Clifford Wolf	2014-07-21	1	-4/+4
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*	Added call_on_selection() and call_on_module() API	Clifford Wolf	2014-07-20	1	-9/+1
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*	Added support for "blackbox" attribute to iopadmap	Clifford Wolf	2014-07-17	1	-1/+1
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*	Added support for "blackbox" attribute to flatten/techmap	Clifford Wolf	2014-07-17	1	-1/+4
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*	be more verbose when techmap yielded processes	Johann Glaser	2014-05-26	1	-1/+5
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*	Merged OSX fixes from Siesh1oo with some modifications	Clifford Wolf	2014-03-13	1	-0/+1
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*	- kernel/register.h, kernel/driver.cc: refactor ↵	Siesh1oo	2014-03-12	1	-1/+2
\| \| \| \| \| \| \|	rewrite_yosys_exe()/get_share_file_name() to portable proc_self_dirname()/proc_share_dirname(). This refactoring improves robustness and allows OSX support with only 7 new lines of code, and easy extension for other systems. - passes/abc/abc.cc, passes/cmds/show.cc, passes/techmap/techmap.cc: use new, refactored semantics.
*	OSX compatible creation of stdcells.inc, using code from ↵	Clifford Wolf	2014-03-11	1	-2/+3
\| \| \| \| \| \|	github.com/Siesh1oo/yosys (see https://github.com/cliffordwolf/yosys/pull/28)
*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-0/+1
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Fixed dumping of timing() { .. } block in libparse	Clifford Wolf	2014-03-09	1	-2/+3
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*	Added techmap -max_iter option	Clifford Wolf	2014-03-06	1	-0/+10
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*	Added _TECHMAP_REPLACE_ feature to techmap	Clifford Wolf	2014-02-20	1	-4/+21
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*	Added "extract -ignore_parameters" and "extract -ignore_param ..."	Clifford Wolf	2014-02-20	1	-0/+79
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*	Added "extract -map %<design_name>"	Clifford Wolf	2014-02-20	1	-10/+30
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*	Added techmap support for _TECHMAP_CONNMAP_*_	Clifford Wolf	2014-02-18	1	-0/+39
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*	Better preserve wires when flattening (in comparison to techmap)	Clifford Wolf	2014-02-17	1	-12/+12
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*	Added some additional checks to techmap	Clifford Wolf	2014-02-16	1	-0/+14
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*	Added CONSTMSK and CONSTVAL feature to techmap	Clifford Wolf	2014-02-16	1	-0/+23
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*	Added recursion support to techmap	Clifford Wolf	2014-02-16	1	-260/+262
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*	Added iopadmap -bits	Clifford Wolf	2014-02-15	1	-14/+48
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*	Fixed dfflibmap for cell libraries with no set-reset-ff	Clifford Wolf	2014-02-15	1	-1/+1
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*	Moved some passes to other source directories	Clifford Wolf	2014-02-08	2	-0/+681
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*	Added $slice and $concat cell types	Clifford Wolf	2014-02-07	1	-0/+18
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*	Changed techmap description from "simple" to "generic"	Clifford Wolf	2014-02-06	1	-1/+1
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*	Added support for // comments in liberty parser	Clifford Wolf	2014-01-25	1	-0/+5
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*	Added hilomap command	Clifford Wolf	2014-01-19	2	-0/+130
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