iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)	Clifford Wolf	2016-02-01	1	-8/+68
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*	Added support for "dfflibmap -liberty +/..."	Clifford Wolf	2015-09-18	1	-0/+1
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*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-5/+5
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*	Added liberty dont_use support to dfflibmap	Clifford Wolf	2015-05-31	1	-0/+4
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*	Added ENABLE_NDEBUG makefile options	Clifford Wolf	2015-01-24	1	-2/+6
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*	Added "dfflibmap -prepare" help	Clifford Wolf	2014-12-24	1	-1/+5
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*	Added "dfflibmap -prepare"	Clifford Wolf	2014-12-24	1	-31/+54
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*	Fixed various VS warnings	Clifford Wolf	2014-10-18	1	-4/+4
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*	Renamed SIZE() to GetSize() because of name collision on Win32	Clifford Wolf	2014-10-10	1	-1/+1
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*	namespace Yosys	Clifford Wolf	2014-09-27	1	-1/+3
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*	Fixed inserting of Q-inverters in dfflibmap	Clifford Wolf	2014-08-27	1	-0/+5
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*	Changed frontend-api from FILE to std::istream	Clifford Wolf	2014-08-23	1	-3/+4
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*	Renamed $_INV_ cell type to $_NOT_	Clifford Wolf	2014-08-15	1	-1/+1
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*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-2/+2
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*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-1/+1
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Manual fixes for new cell connections API	Clifford Wolf	2014-07-26	1	-1/+1
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-2/+2
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-2/+2
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-20/+15
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*	Merged a few fixes for non-posix systems from github.com/Siesh1oo/yosys	Clifford Wolf	2014-03-11	1	-0/+1
\| \| \| \|	(see https://github.com/cliffordwolf/yosys/pull/28)
*	Fixed dfflibmap for cell libraries with no set-reset-ff	Clifford Wolf	2014-02-15	1	-1/+1
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*	renamed LibertyParer to LibertyParser	Clifford Wolf	2014-01-14	1	-1/+1
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*	Fixed dfflibmap for unused output ports	Clifford Wolf	2013-12-21	1	-0/+1
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*	Now prefer smallest cells in dfflibmap	Clifford Wolf	2013-12-21	1	-2/+22
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*	Cleanup of dfflibmap cellmap exploration code	Clifford Wolf	2013-12-20	1	-17/+20
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*	Further improved dfflibmap cellmap exploration	Clifford Wolf	2013-12-20	1	-14/+18
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*	Fixed dfflibmap endless-loop bug	Clifford Wolf	2013-12-20	1	-0/+1
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*	Prefer non-inverted clocks in dfflibmap	Clifford Wolf	2013-12-19	1	-6/+8
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*	Renamed "placeholder" to "blackbox"	Clifford Wolf	2013-11-22	1	-1/+1
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*	Added placeholder check to dfflibmap and cleaned up some other placeholder ↵	Clifford Wolf	2013-10-31	1	-1/+1
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*	Added support for sr flip-flops to dfflibmap	Clifford Wolf	2013-10-24	1	-3/+168
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*	Moved dfflibmap from passes/dfflibmap to passes/techmap	Clifford Wolf	2013-10-16	1	-0/+342