iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Using log_assert() instead of assert()	Clifford Wolf	2014-07-28	1	-1/+1
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*	Using new obj iterator API in a few places	Clifford Wolf	2014-07-27	1	-5/+5
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*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Replaced more old SigChunk programming patterns	Clifford Wolf	2014-07-24	1	-10/+9
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*	Removed RTLIL::SigSpec::optimize()	Clifford Wolf	2014-07-23	1	-2/+0
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-6/+6
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-6/+6
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*	Major improvements in mem2reg and added "init" sync rules	Clifford Wolf	2013-11-21	1	-0/+114