| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Also add first.Q to chain_bits since variable length | Eddie Hung | 2019-08-23 | 1 | -0/+1 |
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| * | Do not enforce !EN_POLARITY on $dffe | Eddie Hung | 2019-08-23 | 1 | -2/+0 |
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| * | Create new cell for fixed length SRL | Eddie Hung | 2019-08-23 | 1 | -14/+22 |
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| * | Cleanup FDRE matching | Eddie Hung | 2019-08-23 | 1 | -45/+19 |
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| * | Oops don't need a finally block | Eddie Hung | 2019-08-23 | 1 | -5/+0 |
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| * | Keep track of bits in variable length chain, to check for taps | Eddie Hung | 2019-08-23 | 1 | -0/+12 |
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| * | Don't forget $dff has no EN | Eddie Hung | 2019-08-23 | 1 | -2/+4 |
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| * | Same for variable length | Eddie Hung | 2019-08-23 | 1 | -2/+10 |
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| * | Filter on en_port for fixed length | Eddie Hung | 2019-08-23 | 1 | -4/+24 |
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| * | Check clock is consistent | Eddie Hung | 2019-08-23 | 1 | -5/+25 |
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| * | Fix last_cell.D | Eddie Hung | 2019-08-23 | 1 | -2/+1 |
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| * | Revert "Add a unique argument to pmgen's nusers()" | Eddie Hung | 2019-08-23 | 1 | -8/+4 |
| | | | | | This reverts commit 1d88887cfdbeedff7dce9024d8fb4ceb014cb2ef. | ||||
| * | Revert "Fix polarity" | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
| | | | | | This reverts commit 9cd23cf0feda3e12ceda1f8fa5d28d2b38f2314d. | ||||
| * | Fix polarity | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| * | Check for non unique nusers/fanouts | Eddie Hung | 2019-08-23 | 1 | -2/+2 |
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| * | Add a unique argument to pmgen's nusers() | Eddie Hung | 2019-08-23 | 1 | -4/+8 |
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| * | Update doc | Eddie Hung | 2019-08-23 | 1 | -12/+19 |
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| * | Remove (* init *) entry when consumed into SRL | Eddie Hung | 2019-08-23 | 1 | -2/+6 |
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| * | indo -> into | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| * | Forgot to slice | Eddie Hung | 2019-08-23 | 1 | -1/+2 |
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| * | Cope with possibility that D could connect to Q on same cell | Eddie Hung | 2019-08-23 | 1 | -1/+1 |
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| * | xilinx_srl to use 'slice' features of pmgen for word level | Eddie Hung | 2019-08-23 | 2 | -32/+49 |
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| * | Merge remote-tracking branch 'origin/clifford/pmgen' into eddie/xilinx_srl | Eddie Hung | 2019-08-23 | 4 | -34/+279 |
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| | * | Fix port hanlding in pmgen | Clifford Wolf | 2019-08-23 | 1 | -4/+3 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| | * | Add pmgen slices and choices | Clifford Wolf | 2019-08-23 | 4 | -28/+276 |
| | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | | Add doc | Eddie Hung | 2019-08-22 | 1 | -1/+14 |
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| * | | Add copyright | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
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| * | | pmgen to also iterate over all module ports | Eddie Hung | 2019-08-22 | 1 | -2/+4 |
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| * | | Remove output_bits | Eddie Hung | 2019-08-22 | 2 | -16/+7 |
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| * | | Forgot to set ud_variable.minlen | Eddie Hung | 2019-08-22 | 1 | -0/+1 |
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| * | | Do not run xilinx_srl_pm in fixed loop | Eddie Hung | 2019-08-22 | 1 | -28/+24 |
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| * | | Merge remote-tracking branch 'origin/master' into eddie/xilinx_srl | Eddie Hung | 2019-08-22 | 1 | -1/+1 |
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| | * | Fix test_pmgen deps | Miodrag Milanovic | 2019-08-21 | 1 | -1/+1 |
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| * | | Reuse var | Eddie Hung | 2019-08-21 | 1 | -1/+1 |
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| * | | Revert "Trim shiftx_width when upper bits are 1'bx" | Eddie Hung | 2019-08-21 | 1 | -6/+1 |
| | | | | | | | | | This reverts commit 7e7965ca7b3bbeb79cb70014da7bc48c08a74adb. | ||||
| * | | Trim shiftx_width when upper bits are 1'bx | Eddie Hung | 2019-08-21 | 1 | -1/+6 |
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| * | | Add comment | Eddie Hung | 2019-08-21 | 1 | -0/+4 |
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| * | | Add variable length support to xilinx_srl | Eddie Hung | 2019-08-21 | 2 | -14/+164 |
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| * | | Rename pattern to fixed | Eddie Hung | 2019-08-21 | 2 | -10/+10 |
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| * | | attribute -> attr | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | | Use Cell::has_keep_attribute() | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | | xilinx_srl to support FDRE and FDRE_1 | Eddie Hung | 2019-08-21 | 2 | -10/+73 |
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| * | | Fix polarity of EN_POL | Eddie Hung | 2019-08-21 | 1 | -2/+2 |
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| * | | Add CLKPOL == 0 | Eddie Hung | 2019-08-21 | 1 | -0/+2 |
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| * | | Reject if not minlen from inside pattern matcher | Eddie Hung | 2019-08-21 | 2 | -8/+11 |
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| * | | Get wire via SigBit | Eddie Hung | 2019-08-21 | 1 | -4/+4 |
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| * | | Respect \keep on cells or wires | Eddie Hung | 2019-08-21 | 1 | -2/+10 |
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| * | | Add init support | Eddie Hung | 2019-08-21 | 1 | -2/+11 |
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| * | | Fix spacing | Eddie Hung | 2019-08-21 | 1 | -2/+2 |
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| * | | Initial progress on xilinx_srl | Eddie Hung | 2019-08-21 | 3 | -0/+213 |
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 |
index : iCE40/yosys | |
| clone of https://github.com/YosysHQ/yosys |
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