iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Check for either sign or zero extension for postAdd packing	Eddie Hung	2019-11-26	1	-3/+3
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*	Fix #1462, #1480.	Marcin Kościelnicki	2019-11-19	1	-5/+7
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*	Add comment on why we have to match for clock-enable/reset muxes	Eddie Hung	2019-10-05	1	-1/+4
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*	Add note on pattern detector	Eddie Hung	2019-10-05	1	-3/+7
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*	Restore optimisation for sigM.empty()	Eddie Hung	2019-10-04	1	-1/+4
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*	Retry on fixing TODOs	Eddie Hung	2019-10-04	1	-8/+1
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*	Revert "Fix TODOs"	Eddie Hung	2019-10-04	1	-0/+15
\| \| \| \|	This reverts commit 8674a6c68d563908014d16671567459499c6dc99.
*	More comments, cleanup	Eddie Hung	2019-10-04	1	-31/+75
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*	Fix TODOs	Eddie Hung	2019-10-04	1	-15/+0
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*	Add comments for xilinx_dsp	Eddie Hung	2019-10-04	1	-2/+91
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*	Fix xilinx_dsp for unsigned extensions	Eddie Hung	2019-10-04	1	-1/+3
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*	Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)	Eddie Hung	2019-09-25	1	-1/+5
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*	Reject if (* init *) present	Eddie Hung	2019-09-25	1	-0/+3
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*	Rework xilinx_dsp postAdd for new wreduce call	Eddie Hung	2019-09-25	1	-3/+3
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*	Call 'wreduce' after mul2dsp to avoid unextend()	Eddie Hung	2019-09-25	1	-5/+4
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*	Separate out CREG packing into new pattern, to avoid conflict with PREG	Eddie Hung	2019-09-23	1	-24/+6
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*	Use new port() overload once more	Eddie Hung	2019-09-23	1	-2/+2
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*	Use new port/param overload in pmg	Eddie Hung	2019-09-20	1	-4/+4
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*	Cleanup xilinx_dsp	Eddie Hung	2019-09-20	1	-1/+1
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*	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	Eddie Hung	2019-09-20	1	-1/+1
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*	Add an index	Eddie Hung	2019-09-19	1	-0/+2
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*	Do not perform width-checks for DSP48E1 which is much more complicated	Eddie Hung	2019-09-19	1	-11/+0
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*	Cleanup xilinx_dsp too	Eddie Hung	2019-09-19	1	-37/+28
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*	Cleanup	Eddie Hung	2019-09-19	1	-8/+4
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*	Check overflow condition is power of 2 without using int32	Eddie Hung	2019-09-18	1	-2/+2
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*	Add support for overflow using pattern detector	Eddie Hung	2019-09-18	1	-1/+12
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*	Separate dffrstmux from dffcemux, fix typos	Eddie Hung	2019-09-18	1	-20/+32
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*	Add support for A1 and B1 registers	Eddie Hung	2019-09-11	1	-5/+65
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*	Rename {A,B} -> {A2,B2}	Eddie Hung	2019-09-11	1	-19/+20
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*	Make unextend a udata	Eddie Hung	2019-09-11	1	-3/+2
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*	Add support for A/B/C/D/AD reset	Eddie Hung	2019-09-11	1	-56/+103
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*	Add support for RSTM	Eddie Hung	2019-09-11	1	-64/+88
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*	Only pack out registers if \init is zero or x; then remove \init from PREG	Eddie Hung	2019-09-10	1	-4/+8
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*	Add support for RSTP	Eddie Hung	2019-09-10	1	-22/+58
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*	enpol -> cepol	Eddie Hung	2019-09-10	1	-46/+48
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*	d?ffmux -> d?ffcemux	Eddie Hung	2019-09-10	1	-34/+33
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*	Refactor MREG and PREG to out_dffe subpattern	Eddie Hung	2019-09-10	1	-155/+122
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*	Only trim sigM if USE_MULT; only look for ffM then too	Eddie Hung	2019-09-09	1	-9/+13
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*	Rename	Eddie Hung	2019-09-09	1	-27/+27
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*	Oops	Eddie Hung	2019-09-09	1	-2/+1
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*	Tidy up	Eddie Hung	2019-09-09	1	-6/+5
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*	Refactor using subpattern in_dffe	Eddie Hung	2019-09-09	1	-240/+146
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*	Pack CREG	Eddie Hung	2019-09-06	1	-19/+70
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*	Use unextend lambda	Eddie Hung	2019-09-06	1	-19/+18
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*	Fix ffP just like ffPmux	Eddie Hung	2019-09-06	1	-4/+4
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*	Perform D replacement properly	Eddie Hung	2019-09-06	1	-5/+0
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*	Add support for DREG	Eddie Hung	2019-09-06	1	-2/+57
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*	Fine tune nusers when postAdd	Eddie Hung	2019-09-06	1	-3/+3
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*	Fix macc and mul tests	Eddie Hung	2019-09-06	1	-3/+17
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*	Fix enable polarity	Eddie Hung	2019-09-06	1	-12/+12
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