iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Consistent use of 'override' for virtual methods in derived classes.	Henner Zeller	2018-07-20	1	-2/+2
*	Fix opt_rmdff handling of $dlatchsr	Clifford Wolf	2018-02-26	1	-0/+3
*	Fix memory corruption bug in opt_rmdff	Clifford Wolf	2017-10-26	1	-0/+3
*	Add support for set-reset cell variants to opt_rmdff	Clifford Wolf	2017-08-09	1	-0/+182
*	Add handling of constant reset signals to opt_rmdff	Clifford Wolf	2017-08-06	1	-1/+23
*	Fix handling of init attributes with strange width	Clifford Wolf	2017-02-09	1	-1/+3
*	Improve opt_rmdff support for $dlatch cells	Clifford Wolf	2017-01-31	1	-4/+22
*	Added opt_rmdff support for $ff cells	Clifford Wolf	2016-10-14	1	-5/+13
*	Added "opt_rmdff -keepdc"	Clifford Wolf	2016-09-30	1	-3/+14
*	Improved init spec handling in opt_rmdff, modernized the code a bit	Clifford Wolf	2016-08-30	1	-39/+82
*	Added "yosys -D" feature	Clifford Wolf	2016-04-21	1	-1/+1
*	Properly clean up unused "init" attributes	Clifford Wolf	2015-08-18	1	-2/+18
*	Some cleanups in opt_rmdff	Clifford Wolf	2015-07-25	1	-16/+9
*	Improved $adff simplification	Clifford Wolf	2015-07-24	1	-1/+1
*	Fixed trailing whitespaces	Clifford Wolf	2015-07-02	1	-3/+3
*	Added simple $dlatch support to opt_rmdff	Clifford Wolf	2015-05-23	1	-0/+35
*	Improved handling of init values in opt_rmdff	Clifford Wolf	2015-04-18	1	-11/+9
*	Don't be too smart with $dff cells with "init" attribute on out signal	Clifford Wolf	2014-10-16	1	-1/+1
*	namespace Yosys	Clifford Wolf	2014-09-27	1	-3/+7
*	Added design->scratchpad	Clifford Wolf	2014-08-30	1	-2/+3
*	More cleanups related to RTLIL::IdString usage	Clifford Wolf	2014-08-02	1	-1/+1
*	Renamed port access function on RTLIL::Cell, added param access functions	Clifford Wolf	2014-07-31	1	-18/+18
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-3/+3
*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-26/+26
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-26/+26
*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-2/+1
*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-7/+7
*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-7/+7
*	Fixed detection of init attribute in opt_rmdff	Clifford Wolf	2014-02-04	1	-1/+1
*	Improved handling of reg init in opt_share and opt_rmdff	Clifford Wolf	2014-02-04	1	-7/+29
*	Added constant-clock case to opt_rmdff	Clifford Wolf	2014-02-02	1	-0/+8
*	Added support for $adff with undef data inputs to opt_rmdff	Clifford Wolf	2014-01-17	1	-0/+6
*	Added log_abort() api	Clifford Wolf	2013-05-24	1	-1/+1
*	Some improvements in opt_rmdff	Clifford Wolf	2013-05-23	1	-2/+33
*	Added help messages for opt_* passes	Clifford Wolf	2013-03-01	1	-1/+16
*	initial import	Clifford Wolf	2013-01-05	1	-0/+135