iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	Refactoring: Renamed RTLIL::Design::modules to modules_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::cells to cells_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Refactoring: Renamed RTLIL::Module::wires to wires_	Clifford Wolf	2014-07-27	1	-1/+1
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*	Changed a lot of code to the new RTLIL::Wire constructors	Clifford Wolf	2014-07-26	1	-39/+14
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*	Changed users of cell->connections_ to the new API (sed command)	Clifford Wolf	2014-07-26	1	-37/+37
\| \| \| \| \| \| \| \| \|	git grep -l 'connections_' \| xargs sed -i -r -e ' s/(->\|\.)connections_\["([^"])"\] = (.);/\1set("\2", \3);/g; s/(->\|\.)connections_\["([^"])"\]/\1get("\2")/g; s/(->\|\.)connections_.at$"([^"])"$/\1get("\2")/g; s/(->\|\.)connections_.push_back/\1connect/g; s/(->\|\.)connections_/\1connections()/g;'
*	Renamed RTLIL::{Module,Cell}::connections to connections_	Clifford Wolf	2014-07-26	1	-37/+37
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*	Use only module->addCell() and module->remove() to create and delete cells	Clifford Wolf	2014-07-25	1	-33/+9
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*	SigSpec refactoring: using the accessor functions everywhere	Clifford Wolf	2014-07-22	1	-4/+4
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*	SigSpec refactoring: renamed chunks and width to __chunks and __width	Clifford Wolf	2014-07-22	1	-4/+4
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*	Changes to "memory" pass for new $memwr/$mem WR_EN interface	Clifford Wolf	2014-07-16	1	-35/+53
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*	Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)	Clifford Wolf	2014-02-03	1	-34/+37
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*	Only generate write-enable $and if WE is not constant 1 in memory_map	Clifford Wolf	2014-02-02	1	-15/+18
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*	Replaced RTLIL::Const::str with generic decoder method	Clifford Wolf	2013-12-04	1	-1/+1
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*	Fixed bug in synthesis of memories that are never written	Clifford Wolf	2013-10-17	1	-2/+7
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*	Added help messages to memory_* passes	Clifford Wolf	2013-03-01	1	-4/+15
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*	initial import	Clifford Wolf	2013-01-05	1	-0/+334