| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Add "rename -output" | Clifford Wolf | 2019-03-27 | 1 | -3/+23 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Improve "rename" help message | Clifford Wolf | 2019-03-27 | 1 | -0/+6 |
| | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at> | ||||
| * | Rename cells based on the wires they drive. | Scott Mansell | 2019-01-06 | 1 | -0/+66 |
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| * | rename: add -src, for inferring names from source locations. | whitequark | 2018-12-05 | 1 | -0/+50 |
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| * | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -2/+2 |
| | | | | | | | | | | o Not all derived methods were marked 'override', but it is a great feature of C++11 that we should make use of. o While at it: touched header files got a -*- c++ -*- for emacs to provide support for that language. o use YS_OVERRIDE for all override keywords (though we should probably use the plain keyword going forward now that C++11 is established) | ||||
| * | Fixed trailing whitespaces | Clifford Wolf | 2015-07-02 | 1 | -3/+3 |
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| * | Added design->rename(module, new_name) | Clifford Wolf | 2015-06-30 | 1 | -3/+1 |
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| * | Added "rename -top new_name" | Clifford Wolf | 2015-06-17 | 1 | -0/+27 |
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| * | Fixed iterator invalidation bug in "rename" command | Clifford Wolf | 2015-02-09 | 1 | -3/+4 |
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| * | Added Yosys::{dict,nodict,vector} container types | Clifford Wolf | 2014-12-26 | 1 | -4/+4 |
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| * | Added missing fixup_ports() calls to "rename" command | Clifford Wolf | 2014-11-08 | 1 | -0/+4 |
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| * | namespace Yosys | Clifford Wolf | 2014-09-27 | 1 | -0/+4 |
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| * | Implemented "rename -enumerate -pattern" | Clifford Wolf | 2014-08-26 | 1 | -4/+13 |
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| * | Refactoring: Renamed RTLIL::Design::modules to modules_ | Clifford Wolf | 2014-07-27 | 1 | -7/+7 |
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| * | Refactoring: Renamed RTLIL::Module::cells to cells_ | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
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| * | Refactoring: Renamed RTLIL::Module::wires to wires_ | Clifford Wolf | 2014-07-27 | 1 | -5/+5 |
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| * | Changed more code to the new RTLIL::Wire constructors | Clifford Wolf | 2014-07-26 | 1 | -10/+4 |
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| * | Added "rename -hide" command | Clifford Wolf | 2014-01-02 | 1 | -1/+44 |
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| * | Improved handling of private names in opt_clean and rename commands | Clifford Wolf | 2013-08-07 | 1 | -5/+37 |
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| * | Added renaming of wires and cells to "rename" command | Clifford Wolf | 2013-06-19 | 1 | -2/+28 |
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| * | Added "rename" command | Clifford Wolf | 2013-06-10 | 1 | -0/+94 |
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