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* Add support for memory writes in processes.Marcelina Koƛcielnicka2021-03-081-2/+3
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* Adds appendix on RTLIL text formatRobert Baruch2020-11-221-0/+4
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* manual: fix typo.whitequark2020-08-271-1/+1
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* Replace "ILANG" with "RTLIL" everywhere.whitequark2020-08-261-9/+8
| | | | | | | | | | The only difference between "RTLIL" and "ILANG" is that the latter is the text representation of the former, as opposed to the in-memory graph representation. This distinction serves no purpose but confuses people: it is not obvious that the ILANG backend writes RTLIL graphs. Passes `write_ilang` and `read_ilang` are provided as aliases to `write_rtlil` and `read_rtlil` for compatibility.
* flatten: preserve original object names via hdlname attribute.whitequark2020-06-081-0/+7
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* Restrict RTLIL::IdString to not contain whitespace or control chars.whitequark2020-05-291-3/+6
| | | | | This is an existing invariant (most backends can't cope with these) but one that was not checked or documented.
* manual: explain RTLIL::Wire::{upto,offset}.whitequark2020-02-091-0/+7
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* manual: explain the purpose of `sync always`.whitequark2019-07-021-2/+3
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* Explain exact semantics of switch and case rules in the manual.whitequark2019-06-191-0/+12
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* manual: document $meminit cell and memory_* passes.whitequark2018-12-201-2/+2
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* Renamed opt_share to opt_mergeClifford Wolf2016-03-311-2/+2
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* Renamed opt_const to opt_exprClifford Wolf2016-03-311-1/+1
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* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-2/+2
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* Fixed trailing whitespacesClifford Wolf2015-07-021-5/+5
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* Typos and grammar fixes through chapter 4.Anthony J. Bentley2014-05-021-25/+25
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* presentation progressClifford Wolf2014-02-031-1/+0
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* Updated manualClifford Wolf2013-09-151-2/+4
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* Added RTLIL and Liberty syntax highlighting to manualClifford Wolf2013-07-251-3/+3
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* Added Yosys ManualClifford Wolf2013-07-201-0/+525