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* Added query() API to ModIndexClifford Wolf2014-08-031-8/+46
* Added ID() macro for static IdStringsClifford Wolf2014-08-031-0/+3
* Fixed a va_list corruption in logv_error()Clifford Wolf2014-08-021-4/+3
* Bugfix in "techmap -extern"Clifford Wolf2014-08-021-10/+16
* Removed at() method from RTLIL::IdStringClifford Wolf2014-08-022-7/+6
* No implicit conversion from IdString to anything elseClifford Wolf2014-08-024-22/+22
* More bugfixes related to new RTLIL::IdStringClifford Wolf2014-08-023-17/+31
* Limit size of log_signal buffer to 100 elementsClifford Wolf2014-08-022-2/+9
* Improvements in new RTLIL::IdString implementationClifford Wolf2014-08-025-33/+65
* Implemented new reference counting RTLIL::IdStringClifford Wolf2014-08-022-15/+90
* Fixed memory corruption related to id2cstr()Clifford Wolf2014-08-021-2/+2
* More cleanups related to RTLIL::IdString usageClifford Wolf2014-08-022-63/+36
* Preparations for RTLIL::IdString redesign: cleanup of existing codeClifford Wolf2014-08-026-22/+61
* Added logfile hash to statistics footerClifford Wolf2014-08-015-45/+79
* Added per-pass cpu usage statisticsClifford Wolf2014-08-014-12/+86
* Added ModIndex helper class, some changes to RTLIL::MonitorClifford Wolf2014-08-017-24/+165
* Packed SigBit::data and SigBit::offset in a unionClifford Wolf2014-08-012-10/+14
* Renamed modwalker.h to modtools.hClifford Wolf2014-07-311-2/+2
* Renamed port access function on RTLIL::Cell, added param access functionsClifford Wolf2014-07-314-179/+206
* Added "trace" commandClifford Wolf2014-07-311-0/+3
* Added RTLIL::MonitorClifford Wolf2014-07-312-96/+97
* Added module->design and cell->module, wire->module pointersClifford Wolf2014-07-312-0/+103
* Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespaceClifford Wolf2014-07-3111-597/+653
* Added "yosys -A"Clifford Wolf2014-07-311-1/+10
* Added "yosys -Q"Clifford Wolf2014-07-311-26/+35
* Added techmap CONSTMAP featureClifford Wolf2014-07-301-0/+3
* Added write_file commandClifford Wolf2014-07-302-5/+7
* Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT modelsClifford Wolf2014-07-301-36/+39
* Added "log_dump_val_worker(char *v)"Clifford Wolf2014-07-301-0/+1
* Added "kernel/yosys.h" and "kernel/yosys.cc"Clifford Wolf2014-07-307-60/+132
* Added "test_cell" commandClifford Wolf2014-07-291-1/+1
* Renamed "write_autotest" to "test_autotb" and moved to passes/tests/Clifford Wolf2014-07-291-1/+3
* Added "techmap -map %{design-name}"Clifford Wolf2014-07-292-0/+10
* Added $shift and $shiftx cell types (needed for correct part select behavior)Clifford Wolf2014-07-295-19/+75
* Added wire->upto flag for signals such as "wire [0:7] x;"Clifford Wolf2014-07-282-1/+3
* Using log_assert() instead of assert()Clifford Wolf2014-07-2812-144/+157
* Added std::initializer_list<> constructor to SigSpecClifford Wolf2014-07-282-0/+15
* Added cover() to all SigSpec constructorsClifford Wolf2014-07-281-0/+22
* Added proper Design->addModule interfaceClifford Wolf2014-07-272-4/+42
* Added topological sorting to techmapClifford Wolf2014-07-271-1/+2
* Added SigPool::check(bit)Clifford Wolf2014-07-271-0/+5
* Small improvements in PerformanceTimer APIClifford Wolf2014-07-271-6/+7
* Improved performance of opt_const on large modulesClifford Wolf2014-07-271-0/+103
* Added RTLIL::SigSpec::remove_const() handling of packed SigSpecsClifford Wolf2014-07-271-9/+26
* Added RTLIL::SigSpecConstIteratorClifford Wolf2014-07-271-0/+18
* Added log_cmd_error_expectionClifford Wolf2014-07-273-4/+6
* Added RTLIL::Module::wire(id) and cell(id) lookup functionsClifford Wolf2014-07-272-2/+20
* Added RTLIL::Design::modules()Clifford Wolf2014-07-271-0/+3
* Refactoring: Renamed RTLIL::Design::modules to modules_Clifford Wolf2014-07-274-20/+20
* Added conversion from ObjRange to std::vector and std::setClifford Wolf2014-07-271-0/+15