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* Merge remote-tracking branch 'origin/xaig' into xc7muxEddie Hung2019-06-211-0/+1
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| * Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-211-0/+1
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| | * Add a few more filename rewritesBen Widawsky2019-06-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This now allows a full pipeline to work, something such as: yosys -p "synth_ecp5 -json ~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v" Otherwise, you will get something along the lines of: ERROR: Can't open output file `~/work/fpga/prjtrellis/examples/ecp5_evn/blinky.v' for writing: No such file or directory Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-202-1/+32
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* | | Merge remote-tracking branch 'origin/eddie/fix1115' into xc7muxEddie Hung2019-06-201-1/+1
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| * | | Revert "Fix sign extension when sign is 1'bx"Eddie Hung2019-06-201-1/+1
| | | | | | | | | | | | | | | | This reverts commit 0221f3e1c5b427678c5679027ee47ec7c0b8321d.
* | | | Merge remote-tracking branch 'origin/eddie/fix1115' into xc7muxEddie Hung2019-06-201-1/+1
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| * | | Fix sign extension when sign is 1'bxEddie Hung2019-06-201-1/+1
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* | | Merge remote-tracking branch 'origin/master' into xc7muxEddie Hung2019-06-202-1/+32
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| * | Merge pull request #1100 from bwidawsk/homeClifford Wolf2019-06-191-0/+4
| |\ \ | | | | | | | | Support ~ in filename parsing
| | * | Support ~ for home directoryBen Widawsky2019-06-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on Linux only v2: Wrap functioanlity in ifndef _WIN32 (eddiehung) Find '~/' instead of '~' (cliffordwolf) Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
| * | | In RTLIL::Module::check(), check process invariants.whitequark2019-06-191-1/+28
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* | / Remove iterator based Module::remove as per @cliffordwolfEddie Hung2019-06-182-11/+3
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* | Fix leak removing cells during ABC integration; also preserve attrEddie Hung2019-06-172-2/+11
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* | Further cleanup based on @daveshah1Eddie Hung2019-06-141-0/+6
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* | Move ConstEvalAig to aigerparse.ccEddie Hung2019-06-131-157/+0
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* | More slimmingEddie Hung2019-06-131-35/+35
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* | Add ConstEvalAig specialised for AIGsEddie Hung2019-06-131-0/+157
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-06-129-21/+187
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| * Fixes and cleanups in AST_TECALL handlingClifford Wolf2019-06-071-4/+4
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge branch 'pr_elab_sys_tasks' of https://github.com/udif/yosys into ↵Clifford Wolf2019-06-072-0/+12
| |\ | | | | | | | | | clifford/pr983
| | * Initial implementation of elaboration system tasksUdi Finkelstein2019-05-032-0/+12
| | | | | | | | | | | | | | | | | | | | | (IEEE1800-2017 section 20.11) This PR allows us to use $info/$warning/$error/$fatal **at elaboration time** within a generate block. This is very useful to stop a synthesis of a parametrized block when an illegal combination of parameters is chosen.
| * | Refactor hierarchy wand/wor handlingClifford Wolf2019-05-281-0/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Fix handling of warning and error messages within log_make_debug-blocksClifford Wolf2019-05-221-0/+9
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add rewrite_sigspecs2, Improve remove() wiresClifford Wolf2019-05-152-7/+82
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge pull request #991 from kristofferkoch/gcc9-warningsClifford Wolf2019-05-081-0/+3
| |\ \ | | | | | | | | Fix all warnings that occurred when compiling with gcc9
| | * | Fix all warnings that occurred when compiling with gcc9Kristoffer Ellersgaard Koch2019-05-081-0/+3
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| * | Merge pull request #998 from mdaiter/get_bool_attribute_optsClifford Wolf2019-05-081-4/+8
| |\ \ | | | | | | | | Minor optimization to get_attribute_bool
| | * | Minor optimization to get_attribute_boolMatthew Daiter2019-05-071-4/+8
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| * | | Optimize ceil_log2 functionMatthew Daiter2019-05-072-3/+5
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| * | Improve write_verilog specify supportClifford Wolf2019-05-041-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Merge remote-tracking branch 'origin/master' into clifford/specifyEddie Hung2019-05-034-3/+18
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| | * Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970Clifford Wolf2019-04-301-1/+1
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| | * fix codestyle formattingOleg Endo2019-04-293-14/+14
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| | * escape spaces with backslash when writing dep fileOleg Endo2019-04-293-2/+17
| | | | | | | | | | | | | | | | | | filenames are sparated by spaces in the dep file. if a filename in the dep file contains spaces they must be escaped, otherwise the tool that reads the dep file will see multiple wrong filenames.
| * | Improve $specrule interfaceClifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Improve $specrule interfaceClifford Wolf2019-04-231-1/+2
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add $specrule cells for $setup/$hold/$skew specify rulesClifford Wolf2019-04-232-0/+17
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std ↵Clifford Wolf2019-04-231-2/+2
| | | | | | | | | | | | | | | | | | nomenclature Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add CellTypes support for $specify2 and $specify3Clifford Wolf2019-04-231-0/+3
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add InternalCellChecker support for $specify2 and $specify3Clifford Wolf2019-04-231-7/+21
| | | | | | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * | Add specify parserClifford Wolf2019-04-231-0/+10
| |/ | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Fixes for OAI4 cell implementationDavid Shah2019-04-232-2/+2
| | | | | | | | | | | | Fixes #955 and the underlying issue in #954 Signed-off-by: David Shah <dave@ds0.me>
* | Remove kernel/cost.cc since master has refactored itEddie Hung2019-04-221-75/+0
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* | Merge remote-tracking branch 'origin/master' into xaigEddie Hung2019-04-229-5/+289
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| * Add log_debug() frameworkClifford Wolf2019-04-224-1/+58
| | | | | | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
| * Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-226-4/+184
| |\ | | | | | | Feature/python bindings
| | * Global lists in rtlil.cc are now static objectsBenedikt Tutzer2019-04-031-10/+10
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| | * Added support for changing Yosys namespaceBenedikt Tutzer2019-04-031-0/+1
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| | * Fixed identationBenedikt Tutzer2019-04-011-1/+1
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