aboutsummaryrefslogtreecommitdiffstats
path: root/kernel
Commit message (Collapse)AuthorAgeFilesLines
* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-0210-679/+822
|
* kernel: IdString::in(const IdString &) as per @TjoppenEddie Hung2020-04-021-1/+1
|
* kernel: fix formatting (thanks @boqwxp)Eddie Hung2020-04-021-6/+4
|
* kernel: use C++11 fold hack to prevent recursionEddie Hung2020-04-021-3/+8
|
* Revert "kernel: IdString:in() to use perfect forwarding"Eddie Hung2020-04-021-2/+2
| | | | This reverts commit 7b2a85aedf24affc2e1202c78e70e6a317f5bf29.
* kernel: separate IdString::put_reference() out to help inliningEddie Hung2020-04-021-1/+4
|
* kernel: IdString:in() to use perfect forwardingEddie Hung2020-04-021-2/+2
|
* kernel: Use constids.inc for global/constant IdStringsEddie Hung2020-04-024-17/+37
|
* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-024-505/+477
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: pass-by-value into Design::scratchpad_set_string() tooEddie Hung2020-03-272-3/+3
| |
| * kernel: const Wire* overload -> Wire* !!!Eddie Hung2020-03-261-1/+1
| |
| * kernel: Cell::set{Port,Param}() to pass by value, but use std::moveEddie Hung2020-03-262-7/+7
| | | | | | | | Otherwise cell->setPort(ID::A, cell->getPort(ID::B)) could be invalid
| * kernel: SigSpec copies to not trigger pack()Eddie Hung2020-03-182-34/+5
| |
| * kernel: more pass by const ref, more speedupsEddie Hung2020-03-183-361/+355
| |
| * kernel: speedupEddie Hung2020-03-181-30/+23
| |
| * kernel: use const reference for SigSet tooEddie Hung2020-03-171-18/+18
| |
| * kernel: fix DeleteWireWorkerEddie Hung2020-03-171-9/+4
| |
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-132-38/+52
| |
| * kernel: optimise Module::remove(const pool<RTLIL::Wire*>()Eddie Hung2020-03-122-10/+9
| |
| * kernel: SigPool to use const& + overloads to prevent implicit SigSpecEddie Hung2020-03-121-19/+25
| |
* | Merge pull request #1828 from YosysHQ/eddie/celltypes_speedupEddie Hung2020-04-011-10/+3
|\ \ | | | | | | kernel: share a single CellTypes within a pass
| * | kernel: share a single CellTypes within a passEddie Hung2020-03-181-10/+3
| |/
* | Clean up pseudo-private member usage in `kernel/yosys.cc`.Alberto Gonzalez2020-04-011-14/+13
| |
* | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-272-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* | Update CopyrightClaire Wolf2020-03-161-1/+1
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | License: bump year and add titleWaldir Pimenta2020-03-141-1/+1
| |
* | exclude clang from checkingMiodrag Milanovic2020-03-131-1/+1
| |
* | Add YS_ prefix to macros, add explanation and apply to older version as wellMiodrag Milanovic2020-03-133-20/+23
| |
* | Use boost xpressive for gcc 4.8Miodrag Milanovic2020-03-133-23/+29
|/
* Fix compilation for emccjiegec2020-03-112-1/+4
|
* Add ScriptPass::run_nocheck and use for abc9David Shah2020-03-092-0/+13
| | | | Signed-off-by: David Shah <dave@ds0.me>
* Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-031-2/+0
|\ | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * Closes #1717. Add more precise Verilog source location information to AST ↵Alberto Gonzalez2020-02-231-2/+0
| | | | | | | | and RTLIL nodes.
* | Small fixesEddie Hung2020-02-271-2/+2
| |
* | Fixes for older compilersEddie Hung2020-02-271-1/+8
| |
* | Make TimingInfo::TimingInfo(SigBit) constructor explicitEddie Hung2020-02-271-4/+5
| |
* | TimingInfo: index by (port_name,offset)Eddie Hung2020-02-271-9/+19
| |
* | Fix spacingEddie Hung2020-02-271-50/+50
| |
* | Get rid of (* abc9_{arrival,required} *) entirelyEddie Hung2020-02-271-3/+4
| |
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-1/+4
| |
* | abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-18/+2
| |
* | abc9_ops: add and use new TimingInfo structEddie Hung2020-02-271-0/+173
| |
* | Merge pull request #1705 from YosysHQ/logger_passMiodrag Milanović2020-02-263-2/+100
|\ \ | |/ |/| Logger pass
| * Remove duplicate warning detectionMiodrag Milanovic2020-02-231-0/+6
| |
| * Handle expect no warnings together with expectedMiodrag Milanovic2020-02-223-4/+12
| |
| * Prevent double error messageMiodrag Milanovic2020-02-171-1/+3
| |
| * Option to expect no warningsMiodrag Milanovic2020-02-173-0/+5
| |
| * No new error if already failingMiodrag Milanovic2020-02-171-1/+2
| |
| * remove whitespaceMiodrag Milanovic2020-02-141-1/+1
| |
| * Add expect option to logger commandMiodrag Milanovic2020-02-143-2/+78
| |
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-07 13:47:35 +0000